SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/mtd/nand/fsl_elbc_nand.c

   1 /* Freescale Enhanced Local Bus Controller NAND driver
   2  *
   3  * Copyright (c) 2006-2007 Freescale Semiconductor
   4  *
   5  * Authors: Nick Spence <nick.spence@freescale.com>,
   6  *          Scott Wood <scottwood@freescale.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/types.h>
  25 #include <linux/init.h>
  26 #include <linux/kernel.h>
  27 #include <linux/string.h>
  28 #include <linux/ioport.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/slab.h>
  31 #include <linux/interrupt.h>
  32
  33 #include <linux/mtd/mtd.h>
  34 #include <linux/mtd/nand.h>
  35 #include <linux/mtd/nand_ecc.h>
  36 #include <linux/mtd/partitions.h>
  37
  38 #include <asm/io.h>
  39 #include <asm/fsl_lbc.h>
  40
  41 #define MAX_BANKS 8
  42 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
  43 #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
  44
  45 struct fsl_elbc_ctrl;
  46
  47 /* mtd information per set */
  48
  49 struct fsl_elbc_mtd {
  50         struct mtd_info mtd;
  51         struct nand_chip chip;
  52         struct fsl_elbc_ctrl *ctrl;
  53
  54         struct device *dev;
  55         int bank;               /* Chip select bank number           */
  56         u8 __iomem *vbase;      /* Chip select base virtual address  */
  57         int page_size;          /* NAND page size (0=512, 1=2048)    */
  58         unsigned int fmr;       /* FCM Flash Mode Register value     */
  59 };
  60
  61 /* overview of the fsl elbc controller */
  62
  63 struct fsl_elbc_ctrl {
  64         struct nand_hw_control controller;
  65         struct fsl_elbc_mtd *chips[MAX_BANKS];
  66
  67         /* device info */
  68         struct device *dev;
  69         struct fsl_lbc_regs __iomem *regs;
  70         int irq;
  71         wait_queue_head_t irq_wait;
  72         unsigned int irq_status; /* status read from LTESR by irq handler */
  73         u8 __iomem *addr;        /* Address of assigned FCM buffer        */
  74         unsigned int page;       /* Last page written to / read from      */
  75         unsigned int read_bytes; /* Number of bytes read during command   */
  76         unsigned int column;     /* Saved column from SEQIN               */
  77         unsigned int index;      /* Pointer to next byte to 'read'        */
  78         unsigned int status;     /* status read from LTESR after last op  */
  79         unsigned int mdr;        /* UPM/FCM Data Register value           */
  80         unsigned int use_mdr;    /* Non zero if the MDR is to be set      */
  81         unsigned int oob;        /* Non zero if operating on OOB data     */
  82         char *oob_poi;           /* Place to write ECC after read back    */
  83 };
  84
  85 /* These map to the positions used by the FCM hardware ECC generator */
  86
  87 /* Small Page FLASH with FMR[ECCM] = 0 */
  88 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
  89         .eccbytes = 3,
  90         .eccpos = {6, 7, 8},
  91         .oobfree = { {0, 5}, {9, 7} },
  92         .oobavail = 12,
  93 };
  94
  95 /* Small Page FLASH with FMR[ECCM] = 1 */
  96 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
  97         .eccbytes = 3,
  98         .eccpos = {8, 9, 10},
  99         .oobfree = { {0, 5}, {6, 2}, {11, 5} },
 100         .oobavail = 12,
 101 };
 102
 103 /* Large Page FLASH with FMR[ECCM] = 0 */
 104 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
 105         .eccbytes = 12,
 106         .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
 107         .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
 108         .oobavail = 48,
 109 };
 110
 111 /* Large Page FLASH with FMR[ECCM] = 1 */
 112 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
 113         .eccbytes = 12,
 114         .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
 115         .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
 116         .oobavail = 48,
 117 };
 118
 119 /*
 120  * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
 121  * 1, so we have to adjust bad block pattern. This pattern should be used for
 122  * x8 chips only. So far hardware does not support x16 chips anyway.
 123  */
 124 static u8 scan_ff_pattern[] = { 0xff, };
 125
 126 static struct nand_bbt_descr largepage_memorybased = {
 127         .options = 0,
 128         .offs = 0,
 129         .len = 1,
 130         .pattern = scan_ff_pattern,
 131 };
 132
 133 /*=================================*/
 134
 135 /*
 136  * Set up the FCM hardware block and page address fields, and the fcm
 137  * structure addr field to point to the correct FCM buffer in memory
 138  */
 139 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 140 {
 141         struct nand_chip *chip = mtd->priv;
 142         struct fsl_elbc_mtd *priv = chip->priv;
 143         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 144         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 145         int buf_num;
 146
 147         ctrl->page = page_addr;
 148
 149         out_be32(&lbc->fbar,
 150                  page_addr >> (chip->phys_erase_shift - chip->page_shift));
 151
 152         if (priv->page_size) {
 153                 out_be32(&lbc->fpar,
 154                          ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
 155                          (oob ? FPAR_LP_MS : 0) | column);
 156                 buf_num = (page_addr & 1) << 2;
 157         } else {
 158                 out_be32(&lbc->fpar,
 159                          ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
 160                          (oob ? FPAR_SP_MS : 0) | column);
 161                 buf_num = page_addr & 7;
 162         }
 163
 164         ctrl->addr = priv->vbase + buf_num * 1024;
 165         ctrl->index = column;
 166
 167         /* for OOB data point to the second half of the buffer */
 168         if (oob)
 169                 ctrl->index += priv->page_size ? 2048 : 512;
 170
 171         dev_vdbg(ctrl->dev, "set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
 172                             "index %x, pes %d ps %d\n",
 173                  buf_num, ctrl->addr, priv->vbase, ctrl->index,
 174                  chip->phys_erase_shift, chip->page_shift);
 175 }
 176
 177 /*
 178  * execute FCM command and wait for it to complete
 179  */
 180 static int fsl_elbc_run_command(struct mtd_info *mtd)
 181 {
 182         struct nand_chip *chip = mtd->priv;
 183         struct fsl_elbc_mtd *priv = chip->priv;
 184         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 185         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 186
 187         /* Setup the FMR[OP] to execute without write protection */
 188         out_be32(&lbc->fmr, priv->fmr | 3);
 189         if (ctrl->use_mdr)
 190                 out_be32(&lbc->mdr, ctrl->mdr);
 191
 192         dev_vdbg(ctrl->dev,
 193                  "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
 194                  in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
 195         dev_vdbg(ctrl->dev,
 196                  "fsl_elbc_run_command: fbar=%08x fpar=%08x "
 197                  "fbcr=%08x bank=%d\n",
 198                  in_be32(&lbc->fbar), in_be32(&lbc->fpar),
 199                  in_be32(&lbc->fbcr), priv->bank);
 200
 201         ctrl->irq_status = 0;
 202         /* execute special operation */
 203         out_be32(&lbc->lsor, priv->bank);
 204
 205         /* wait for FCM complete flag or timeout */
 206         wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
 207                            FCM_TIMEOUT_MSECS * HZ/1000);
 208         ctrl->status = ctrl->irq_status;
 209
 210         /* store mdr value in case it was needed */
 211         if (ctrl->use_mdr)
 212                 ctrl->mdr = in_be32(&lbc->mdr);
 213
 214         ctrl->use_mdr = 0;
 215
 216         dev_vdbg(ctrl->dev,
 217                  "fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
 218                  ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
 219
 220         /* returns 0 on success otherwise non-zero) */
 221         return ctrl->status == LTESR_CC ? 0 : -EIO;
 222 }
 223
 224 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 225 {
 226         struct fsl_elbc_mtd *priv = chip->priv;
 227         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 228         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 229
 230         if (priv->page_size) {
 231                 out_be32(&lbc->fir,
 232                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 233                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 234                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 235                          (FIR_OP_CW1 << FIR_OP3_SHIFT) |
 236                          (FIR_OP_RBW << FIR_OP4_SHIFT));
 237
 238                 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
 239                                     (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
 240         } else {
 241                 out_be32(&lbc->fir,
 242                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 243                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 244                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 245                          (FIR_OP_RBW << FIR_OP3_SHIFT));
 246
 247                 if (oob)
 248                         out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
 249                 else
 250                         out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
 251         }
 252 }
 253
 254 /* cmdfunc send commands to the FCM */
 255 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 256                              int column, int page_addr)
 257 {
 258         struct nand_chip *chip = mtd->priv;
 259         struct fsl_elbc_mtd *priv = chip->priv;
 260         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 261         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 262
 263         ctrl->use_mdr = 0;
 264
 265         /* clear the read buffer */
 266         ctrl->read_bytes = 0;
 267         if (command != NAND_CMD_PAGEPROG)
 268                 ctrl->index = 0;
 269
 270         switch (command) {
 271         /* READ0 and READ1 read the entire buffer to use hardware ECC. */
 272         case NAND_CMD_READ1:
 273                 column += 256;
 274
 275         /* fall-through */
 276         case NAND_CMD_READ0:
 277                 dev_dbg(ctrl->dev,
 278                         "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
 279                         " 0x%x, column: 0x%x.\n", page_addr, column);
 280
 281
 282                 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
 283                 set_addr(mtd, 0, page_addr, 0);
 284
 285                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 286                 ctrl->index += column;
 287
 288                 fsl_elbc_do_read(chip, 0);
 289                 fsl_elbc_run_command(mtd);
 290                 return;
 291
 292         /* READOOB reads only the OOB because no ECC is performed. */
 293         case NAND_CMD_READOOB:
 294                 dev_vdbg(ctrl->dev,
 295                          "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
 296                          " 0x%x, column: 0x%x.\n", page_addr, column);
 297
 298                 out_be32(&lbc->fbcr, mtd->oobsize - column);
 299                 set_addr(mtd, column, page_addr, 1);
 300
 301                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 302
 303                 fsl_elbc_do_read(chip, 1);
 304                 fsl_elbc_run_command(mtd);
 305                 return;
 306
 307         /* READID must read all 5 possible bytes while CEB is active */
 308         case NAND_CMD_READID:
 309                 dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
 310
 311                 out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 312                                     (FIR_OP_UA  << FIR_OP1_SHIFT) |
 313                                     (FIR_OP_RBW << FIR_OP2_SHIFT));
 314                 out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
 315                 /* 5 bytes for manuf, device and exts */
 316                 out_be32(&lbc->fbcr, 5);
 317                 ctrl->read_bytes = 5;
 318                 ctrl->use_mdr = 1;
 319                 ctrl->mdr = 0;
 320
 321                 set_addr(mtd, 0, 0, 0);
 322                 fsl_elbc_run_command(mtd);
 323                 return;
 324
 325         /* ERASE1 stores the block and page address */
 326         case NAND_CMD_ERASE1:
 327                 dev_vdbg(ctrl->dev,
 328                          "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
 329                          "page_addr: 0x%x.\n", page_addr);
 330                 set_addr(mtd, 0, page_addr, 0);
 331                 return;
 332
 333         /* ERASE2 uses the block and page address from ERASE1 */
 334         case NAND_CMD_ERASE2:
 335                 dev_vdbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
 336
 337                 out_be32(&lbc->fir,
 338                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 339                          (FIR_OP_PA  << FIR_OP1_SHIFT) |
 340                          (FIR_OP_CM1 << FIR_OP2_SHIFT));
 341
 342                 out_be32(&lbc->fcr,
 343                          (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
 344                          (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
 345
 346                 out_be32(&lbc->fbcr, 0);
 347                 ctrl->read_bytes = 0;
 348
 349                 fsl_elbc_run_command(mtd);
 350                 return;
 351
 352         /* SEQIN sets up the addr buffer and all registers except the length */
 353         case NAND_CMD_SEQIN: {
 354                 __be32 fcr;
 355                 dev_vdbg(ctrl->dev,
 356                          "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
 357                          "page_addr: 0x%x, column: 0x%x.\n",
 358                          page_addr, column);
 359
 360                 ctrl->column = column;
 361                 ctrl->oob = 0;
 362
 363                 if (priv->page_size) {
 364                         fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) |
 365                               (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT);
 366
 367                         out_be32(&lbc->fir,
 368                                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 369                                  (FIR_OP_CA  << FIR_OP1_SHIFT) |
 370                                  (FIR_OP_PA  << FIR_OP2_SHIFT) |
 371                                  (FIR_OP_WB  << FIR_OP3_SHIFT) |
 372                                  (FIR_OP_CW1 << FIR_OP4_SHIFT));
 373                 } else {
 374                         fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
 375                               (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
 376
 377                         out_be32(&lbc->fir,
 378                                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 379                                  (FIR_OP_CM2 << FIR_OP1_SHIFT) |
 380                                  (FIR_OP_CA  << FIR_OP2_SHIFT) |
 381                                  (FIR_OP_PA  << FIR_OP3_SHIFT) |
 382                                  (FIR_OP_WB  << FIR_OP4_SHIFT) |
 383                                  (FIR_OP_CW1 << FIR_OP5_SHIFT));
 384
 385                         if (column >= mtd->writesize) {
 386                                 /* OOB area --> READOOB */
 387                                 column -= mtd->writesize;
 388                                 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
 389                                 ctrl->oob = 1;
 390                         } else if (column < 256) {
 391                                 /* First 256 bytes --> READ0 */
 392                                 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
 393                         } else {
 394                                 /* Second 256 bytes --> READ1 */
 395                                 fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
 396                         }
 397                 }
 398
 399                 out_be32(&lbc->fcr, fcr);
 400                 set_addr(mtd, column, page_addr, ctrl->oob);
 401                 return;
 402         }
 403
 404         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 405         case NAND_CMD_PAGEPROG: {
 406                 int full_page;
 407                 dev_vdbg(ctrl->dev,
 408                          "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
 409                          "writing %d bytes.\n", ctrl->index);
 410
 411                 /* if the write did not start at 0 or is not a full page
 412                  * then set the exact length, otherwise use a full page
 413                  * write so the HW generates the ECC.
 414                  */
 415                 if (ctrl->oob || ctrl->column != 0 ||
 416                     ctrl->index != mtd->writesize + mtd->oobsize) {
 417                         out_be32(&lbc->fbcr, ctrl->index);
 418                         full_page = 0;
 419                 } else {
 420                         out_be32(&lbc->fbcr, 0);
 421                         full_page = 1;
 422                 }
 423
 424                 fsl_elbc_run_command(mtd);
 425
 426                 /* Read back the page in order to fill in the ECC for the
 427                  * caller.  Is this really needed?
 428                  */
 429                 if (full_page && ctrl->oob_poi) {
 430                         out_be32(&lbc->fbcr, 3);
 431                         set_addr(mtd, 6, page_addr, 1);
 432
 433                         ctrl->read_bytes = mtd->writesize + 9;
 434
 435                         fsl_elbc_do_read(chip, 1);
 436                         fsl_elbc_run_command(mtd);
 437
 438                         memcpy_fromio(ctrl->oob_poi + 6,
 439                                       &ctrl->addr[ctrl->index], 3);
 440                         ctrl->index += 3;
 441                 }
 442
 443                 ctrl->oob_poi = NULL;
 444                 return;
 445         }
 446
 447         /* CMD_STATUS must read the status byte while CEB is active */
 448         /* Note - it does not wait for the ready line */
 449         case NAND_CMD_STATUS:
 450                 out_be32(&lbc->fir,
 451                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 452                          (FIR_OP_RBW << FIR_OP1_SHIFT));
 453                 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 454                 out_be32(&lbc->fbcr, 1);
 455                 set_addr(mtd, 0, 0, 0);
 456                 ctrl->read_bytes = 1;
 457
 458                 fsl_elbc_run_command(mtd);
 459
 460                 /* The chip always seems to report that it is
 461                  * write-protected, even when it is not.
 462                  */
 463                 setbits8(ctrl->addr, NAND_STATUS_WP);
 464                 return;
 465
 466         /* RESET without waiting for the ready line */
 467         case NAND_CMD_RESET:
 468                 dev_dbg(ctrl->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
 469                 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
 470                 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
 471                 fsl_elbc_run_command(mtd);
 472                 return;
 473
 474         default:
 475                 dev_err(ctrl->dev,
 476                         "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
 477                         command);
 478         }
 479 }
 480
 481 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
 482 {
 483         /* The hardware does not seem to support multiple
 484          * chips per bank.
 485          */
 486 }
 487
 488 /*
 489  * Write buf to the FCM Controller Data Buffer
 490  */
 491 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 492 {
 493         struct nand_chip *chip = mtd->priv;
 494         struct fsl_elbc_mtd *priv = chip->priv;
 495         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 496         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 497
 498         if (len <= 0) {
 499                 dev_err(ctrl->dev, "write_buf of %d bytes", len);
 500                 ctrl->status = 0;
 501                 return;
 502         }
 503
 504         if ((unsigned int)len > bufsize - ctrl->index) {
 505                 dev_err(ctrl->dev,
 506                         "write_buf beyond end of buffer "
 507                         "(%d requested, %u available)\n",
 508                         len, bufsize - ctrl->index);
 509                 len = bufsize - ctrl->index;
 510         }
 511
 512         memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
 513         /*
 514          * This is workaround for the weird elbc hangs during nand write,
 515          * Scott Wood says: "...perhaps difference in how long it takes a
 516          * write to make it through the localbus compared to a write to IMMR
 517          * is causing problems, and sync isn't helping for some reason."
 518          * Reading back the last byte helps though.
 519          */
 520         in_8(&ctrl->addr[ctrl->index] + len - 1);
 521
 522         ctrl->index += len;
 523 }
 524
 525 /*
 526  * read a byte from either the FCM hardware buffer if it has any data left
 527  * otherwise issue a command to read a single byte.
 528  */
 529 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
 530 {
 531         struct nand_chip *chip = mtd->priv;
 532         struct fsl_elbc_mtd *priv = chip->priv;
 533         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 534
 535         /* If there are still bytes in the FCM, then use the next byte. */
 536         if (ctrl->index < ctrl->read_bytes)
 537                 return in_8(&ctrl->addr[ctrl->index++]);
 538
 539         dev_err(ctrl->dev, "read_byte beyond end of buffer\n");
 540         return ERR_BYTE;
 541 }
 542
 543 /*
 544  * Read from the FCM Controller Data Buffer
 545  */
 546 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 547 {
 548         struct nand_chip *chip = mtd->priv;
 549         struct fsl_elbc_mtd *priv = chip->priv;
 550         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 551         int avail;
 552
 553         if (len < 0)
 554                 return;
 555
 556         avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
 557         memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
 558         ctrl->index += avail;
 559
 560         if (len > avail)
 561                 dev_err(ctrl->dev,
 562                         "read_buf beyond end of buffer "
 563                         "(%d requested, %d available)\n",
 564                         len, avail);
 565 }
 566
 567 /*
 568  * Verify buffer against the FCM Controller Data Buffer
 569  */
 570 static int fsl_elbc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
 571 {
 572         struct nand_chip *chip = mtd->priv;
 573         struct fsl_elbc_mtd *priv = chip->priv;
 574         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 575         int i;
 576
 577         if (len < 0) {
 578                 dev_err(ctrl->dev, "write_buf of %d bytes", len);
 579                 return -EINVAL;
 580         }
 581
 582         if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
 583                 dev_err(ctrl->dev,
 584                         "verify_buf beyond end of buffer "
 585                         "(%d requested, %u available)\n",
 586                         len, ctrl->read_bytes - ctrl->index);
 587
 588                 ctrl->index = ctrl->read_bytes;
 589                 return -EINVAL;
 590         }
 591
 592         for (i = 0; i < len; i++)
 593                 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
 594                         break;
 595
 596         ctrl->index += len;
 597         return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
 598 }
 599
 600 /* This function is called after Program and Erase Operations to
 601  * check for success or failure.
 602  */
 603 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 604 {
 605         struct fsl_elbc_mtd *priv = chip->priv;
 606         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 607         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 608
 609         if (ctrl->status != LTESR_CC)
 610                 return NAND_STATUS_FAIL;
 611
 612         /* Use READ_STATUS command, but wait for the device to be ready */
 613         ctrl->use_mdr = 0;
 614         out_be32(&lbc->fir,
 615                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 616                  (FIR_OP_RBW << FIR_OP1_SHIFT));
 617         out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 618         out_be32(&lbc->fbcr, 1);
 619         set_addr(mtd, 0, 0, 0);
 620         ctrl->read_bytes = 1;
 621
 622         fsl_elbc_run_command(mtd);
 623
 624         if (ctrl->status != LTESR_CC)
 625                 return NAND_STATUS_FAIL;
 626
 627         /* The chip always seems to report that it is
 628          * write-protected, even when it is not.
 629          */
 630         setbits8(ctrl->addr, NAND_STATUS_WP);
 631         return fsl_elbc_read_byte(mtd);
 632 }
 633
 634 static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
 635 {
 636         struct nand_chip *chip = mtd->priv;
 637         struct fsl_elbc_mtd *priv = chip->priv;
 638         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 639         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 640         unsigned int al;
 641
 642         /* calculate FMR Address Length field */
 643         al = 0;
 644         if (chip->pagemask & 0xffff0000)
 645                 al++;
 646         if (chip->pagemask & 0xff000000)
 647                 al++;
 648
 649         /* add to ECCM mode set in fsl_elbc_init */
 650         priv->fmr |= (12 << FMR_CWTO_SHIFT) |  /* Timeout > 12 ms */
 651                      (al << FMR_AL_SHIFT);
 652
 653         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->numchips = %d\n",
 654                 chip->numchips);
 655         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chipsize = %ld\n",
 656                 chip->chipsize);
 657         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
 658                 chip->pagemask);
 659         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
 660                 chip->chip_delay);
 661         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
 662                 chip->badblockpos);
 663         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
 664                 chip->chip_shift);
 665         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->page_shift = %d\n",
 666                 chip->page_shift);
 667         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
 668                 chip->phys_erase_shift);
 669         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecclayout = %p\n",
 670                 chip->ecclayout);
 671         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
 672                 chip->ecc.mode);
 673         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
 674                 chip->ecc.steps);
 675         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
 676                 chip->ecc.bytes);
 677         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
 678                 chip->ecc.total);
 679         dev_dbg(ctrl->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
 680                 chip->ecc.layout);
 681         dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
 682         dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->size = %d\n", mtd->size);
 683         dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
 684                 mtd->erasesize);
 685         dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->writesize = %d\n",
 686                 mtd->writesize);
 687         dev_dbg(ctrl->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
 688                 mtd->oobsize);
 689
 690         /* adjust Option Register and ECC to match Flash page size */
 691         if (mtd->writesize == 512) {
 692                 priv->page_size = 0;
 693                 clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
 694         } else if (mtd->writesize == 2048) {
 695                 priv->page_size = 1;
 696                 setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
 697                 /* adjust ecc setup if needed */
 698                 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
 699                     BR_DECC_CHK_GEN) {
 700                         chip->ecc.size = 512;
 701                         chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
 702                                            &fsl_elbc_oob_lp_eccm1 :
 703                                            &fsl_elbc_oob_lp_eccm0;
 704                         chip->badblock_pattern = &largepage_memorybased;
 705                         mtd->ecclayout = chip->ecc.layout;
 706                         mtd->oobavail = chip->ecc.layout->oobavail;
 707                 }
 708         } else {
 709                 dev_err(ctrl->dev,
 710                         "fsl_elbc_init: page size %d is not supported\n",
 711                         mtd->writesize);
 712                 return -1;
 713         }
 714
 715         return 0;
 716 }
 717
 718 static int fsl_elbc_read_page(struct mtd_info *mtd,
 719                               struct nand_chip *chip,
 720                               uint8_t *buf)
 721 {
 722         fsl_elbc_read_buf(mtd, buf, mtd->writesize);
 723         fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 724
 725         if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
 726                 mtd->ecc_stats.failed++;
 727
 728         return 0;
 729 }
 730
 731 /* ECC will be calculated automatically, and errors will be detected in
 732  * waitfunc.
 733  */
 734 static void fsl_elbc_write_page(struct mtd_info *mtd,
 735                                 struct nand_chip *chip,
 736                                 const uint8_t *buf)
 737 {
 738         struct fsl_elbc_mtd *priv = chip->priv;
 739         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 740
 741         fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 742         fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 743
 744         ctrl->oob_poi = chip->oob_poi;
 745 }
 746
 747 static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
 748 {
 749         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 750         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 751         struct nand_chip *chip = &priv->chip;
 752
 753         dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
 754
 755         /* Fill in fsl_elbc_mtd structure */
 756         priv->mtd.priv = chip;
 757         priv->mtd.owner = THIS_MODULE;
 758         priv->fmr = 0; /* rest filled in later */
 759
 760         /* fill in nand_chip structure */
 761         /* set up function call table */
 762         chip->read_byte = fsl_elbc_read_byte;
 763         chip->write_buf = fsl_elbc_write_buf;
 764         chip->read_buf = fsl_elbc_read_buf;
 765         chip->verify_buf = fsl_elbc_verify_buf;
 766         chip->select_chip = fsl_elbc_select_chip;
 767         chip->cmdfunc = fsl_elbc_cmdfunc;
 768         chip->waitfunc = fsl_elbc_wait;
 769
 770         /* set up nand options */
 771         chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR;
 772
 773         chip->controller = &ctrl->controller;
 774         chip->priv = priv;
 775
 776         chip->ecc.read_page = fsl_elbc_read_page;
 777         chip->ecc.write_page = fsl_elbc_write_page;
 778
 779         /* If CS Base Register selects full hardware ECC then use it */
 780         if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
 781             BR_DECC_CHK_GEN) {
 782                 chip->ecc.mode = NAND_ECC_HW;
 783                 /* put in small page settings and adjust later if needed */
 784                 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
 785                                 &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
 786                 chip->ecc.size = 512;
 787                 chip->ecc.bytes = 3;
 788         } else {
 789                 /* otherwise fall back to default software ECC */
 790                 chip->ecc.mode = NAND_ECC_SOFT;
 791         }
 792
 793         return 0;
 794 }
 795
 796 static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
 797 {
 798         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 799
 800         nand_release(&priv->mtd);
 801
 802         kfree(priv->mtd.name);
 803
 804         if (priv->vbase)
 805                 iounmap(priv->vbase);
 806
 807         ctrl->chips[priv->bank] = NULL;
 808         kfree(priv);
 809
 810         return 0;
 811 }
 812
 813 static int fsl_elbc_chip_probe(struct fsl_elbc_ctrl *ctrl,
 814                                struct device_node *node)
 815 {
 816         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 817         struct fsl_elbc_mtd *priv;
 818         struct resource res;
 819 #ifdef CONFIG_MTD_PARTITIONS
 820         static const char *part_probe_types[]
 821                 = { "cmdlinepart", "RedBoot", NULL };
 822         struct mtd_partition *parts;
 823 #endif
 824         int ret;
 825         int bank;
 826
 827         /* get, allocate and map the memory resource */
 828         ret = of_address_to_resource(node, 0, &res);
 829         if (ret) {
 830                 dev_err(ctrl->dev, "failed to get resource\n");
 831                 return ret;
 832         }
 833
 834         /* find which chip select it is connected to */
 835         for (bank = 0; bank < MAX_BANKS; bank++)
 836                 if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
 837                     (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
 838                     (in_be32(&lbc->bank[bank].br) &
 839                      in_be32(&lbc->bank[bank].or) & BR_BA)
 840                      == res.start)
 841                         break;
 842
 843         if (bank >= MAX_BANKS) {
 844                 dev_err(ctrl->dev, "address did not match any chip selects\n");
 845                 return -ENODEV;
 846         }
 847
 848         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 849         if (!priv)
 850                 return -ENOMEM;
 851
 852         ctrl->chips[bank] = priv;
 853         priv->bank = bank;
 854         priv->ctrl = ctrl;
 855         priv->dev = ctrl->dev;
 856
 857         priv->vbase = ioremap(res.start, res.end - res.start + 1);
 858         if (!priv->vbase) {
 859                 dev_err(ctrl->dev, "failed to map chip region\n");
 860                 ret = -ENOMEM;
 861                 goto err;
 862         }
 863
 864         priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", res.start);
 865         if (!priv->mtd.name) {
 866                 ret = -ENOMEM;
 867                 goto err;
 868         }
 869
 870         ret = fsl_elbc_chip_init(priv);
 871         if (ret)
 872                 goto err;
 873
 874         ret = nand_scan_ident(&priv->mtd, 1);
 875         if (ret)
 876                 goto err;
 877
 878         ret = fsl_elbc_chip_init_tail(&priv->mtd);
 879         if (ret)
 880                 goto err;
 881
 882         ret = nand_scan_tail(&priv->mtd);
 883         if (ret)
 884                 goto err;
 885
 886 #ifdef CONFIG_MTD_PARTITIONS
 887         /* First look for RedBoot table or partitions on the command
 888          * line, these take precedence over device tree information */
 889         ret = parse_mtd_partitions(&priv->mtd, part_probe_types, &parts, 0);
 890         if (ret < 0)
 891                 goto err;
 892
 893 #ifdef CONFIG_MTD_OF_PARTS
 894         if (ret == 0) {
 895                 ret = of_mtd_parse_partitions(priv->dev, &priv->mtd,
 896                                               node, &parts);
 897                 if (ret < 0)
 898                         goto err;
 899         }
 900 #endif
 901
 902         if (ret > 0)
 903                 add_mtd_partitions(&priv->mtd, parts, ret);
 904         else
 905 #endif
 906                 add_mtd_device(&priv->mtd);
 907
 908         printk(KERN_INFO "eLBC NAND device at 0x%zx, bank %d\n",
 909                res.start, priv->bank);
 910         return 0;
 911
 912 err:
 913         fsl_elbc_chip_remove(priv);
 914         return ret;
 915 }
 916
 917 static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl)
 918 {
 919         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 920
 921         /* clear event registers */
 922         setbits32(&lbc->ltesr, LTESR_NAND_MASK);
 923         out_be32(&lbc->lteatr, 0);
 924
 925         /* Enable interrupts for any detected events */
 926         out_be32(&lbc->lteir, LTESR_NAND_MASK);
 927
 928         ctrl->read_bytes = 0;
 929         ctrl->index = 0;
 930         ctrl->addr = NULL;
 931
 932         return 0;
 933 }
 934
 935 static int fsl_elbc_ctrl_remove(struct of_device *ofdev)
 936 {
 937         struct fsl_elbc_ctrl *ctrl = dev_get_drvdata(&ofdev->dev);
 938         int i;
 939
 940         for (i = 0; i < MAX_BANKS; i++)
 941                 if (ctrl->chips[i])
 942                         fsl_elbc_chip_remove(ctrl->chips[i]);
 943
 944         if (ctrl->irq)
 945                 free_irq(ctrl->irq, ctrl);
 946
 947         if (ctrl->regs)
 948                 iounmap(ctrl->regs);
 949
 950         dev_set_drvdata(&ofdev->dev, NULL);
 951         kfree(ctrl);
 952         return 0;
 953 }
 954
 955 /* NOTE: This interrupt is also used to report other localbus events,
 956  * such as transaction errors on other chipselects.  If we want to
 957  * capture those, we'll need to move the IRQ code into a shared
 958  * LBC driver.
 959  */
 960
 961 static irqreturn_t fsl_elbc_ctrl_irq(int irqno, void *data)
 962 {
 963         struct fsl_elbc_ctrl *ctrl = data;
 964         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 965         __be32 status = in_be32(&lbc->ltesr) & LTESR_NAND_MASK;
 966
 967         if (status) {
 968                 out_be32(&lbc->ltesr, status);
 969                 out_be32(&lbc->lteatr, 0);
 970
 971                 ctrl->irq_status = status;
 972                 smp_wmb();
 973                 wake_up(&ctrl->irq_wait);
 974
 975                 return IRQ_HANDLED;
 976         }
 977
 978         return IRQ_NONE;
 979 }
 980
 981 /* fsl_elbc_ctrl_probe
 982  *
 983  * called by device layer when it finds a device matching
 984  * one our driver can handled. This code allocates all of
 985  * the resources needed for the controller only.  The
 986  * resources for the NAND banks themselves are allocated
 987  * in the chip probe function.
 988 */
 989
 990 static int __devinit fsl_elbc_ctrl_probe(struct of_device *ofdev,
 991                                          const struct of_device_id *match)
 992 {
 993         struct device_node *child;
 994         struct fsl_elbc_ctrl *ctrl;
 995         int ret;
 996
 997         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
 998         if (!ctrl)
 999                 return -ENOMEM;
1000
1001         dev_set_drvdata(&ofdev->dev, ctrl);
1002
1003         spin_lock_init(&ctrl->controller.lock);
1004         init_waitqueue_head(&ctrl->controller.wq);
1005         init_waitqueue_head(&ctrl->irq_wait);
1006
1007         ctrl->regs = of_iomap(ofdev->node, 0);
1008         if (!ctrl->regs) {
1009                 dev_err(&ofdev->dev, "failed to get memory region\n");
1010                 ret = -ENODEV;
1011                 goto err;
1012         }
1013
1014         ctrl->irq = of_irq_to_resource(ofdev->node, 0, NULL);
1015         if (ctrl->irq == NO_IRQ) {
1016                 dev_err(&ofdev->dev, "failed to get irq resource\n");
1017                 ret = -ENODEV;
1018                 goto err;
1019         }
1020
1021         ctrl->dev = &ofdev->dev;
1022
1023         ret = fsl_elbc_ctrl_init(ctrl);
1024         if (ret < 0)
1025                 goto err;
1026
1027         ret = request_irq(ctrl->irq, fsl_elbc_ctrl_irq, 0, "fsl-elbc", ctrl);
1028         if (ret != 0) {
1029                 dev_err(&ofdev->dev, "failed to install irq (%d)\n",
1030                         ctrl->irq);
1031                 ret = ctrl->irq;
1032                 goto err;
1033         }
1034
1035         for_each_child_of_node(ofdev->node, child)
1036                 if (of_device_is_compatible(child, "fsl,elbc-fcm-nand"))
1037                         fsl_elbc_chip_probe(ctrl, child);
1038
1039         return 0;
1040
1041 err:
1042         fsl_elbc_ctrl_remove(ofdev);
1043         return ret;
1044 }
1045
1046 static const struct of_device_id fsl_elbc_match[] = {
1047         {
1048                 .compatible = "fsl,elbc",
1049         },
1050         {}
1051 };
1052
1053 static struct of_platform_driver fsl_elbc_ctrl_driver = {
1054         .driver = {
1055                 .name   = "fsl-elbc",
1056         },
1057         .match_table = fsl_elbc_match,
1058         .probe = fsl_elbc_ctrl_probe,
1059         .remove = fsl_elbc_ctrl_remove,
1060 };
1061
1062 static int __init fsl_elbc_init(void)
1063 {
1064         return of_register_platform_driver(&fsl_elbc_ctrl_driver);
1065 }
1066
1067 static void __exit fsl_elbc_exit(void)
1068 {
1069         of_unregister_platform_driver(&fsl_elbc_ctrl_driver);
1070 }
1071
1072 module_init(fsl_elbc_init);
1073 module_exit(fsl_elbc_exit);
1074
1075 MODULE_LICENSE("GPL");
1076 MODULE_AUTHOR("Freescale");
1077 MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");