2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
9 * 2_by_8 routines added by Simon Munton
11 * 4_by_16 work by Carolyn J. Smith
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/init.h>
29 #include <asm/byteorder.h>
31 #include <linux/errno.h>
32 #include <linux/slab.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/reboot.h>
36 #include <linux/mtd/compatmac.h>
37 #include <linux/mtd/map.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/cfi.h>
40 #include <linux/mtd/xip.h>
42 #define AMD_BOOTLOC_BUG
43 #define FORCE_WORD_WRITE 0
45 #define MAX_WORD_RETRIES 3
47 #define SST49LF004B 0x0060
48 #define SST49LF040B 0x0050
49 #define SST49LF008A 0x005a
50 #define AT49BV6416 0x00d6
52 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
53 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
54 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
55 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
56 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
57 static void cfi_amdstd_sync (struct mtd_info *);
58 static int cfi_amdstd_suspend (struct mtd_info *);
59 static void cfi_amdstd_resume (struct mtd_info *);
60 static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *);
61 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
63 static void cfi_amdstd_destroy(struct mtd_info *);
65 struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
66 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
68 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
69 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
72 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
73 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
75 static struct mtd_chip_driver cfi_amdstd_chipdrv = {
76 .probe = NULL, /* Not usable directly */
77 .destroy = cfi_amdstd_destroy,
78 .name = "cfi_cmdset_0002",
83 /* #define DEBUG_CFI_FEATURES */
86 #ifdef DEBUG_CFI_FEATURES
87 static void cfi_tell_features(struct cfi_pri_amdstd *extp)
89 const char* erase_suspend[3] = {
90 "Not supported", "Read only", "Read/write"
92 const char* top_bottom[6] = {
93 "No WP", "8x8KiB sectors at top & bottom, no WP",
94 "Bottom boot", "Top boot",
95 "Uniform, Bottom WP", "Uniform, Top WP"
98 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
99 printk(" Address sensitive unlock: %s\n",
100 (extp->SiliconRevision & 1) ? "Not required" : "Required");
102 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
103 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
105 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
107 if (extp->BlkProt == 0)
108 printk(" Block protection: Not supported\n");
110 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
113 printk(" Temporary block unprotect: %s\n",
114 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
115 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
116 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
117 printk(" Burst mode: %s\n",
118 extp->BurstMode ? "Supported" : "Not supported");
119 if (extp->PageMode == 0)
120 printk(" Page mode: Not supported\n");
122 printk(" Page mode: %d word page\n", extp->PageMode << 2);
124 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
125 extp->VppMin >> 4, extp->VppMin & 0xf);
126 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
127 extp->VppMax >> 4, extp->VppMax & 0xf);
129 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
130 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
132 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
136 #ifdef AMD_BOOTLOC_BUG
137 /* Wheee. Bring me the head of someone at AMD. */
138 static void fixup_amd_bootblock(struct mtd_info *mtd, void* param)
140 struct map_info *map = mtd->priv;
141 struct cfi_private *cfi = map->fldrv_priv;
142 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
143 __u8 major = extp->MajorVersion;
144 __u8 minor = extp->MinorVersion;
146 if (((major << 8) | minor) < 0x3131) {
147 /* CFI version 1.0 => don't trust bootloc */
149 DEBUG(MTD_DEBUG_LEVEL1,
150 "%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n",
151 map->name, cfi->mfr, cfi->id);
153 /* AFAICS all 29LV400 with a bottom boot block have a device ID
154 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode.
155 * These were badly detected as they have the 0x80 bit set
156 * so treat them as a special case.
158 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) &&
160 /* Macronix added CFI to their 2nd generation
161 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD,
162 * Fujitsu, Spansion, EON, ESI and older Macronix)
165 * Therefore also check the manufacturer.
166 * This reduces the risk of false detection due to
167 * the 8-bit device ID.
169 (cfi->mfr == CFI_MFR_MACRONIX)) {
170 DEBUG(MTD_DEBUG_LEVEL1,
171 "%s: Macronix MX29LV400C with bottom boot block"
172 " detected\n", map->name);
173 extp->TopBottom = 2; /* bottom boot */
175 if (cfi->id & 0x80) {
176 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
177 extp->TopBottom = 3; /* top boot */
179 extp->TopBottom = 2; /* bottom boot */
182 DEBUG(MTD_DEBUG_LEVEL1,
183 "%s: AMD CFI PRI V%c.%c has no boot block field;"
184 " deduced %s from Device ID\n", map->name, major, minor,
185 extp->TopBottom == 2 ? "bottom" : "top");
190 static void fixup_use_write_buffers(struct mtd_info *mtd, void *param)
192 struct map_info *map = mtd->priv;
193 struct cfi_private *cfi = map->fldrv_priv;
194 if (cfi->cfiq->BufWriteTimeoutTyp) {
195 DEBUG(MTD_DEBUG_LEVEL1, "Using buffer write method\n" );
196 mtd->write = cfi_amdstd_write_buffers;
200 /* Atmel chips don't use the same PRI format as AMD chips */
201 static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
203 struct map_info *map = mtd->priv;
204 struct cfi_private *cfi = map->fldrv_priv;
205 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
206 struct cfi_pri_atmel atmel_pri;
208 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
209 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
211 if (atmel_pri.Features & 0x02)
212 extp->EraseSuspend = 2;
214 /* Some chips got it backwards... */
215 if (cfi->id == AT49BV6416) {
216 if (atmel_pri.BottomBoot)
221 if (atmel_pri.BottomBoot)
227 /* burst write mode not supported */
228 cfi->cfiq->BufWriteTimeoutTyp = 0;
229 cfi->cfiq->BufWriteTimeoutMax = 0;
232 static void fixup_use_secsi(struct mtd_info *mtd, void *param)
234 /* Setup for chips with a secsi area */
235 mtd->read_user_prot_reg = cfi_amdstd_secsi_read;
236 mtd->read_fact_prot_reg = cfi_amdstd_secsi_read;
239 static void fixup_use_erase_chip(struct mtd_info *mtd, void *param)
241 struct map_info *map = mtd->priv;
242 struct cfi_private *cfi = map->fldrv_priv;
243 if ((cfi->cfiq->NumEraseRegions == 1) &&
244 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
245 mtd->erase = cfi_amdstd_erase_chip;
251 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
254 static void fixup_use_atmel_lock(struct mtd_info *mtd, void *param)
256 mtd->lock = cfi_atmel_lock;
257 mtd->unlock = cfi_atmel_unlock;
258 mtd->flags |= MTD_POWERUP_LOCK;
261 static void fixup_old_sst_eraseregion(struct mtd_info *mtd)
263 struct map_info *map = mtd->priv;
264 struct cfi_private *cfi = map->fldrv_priv;
267 * These flashes report two seperate eraseblock regions based on the
268 * sector_erase-size and block_erase-size, although they both operate on the
269 * same memory. This is not allowed according to CFI, so we just pick the
272 cfi->cfiq->NumEraseRegions = 1;
275 static void fixup_sst39vf(struct mtd_info *mtd, void *param)
277 struct map_info *map = mtd->priv;
278 struct cfi_private *cfi = map->fldrv_priv;
280 fixup_old_sst_eraseregion(mtd);
282 cfi->addr_unlock1 = 0x5555;
283 cfi->addr_unlock2 = 0x2AAA;
286 static void fixup_sst39vf_rev_b(struct mtd_info *mtd, void *param)
288 struct map_info *map = mtd->priv;
289 struct cfi_private *cfi = map->fldrv_priv;
291 fixup_old_sst_eraseregion(mtd);
293 cfi->addr_unlock1 = 0x555;
294 cfi->addr_unlock2 = 0x2AA;
297 static void fixup_s29gl064n_sectors(struct mtd_info *mtd, void *param)
299 struct map_info *map = mtd->priv;
300 struct cfi_private *cfi = map->fldrv_priv;
302 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) {
303 cfi->cfiq->EraseRegionInfo[0] |= 0x0040;
304 pr_warning("%s: Bad S29GL064N CFI data, adjust from 64 to 128 sectors\n", mtd->name);
308 static void fixup_s29gl032n_sectors(struct mtd_info *mtd, void *param)
310 struct map_info *map = mtd->priv;
311 struct cfi_private *cfi = map->fldrv_priv;
313 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) {
314 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040;
315 pr_warning("%s: Bad S29GL032N CFI data, adjust from 127 to 63 sectors\n", mtd->name);
319 /* Used to fix CFI-Tables of chips without Extended Query Tables */
320 static struct cfi_fixup cfi_nopri_fixup_table[] = {
321 { CFI_MFR_SST, 0x234A, fixup_sst39vf, NULL, }, // SST39VF1602
322 { CFI_MFR_SST, 0x234B, fixup_sst39vf, NULL, }, // SST39VF1601
323 { CFI_MFR_SST, 0x235A, fixup_sst39vf, NULL, }, // SST39VF3202
324 { CFI_MFR_SST, 0x235B, fixup_sst39vf, NULL, }, // SST39VF3201
325 { CFI_MFR_SST, 0x235C, fixup_sst39vf_rev_b, NULL, }, // SST39VF3202B
326 { CFI_MFR_SST, 0x235D, fixup_sst39vf_rev_b, NULL, }, // SST39VF3201B
327 { CFI_MFR_SST, 0x236C, fixup_sst39vf_rev_b, NULL, }, // SST39VF6402B
328 { CFI_MFR_SST, 0x236D, fixup_sst39vf_rev_b, NULL, }, // SST39VF6401B
332 static struct cfi_fixup cfi_fixup_table[] = {
333 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
334 #ifdef AMD_BOOTLOC_BUG
335 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock, NULL },
336 { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock, NULL },
338 { CFI_MFR_AMD, 0x0050, fixup_use_secsi, NULL, },
339 { CFI_MFR_AMD, 0x0053, fixup_use_secsi, NULL, },
340 { CFI_MFR_AMD, 0x0055, fixup_use_secsi, NULL, },
341 { CFI_MFR_AMD, 0x0056, fixup_use_secsi, NULL, },
342 { CFI_MFR_AMD, 0x005C, fixup_use_secsi, NULL, },
343 { CFI_MFR_AMD, 0x005F, fixup_use_secsi, NULL, },
344 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors, NULL, },
345 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors, NULL, },
346 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors, NULL, },
347 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors, NULL, },
348 #if !FORCE_WORD_WRITE
349 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers, NULL, },
353 static struct cfi_fixup jedec_fixup_table[] = {
354 { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock, NULL, },
355 { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock, NULL, },
356 { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock, NULL, },
360 static struct cfi_fixup fixup_table[] = {
361 /* The CFI vendor ids and the JEDEC vendor IDs appear
362 * to be common. It is like the devices id's are as
363 * well. This table is to pick all cases where
364 * we know that is the case.
366 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip, NULL },
367 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock, NULL },
372 static void cfi_fixup_major_minor(struct cfi_private *cfi,
373 struct cfi_pri_amdstd *extp)
375 if (cfi->mfr == CFI_MFR_SAMSUNG && cfi->id == 0x257e &&
376 extp->MajorVersion == '0')
377 extp->MajorVersion = '1';
380 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
382 struct cfi_private *cfi = map->fldrv_priv;
383 struct mtd_info *mtd;
386 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL);
388 printk(KERN_WARNING "Failed to allocate memory for MTD device\n");
392 mtd->type = MTD_NORFLASH;
394 /* Fill in the default mtd operations */
395 mtd->erase = cfi_amdstd_erase_varsize;
396 mtd->write = cfi_amdstd_write_words;
397 mtd->read = cfi_amdstd_read;
398 mtd->sync = cfi_amdstd_sync;
399 mtd->suspend = cfi_amdstd_suspend;
400 mtd->resume = cfi_amdstd_resume;
401 mtd->flags = MTD_CAP_NORFLASH;
402 mtd->name = map->name;
405 mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot;
407 if (cfi->cfi_mode==CFI_MODE_CFI){
408 unsigned char bootloc;
409 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
410 struct cfi_pri_amdstd *extp;
412 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
415 * It's a real CFI chip, not one for which the probe
416 * routine faked a CFI structure.
418 cfi_fixup_major_minor(cfi, extp);
420 if (extp->MajorVersion != '1' ||
421 (extp->MinorVersion < '0' || extp->MinorVersion > '4')) {
422 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
423 "version %c.%c.\n", extp->MajorVersion,
430 /* Install our own private info structure */
431 cfi->cmdset_priv = extp;
433 /* Apply cfi device specific fixups */
434 cfi_fixup(mtd, cfi_fixup_table);
436 #ifdef DEBUG_CFI_FEATURES
437 /* Tell the user about it in lots of lovely detail */
438 cfi_tell_features(extp);
441 bootloc = extp->TopBottom;
442 if ((bootloc < 2) || (bootloc > 5)) {
443 printk(KERN_WARNING "%s: CFI contains unrecognised boot "
444 "bank location (%d). Assuming bottom.\n",
449 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
450 printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name);
452 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
453 int j = (cfi->cfiq->NumEraseRegions-1)-i;
456 swap = cfi->cfiq->EraseRegionInfo[i];
457 cfi->cfiq->EraseRegionInfo[i] = cfi->cfiq->EraseRegionInfo[j];
458 cfi->cfiq->EraseRegionInfo[j] = swap;
461 /* Set the default CFI lock/unlock addresses */
462 cfi->addr_unlock1 = 0x555;
463 cfi->addr_unlock2 = 0x2aa;
465 cfi_fixup(mtd, cfi_nopri_fixup_table);
467 if (!cfi->addr_unlock1 || !cfi->addr_unlock2) {
473 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
474 /* Apply jedec specific fixups */
475 cfi_fixup(mtd, jedec_fixup_table);
477 /* Apply generic fixups */
478 cfi_fixup(mtd, fixup_table);
480 for (i=0; i< cfi->numchips; i++) {
481 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
482 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
483 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
484 cfi->chips[i].ref_point_counter = 0;
485 init_waitqueue_head(&(cfi->chips[i].wq));
488 map->fldrv = &cfi_amdstd_chipdrv;
490 return cfi_amdstd_setup(mtd);
492 struct mtd_info *cfi_cmdset_0701(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
493 EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
494 EXPORT_SYMBOL_GPL(cfi_cmdset_0701);
496 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
498 struct map_info *map = mtd->priv;
499 struct cfi_private *cfi = map->fldrv_priv;
500 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
501 unsigned long offset = 0;
504 printk(KERN_NOTICE "number of %s chips: %d\n",
505 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
506 /* Select the correct geometry setup */
507 mtd->size = devsize * cfi->numchips;
509 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
510 mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info)
511 * mtd->numeraseregions, GFP_KERNEL);
512 if (!mtd->eraseregions) {
513 printk(KERN_WARNING "Failed to allocate memory for MTD erase region info\n");
517 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
518 unsigned long ernum, ersize;
519 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
520 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
522 if (mtd->erasesize < ersize) {
523 mtd->erasesize = ersize;
525 for (j=0; j<cfi->numchips; j++) {
526 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
527 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
528 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
530 offset += (ersize * ernum);
532 if (offset != devsize) {
534 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
539 for (i=0; i<mtd->numeraseregions;i++){
540 printk("%d: offset=0x%x,size=0x%x,blocks=%d\n",
541 i,mtd->eraseregions[i].offset,
542 mtd->eraseregions[i].erasesize,
543 mtd->eraseregions[i].numblocks);
547 __module_get(THIS_MODULE);
548 register_reboot_notifier(&mtd->reboot_notifier);
552 kfree(mtd->eraseregions);
554 kfree(cfi->cmdset_priv);
560 * Return true if the chip is ready.
562 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
563 * non-suspended sector) and is indicated by no toggle bits toggling.
565 * Note that anything more complicated than checking if no bits are toggling
566 * (including checking DQ5 for an error status) is tricky to get working
567 * correctly and is therefore not done (particulary with interleaved chips
568 * as each chip must be checked independantly of the others).
570 static int __xipram chip_ready(struct map_info *map, unsigned long addr)
574 d = map_read(map, addr);
575 t = map_read(map, addr);
577 return map_word_equal(map, d, t);
581 * Return true if the chip is ready and has the correct value.
583 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
584 * non-suspended sector) and it is indicated by no bits toggling.
586 * Error are indicated by toggling bits or bits held with the wrong value,
587 * or with bits toggling.
589 * Note that anything more complicated than checking if no bits are toggling
590 * (including checking DQ5 for an error status) is tricky to get working
591 * correctly and is therefore not done (particulary with interleaved chips
592 * as each chip must be checked independantly of the others).
595 static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected)
599 oldd = map_read(map, addr);
600 curd = map_read(map, addr);
602 return map_word_equal(map, oldd, curd) &&
603 map_word_equal(map, curd, expected);
606 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
608 DECLARE_WAITQUEUE(wait, current);
609 struct cfi_private *cfi = map->fldrv_priv;
611 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
614 timeo = jiffies + HZ;
616 switch (chip->state) {
620 if (chip_ready(map, adr))
623 if (time_after(jiffies, timeo)) {
624 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
627 mutex_unlock(&chip->mutex);
629 mutex_lock(&chip->mutex);
630 /* Someone else might have been playing with it. */
640 if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||
641 !(mode == FL_READY || mode == FL_POINT ||
642 (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))
645 /* We could check to see if we're trying to access the sector
646 * that is currently being erased. However, no user will try
647 * anything like that so we just wait for the timeout. */
650 /* It's harmless to issue the Erase-Suspend and Erase-Resume
651 * commands when the erase algorithm isn't in progress. */
652 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
653 chip->oldstate = FL_ERASING;
654 chip->state = FL_ERASE_SUSPENDING;
655 chip->erase_suspended = 1;
657 if (chip_ready(map, adr))
660 if (time_after(jiffies, timeo)) {
661 /* Should have suspended the erase by now.
662 * Send an Erase-Resume command as either
663 * there was an error (so leave the erase
664 * routine to recover from it) or we trying to
665 * use the erase-in-progress sector. */
666 map_write(map, CMD(0x30), chip->in_progress_block_addr);
667 chip->state = FL_ERASING;
668 chip->oldstate = FL_READY;
669 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
673 mutex_unlock(&chip->mutex);
675 mutex_lock(&chip->mutex);
676 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
677 So we can just loop here. */
679 chip->state = FL_READY;
682 case FL_XIP_WHILE_ERASING:
683 if (mode != FL_READY && mode != FL_POINT &&
684 (!cfip || !(cfip->EraseSuspend&2)))
686 chip->oldstate = chip->state;
687 chip->state = FL_READY;
691 /* The machine is rebooting */
695 /* Only if there's no operation suspended... */
696 if (mode == FL_READY && chip->oldstate == FL_READY)
701 set_current_state(TASK_UNINTERRUPTIBLE);
702 add_wait_queue(&chip->wq, &wait);
703 mutex_unlock(&chip->mutex);
705 remove_wait_queue(&chip->wq, &wait);
706 mutex_lock(&chip->mutex);
712 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
714 struct cfi_private *cfi = map->fldrv_priv;
716 switch(chip->oldstate) {
718 chip->state = chip->oldstate;
719 map_write(map, CMD(0x30), chip->in_progress_block_addr);
720 chip->oldstate = FL_READY;
721 chip->state = FL_ERASING;
724 case FL_XIP_WHILE_ERASING:
725 chip->state = chip->oldstate;
726 chip->oldstate = FL_READY;
731 /* We should really make set_vpp() count, rather than doing this */
735 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
740 #ifdef CONFIG_MTD_XIP
743 * No interrupt what so ever can be serviced while the flash isn't in array
744 * mode. This is ensured by the xip_disable() and xip_enable() functions
745 * enclosing any code path where the flash is known not to be in array mode.
746 * And within a XIP disabled code path, only functions marked with __xipram
747 * may be called and nothing else (it's a good thing to inspect generated
748 * assembly to make sure inline functions were actually inlined and that gcc
749 * didn't emit calls to its own support functions). Also configuring MTD CFI
750 * support to a single buswidth and a single interleave is also recommended.
753 static void xip_disable(struct map_info *map, struct flchip *chip,
756 /* TODO: chips with no XIP use should ignore and return */
757 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
761 static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
764 struct cfi_private *cfi = map->fldrv_priv;
766 if (chip->state != FL_POINT && chip->state != FL_READY) {
767 map_write(map, CMD(0xf0), adr);
768 chip->state = FL_READY;
770 (void) map_read(map, adr);
776 * When a delay is required for the flash operation to complete, the
777 * xip_udelay() function is polling for both the given timeout and pending
778 * (but still masked) hardware interrupts. Whenever there is an interrupt
779 * pending then the flash erase operation is suspended, array mode restored
780 * and interrupts unmasked. Task scheduling might also happen at that
781 * point. The CPU eventually returns from the interrupt or the call to
782 * schedule() and the suspended flash operation is resumed for the remaining
783 * of the delay period.
785 * Warning: this function _will_ fool interrupt latency tracing tools.
788 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
789 unsigned long adr, int usec)
791 struct cfi_private *cfi = map->fldrv_priv;
792 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
793 map_word status, OK = CMD(0x80);
794 unsigned long suspended, start = xip_currtime();
799 if (xip_irqpending() && extp &&
800 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
801 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
803 * Let's suspend the erase operation when supported.
804 * Note that we currently don't try to suspend
805 * interleaved chips if there is already another
806 * operation suspended (imagine what happens
807 * when one chip was already done with the current
808 * operation while another chip suspended it, then
809 * we resume the whole thing at once). Yes, it
812 map_write(map, CMD(0xb0), adr);
813 usec -= xip_elapsed_since(start);
814 suspended = xip_currtime();
816 if (xip_elapsed_since(suspended) > 100000) {
818 * The chip doesn't want to suspend
819 * after waiting for 100 msecs.
820 * This is a critical error but there
821 * is not much we can do here.
825 status = map_read(map, adr);
826 } while (!map_word_andequal(map, status, OK, OK));
828 /* Suspend succeeded */
829 oldstate = chip->state;
830 if (!map_word_bitsset(map, status, CMD(0x40)))
832 chip->state = FL_XIP_WHILE_ERASING;
833 chip->erase_suspended = 1;
834 map_write(map, CMD(0xf0), adr);
835 (void) map_read(map, adr);
838 mutex_unlock(&chip->mutex);
843 * We're back. However someone else might have
844 * decided to go write to the chip if we are in
845 * a suspended erase state. If so let's wait
848 mutex_lock(&chip->mutex);
849 while (chip->state != FL_XIP_WHILE_ERASING) {
850 DECLARE_WAITQUEUE(wait, current);
851 set_current_state(TASK_UNINTERRUPTIBLE);
852 add_wait_queue(&chip->wq, &wait);
853 mutex_unlock(&chip->mutex);
855 remove_wait_queue(&chip->wq, &wait);
856 mutex_lock(&chip->mutex);
858 /* Disallow XIP again */
861 /* Resume the write or erase operation */
862 map_write(map, CMD(0x30), adr);
863 chip->state = oldstate;
864 start = xip_currtime();
865 } else if (usec >= 1000000/HZ) {
867 * Try to save on CPU power when waiting delay
868 * is at least a system timer tick period.
869 * No need to be extremely accurate here.
873 status = map_read(map, adr);
874 } while (!map_word_andequal(map, status, OK, OK)
875 && xip_elapsed_since(start) < usec);
878 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
881 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
882 * the flash is actively programming or erasing since we have to poll for
883 * the operation to complete anyway. We can't do that in a generic way with
884 * a XIP setup so do it before the actual flash operation in this case
885 * and stub it out from INVALIDATE_CACHE_UDELAY.
887 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
888 INVALIDATE_CACHED_RANGE(map, from, size)
890 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
891 UDELAY(map, chip, adr, usec)
896 * Activating this XIP support changes the way the code works a bit. For
897 * example the code to suspend the current process when concurrent access
898 * happens is never executed because xip_udelay() will always return with the
899 * same chip state as it was entered with. This is why there is no care for
900 * the presence of add_wait_queue() or schedule() calls from within a couple
901 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
902 * The queueing and scheduling are always happening within xip_udelay().
904 * Similarly, get_chip() and put_chip() just happen to always be executed
905 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
906 * is in array mode, therefore never executing many cases therein and not
907 * causing any problem with XIP.
912 #define xip_disable(map, chip, adr)
913 #define xip_enable(map, chip, adr)
914 #define XIP_INVAL_CACHED_RANGE(x...)
916 #define UDELAY(map, chip, adr, usec) \
918 mutex_unlock(&chip->mutex); \
920 mutex_lock(&chip->mutex); \
923 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
925 mutex_unlock(&chip->mutex); \
926 INVALIDATE_CACHED_RANGE(map, adr, len); \
928 mutex_lock(&chip->mutex); \
933 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
935 unsigned long cmd_addr;
936 struct cfi_private *cfi = map->fldrv_priv;
941 /* Ensure cmd read/writes are aligned. */
942 cmd_addr = adr & ~(map_bankwidth(map)-1);
944 mutex_lock(&chip->mutex);
945 ret = get_chip(map, chip, cmd_addr, FL_READY);
947 mutex_unlock(&chip->mutex);
951 if (chip->state != FL_POINT && chip->state != FL_READY) {
952 map_write(map, CMD(0xf0), cmd_addr);
953 chip->state = FL_READY;
956 map_copy_from(map, buf, adr, len);
958 put_chip(map, chip, cmd_addr);
960 mutex_unlock(&chip->mutex);
965 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
967 struct map_info *map = mtd->priv;
968 struct cfi_private *cfi = map->fldrv_priv;
973 /* ofs: offset within the first chip that the first read should start */
975 chipnum = (from >> cfi->chipshift);
976 ofs = from - (chipnum << cfi->chipshift);
982 unsigned long thislen;
984 if (chipnum >= cfi->numchips)
987 if ((len + ofs -1) >> cfi->chipshift)
988 thislen = (1<<cfi->chipshift) - ofs;
992 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1007 static inline int do_read_secsi_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
1009 DECLARE_WAITQUEUE(wait, current);
1010 unsigned long timeo = jiffies + HZ;
1011 struct cfi_private *cfi = map->fldrv_priv;
1014 mutex_lock(&chip->mutex);
1016 if (chip->state != FL_READY){
1018 printk(KERN_DEBUG "Waiting for chip to read, status = %d\n", chip->state);
1020 set_current_state(TASK_UNINTERRUPTIBLE);
1021 add_wait_queue(&chip->wq, &wait);
1023 mutex_unlock(&chip->mutex);
1026 remove_wait_queue(&chip->wq, &wait);
1028 if(signal_pending(current))
1031 timeo = jiffies + HZ;
1038 chip->state = FL_READY;
1040 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1041 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1042 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1044 map_copy_from(map, buf, adr, len);
1046 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1047 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1048 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1049 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1052 mutex_unlock(&chip->mutex);
1057 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1059 struct map_info *map = mtd->priv;
1060 struct cfi_private *cfi = map->fldrv_priv;
1066 /* ofs: offset within the first chip that the first read should start */
1068 /* 8 secsi bytes per chip */
1076 unsigned long thislen;
1078 if (chipnum >= cfi->numchips)
1081 if ((len + ofs -1) >> 3)
1082 thislen = (1<<3) - ofs;
1086 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1101 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, unsigned long adr, map_word datum)
1103 struct cfi_private *cfi = map->fldrv_priv;
1104 unsigned long timeo = jiffies + HZ;
1106 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
1107 * have a max write time of a few hundreds usec). However, we should
1108 * use the maximum timeout value given by the chip at probe time
1109 * instead. Unfortunately, struct flchip does have a field for
1110 * maximum timeout, only for typical which can be far too short
1111 * depending of the conditions. The ' + 1' is to avoid having a
1112 * timeout of 0 jiffies if HZ is smaller than 1000.
1114 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1121 mutex_lock(&chip->mutex);
1122 ret = get_chip(map, chip, adr, FL_WRITING);
1124 mutex_unlock(&chip->mutex);
1128 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1129 __func__, adr, datum.x[0] );
1132 * Check for a NOP for the case when the datum to write is already
1133 * present - it saves time and works around buggy chips that corrupt
1134 * data at other locations when 0xff is written to a location that
1135 * already contains 0xff.
1137 oldd = map_read(map, adr);
1138 if (map_word_equal(map, oldd, datum)) {
1139 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): NOP\n",
1144 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1146 xip_disable(map, chip, adr);
1148 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1149 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1150 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1151 map_write(map, datum, adr);
1152 chip->state = FL_WRITING;
1154 INVALIDATE_CACHE_UDELAY(map, chip,
1155 adr, map_bankwidth(map),
1156 chip->word_write_time);
1158 /* See comment above for timeout value. */
1159 timeo = jiffies + uWriteTimeout;
1161 if (chip->state != FL_WRITING) {
1162 /* Someone's suspended the write. Sleep */
1163 DECLARE_WAITQUEUE(wait, current);
1165 set_current_state(TASK_UNINTERRUPTIBLE);
1166 add_wait_queue(&chip->wq, &wait);
1167 mutex_unlock(&chip->mutex);
1169 remove_wait_queue(&chip->wq, &wait);
1170 timeo = jiffies + (HZ / 2); /* FIXME */
1171 mutex_lock(&chip->mutex);
1175 if (time_after(jiffies, timeo) && !chip_ready(map, adr)){
1176 xip_enable(map, chip, adr);
1177 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1178 xip_disable(map, chip, adr);
1182 if (chip_ready(map, adr))
1185 /* Latency issues. Drop the lock, wait a while and retry */
1186 UDELAY(map, chip, adr, 1);
1188 /* Did we succeed? */
1189 if (!chip_good(map, adr, datum)) {
1190 /* reset on all failures. */
1191 map_write( map, CMD(0xF0), chip->start );
1192 /* FIXME - should have reset delay before continuing */
1194 if (++retry_cnt <= MAX_WORD_RETRIES)
1199 xip_enable(map, chip, adr);
1201 chip->state = FL_READY;
1202 put_chip(map, chip, adr);
1203 mutex_unlock(&chip->mutex);
1209 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1210 size_t *retlen, const u_char *buf)
1212 struct map_info *map = mtd->priv;
1213 struct cfi_private *cfi = map->fldrv_priv;
1216 unsigned long ofs, chipstart;
1217 DECLARE_WAITQUEUE(wait, current);
1223 chipnum = to >> cfi->chipshift;
1224 ofs = to - (chipnum << cfi->chipshift);
1225 chipstart = cfi->chips[chipnum].start;
1227 /* If it's not bus-aligned, do the first byte write */
1228 if (ofs & (map_bankwidth(map)-1)) {
1229 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1230 int i = ofs - bus_ofs;
1235 mutex_lock(&cfi->chips[chipnum].mutex);
1237 if (cfi->chips[chipnum].state != FL_READY) {
1239 printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state);
1241 set_current_state(TASK_UNINTERRUPTIBLE);
1242 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1244 mutex_unlock(&cfi->chips[chipnum].mutex);
1247 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1249 if(signal_pending(current))
1255 /* Load 'tmp_buf' with old contents of flash */
1256 tmp_buf = map_read(map, bus_ofs+chipstart);
1258 mutex_unlock(&cfi->chips[chipnum].mutex);
1260 /* Number of bytes to copy from buffer */
1261 n = min_t(int, len, map_bankwidth(map)-i);
1263 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1265 ret = do_write_oneword(map, &cfi->chips[chipnum],
1275 if (ofs >> cfi->chipshift) {
1278 if (chipnum == cfi->numchips)
1283 /* We are now aligned, write as much as possible */
1284 while(len >= map_bankwidth(map)) {
1287 datum = map_word_load(map, buf);
1289 ret = do_write_oneword(map, &cfi->chips[chipnum],
1294 ofs += map_bankwidth(map);
1295 buf += map_bankwidth(map);
1296 (*retlen) += map_bankwidth(map);
1297 len -= map_bankwidth(map);
1299 if (ofs >> cfi->chipshift) {
1302 if (chipnum == cfi->numchips)
1304 chipstart = cfi->chips[chipnum].start;
1308 /* Write the trailing bytes if any */
1309 if (len & (map_bankwidth(map)-1)) {
1313 mutex_lock(&cfi->chips[chipnum].mutex);
1315 if (cfi->chips[chipnum].state != FL_READY) {
1317 printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state);
1319 set_current_state(TASK_UNINTERRUPTIBLE);
1320 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1322 mutex_unlock(&cfi->chips[chipnum].mutex);
1325 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1327 if(signal_pending(current))
1333 tmp_buf = map_read(map, ofs + chipstart);
1335 mutex_unlock(&cfi->chips[chipnum].mutex);
1337 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1339 ret = do_write_oneword(map, &cfi->chips[chipnum],
1352 * FIXME: interleaved mode not tested, and probably not supported!
1354 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
1355 unsigned long adr, const u_char *buf,
1358 struct cfi_private *cfi = map->fldrv_priv;
1359 unsigned long timeo = jiffies + HZ;
1360 /* see comments in do_write_oneword() regarding uWriteTimeo. */
1361 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1363 unsigned long cmd_adr;
1370 mutex_lock(&chip->mutex);
1371 ret = get_chip(map, chip, adr, FL_WRITING);
1373 mutex_unlock(&chip->mutex);
1377 datum = map_word_load(map, buf);
1379 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1380 __func__, adr, datum.x[0] );
1382 XIP_INVAL_CACHED_RANGE(map, adr, len);
1384 xip_disable(map, chip, cmd_adr);
1386 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1387 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1388 //cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1390 /* Write Buffer Load */
1391 map_write(map, CMD(0x25), cmd_adr);
1393 chip->state = FL_WRITING_TO_BUFFER;
1395 /* Write length of data to come */
1396 words = len / map_bankwidth(map);
1397 map_write(map, CMD(words - 1), cmd_adr);
1400 while(z < words * map_bankwidth(map)) {
1401 datum = map_word_load(map, buf);
1402 map_write(map, datum, adr + z);
1404 z += map_bankwidth(map);
1405 buf += map_bankwidth(map);
1407 z -= map_bankwidth(map);
1411 /* Write Buffer Program Confirm: GO GO GO */
1412 map_write(map, CMD(0x29), cmd_adr);
1413 chip->state = FL_WRITING;
1415 INVALIDATE_CACHE_UDELAY(map, chip,
1416 adr, map_bankwidth(map),
1417 chip->word_write_time);
1419 timeo = jiffies + uWriteTimeout;
1422 if (chip->state != FL_WRITING) {
1423 /* Someone's suspended the write. Sleep */
1424 DECLARE_WAITQUEUE(wait, current);
1426 set_current_state(TASK_UNINTERRUPTIBLE);
1427 add_wait_queue(&chip->wq, &wait);
1428 mutex_unlock(&chip->mutex);
1430 remove_wait_queue(&chip->wq, &wait);
1431 timeo = jiffies + (HZ / 2); /* FIXME */
1432 mutex_lock(&chip->mutex);
1436 if (time_after(jiffies, timeo) && !chip_ready(map, adr))
1439 if (chip_ready(map, adr)) {
1440 xip_enable(map, chip, adr);
1444 /* Latency issues. Drop the lock, wait a while and retry */
1445 UDELAY(map, chip, adr, 1);
1448 /* reset on all failures. */
1449 map_write( map, CMD(0xF0), chip->start );
1450 xip_enable(map, chip, adr);
1451 /* FIXME - should have reset delay before continuing */
1453 printk(KERN_WARNING "MTD %s(): software timeout\n",
1458 chip->state = FL_READY;
1459 put_chip(map, chip, adr);
1460 mutex_unlock(&chip->mutex);
1466 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
1467 size_t *retlen, const u_char *buf)
1469 struct map_info *map = mtd->priv;
1470 struct cfi_private *cfi = map->fldrv_priv;
1471 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
1480 chipnum = to >> cfi->chipshift;
1481 ofs = to - (chipnum << cfi->chipshift);
1483 /* If it's not bus-aligned, do the first word write */
1484 if (ofs & (map_bankwidth(map)-1)) {
1485 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
1486 if (local_len > len)
1488 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1489 local_len, retlen, buf);
1496 if (ofs >> cfi->chipshift) {
1499 if (chipnum == cfi->numchips)
1504 /* Write buffer is worth it only if more than one word to write... */
1505 while (len >= map_bankwidth(map) * 2) {
1506 /* We must not cross write block boundaries */
1507 int size = wbufsize - (ofs & (wbufsize-1));
1511 if (size % map_bankwidth(map))
1512 size -= size % map_bankwidth(map);
1514 ret = do_write_buffer(map, &cfi->chips[chipnum],
1524 if (ofs >> cfi->chipshift) {
1527 if (chipnum == cfi->numchips)
1533 size_t retlen_dregs = 0;
1535 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1536 len, &retlen_dregs, buf);
1538 *retlen += retlen_dregs;
1547 * Handle devices with one erase region, that only implement
1548 * the chip erase command.
1550 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
1552 struct cfi_private *cfi = map->fldrv_priv;
1553 unsigned long timeo = jiffies + HZ;
1554 unsigned long int adr;
1555 DECLARE_WAITQUEUE(wait, current);
1558 adr = cfi->addr_unlock1;
1560 mutex_lock(&chip->mutex);
1561 ret = get_chip(map, chip, adr, FL_WRITING);
1563 mutex_unlock(&chip->mutex);
1567 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1568 __func__, chip->start );
1570 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
1572 xip_disable(map, chip, adr);
1574 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1575 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1576 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1577 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1578 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1579 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1581 chip->state = FL_ERASING;
1582 chip->erase_suspended = 0;
1583 chip->in_progress_block_addr = adr;
1585 INVALIDATE_CACHE_UDELAY(map, chip,
1587 chip->erase_time*500);
1589 timeo = jiffies + (HZ*20);
1592 if (chip->state != FL_ERASING) {
1593 /* Someone's suspended the erase. Sleep */
1594 set_current_state(TASK_UNINTERRUPTIBLE);
1595 add_wait_queue(&chip->wq, &wait);
1596 mutex_unlock(&chip->mutex);
1598 remove_wait_queue(&chip->wq, &wait);
1599 mutex_lock(&chip->mutex);
1602 if (chip->erase_suspended) {
1603 /* This erase was suspended and resumed.
1604 Adjust the timeout */
1605 timeo = jiffies + (HZ*20); /* FIXME */
1606 chip->erase_suspended = 0;
1609 if (chip_ready(map, adr))
1612 if (time_after(jiffies, timeo)) {
1613 printk(KERN_WARNING "MTD %s(): software timeout\n",
1618 /* Latency issues. Drop the lock, wait a while and retry */
1619 UDELAY(map, chip, adr, 1000000/HZ);
1621 /* Did we succeed? */
1622 if (!chip_good(map, adr, map_word_ff(map))) {
1623 /* reset on all failures. */
1624 map_write( map, CMD(0xF0), chip->start );
1625 /* FIXME - should have reset delay before continuing */
1630 chip->state = FL_READY;
1631 xip_enable(map, chip, adr);
1632 put_chip(map, chip, adr);
1633 mutex_unlock(&chip->mutex);
1639 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
1641 struct cfi_private *cfi = map->fldrv_priv;
1642 unsigned long timeo = jiffies + HZ;
1643 DECLARE_WAITQUEUE(wait, current);
1648 mutex_lock(&chip->mutex);
1649 ret = get_chip(map, chip, adr, FL_ERASING);
1651 mutex_unlock(&chip->mutex);
1655 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1658 XIP_INVAL_CACHED_RANGE(map, adr, len);
1660 xip_disable(map, chip, adr);
1662 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1663 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1664 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1665 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1666 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1667 map_write(map, CMD(0x30), adr);
1669 chip->state = FL_ERASING;
1670 chip->erase_suspended = 0;
1671 chip->in_progress_block_addr = adr;
1673 INVALIDATE_CACHE_UDELAY(map, chip,
1675 chip->erase_time*500);
1677 timeo = jiffies + (HZ*20);
1680 if (chip->state != FL_ERASING) {
1681 /* Someone's suspended the erase. Sleep */
1682 set_current_state(TASK_UNINTERRUPTIBLE);
1683 add_wait_queue(&chip->wq, &wait);
1684 mutex_unlock(&chip->mutex);
1686 remove_wait_queue(&chip->wq, &wait);
1687 mutex_lock(&chip->mutex);
1690 if (chip->erase_suspended) {
1691 /* This erase was suspended and resumed.
1692 Adjust the timeout */
1693 timeo = jiffies + (HZ*20); /* FIXME */
1694 chip->erase_suspended = 0;
1697 if (chip_ready(map, adr)) {
1698 xip_enable(map, chip, adr);
1702 if (time_after(jiffies, timeo)) {
1703 xip_enable(map, chip, adr);
1704 printk(KERN_WARNING "MTD %s(): software timeout\n",
1709 /* Latency issues. Drop the lock, wait a while and retry */
1710 UDELAY(map, chip, adr, 1000000/HZ);
1712 /* Did we succeed? */
1713 if (!chip_good(map, adr, map_word_ff(map))) {
1714 /* reset on all failures. */
1715 map_write( map, CMD(0xF0), chip->start );
1716 /* FIXME - should have reset delay before continuing */
1721 chip->state = FL_READY;
1722 put_chip(map, chip, adr);
1723 mutex_unlock(&chip->mutex);
1728 static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
1730 unsigned long ofs, len;
1736 ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL);
1740 instr->state = MTD_ERASE_DONE;
1741 mtd_erase_callback(instr);
1747 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
1749 struct map_info *map = mtd->priv;
1750 struct cfi_private *cfi = map->fldrv_priv;
1753 if (instr->addr != 0)
1756 if (instr->len != mtd->size)
1759 ret = do_erase_chip(map, &cfi->chips[0]);
1763 instr->state = MTD_ERASE_DONE;
1764 mtd_erase_callback(instr);
1769 static int do_atmel_lock(struct map_info *map, struct flchip *chip,
1770 unsigned long adr, int len, void *thunk)
1772 struct cfi_private *cfi = map->fldrv_priv;
1775 mutex_lock(&chip->mutex);
1776 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
1779 chip->state = FL_LOCKING;
1781 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n",
1782 __func__, adr, len);
1784 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1785 cfi->device_type, NULL);
1786 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1787 cfi->device_type, NULL);
1788 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
1789 cfi->device_type, NULL);
1790 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1791 cfi->device_type, NULL);
1792 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1793 cfi->device_type, NULL);
1794 map_write(map, CMD(0x40), chip->start + adr);
1796 chip->state = FL_READY;
1797 put_chip(map, chip, adr + chip->start);
1801 mutex_unlock(&chip->mutex);
1805 static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
1806 unsigned long adr, int len, void *thunk)
1808 struct cfi_private *cfi = map->fldrv_priv;
1811 mutex_lock(&chip->mutex);
1812 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
1815 chip->state = FL_UNLOCKING;
1817 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n",
1818 __func__, adr, len);
1820 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1821 cfi->device_type, NULL);
1822 map_write(map, CMD(0x70), adr);
1824 chip->state = FL_READY;
1825 put_chip(map, chip, adr + chip->start);
1829 mutex_unlock(&chip->mutex);
1833 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1835 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
1838 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1840 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
1844 static void cfi_amdstd_sync (struct mtd_info *mtd)
1846 struct map_info *map = mtd->priv;
1847 struct cfi_private *cfi = map->fldrv_priv;
1849 struct flchip *chip;
1851 DECLARE_WAITQUEUE(wait, current);
1853 for (i=0; !ret && i<cfi->numchips; i++) {
1854 chip = &cfi->chips[i];
1857 mutex_lock(&chip->mutex);
1859 switch(chip->state) {
1863 case FL_JEDEC_QUERY:
1864 chip->oldstate = chip->state;
1865 chip->state = FL_SYNCING;
1866 /* No need to wake_up() on this state change -
1867 * as the whole point is that nobody can do anything
1868 * with the chip now anyway.
1871 mutex_unlock(&chip->mutex);
1875 /* Not an idle state */
1876 set_current_state(TASK_UNINTERRUPTIBLE);
1877 add_wait_queue(&chip->wq, &wait);
1879 mutex_unlock(&chip->mutex);
1883 remove_wait_queue(&chip->wq, &wait);
1889 /* Unlock the chips again */
1891 for (i--; i >=0; i--) {
1892 chip = &cfi->chips[i];
1894 mutex_lock(&chip->mutex);
1896 if (chip->state == FL_SYNCING) {
1897 chip->state = chip->oldstate;
1900 mutex_unlock(&chip->mutex);
1905 static int cfi_amdstd_suspend(struct mtd_info *mtd)
1907 struct map_info *map = mtd->priv;
1908 struct cfi_private *cfi = map->fldrv_priv;
1910 struct flchip *chip;
1913 for (i=0; !ret && i<cfi->numchips; i++) {
1914 chip = &cfi->chips[i];
1916 mutex_lock(&chip->mutex);
1918 switch(chip->state) {
1922 case FL_JEDEC_QUERY:
1923 chip->oldstate = chip->state;
1924 chip->state = FL_PM_SUSPENDED;
1925 /* No need to wake_up() on this state change -
1926 * as the whole point is that nobody can do anything
1927 * with the chip now anyway.
1929 case FL_PM_SUSPENDED:
1936 mutex_unlock(&chip->mutex);
1939 /* Unlock the chips again */
1942 for (i--; i >=0; i--) {
1943 chip = &cfi->chips[i];
1945 mutex_lock(&chip->mutex);
1947 if (chip->state == FL_PM_SUSPENDED) {
1948 chip->state = chip->oldstate;
1951 mutex_unlock(&chip->mutex);
1959 static void cfi_amdstd_resume(struct mtd_info *mtd)
1961 struct map_info *map = mtd->priv;
1962 struct cfi_private *cfi = map->fldrv_priv;
1964 struct flchip *chip;
1966 for (i=0; i<cfi->numchips; i++) {
1968 chip = &cfi->chips[i];
1970 mutex_lock(&chip->mutex);
1972 if (chip->state == FL_PM_SUSPENDED) {
1973 chip->state = FL_READY;
1974 map_write(map, CMD(0xF0), chip->start);
1978 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
1980 mutex_unlock(&chip->mutex);
1986 * Ensure that the flash device is put back into read array mode before
1987 * unloading the driver or rebooting. On some systems, rebooting while
1988 * the flash is in query/program/erase mode will prevent the CPU from
1989 * fetching the bootloader code, requiring a hard reset or power cycle.
1991 static int cfi_amdstd_reset(struct mtd_info *mtd)
1993 struct map_info *map = mtd->priv;
1994 struct cfi_private *cfi = map->fldrv_priv;
1996 struct flchip *chip;
1998 for (i = 0; i < cfi->numchips; i++) {
2000 chip = &cfi->chips[i];
2002 mutex_lock(&chip->mutex);
2004 ret = get_chip(map, chip, chip->start, FL_SHUTDOWN);
2006 map_write(map, CMD(0xF0), chip->start);
2007 chip->state = FL_SHUTDOWN;
2008 put_chip(map, chip, chip->start);
2011 mutex_unlock(&chip->mutex);
2018 static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val,
2021 struct mtd_info *mtd;
2023 mtd = container_of(nb, struct mtd_info, reboot_notifier);
2024 cfi_amdstd_reset(mtd);
2029 static void cfi_amdstd_destroy(struct mtd_info *mtd)
2031 struct map_info *map = mtd->priv;
2032 struct cfi_private *cfi = map->fldrv_priv;
2034 cfi_amdstd_reset(mtd);
2035 unregister_reboot_notifier(&mtd->reboot_notifier);
2036 kfree(cfi->cmdset_priv);
2039 kfree(mtd->eraseregions);
2042 MODULE_LICENSE("GPL");
2043 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
2044 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");
2045 MODULE_ALIAS("cfi_cmdset_0701");