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   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/highmem.h>
  14 #include <linux/pci.h>
  15 #include <linux/dma-mapping.h>
  16
  17 #include <linux/mmc/host.h>
  18
  19 #include <asm/scatterlist.h>
  20
  21 #include "sdhci.h"
  22
  23 #define DRIVER_NAME "sdhci"
  24
  25 #define DBG(f, x...) \
  26         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  27
  28 static unsigned int debug_nodma = 0;
  29 static unsigned int debug_forcedma = 0;
  30 static unsigned int debug_quirks = 0;
  31
  32 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET                  (1<<0)
  33 #define SDHCI_QUIRK_FORCE_DMA                           (1<<1)
  34 /* Controller doesn't like some resets when there is no card inserted. */
  35 #define SDHCI_QUIRK_NO_CARD_NO_RESET                    (1<<2)
  36 #define SDHCI_QUIRK_SINGLE_POWER_WRITE                  (1<<3)
  37 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS               (1<<4)
  38
  39 static const struct pci_device_id pci_ids[] __devinitdata = {
  40         {
  41                 .vendor         = PCI_VENDOR_ID_RICOH,
  42                 .device         = PCI_DEVICE_ID_RICOH_R5C822,
  43                 .subvendor      = PCI_VENDOR_ID_IBM,
  44                 .subdevice      = PCI_ANY_ID,
  45                 .driver_data    = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
  46                                   SDHCI_QUIRK_FORCE_DMA,
  47         },
  48
  49         {
  50                 .vendor         = PCI_VENDOR_ID_RICOH,
  51                 .device         = PCI_DEVICE_ID_RICOH_R5C822,
  52                 .subvendor      = PCI_ANY_ID,
  53                 .subdevice      = PCI_ANY_ID,
  54                 .driver_data    = SDHCI_QUIRK_FORCE_DMA |
  55                                   SDHCI_QUIRK_NO_CARD_NO_RESET,
  56         },
  57
  58         {
  59                 .vendor         = PCI_VENDOR_ID_TI,
  60                 .device         = PCI_DEVICE_ID_TI_XX21_XX11_SD,
  61                 .subvendor      = PCI_ANY_ID,
  62                 .subdevice      = PCI_ANY_ID,
  63                 .driver_data    = SDHCI_QUIRK_FORCE_DMA,
  64         },
  65
  66         {
  67                 .vendor         = PCI_VENDOR_ID_ENE,
  68                 .device         = PCI_DEVICE_ID_ENE_CB712_SD,
  69                 .subvendor      = PCI_ANY_ID,
  70                 .subdevice      = PCI_ANY_ID,
  71                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE,
  72         },
  73
  74         {
  75                 .vendor         = PCI_VENDOR_ID_ENE,
  76                 .device         = PCI_DEVICE_ID_ENE_CB712_SD_2,
  77                 .subvendor      = PCI_ANY_ID,
  78                 .subdevice      = PCI_ANY_ID,
  79                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE,
  80         },
  81
  82         {
  83                 .vendor         = PCI_VENDOR_ID_ENE,
  84                 .device         = PCI_DEVICE_ID_ENE_CB714_SD,
  85                 .subvendor      = PCI_ANY_ID,
  86                 .subdevice      = PCI_ANY_ID,
  87                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
  88                                   SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
  89         },
  90
  91         {
  92                 .vendor         = PCI_VENDOR_ID_ENE,
  93                 .device         = PCI_DEVICE_ID_ENE_CB714_SD_2,
  94                 .subvendor      = PCI_ANY_ID,
  95                 .subdevice      = PCI_ANY_ID,
  96                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
  97                                   SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
  98         },
  99
 100         {       /* Generic SD host controller */
 101                 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
 102         },
 103
 104         { /* end: all zeroes */ },
 105 };
 106
 107 MODULE_DEVICE_TABLE(pci, pci_ids);
 108
 109 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
 110 static void sdhci_finish_data(struct sdhci_host *);
 111
 112 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
 113 static void sdhci_finish_command(struct sdhci_host *);
 114
 115 static void sdhci_dumpregs(struct sdhci_host *host)
 116 {
 117         printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
 118
 119         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
 120                 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
 121                 readw(host->ioaddr + SDHCI_HOST_VERSION));
 122         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
 123                 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
 124                 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
 125         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
 126                 readl(host->ioaddr + SDHCI_ARGUMENT),
 127                 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
 128         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
 129                 readl(host->ioaddr + SDHCI_PRESENT_STATE),
 130                 readb(host->ioaddr + SDHCI_HOST_CONTROL));
 131         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
 132                 readb(host->ioaddr + SDHCI_POWER_CONTROL),
 133                 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
 134         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 135                 readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
 136                 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
 137         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 138                 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
 139                 readl(host->ioaddr + SDHCI_INT_STATUS));
 140         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 141                 readl(host->ioaddr + SDHCI_INT_ENABLE),
 142                 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
 143         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 144                 readw(host->ioaddr + SDHCI_ACMD12_ERR),
 145                 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
 146         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Max curr: 0x%08x\n",
 147                 readl(host->ioaddr + SDHCI_CAPABILITIES),
 148                 readl(host->ioaddr + SDHCI_MAX_CURRENT));
 149
 150         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
 151 }
 152
 153 /*****************************************************************************\
 154  *                                                                           *
 155  * Low level functions                                                       *
 156  *                                                                           *
 157 \*****************************************************************************/
 158
 159 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 160 {
 161         unsigned long timeout;
 162
 163         if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 164                 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
 165                         SDHCI_CARD_PRESENT))
 166                         return;
 167         }
 168
 169         writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
 170
 171         if (mask & SDHCI_RESET_ALL)
 172                 host->clock = 0;
 173
 174         /* Wait max 100 ms */
 175         timeout = 100;
 176
 177         /* hw clears the bit when it's done */
 178         while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
 179                 if (timeout == 0) {
 180                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
 181                                 mmc_hostname(host->mmc), (int)mask);
 182                         sdhci_dumpregs(host);
 183                         return;
 184                 }
 185                 timeout--;
 186                 mdelay(1);
 187         }
 188 }
 189
 190 static void sdhci_init(struct sdhci_host *host)
 191 {
 192         u32 intmask;
 193
 194         sdhci_reset(host, SDHCI_RESET_ALL);
 195
 196         intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 197                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 198                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 199                 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
 200                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
 201                 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
 202
 203         writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
 204         writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
 205 }
 206
 207 static void sdhci_activate_led(struct sdhci_host *host)
 208 {
 209         u8 ctrl;
 210
 211         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 212         ctrl |= SDHCI_CTRL_LED;
 213         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 214 }
 215
 216 static void sdhci_deactivate_led(struct sdhci_host *host)
 217 {
 218         u8 ctrl;
 219
 220         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 221         ctrl &= ~SDHCI_CTRL_LED;
 222         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 223 }
 224
 225 /*****************************************************************************\
 226  *                                                                           *
 227  * Core functions                                                            *
 228  *                                                                           *
 229 \*****************************************************************************/
 230
 231 static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
 232 {
 233         return page_address(host->cur_sg->page) + host->cur_sg->offset;
 234 }
 235
 236 static inline int sdhci_next_sg(struct sdhci_host* host)
 237 {
 238         /*
 239          * Skip to next SG entry.
 240          */
 241         host->cur_sg++;
 242         host->num_sg--;
 243
 244         /*
 245          * Any entries left?
 246          */
 247         if (host->num_sg > 0) {
 248                 host->offset = 0;
 249                 host->remain = host->cur_sg->length;
 250         }
 251
 252         return host->num_sg;
 253 }
 254
 255 static void sdhci_read_block_pio(struct sdhci_host *host)
 256 {
 257         int blksize, chunk_remain;
 258         u32 data;
 259         char *buffer;
 260         int size;
 261
 262         DBG("PIO reading\n");
 263
 264         blksize = host->data->blksz;
 265         chunk_remain = 0;
 266         data = 0;
 267
 268         buffer = sdhci_sg_to_buffer(host) + host->offset;
 269
 270         while (blksize) {
 271                 if (chunk_remain == 0) {
 272                         data = readl(host->ioaddr + SDHCI_BUFFER);
 273                         chunk_remain = min(blksize, 4);
 274                 }
 275
 276                 size = min(host->remain, chunk_remain);
 277
 278                 chunk_remain -= size;
 279                 blksize -= size;
 280                 host->offset += size;
 281                 host->remain -= size;
 282
 283                 while (size) {
 284                         *buffer = data & 0xFF;
 285                         buffer++;
 286                         data >>= 8;
 287                         size--;
 288                 }
 289
 290                 if (host->remain == 0) {
 291                         if (sdhci_next_sg(host) == 0) {
 292                                 BUG_ON(blksize != 0);
 293                                 return;
 294                         }
 295                         buffer = sdhci_sg_to_buffer(host);
 296                 }
 297         }
 298 }
 299
 300 static void sdhci_write_block_pio(struct sdhci_host *host)
 301 {
 302         int blksize, chunk_remain;
 303         u32 data;
 304         char *buffer;
 305         int bytes, size;
 306
 307         DBG("PIO writing\n");
 308
 309         blksize = host->data->blksz;
 310         chunk_remain = 4;
 311         data = 0;
 312
 313         bytes = 0;
 314         buffer = sdhci_sg_to_buffer(host) + host->offset;
 315
 316         while (blksize) {
 317                 size = min(host->remain, chunk_remain);
 318
 319                 chunk_remain -= size;
 320                 blksize -= size;
 321                 host->offset += size;
 322                 host->remain -= size;
 323
 324                 while (size) {
 325                         data >>= 8;
 326                         data |= (u32)*buffer << 24;
 327                         buffer++;
 328                         size--;
 329                 }
 330
 331                 if (chunk_remain == 0) {
 332                         writel(data, host->ioaddr + SDHCI_BUFFER);
 333                         chunk_remain = min(blksize, 4);
 334                 }
 335
 336                 if (host->remain == 0) {
 337                         if (sdhci_next_sg(host) == 0) {
 338                                 BUG_ON(blksize != 0);
 339                                 return;
 340                         }
 341                         buffer = sdhci_sg_to_buffer(host);
 342                 }
 343         }
 344 }
 345
 346 static void sdhci_transfer_pio(struct sdhci_host *host)
 347 {
 348         u32 mask;
 349
 350         BUG_ON(!host->data);
 351
 352         if (host->num_sg == 0)
 353                 return;
 354
 355         if (host->data->flags & MMC_DATA_READ)
 356                 mask = SDHCI_DATA_AVAILABLE;
 357         else
 358                 mask = SDHCI_SPACE_AVAILABLE;
 359
 360         while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
 361                 if (host->data->flags & MMC_DATA_READ)
 362                         sdhci_read_block_pio(host);
 363                 else
 364                         sdhci_write_block_pio(host);
 365
 366                 if (host->num_sg == 0)
 367                         break;
 368         }
 369
 370         DBG("PIO transfer complete.\n");
 371 }
 372
 373 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
 374 {
 375         u8 count;
 376         unsigned target_timeout, current_timeout;
 377
 378         WARN_ON(host->data);
 379
 380         if (data == NULL)
 381                 return;
 382
 383         DBG("blksz %04x blks %04x flags %08x\n",
 384                 data->blksz, data->blocks, data->flags);
 385         DBG("tsac %d ms nsac %d clk\n",
 386                 data->timeout_ns / 1000000, data->timeout_clks);
 387
 388         /* Sanity checks */
 389         BUG_ON(data->blksz * data->blocks > 524288);
 390         BUG_ON(data->blksz > host->mmc->max_blk_size);
 391         BUG_ON(data->blocks > 65535);
 392
 393         /* timeout in us */
 394         target_timeout = data->timeout_ns / 1000 +
 395                 data->timeout_clks / host->clock;
 396
 397         /*
 398          * Figure out needed cycles.
 399          * We do this in steps in order to fit inside a 32 bit int.
 400          * The first step is the minimum timeout, which will have a
 401          * minimum resolution of 6 bits:
 402          * (1) 2^13*1000 > 2^22,
 403          * (2) host->timeout_clk < 2^16
 404          *     =>
 405          *     (1) / (2) > 2^6
 406          */
 407         count = 0;
 408         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 409         while (current_timeout < target_timeout) {
 410                 count++;
 411                 current_timeout <<= 1;
 412                 if (count >= 0xF)
 413                         break;
 414         }
 415
 416         if (count >= 0xF) {
 417                 printk(KERN_WARNING "%s: Too large timeout requested!\n",
 418                         mmc_hostname(host->mmc));
 419                 count = 0xE;
 420         }
 421
 422         writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
 423
 424         if (host->flags & SDHCI_USE_DMA) {
 425                 int count;
 426
 427                 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
 428                         (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
 429                 BUG_ON(count != 1);
 430
 431                 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
 432         } else {
 433                 host->cur_sg = data->sg;
 434                 host->num_sg = data->sg_len;
 435
 436                 host->offset = 0;
 437                 host->remain = host->cur_sg->length;
 438         }
 439
 440         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
 441         writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
 442                 host->ioaddr + SDHCI_BLOCK_SIZE);
 443         writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
 444 }
 445
 446 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 447         struct mmc_data *data)
 448 {
 449         u16 mode;
 450
 451         WARN_ON(host->data);
 452
 453         if (data == NULL)
 454                 return;
 455
 456         mode = SDHCI_TRNS_BLK_CNT_EN;
 457         if (data->blocks > 1)
 458                 mode |= SDHCI_TRNS_MULTI;
 459         if (data->flags & MMC_DATA_READ)
 460                 mode |= SDHCI_TRNS_READ;
 461         if (host->flags & SDHCI_USE_DMA)
 462                 mode |= SDHCI_TRNS_DMA;
 463
 464         writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
 465 }
 466
 467 static void sdhci_finish_data(struct sdhci_host *host)
 468 {
 469         struct mmc_data *data;
 470         u16 blocks;
 471
 472         BUG_ON(!host->data);
 473
 474         data = host->data;
 475         host->data = NULL;
 476
 477         if (host->flags & SDHCI_USE_DMA) {
 478                 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
 479                         (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
 480         }
 481
 482         /*
 483          * Controller doesn't count down when in single block mode.
 484          */
 485         if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
 486                 blocks = 0;
 487         else
 488                 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
 489         data->bytes_xfered = data->blksz * (data->blocks - blocks);
 490
 491         if ((data->error == MMC_ERR_NONE) && blocks) {
 492                 printk(KERN_ERR "%s: Controller signalled completion even "
 493                         "though there were blocks left.\n",
 494                         mmc_hostname(host->mmc));
 495                 data->error = MMC_ERR_FAILED;
 496         }
 497
 498         DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
 499
 500         if (data->stop) {
 501                 /*
 502                  * The controller needs a reset of internal state machines
 503                  * upon error conditions.
 504                  */
 505                 if (data->error != MMC_ERR_NONE) {
 506                         sdhci_reset(host, SDHCI_RESET_CMD);
 507                         sdhci_reset(host, SDHCI_RESET_DATA);
 508                 }
 509
 510                 sdhci_send_command(host, data->stop);
 511         } else
 512                 tasklet_schedule(&host->finish_tasklet);
 513 }
 514
 515 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 516 {
 517         int flags;
 518         u32 mask;
 519         unsigned long timeout;
 520
 521         WARN_ON(host->cmd);
 522
 523         DBG("Sending cmd (%x)\n", cmd->opcode);
 524
 525         /* Wait max 10 ms */
 526         timeout = 10;
 527
 528         mask = SDHCI_CMD_INHIBIT;
 529         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 530                 mask |= SDHCI_DATA_INHIBIT;
 531
 532         /* We shouldn't wait for data inihibit for stop commands, even
 533            though they might use busy signaling */
 534         if (host->mrq->data && (cmd == host->mrq->data->stop))
 535                 mask &= ~SDHCI_DATA_INHIBIT;
 536
 537         while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
 538                 if (timeout == 0) {
 539                         printk(KERN_ERR "%s: Controller never released "
 540                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 541                         sdhci_dumpregs(host);
 542                         cmd->error = MMC_ERR_FAILED;
 543                         tasklet_schedule(&host->finish_tasklet);
 544                         return;
 545                 }
 546                 timeout--;
 547                 mdelay(1);
 548         }
 549
 550         mod_timer(&host->timer, jiffies + 10 * HZ);
 551
 552         host->cmd = cmd;
 553
 554         sdhci_prepare_data(host, cmd->data);
 555
 556         writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
 557
 558         sdhci_set_transfer_mode(host, cmd->data);
 559
 560         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 561                 printk(KERN_ERR "%s: Unsupported response type!\n",
 562                         mmc_hostname(host->mmc));
 563                 cmd->error = MMC_ERR_INVALID;
 564                 tasklet_schedule(&host->finish_tasklet);
 565                 return;
 566         }
 567
 568         if (!(cmd->flags & MMC_RSP_PRESENT))
 569                 flags = SDHCI_CMD_RESP_NONE;
 570         else if (cmd->flags & MMC_RSP_136)
 571                 flags = SDHCI_CMD_RESP_LONG;
 572         else if (cmd->flags & MMC_RSP_BUSY)
 573                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 574         else
 575                 flags = SDHCI_CMD_RESP_SHORT;
 576
 577         if (cmd->flags & MMC_RSP_CRC)
 578                 flags |= SDHCI_CMD_CRC;
 579         if (cmd->flags & MMC_RSP_OPCODE)
 580                 flags |= SDHCI_CMD_INDEX;
 581         if (cmd->data)
 582                 flags |= SDHCI_CMD_DATA;
 583
 584         writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
 585                 host->ioaddr + SDHCI_COMMAND);
 586 }
 587
 588 static void sdhci_finish_command(struct sdhci_host *host)
 589 {
 590         int i;
 591
 592         BUG_ON(host->cmd == NULL);
 593
 594         if (host->cmd->flags & MMC_RSP_PRESENT) {
 595                 if (host->cmd->flags & MMC_RSP_136) {
 596                         /* CRC is stripped so we need to do some shifting. */
 597                         for (i = 0;i < 4;i++) {
 598                                 host->cmd->resp[i] = readl(host->ioaddr +
 599                                         SDHCI_RESPONSE + (3-i)*4) << 8;
 600                                 if (i != 3)
 601                                         host->cmd->resp[i] |=
 602                                                 readb(host->ioaddr +
 603                                                 SDHCI_RESPONSE + (3-i)*4-1);
 604                         }
 605                 } else {
 606                         host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
 607                 }
 608         }
 609
 610         host->cmd->error = MMC_ERR_NONE;
 611
 612         DBG("Ending cmd (%x)\n", host->cmd->opcode);
 613
 614         if (host->cmd->data)
 615                 host->data = host->cmd->data;
 616         else
 617                 tasklet_schedule(&host->finish_tasklet);
 618
 619         host->cmd = NULL;
 620 }
 621
 622 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 623 {
 624         int div;
 625         u16 clk;
 626         unsigned long timeout;
 627
 628         if (clock == host->clock)
 629                 return;
 630
 631         writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
 632
 633         if (clock == 0)
 634                 goto out;
 635
 636         for (div = 1;div < 256;div *= 2) {
 637                 if ((host->max_clk / div) <= clock)
 638                         break;
 639         }
 640         div >>= 1;
 641
 642         clk = div << SDHCI_DIVIDER_SHIFT;
 643         clk |= SDHCI_CLOCK_INT_EN;
 644         writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
 645
 646         /* Wait max 10 ms */
 647         timeout = 10;
 648         while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
 649                 & SDHCI_CLOCK_INT_STABLE)) {
 650                 if (timeout == 0) {
 651                         printk(KERN_ERR "%s: Internal clock never "
 652                                 "stabilised.\n", mmc_hostname(host->mmc));
 653                         sdhci_dumpregs(host);
 654                         return;
 655                 }
 656                 timeout--;
 657                 mdelay(1);
 658         }
 659
 660         clk |= SDHCI_CLOCK_CARD_EN;
 661         writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
 662
 663 out:
 664         host->clock = clock;
 665 }
 666
 667 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 668 {
 669         u8 pwr;
 670
 671         if (host->power == power)
 672                 return;
 673
 674         if (power == (unsigned short)-1) {
 675                 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
 676                 goto out;
 677         }
 678
 679         /*
 680          * Spec says that we should clear the power reg before setting
 681          * a new value. Some controllers don't seem to like this though.
 682          */
 683         if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
 684                 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
 685
 686         pwr = SDHCI_POWER_ON;
 687
 688         switch (1 << power) {
 689         case MMC_VDD_165_195:
 690                 pwr |= SDHCI_POWER_180;
 691                 break;
 692         case MMC_VDD_29_30:
 693         case MMC_VDD_30_31:
 694                 pwr |= SDHCI_POWER_300;
 695                 break;
 696         case MMC_VDD_32_33:
 697         case MMC_VDD_33_34:
 698                 pwr |= SDHCI_POWER_330;
 699                 break;
 700         default:
 701                 BUG();
 702         }
 703
 704         writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
 705
 706 out:
 707         host->power = power;
 708 }
 709
 710 /*****************************************************************************\
 711  *                                                                           *
 712  * MMC callbacks                                                             *
 713  *                                                                           *
 714 \*****************************************************************************/
 715
 716 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 717 {
 718         struct sdhci_host *host;
 719         unsigned long flags;
 720
 721         host = mmc_priv(mmc);
 722
 723         spin_lock_irqsave(&host->lock, flags);
 724
 725         WARN_ON(host->mrq != NULL);
 726
 727         sdhci_activate_led(host);
 728
 729         host->mrq = mrq;
 730
 731         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
 732                 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
 733                 tasklet_schedule(&host->finish_tasklet);
 734         } else
 735                 sdhci_send_command(host, mrq->cmd);
 736
 737         mmiowb();
 738         spin_unlock_irqrestore(&host->lock, flags);
 739 }
 740
 741 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 742 {
 743         struct sdhci_host *host;
 744         unsigned long flags;
 745         u8 ctrl;
 746
 747         host = mmc_priv(mmc);
 748
 749         spin_lock_irqsave(&host->lock, flags);
 750
 751         /*
 752          * Reset the chip on each power off.
 753          * Should clear out any weird states.
 754          */
 755         if (ios->power_mode == MMC_POWER_OFF) {
 756                 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
 757                 sdhci_init(host);
 758         }
 759
 760         sdhci_set_clock(host, ios->clock);
 761
 762         if (ios->power_mode == MMC_POWER_OFF)
 763                 sdhci_set_power(host, -1);
 764         else
 765                 sdhci_set_power(host, ios->vdd);
 766
 767         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 768
 769         if (ios->bus_width == MMC_BUS_WIDTH_4)
 770                 ctrl |= SDHCI_CTRL_4BITBUS;
 771         else
 772                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 773
 774         if (ios->timing == MMC_TIMING_SD_HS)
 775                 ctrl |= SDHCI_CTRL_HISPD;
 776         else
 777                 ctrl &= ~SDHCI_CTRL_HISPD;
 778
 779         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 780
 781         /*
 782          * Some (ENE) controllers go apeshit on some ios operation,
 783          * signalling timeout and CRC errors even on CMD0. Resetting
 784          * it on each ios seems to solve the problem.
 785          */
 786         if(host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
 787                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 788
 789         mmiowb();
 790         spin_unlock_irqrestore(&host->lock, flags);
 791 }
 792
 793 static int sdhci_get_ro(struct mmc_host *mmc)
 794 {
 795         struct sdhci_host *host;
 796         unsigned long flags;
 797         int present;
 798
 799         host = mmc_priv(mmc);
 800
 801         spin_lock_irqsave(&host->lock, flags);
 802
 803         present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
 804
 805         spin_unlock_irqrestore(&host->lock, flags);
 806
 807         return !(present & SDHCI_WRITE_PROTECT);
 808 }
 809
 810 static const struct mmc_host_ops sdhci_ops = {
 811         .request        = sdhci_request,
 812         .set_ios        = sdhci_set_ios,
 813         .get_ro         = sdhci_get_ro,
 814 };
 815
 816 /*****************************************************************************\
 817  *                                                                           *
 818  * Tasklets                                                                  *
 819  *                                                                           *
 820 \*****************************************************************************/
 821
 822 static void sdhci_tasklet_card(unsigned long param)
 823 {
 824         struct sdhci_host *host;
 825         unsigned long flags;
 826
 827         host = (struct sdhci_host*)param;
 828
 829         spin_lock_irqsave(&host->lock, flags);
 830
 831         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
 832                 if (host->mrq) {
 833                         printk(KERN_ERR "%s: Card removed during transfer!\n",
 834                                 mmc_hostname(host->mmc));
 835                         printk(KERN_ERR "%s: Resetting controller.\n",
 836                                 mmc_hostname(host->mmc));
 837
 838                         sdhci_reset(host, SDHCI_RESET_CMD);
 839                         sdhci_reset(host, SDHCI_RESET_DATA);
 840
 841                         host->mrq->cmd->error = MMC_ERR_FAILED;
 842                         tasklet_schedule(&host->finish_tasklet);
 843                 }
 844         }
 845
 846         spin_unlock_irqrestore(&host->lock, flags);
 847
 848         mmc_detect_change(host->mmc, msecs_to_jiffies(500));
 849 }
 850
 851 static void sdhci_tasklet_finish(unsigned long param)
 852 {
 853         struct sdhci_host *host;
 854         unsigned long flags;
 855         struct mmc_request *mrq;
 856
 857         host = (struct sdhci_host*)param;
 858
 859         spin_lock_irqsave(&host->lock, flags);
 860
 861         del_timer(&host->timer);
 862
 863         mrq = host->mrq;
 864
 865         DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
 866
 867         /*
 868          * The controller needs a reset of internal state machines
 869          * upon error conditions.
 870          */
 871         if ((mrq->cmd->error != MMC_ERR_NONE) ||
 872                 (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
 873                 (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
 874
 875                 /* Some controllers need this kick or reset won't work here */
 876                 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
 877                         unsigned int clock;
 878
 879                         /* This is to force an update */
 880                         clock = host->clock;
 881                         host->clock = 0;
 882                         sdhci_set_clock(host, clock);
 883                 }
 884
 885                 /* Spec says we should do both at the same time, but Ricoh
 886                    controllers do not like that. */
 887                 sdhci_reset(host, SDHCI_RESET_CMD);
 888                 sdhci_reset(host, SDHCI_RESET_DATA);
 889         }
 890
 891         host->mrq = NULL;
 892         host->cmd = NULL;
 893         host->data = NULL;
 894
 895         sdhci_deactivate_led(host);
 896
 897         mmiowb();
 898         spin_unlock_irqrestore(&host->lock, flags);
 899
 900         mmc_request_done(host->mmc, mrq);
 901 }
 902
 903 static void sdhci_timeout_timer(unsigned long data)
 904 {
 905         struct sdhci_host *host;
 906         unsigned long flags;
 907
 908         host = (struct sdhci_host*)data;
 909
 910         spin_lock_irqsave(&host->lock, flags);
 911
 912         if (host->mrq) {
 913                 printk(KERN_ERR "%s: Timeout waiting for hardware "
 914                         "interrupt.\n", mmc_hostname(host->mmc));
 915                 sdhci_dumpregs(host);
 916
 917                 if (host->data) {
 918                         host->data->error = MMC_ERR_TIMEOUT;
 919                         sdhci_finish_data(host);
 920                 } else {
 921                         if (host->cmd)
 922                                 host->cmd->error = MMC_ERR_TIMEOUT;
 923                         else
 924                                 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
 925
 926                         tasklet_schedule(&host->finish_tasklet);
 927                 }
 928         }
 929
 930         mmiowb();
 931         spin_unlock_irqrestore(&host->lock, flags);
 932 }
 933
 934 /*****************************************************************************\
 935  *                                                                           *
 936  * Interrupt handling                                                        *
 937  *                                                                           *
 938 \*****************************************************************************/
 939
 940 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
 941 {
 942         BUG_ON(intmask == 0);
 943
 944         if (!host->cmd) {
 945                 printk(KERN_ERR "%s: Got command interrupt even though no "
 946                         "command operation was in progress.\n",
 947                         mmc_hostname(host->mmc));
 948                 sdhci_dumpregs(host);
 949                 return;
 950         }
 951
 952         if (intmask & SDHCI_INT_TIMEOUT)
 953                 host->cmd->error = MMC_ERR_TIMEOUT;
 954         else if (intmask & SDHCI_INT_CRC)
 955                 host->cmd->error = MMC_ERR_BADCRC;
 956         else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
 957                 host->cmd->error = MMC_ERR_FAILED;
 958
 959         if (host->cmd->error != MMC_ERR_NONE)
 960                 tasklet_schedule(&host->finish_tasklet);
 961         else if (intmask & SDHCI_INT_RESPONSE)
 962                 sdhci_finish_command(host);
 963 }
 964
 965 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
 966 {
 967         BUG_ON(intmask == 0);
 968
 969         if (!host->data) {
 970                 /*
 971                  * A data end interrupt is sent together with the response
 972                  * for the stop command.
 973                  */
 974                 if (intmask & SDHCI_INT_DATA_END)
 975                         return;
 976
 977                 printk(KERN_ERR "%s: Got data interrupt even though no "
 978                         "data operation was in progress.\n",
 979                         mmc_hostname(host->mmc));
 980                 sdhci_dumpregs(host);
 981
 982                 return;
 983         }
 984
 985         if (intmask & SDHCI_INT_DATA_TIMEOUT)
 986                 host->data->error = MMC_ERR_TIMEOUT;
 987         else if (intmask & SDHCI_INT_DATA_CRC)
 988                 host->data->error = MMC_ERR_BADCRC;
 989         else if (intmask & SDHCI_INT_DATA_END_BIT)
 990                 host->data->error = MMC_ERR_FAILED;
 991
 992         if (host->data->error != MMC_ERR_NONE)
 993                 sdhci_finish_data(host);
 994         else {
 995                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
 996                         sdhci_transfer_pio(host);
 997
 998                 /*
 999                  * We currently don't do anything fancy with DMA
1000                  * boundaries, but as we can't disable the feature
1001                  * we need to at least restart the transfer.
1002                  */
1003                 if (intmask & SDHCI_INT_DMA_END)
1004                         writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1005                                 host->ioaddr + SDHCI_DMA_ADDRESS);
1006
1007                 if (intmask & SDHCI_INT_DATA_END)
1008                         sdhci_finish_data(host);
1009         }
1010 }
1011
1012 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1013 {
1014         irqreturn_t result;
1015         struct sdhci_host* host = dev_id;
1016         u32 intmask;
1017
1018         spin_lock(&host->lock);
1019
1020         intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1021
1022         if (!intmask || intmask == 0xffffffff) {
1023                 result = IRQ_NONE;
1024                 goto out;
1025         }
1026
1027         DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1028
1029         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1030                 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1031                         host->ioaddr + SDHCI_INT_STATUS);
1032                 tasklet_schedule(&host->card_tasklet);
1033         }
1034
1035         intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1036
1037         if (intmask & SDHCI_INT_CMD_MASK) {
1038                 writel(intmask & SDHCI_INT_CMD_MASK,
1039                         host->ioaddr + SDHCI_INT_STATUS);
1040                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1041         }
1042
1043         if (intmask & SDHCI_INT_DATA_MASK) {
1044                 writel(intmask & SDHCI_INT_DATA_MASK,
1045                         host->ioaddr + SDHCI_INT_STATUS);
1046                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1047         }
1048
1049         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1050
1051         intmask &= ~SDHCI_INT_ERROR;
1052
1053         if (intmask & SDHCI_INT_BUS_POWER) {
1054                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1055                         mmc_hostname(host->mmc));
1056                 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1057         }
1058
1059         intmask &= ~SDHCI_INT_BUS_POWER;
1060
1061         if (intmask) {
1062                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1063                         mmc_hostname(host->mmc), intmask);
1064                 sdhci_dumpregs(host);
1065
1066                 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1067         }
1068
1069         result = IRQ_HANDLED;
1070
1071         mmiowb();
1072 out:
1073         spin_unlock(&host->lock);
1074
1075         return result;
1076 }
1077
1078 /*****************************************************************************\
1079  *                                                                           *
1080  * Suspend/resume                                                            *
1081  *                                                                           *
1082 \*****************************************************************************/
1083
1084 #ifdef CONFIG_PM
1085
1086 static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1087 {
1088         struct sdhci_chip *chip;
1089         int i, ret;
1090
1091         chip = pci_get_drvdata(pdev);
1092         if (!chip)
1093                 return 0;
1094
1095         DBG("Suspending...\n");
1096
1097         for (i = 0;i < chip->num_slots;i++) {
1098                 if (!chip->hosts[i])
1099                         continue;
1100                 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1101                 if (ret) {
1102                         for (i--;i >= 0;i--)
1103                                 mmc_resume_host(chip->hosts[i]->mmc);
1104                         return ret;
1105                 }
1106         }
1107
1108         pci_save_state(pdev);
1109         pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1110
1111         for (i = 0;i < chip->num_slots;i++) {
1112                 if (!chip->hosts[i])
1113                         continue;
1114                 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1115         }
1116
1117         pci_disable_device(pdev);
1118         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1119
1120         return 0;
1121 }
1122
1123 static int sdhci_resume (struct pci_dev *pdev)
1124 {
1125         struct sdhci_chip *chip;
1126         int i, ret;
1127
1128         chip = pci_get_drvdata(pdev);
1129         if (!chip)
1130                 return 0;
1131
1132         DBG("Resuming...\n");
1133
1134         pci_set_power_state(pdev, PCI_D0);
1135         pci_restore_state(pdev);
1136         ret = pci_enable_device(pdev);
1137         if (ret)
1138                 return ret;
1139
1140         for (i = 0;i < chip->num_slots;i++) {
1141                 if (!chip->hosts[i])
1142                         continue;
1143                 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1144                         pci_set_master(pdev);
1145                 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1146                         IRQF_SHARED, chip->hosts[i]->slot_descr,
1147                         chip->hosts[i]);
1148                 if (ret)
1149                         return ret;
1150                 sdhci_init(chip->hosts[i]);
1151                 mmiowb();
1152                 ret = mmc_resume_host(chip->hosts[i]->mmc);
1153                 if (ret)
1154                         return ret;
1155         }
1156
1157         return 0;
1158 }
1159
1160 #else /* CONFIG_PM */
1161
1162 #define sdhci_suspend NULL
1163 #define sdhci_resume NULL
1164
1165 #endif /* CONFIG_PM */
1166
1167 /*****************************************************************************\
1168  *                                                                           *
1169  * Device probing/removal                                                    *
1170  *                                                                           *
1171 \*****************************************************************************/
1172
1173 static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1174 {
1175         int ret;
1176         unsigned int version;
1177         struct sdhci_chip *chip;
1178         struct mmc_host *mmc;
1179         struct sdhci_host *host;
1180
1181         u8 first_bar;
1182         unsigned int caps;
1183
1184         chip = pci_get_drvdata(pdev);
1185         BUG_ON(!chip);
1186
1187         ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1188         if (ret)
1189                 return ret;
1190
1191         first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1192
1193         if (first_bar > 5) {
1194                 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1195                 return -ENODEV;
1196         }
1197
1198         if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1199                 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1200                 return -ENODEV;
1201         }
1202
1203         if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1204                 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1205                         "You may experience problems.\n");
1206         }
1207
1208         if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1209                 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1210                 return -ENODEV;
1211         }
1212
1213         if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1214                 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1215                 return -ENODEV;
1216         }
1217
1218         mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1219         if (!mmc)
1220                 return -ENOMEM;
1221
1222         host = mmc_priv(mmc);
1223         host->mmc = mmc;
1224
1225         host->chip = chip;
1226         chip->hosts[slot] = host;
1227
1228         host->bar = first_bar + slot;
1229
1230         host->addr = pci_resource_start(pdev, host->bar);
1231         host->irq = pdev->irq;
1232
1233         DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1234
1235         snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1236
1237         ret = pci_request_region(pdev, host->bar, host->slot_descr);
1238         if (ret)
1239                 goto free;
1240
1241         host->ioaddr = ioremap_nocache(host->addr,
1242                 pci_resource_len(pdev, host->bar));
1243         if (!host->ioaddr) {
1244                 ret = -ENOMEM;
1245                 goto release;
1246         }
1247
1248         sdhci_reset(host, SDHCI_RESET_ALL);
1249
1250         version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1251         version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1252         if (version != 0) {
1253                 printk(KERN_ERR "%s: Unknown controller version (%d). "
1254                         "You may experience problems.\n", host->slot_descr,
1255                         version);
1256         }
1257
1258         caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1259
1260         if (debug_nodma)
1261                 DBG("DMA forced off\n");
1262         else if (debug_forcedma) {
1263                 DBG("DMA forced on\n");
1264                 host->flags |= SDHCI_USE_DMA;
1265         } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1266                 host->flags |= SDHCI_USE_DMA;
1267         else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
1268                 DBG("Controller doesn't have DMA interface\n");
1269         else if (!(caps & SDHCI_CAN_DO_DMA))
1270                 DBG("Controller doesn't have DMA capability\n");
1271         else
1272                 host->flags |= SDHCI_USE_DMA;
1273
1274         if (host->flags & SDHCI_USE_DMA) {
1275                 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1276                         printk(KERN_WARNING "%s: No suitable DMA available. "
1277                                 "Falling back to PIO.\n", host->slot_descr);
1278                         host->flags &= ~SDHCI_USE_DMA;
1279                 }
1280         }
1281
1282         if (host->flags & SDHCI_USE_DMA)
1283                 pci_set_master(pdev);
1284         else /* XXX: Hack to get MMC layer to avoid highmem */
1285                 pdev->dma_mask = 0;
1286
1287         host->max_clk =
1288                 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1289         if (host->max_clk == 0) {
1290                 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1291                         "frequency.\n", host->slot_descr);
1292                 ret = -ENODEV;
1293                 goto unmap;
1294         }
1295         host->max_clk *= 1000000;
1296
1297         host->timeout_clk =
1298                 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1299         if (host->timeout_clk == 0) {
1300                 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1301                         "frequency.\n", host->slot_descr);
1302                 ret = -ENODEV;
1303                 goto unmap;
1304         }
1305         if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1306                 host->timeout_clk *= 1000;
1307
1308         /*
1309          * Set host parameters.
1310          */
1311         mmc->ops = &sdhci_ops;
1312         mmc->f_min = host->max_clk / 256;
1313         mmc->f_max = host->max_clk;
1314         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
1315
1316         if (caps & SDHCI_CAN_DO_HISPD)
1317                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1318
1319         mmc->ocr_avail = 0;
1320         if (caps & SDHCI_CAN_VDD_330)
1321                 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1322         if (caps & SDHCI_CAN_VDD_300)
1323                 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1324         if (caps & SDHCI_CAN_VDD_180)
1325                 mmc->ocr_avail |= MMC_VDD_165_195;
1326
1327         if (mmc->ocr_avail == 0) {
1328                 printk(KERN_ERR "%s: Hardware doesn't report any "
1329                         "support voltages.\n", host->slot_descr);
1330                 ret = -ENODEV;
1331                 goto unmap;
1332         }
1333
1334         spin_lock_init(&host->lock);
1335
1336         /*
1337          * Maximum number of segments. Hardware cannot do scatter lists.
1338          */
1339         if (host->flags & SDHCI_USE_DMA)
1340                 mmc->max_hw_segs = 1;
1341         else
1342                 mmc->max_hw_segs = 16;
1343         mmc->max_phys_segs = 16;
1344
1345         /*
1346          * Maximum number of sectors in one transfer. Limited by DMA boundary
1347          * size (512KiB).
1348          */
1349         mmc->max_req_size = 524288;
1350
1351         /*
1352          * Maximum segment size. Could be one segment with the maximum number
1353          * of bytes.
1354          */
1355         mmc->max_seg_size = mmc->max_req_size;
1356
1357         /*
1358          * Maximum block size. This varies from controller to controller and
1359          * is specified in the capabilities register.
1360          */
1361         mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1362         if (mmc->max_blk_size >= 3) {
1363                 printk(KERN_ERR "%s: Invalid maximum block size.\n",
1364                         host->slot_descr);
1365                 ret = -ENODEV;
1366                 goto unmap;
1367         }
1368         mmc->max_blk_size = 512 << mmc->max_blk_size;
1369
1370         /*
1371          * Maximum block count.
1372          */
1373         mmc->max_blk_count = 65535;
1374
1375         /*
1376          * Init tasklets.
1377          */
1378         tasklet_init(&host->card_tasklet,
1379                 sdhci_tasklet_card, (unsigned long)host);
1380         tasklet_init(&host->finish_tasklet,
1381                 sdhci_tasklet_finish, (unsigned long)host);
1382
1383         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1384
1385         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1386                 host->slot_descr, host);
1387         if (ret)
1388                 goto untasklet;
1389
1390         sdhci_init(host);
1391
1392 #ifdef CONFIG_MMC_DEBUG
1393         sdhci_dumpregs(host);
1394 #endif
1395
1396         mmiowb();
1397
1398         mmc_add_host(mmc);
1399
1400         printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1401                 host->addr, host->irq,
1402                 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1403
1404         return 0;
1405
1406 untasklet:
1407         tasklet_kill(&host->card_tasklet);
1408         tasklet_kill(&host->finish_tasklet);
1409 unmap:
1410         iounmap(host->ioaddr);
1411 release:
1412         pci_release_region(pdev, host->bar);
1413 free:
1414         mmc_free_host(mmc);
1415
1416         return ret;
1417 }
1418
1419 static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1420 {
1421         struct sdhci_chip *chip;
1422         struct mmc_host *mmc;
1423         struct sdhci_host *host;
1424
1425         chip = pci_get_drvdata(pdev);
1426         host = chip->hosts[slot];
1427         mmc = host->mmc;
1428
1429         chip->hosts[slot] = NULL;
1430
1431         mmc_remove_host(mmc);
1432
1433         sdhci_reset(host, SDHCI_RESET_ALL);
1434
1435         free_irq(host->irq, host);
1436
1437         del_timer_sync(&host->timer);
1438
1439         tasklet_kill(&host->card_tasklet);
1440         tasklet_kill(&host->finish_tasklet);
1441
1442         iounmap(host->ioaddr);
1443
1444         pci_release_region(pdev, host->bar);
1445
1446         mmc_free_host(mmc);
1447 }
1448
1449 static int __devinit sdhci_probe(struct pci_dev *pdev,
1450         const struct pci_device_id *ent)
1451 {
1452         int ret, i;
1453         u8 slots, rev;
1454         struct sdhci_chip *chip;
1455
1456         BUG_ON(pdev == NULL);
1457         BUG_ON(ent == NULL);
1458
1459         pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1460
1461         printk(KERN_INFO DRIVER_NAME
1462                 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1463                 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1464                 (int)rev);
1465
1466         ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1467         if (ret)
1468                 return ret;
1469
1470         slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1471         DBG("found %d slot(s)\n", slots);
1472         if (slots == 0)
1473                 return -ENODEV;
1474
1475         ret = pci_enable_device(pdev);
1476         if (ret)
1477                 return ret;
1478
1479         chip = kzalloc(sizeof(struct sdhci_chip) +
1480                 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1481         if (!chip) {
1482                 ret = -ENOMEM;
1483                 goto err;
1484         }
1485
1486         chip->pdev = pdev;
1487         chip->quirks = ent->driver_data;
1488
1489         if (debug_quirks)
1490                 chip->quirks = debug_quirks;
1491
1492         chip->num_slots = slots;
1493         pci_set_drvdata(pdev, chip);
1494
1495         for (i = 0;i < slots;i++) {
1496                 ret = sdhci_probe_slot(pdev, i);
1497                 if (ret) {
1498                         for (i--;i >= 0;i--)
1499                                 sdhci_remove_slot(pdev, i);
1500                         goto free;
1501                 }
1502         }
1503
1504         return 0;
1505
1506 free:
1507         pci_set_drvdata(pdev, NULL);
1508         kfree(chip);
1509
1510 err:
1511         pci_disable_device(pdev);
1512         return ret;
1513 }
1514
1515 static void __devexit sdhci_remove(struct pci_dev *pdev)
1516 {
1517         int i;
1518         struct sdhci_chip *chip;
1519
1520         chip = pci_get_drvdata(pdev);
1521
1522         if (chip) {
1523                 for (i = 0;i < chip->num_slots;i++)
1524                         sdhci_remove_slot(pdev, i);
1525
1526                 pci_set_drvdata(pdev, NULL);
1527
1528                 kfree(chip);
1529         }
1530
1531         pci_disable_device(pdev);
1532 }
1533
1534 static struct pci_driver sdhci_driver = {
1535         .name =         DRIVER_NAME,
1536         .id_table =     pci_ids,
1537         .probe =        sdhci_probe,
1538         .remove =       __devexit_p(sdhci_remove),
1539         .suspend =      sdhci_suspend,
1540         .resume =       sdhci_resume,
1541 };
1542
1543 /*****************************************************************************\
1544  *                                                                           *
1545  * Driver init/exit                                                          *
1546  *                                                                           *
1547 \*****************************************************************************/
1548
1549 static int __init sdhci_drv_init(void)
1550 {
1551         printk(KERN_INFO DRIVER_NAME
1552                 ": Secure Digital Host Controller Interface driver\n");
1553         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1554
1555         return pci_register_driver(&sdhci_driver);
1556 }
1557
1558 static void __exit sdhci_drv_exit(void)
1559 {
1560         DBG("Exiting\n");
1561
1562         pci_unregister_driver(&sdhci_driver);
1563 }
1564
1565 module_init(sdhci_drv_init);
1566 module_exit(sdhci_drv_exit);
1567
1568 module_param(debug_nodma, uint, 0444);
1569 module_param(debug_forcedma, uint, 0444);
1570 module_param(debug_quirks, uint, 0444);
1571
1572 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1573 MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1574 MODULE_LICENSE("GPL");
1575
1576 MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
1577 MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
1578 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");