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   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/io.h>
  29 #include <linux/semaphore.h>
  30 #include <mach/dma.h>
  31 #include <mach/hardware.h>
  32 #include <mach/board.h>
  33 #include <mach/mmc.h>
  34 #include <mach/cpu.h>
  35
  36 /* OMAP HSMMC Host Controller Registers */
  37 #define OMAP_HSMMC_SYSCONFIG    0x0010
  38 #define OMAP_HSMMC_CON          0x002C
  39 #define OMAP_HSMMC_BLK          0x0104
  40 #define OMAP_HSMMC_ARG          0x0108
  41 #define OMAP_HSMMC_CMD          0x010C
  42 #define OMAP_HSMMC_RSP10        0x0110
  43 #define OMAP_HSMMC_RSP32        0x0114
  44 #define OMAP_HSMMC_RSP54        0x0118
  45 #define OMAP_HSMMC_RSP76        0x011C
  46 #define OMAP_HSMMC_DATA         0x0120
  47 #define OMAP_HSMMC_HCTL         0x0128
  48 #define OMAP_HSMMC_SYSCTL       0x012C
  49 #define OMAP_HSMMC_STAT         0x0130
  50 #define OMAP_HSMMC_IE           0x0134
  51 #define OMAP_HSMMC_ISE          0x0138
  52 #define OMAP_HSMMC_CAPA         0x0140
  53
  54 #define VS18                    (1 << 26)
  55 #define VS30                    (1 << 25)
  56 #define SDVS18                  (0x5 << 9)
  57 #define SDVS30                  (0x6 << 9)
  58 #define SDVS33                  (0x7 << 9)
  59 #define SDVS_MASK               0x00000E00
  60 #define SDVSCLR                 0xFFFFF1FF
  61 #define SDVSDET                 0x00000400
  62 #define AUTOIDLE                0x1
  63 #define SDBP                    (1 << 8)
  64 #define DTO                     0xe
  65 #define ICE                     0x1
  66 #define ICS                     0x2
  67 #define CEN                     (1 << 2)
  68 #define CLKD_MASK               0x0000FFC0
  69 #define CLKD_SHIFT              6
  70 #define DTO_MASK                0x000F0000
  71 #define DTO_SHIFT               16
  72 #define INT_EN_MASK             0x307F0033
  73 #define INIT_STREAM             (1 << 1)
  74 #define DP_SELECT               (1 << 21)
  75 #define DDIR                    (1 << 4)
  76 #define DMA_EN                  0x1
  77 #define MSBS                    (1 << 5)
  78 #define BCE                     (1 << 1)
  79 #define FOUR_BIT                (1 << 1)
  80 #define DW8                     (1 << 5)
  81 #define CC                      0x1
  82 #define TC                      0x02
  83 #define OD                      0x1
  84 #define ERR                     (1 << 15)
  85 #define CMD_TIMEOUT             (1 << 16)
  86 #define DATA_TIMEOUT            (1 << 20)
  87 #define CMD_CRC                 (1 << 17)
  88 #define DATA_CRC                (1 << 21)
  89 #define CARD_ERR                (1 << 28)
  90 #define STAT_CLEAR              0xFFFFFFFF
  91 #define INIT_STREAM_CMD         0x00000000
  92 #define DUAL_VOLT_OCR_BIT       7
  93 #define SRC                     (1 << 25)
  94 #define SRD                     (1 << 26)
  95
  96 /*
  97  * FIXME: Most likely all the data using these _DEVID defines should come
  98  * from the platform_data, or implemented in controller and slot specific
  99  * functions.
 100  */
 101 #define OMAP_MMC1_DEVID         0
 102 #define OMAP_MMC2_DEVID         1
 103 #define OMAP_MMC3_DEVID         2
 104
 105 #define MMC_TIMEOUT_MS          20
 106 #define OMAP_MMC_MASTER_CLOCK   96000000
 107 #define DRIVER_NAME             "mmci-omap-hs"
 108
 109 /*
 110  * One controller can have multiple slots, like on some omap boards using
 111  * omap.c controller driver. Luckily this is not currently done on any known
 112  * omap_hsmmc.c device.
 113  */
 114 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 115
 116 /*
 117  * MMC Host controller read/write API's
 118  */
 119 #define OMAP_HSMMC_READ(base, reg)      \
 120         __raw_readl((base) + OMAP_HSMMC_##reg)
 121
 122 #define OMAP_HSMMC_WRITE(base, reg, val) \
 123         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 124
 125 struct mmc_omap_host {
 126         struct  device          *dev;
 127         struct  mmc_host        *mmc;
 128         struct  mmc_request     *mrq;
 129         struct  mmc_command     *cmd;
 130         struct  mmc_data        *data;
 131         struct  clk             *fclk;
 132         struct  clk             *iclk;
 133         struct  clk             *dbclk;
 134         struct  semaphore       sem;
 135         struct  work_struct     mmc_carddetect_work;
 136         void    __iomem         *base;
 137         resource_size_t         mapbase;
 138         unsigned int            id;
 139         unsigned int            dma_len;
 140         unsigned int            dma_sg_idx;
 141         unsigned char           bus_mode;
 142         u32                     *buffer;
 143         u32                     bytesleft;
 144         int                     suspended;
 145         int                     irq;
 146         int                     carddetect;
 147         int                     use_dma, dma_ch;
 148         int                     dma_line_tx, dma_line_rx;
 149         int                     slot_id;
 150         int                     dbclk_enabled;
 151         int                     response_busy;
 152         struct  omap_mmc_platform_data  *pdata;
 153 };
 154
 155 /*
 156  * Stop clock to the card
 157  */
 158 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 159 {
 160         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 161                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 162         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 163                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 164 }
 165
 166 /*
 167  * Send init stream sequence to card
 168  * before sending IDLE command
 169  */
 170 static void send_init_stream(struct mmc_omap_host *host)
 171 {
 172         int reg = 0;
 173         unsigned long timeout;
 174
 175         disable_irq(host->irq);
 176         OMAP_HSMMC_WRITE(host->base, CON,
 177                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 178         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 179
 180         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 181         while ((reg != CC) && time_before(jiffies, timeout))
 182                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 183
 184         OMAP_HSMMC_WRITE(host->base, CON,
 185                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 186         enable_irq(host->irq);
 187 }
 188
 189 static inline
 190 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
 191 {
 192         int r = 1;
 193
 194         if (host->pdata->slots[host->slot_id].get_cover_state)
 195                 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
 196                         host->slot_id);
 197         return r;
 198 }
 199
 200 static ssize_t
 201 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 202                            char *buf)
 203 {
 204         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 205         struct mmc_omap_host *host = mmc_priv(mmc);
 206
 207         return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
 208                        "open");
 209 }
 210
 211 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 212
 213 static ssize_t
 214 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 215                         char *buf)
 216 {
 217         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 218         struct mmc_omap_host *host = mmc_priv(mmc);
 219         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 220
 221         return sprintf(buf, "%s\n", slot.name);
 222 }
 223
 224 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 225
 226 /*
 227  * Configure the response type and send the cmd.
 228  */
 229 static void
 230 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 231         struct mmc_data *data)
 232 {
 233         int cmdreg = 0, resptype = 0, cmdtype = 0;
 234
 235         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 236                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 237         host->cmd = cmd;
 238
 239         /*
 240          * Clear status bits and enable interrupts
 241          */
 242         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 243         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 244         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 245
 246         host->response_busy = 0;
 247         if (cmd->flags & MMC_RSP_PRESENT) {
 248                 if (cmd->flags & MMC_RSP_136)
 249                         resptype = 1;
 250                 else if (cmd->flags & MMC_RSP_BUSY) {
 251                         resptype = 3;
 252                         host->response_busy = 1;
 253                 } else
 254                         resptype = 2;
 255         }
 256
 257         /*
 258          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 259          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 260          * a val of 0x3, rest 0x0.
 261          */
 262         if (cmd == host->mrq->stop)
 263                 cmdtype = 0x3;
 264
 265         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 266
 267         if (data) {
 268                 cmdreg |= DP_SELECT | MSBS | BCE;
 269                 if (data->flags & MMC_DATA_READ)
 270                         cmdreg |= DDIR;
 271                 else
 272                         cmdreg &= ~(DDIR);
 273         }
 274
 275         if (host->use_dma)
 276                 cmdreg |= DMA_EN;
 277
 278         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 279         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 280 }
 281
 282 static int
 283 mmc_omap_get_dma_dir(struct mmc_omap_host *host, struct mmc_data *data)
 284 {
 285         if (data->flags & MMC_DATA_WRITE)
 286                 return DMA_TO_DEVICE;
 287         else
 288                 return DMA_FROM_DEVICE;
 289 }
 290
 291 /*
 292  * Notify the transfer complete to MMC core
 293  */
 294 static void
 295 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 296 {
 297         if (!data) {
 298                 struct mmc_request *mrq = host->mrq;
 299
 300                 host->mrq = NULL;
 301                 mmc_omap_fclk_lazy_disable(host);
 302                 mmc_request_done(host->mmc, mrq);
 303                 return;
 304         }
 305
 306         host->data = NULL;
 307
 308         if (host->use_dma && host->dma_ch != -1)
 309                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 310                         mmc_omap_get_dma_dir(host, data));
 311
 312         if (!data->error)
 313                 data->bytes_xfered += data->blocks * (data->blksz);
 314         else
 315                 data->bytes_xfered = 0;
 316
 317         if (!data->stop) {
 318                 host->mrq = NULL;
 319                 mmc_request_done(host->mmc, data->mrq);
 320                 return;
 321         }
 322         mmc_omap_start_command(host, data->stop, NULL);
 323 }
 324
 325 /*
 326  * Notify the core about command completion
 327  */
 328 static void
 329 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 330 {
 331         host->cmd = NULL;
 332
 333         if (cmd->flags & MMC_RSP_PRESENT) {
 334                 if (cmd->flags & MMC_RSP_136) {
 335                         /* response type 2 */
 336                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 337                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 338                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 339                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 340                 } else {
 341                         /* response types 1, 1b, 3, 4, 5, 6 */
 342                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 343                 }
 344         }
 345         if ((host->data == NULL && !host->response_busy) || cmd->error) {
 346                 host->mrq = NULL;
 347                 mmc_request_done(host->mmc, cmd->mrq);
 348         }
 349 }
 350
 351 /*
 352  * DMA clean up for command errors
 353  */
 354 static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno)
 355 {
 356         host->data->error = errno;
 357
 358         if (host->use_dma && host->dma_ch != -1) {
 359                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 360                         mmc_omap_get_dma_dir(host, host->data));
 361                 omap_free_dma(host->dma_ch);
 362                 host->dma_ch = -1;
 363                 up(&host->sem);
 364         }
 365         host->data = NULL;
 366 }
 367
 368 /*
 369  * Readable error output
 370  */
 371 #ifdef CONFIG_MMC_DEBUG
 372 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 373 {
 374         /* --- means reserved bit without definition at documentation */
 375         static const char *mmc_omap_status_bits[] = {
 376                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 377                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 378                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 379                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 380         };
 381         char res[256];
 382         char *buf = res;
 383         int len, i;
 384
 385         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 386         buf += len;
 387
 388         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 389                 if (status & (1 << i)) {
 390                         len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
 391                         buf += len;
 392                 }
 393
 394         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
 395 }
 396 #endif  /* CONFIG_MMC_DEBUG */
 397
 398 /*
 399  * MMC controller internal state machines reset
 400  *
 401  * Used to reset command or data internal state machines, using respectively
 402  *  SRC or SRD bit of SYSCTL register
 403  * Can be called from interrupt context
 404  */
 405 static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
 406                 unsigned long bit)
 407 {
 408         unsigned long i = 0;
 409         unsigned long limit = (loops_per_jiffy *
 410                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
 411
 412         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 413                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 414
 415         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 416                 (i++ < limit))
 417                 cpu_relax();
 418
 419         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 420                 dev_err(mmc_dev(host->mmc),
 421                         "Timeout waiting on controller reset in %s\n",
 422                         __func__);
 423 }
 424
 425 /*
 426  * MMC controller IRQ handler
 427  */
 428 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 429 {
 430         struct mmc_omap_host *host = dev_id;
 431         struct mmc_data *data;
 432         int end_cmd = 0, end_trans = 0, status;
 433
 434         if (host->mrq == NULL) {
 435                 OMAP_HSMMC_WRITE(host->base, STAT,
 436                         OMAP_HSMMC_READ(host->base, STAT));
 437                 return IRQ_HANDLED;
 438         }
 439
 440         data = host->data;
 441         status = OMAP_HSMMC_READ(host->base, STAT);
 442         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 443
 444         if (status & ERR) {
 445 #ifdef CONFIG_MMC_DEBUG
 446                 mmc_omap_report_irq(host, status);
 447 #endif
 448                 if ((status & CMD_TIMEOUT) ||
 449                         (status & CMD_CRC)) {
 450                         if (host->cmd) {
 451                                 if (status & CMD_TIMEOUT) {
 452                                         mmc_omap_reset_controller_fsm(host, SRC);
 453                                         host->cmd->error = -ETIMEDOUT;
 454                                 } else {
 455                                         host->cmd->error = -EILSEQ;
 456                                 }
 457                                 end_cmd = 1;
 458                         }
 459                         if (host->data || host->response_busy) {
 460                                 if (host->data)
 461                                         mmc_dma_cleanup(host, -ETIMEDOUT);
 462                                 host->response_busy = 0;
 463                                 mmc_omap_reset_controller_fsm(host, SRD);
 464                         }
 465                 }
 466                 if ((status & DATA_TIMEOUT) ||
 467                         (status & DATA_CRC)) {
 468                         if (host->data || host->response_busy) {
 469                                 int err = (status & DATA_TIMEOUT) ?
 470                                                 -ETIMEDOUT : -EILSEQ;
 471
 472                                 if (host->data)
 473                                         mmc_dma_cleanup(host, err);
 474                                 else
 475                                         host->mrq->cmd->error = err;
 476                                 host->response_busy = 0;
 477                                 mmc_omap_reset_controller_fsm(host, SRD);
 478                                 end_trans = 1;
 479                         }
 480                 }
 481                 if (status & CARD_ERR) {
 482                         dev_dbg(mmc_dev(host->mmc),
 483                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 484                         if (host->cmd)
 485                                 end_cmd = 1;
 486                         if (host->data)
 487                                 end_trans = 1;
 488                 }
 489         }
 490
 491         OMAP_HSMMC_WRITE(host->base, STAT, status);
 492
 493         if (end_cmd || (status & CC))
 494                 mmc_omap_cmd_done(host, host->cmd);
 495         if (end_trans || (status & TC))
 496                 mmc_omap_xfer_done(host, data);
 497
 498         return IRQ_HANDLED;
 499 }
 500
 501 /*
 502  * Switch MMC interface voltage ... only relevant for MMC1.
 503  *
 504  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
 505  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
 506  * Some chips, like eMMC ones, use internal transceivers.
 507  */
 508 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 509 {
 510         u32 reg_val = 0;
 511         int ret;
 512
 513         /* Disable the clocks */
 514         clk_disable(host->fclk);
 515         clk_disable(host->iclk);
 516         clk_disable(host->dbclk);
 517
 518         /* Turn the power off */
 519         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 520         if (ret != 0)
 521                 goto err;
 522
 523         /* Turn the power ON with given VDD 1.8 or 3.0v */
 524         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 525         if (ret != 0)
 526                 goto err;
 527
 528         clk_enable(host->fclk);
 529         clk_enable(host->iclk);
 530         clk_enable(host->dbclk);
 531
 532         OMAP_HSMMC_WRITE(host->base, HCTL,
 533                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 534         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 535
 536         /*
 537          * If a MMC dual voltage card is detected, the set_ios fn calls
 538          * this fn with VDD bit set for 1.8V. Upon card removal from the
 539          * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
 540          *
 541          * Cope with a bit of slop in the range ... per data sheets:
 542          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
 543          *    but recommended values are 1.71V to 1.89V
 544          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
 545          *    but recommended values are 2.7V to 3.3V
 546          *
 547          * Board setup code shouldn't permit anything very out-of-range.
 548          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
 549          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
 550          */
 551         if ((1 << vdd) <= MMC_VDD_23_24)
 552                 reg_val |= SDVS18;
 553         else
 554                 reg_val |= SDVS30;
 555
 556         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 557
 558         OMAP_HSMMC_WRITE(host->base, HCTL,
 559                 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 560
 561         return 0;
 562 err:
 563         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 564         return ret;
 565 }
 566
 567 /*
 568  * Work Item to notify the core about card insertion/removal
 569  */
 570 static void mmc_omap_detect(struct work_struct *work)
 571 {
 572         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 573                                                 mmc_carddetect_work);
 574         struct omap_mmc_slot_data *slot = &mmc_slot(host);
 575
 576         if (mmc_slot(host).card_detect)
 577                 host->carddetect = slot->card_detect(slot->card_detect_irq);
 578         else
 579                 host->carddetect = -ENOSYS;
 580
 581         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 582         if (host->carddetect) {
 583                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 584         } else {
 585                 mmc_omap_reset_controller_fsm(host, SRD);
 586                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 587         }
 588 }
 589
 590 /*
 591  * ISR for handling card insertion and removal
 592  */
 593 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 594 {
 595         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 596
 597         schedule_work(&host->mmc_carddetect_work);
 598
 599         return IRQ_HANDLED;
 600 }
 601
 602 static int mmc_omap_get_dma_sync_dev(struct mmc_omap_host *host,
 603                                      struct mmc_data *data)
 604 {
 605         int sync_dev;
 606
 607         if (data->flags & MMC_DATA_WRITE)
 608                 sync_dev = host->dma_line_tx;
 609         else
 610                 sync_dev = host->dma_line_rx;
 611         return sync_dev;
 612 }
 613
 614 static void mmc_omap_config_dma_params(struct mmc_omap_host *host,
 615                                        struct mmc_data *data,
 616                                        struct scatterlist *sgl)
 617 {
 618         int blksz, nblk, dma_ch;
 619
 620         dma_ch = host->dma_ch;
 621         if (data->flags & MMC_DATA_WRITE) {
 622                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 623                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 624                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 625                         sg_dma_address(sgl), 0, 0);
 626         } else {
 627                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 628                                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 629                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 630                         sg_dma_address(sgl), 0, 0);
 631         }
 632
 633         blksz = host->data->blksz;
 634         nblk = sg_dma_len(sgl) / blksz;
 635
 636         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 637                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
 638                         mmc_omap_get_dma_sync_dev(host, data),
 639                         !(data->flags & MMC_DATA_WRITE));
 640
 641         omap_start_dma(dma_ch);
 642 }
 643
 644 /*
 645  * DMA call back function
 646  */
 647 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 648 {
 649         struct mmc_omap_host *host = data;
 650
 651         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 652                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 653
 654         if (host->dma_ch < 0)
 655                 return;
 656
 657         host->dma_sg_idx++;
 658         if (host->dma_sg_idx < host->dma_len) {
 659                 /* Fire up the next transfer. */
 660                 mmc_omap_config_dma_params(host, host->data,
 661                                            host->data->sg + host->dma_sg_idx);
 662                 return;
 663         }
 664
 665         omap_free_dma(host->dma_ch);
 666         host->dma_ch = -1;
 667         /*
 668          * DMA Callback: run in interrupt context.
 669          * mutex_unlock will through a kernel warning if used.
 670          */
 671         up(&host->sem);
 672 }
 673
 674 /*
 675  * Routine to configure and start DMA for the MMC card
 676  */
 677 static int
 678 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 679 {
 680         int dma_ch = 0, ret = 0, err = 1, i;
 681         struct mmc_data *data = req->data;
 682
 683         /* Sanity check: all the SG entries must be aligned by block size. */
 684         for (i = 0; i < host->dma_len; i++) {
 685                 struct scatterlist *sgl;
 686
 687                 sgl = data->sg + i;
 688                 if (sgl->length % data->blksz)
 689                         return -EINVAL;
 690         }
 691         if ((data->blksz % 4) != 0)
 692                 /* REVISIT: The MMC buffer increments only when MSB is written.
 693                  * Return error for blksz which is non multiple of four.
 694                  */
 695                 return -EINVAL;
 696
 697         /*
 698          * If for some reason the DMA transfer is still active,
 699          * we wait for timeout period and free the dma
 700          */
 701         if (host->dma_ch != -1) {
 702                 set_current_state(TASK_UNINTERRUPTIBLE);
 703                 schedule_timeout(100);
 704                 if (down_trylock(&host->sem)) {
 705                         omap_free_dma(host->dma_ch);
 706                         host->dma_ch = -1;
 707                         up(&host->sem);
 708                         return err;
 709                 }
 710         } else {
 711                 if (down_trylock(&host->sem))
 712                         return err;
 713         }
 714
 715         ret = omap_request_dma(mmc_omap_get_dma_sync_dev(host, data), "MMC/SD",
 716                                mmc_omap_dma_cb,host, &dma_ch);
 717         if (ret != 0) {
 718                 dev_err(mmc_dev(host->mmc),
 719                         "%s: omap_request_dma() failed with %d\n",
 720                         mmc_hostname(host->mmc), ret);
 721                 return ret;
 722         }
 723
 724         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 725                         data->sg_len, mmc_omap_get_dma_dir(host, data));
 726         host->dma_ch = dma_ch;
 727         host->dma_sg_idx = 0;
 728
 729         mmc_omap_config_dma_params(host, data, data->sg);
 730
 731         return 0;
 732 }
 733
 734 static void set_data_timeout(struct mmc_omap_host *host,
 735                              struct mmc_request *req)
 736 {
 737         unsigned int timeout, cycle_ns;
 738         uint32_t reg, clkd, dto = 0;
 739
 740         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
 741         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
 742         if (clkd == 0)
 743                 clkd = 1;
 744
 745         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
 746         timeout = req->data->timeout_ns / cycle_ns;
 747         timeout += req->data->timeout_clks;
 748         if (timeout) {
 749                 while ((timeout & 0x80000000) == 0) {
 750                         dto += 1;
 751                         timeout <<= 1;
 752                 }
 753                 dto = 31 - dto;
 754                 timeout <<= 1;
 755                 if (timeout && dto)
 756                         dto += 1;
 757                 if (dto >= 13)
 758                         dto -= 13;
 759                 else
 760                         dto = 0;
 761                 if (dto > 14)
 762                         dto = 14;
 763         }
 764
 765         reg &= ~DTO_MASK;
 766         reg |= dto << DTO_SHIFT;
 767         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
 768 }
 769
 770 /*
 771  * Configure block length for MMC/SD cards and initiate the transfer.
 772  */
 773 static int
 774 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 775 {
 776         int ret;
 777         host->data = req->data;
 778
 779         if (req->data == NULL) {
 780                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 781                 return 0;
 782         }
 783
 784         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 785                                         | (req->data->blocks << 16));
 786         set_data_timeout(host, req);
 787
 788         if (host->use_dma) {
 789                 ret = mmc_omap_start_dma_transfer(host, req);
 790                 if (ret != 0) {
 791                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 792                         return ret;
 793                 }
 794         }
 795         return 0;
 796 }
 797
 798 /*
 799  * Request function. for read/write operation
 800  */
 801 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 802 {
 803         struct mmc_omap_host *host = mmc_priv(mmc);
 804
 805         WARN_ON(host->mrq != NULL);
 806         host->mrq = req;
 807         mmc_omap_prepare_data(host, req);
 808         mmc_omap_start_command(host, req->cmd, req->data);
 809 }
 810
 811
 812 /* Routine to configure clock values. Exposed API to core */
 813 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 814 {
 815         struct mmc_omap_host *host = mmc_priv(mmc);
 816         u16 dsor = 0;
 817         unsigned long regval;
 818         unsigned long timeout;
 819         u32 con;
 820
 821         switch (ios->power_mode) {
 822         case MMC_POWER_OFF:
 823                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 824                 break;
 825         case MMC_POWER_UP:
 826                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 827                 break;
 828         }
 829
 830         con = OMAP_HSMMC_READ(host->base, CON);
 831         switch (mmc->ios.bus_width) {
 832         case MMC_BUS_WIDTH_8:
 833                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 834                 break;
 835         case MMC_BUS_WIDTH_4:
 836                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 837                 OMAP_HSMMC_WRITE(host->base, HCTL,
 838                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 839                 break;
 840         case MMC_BUS_WIDTH_1:
 841                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 842                 OMAP_HSMMC_WRITE(host->base, HCTL,
 843                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 844                 break;
 845         }
 846
 847         if (host->id == OMAP_MMC1_DEVID) {
 848                 /* Only MMC1 can interface at 3V without some flavor
 849                  * of external transceiver; but they all handle 1.8V.
 850                  */
 851                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 852                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 853                                 /*
 854                                  * The mmc_select_voltage fn of the core does
 855                                  * not seem to set the power_mode to
 856                                  * MMC_POWER_UP upon recalculating the voltage.
 857                                  * vdd 1.8v.
 858                                  */
 859                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 860                                         dev_dbg(mmc_dev(host->mmc),
 861                                                 "Switch operation failed\n");
 862                 }
 863         }
 864
 865         if (ios->clock) {
 866                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 867                 if (dsor < 1)
 868                         dsor = 1;
 869
 870                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 871                         dsor++;
 872
 873                 if (dsor > 250)
 874                         dsor = 250;
 875         }
 876         omap_mmc_stop_clock(host);
 877         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 878         regval = regval & ~(CLKD_MASK);
 879         regval = regval | (dsor << 6) | (DTO << 16);
 880         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 881         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 882                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 883
 884         /* Wait till the ICS bit is set */
 885         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 886         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 887                 && time_before(jiffies, timeout))
 888                 msleep(1);
 889
 890         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 891                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 892
 893         if (ios->power_mode == MMC_POWER_ON)
 894                 send_init_stream(host);
 895
 896         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 897                 OMAP_HSMMC_WRITE(host->base, CON,
 898                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 899 }
 900
 901 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
 902 {
 903         struct mmc_omap_host *host = mmc_priv(mmc);
 904         struct omap_mmc_platform_data *pdata = host->pdata;
 905
 906         if (!pdata->slots[0].card_detect)
 907                 return -ENOSYS;
 908         return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
 909 }
 910
 911 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
 912 {
 913         struct mmc_omap_host *host = mmc_priv(mmc);
 914         struct omap_mmc_platform_data *pdata = host->pdata;
 915
 916         if (!pdata->slots[0].get_ro)
 917                 return -ENOSYS;
 918         return pdata->slots[0].get_ro(host->dev, 0);
 919 }
 920
 921 static void omap_hsmmc_init(struct mmc_omap_host *host)
 922 {
 923         u32 hctl, capa, value;
 924
 925         /* Only MMC1 supports 3.0V */
 926         if (host->id == OMAP_MMC1_DEVID) {
 927                 hctl = SDVS30;
 928                 capa = VS30 | VS18;
 929         } else {
 930                 hctl = SDVS18;
 931                 capa = VS18;
 932         }
 933
 934         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
 935         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
 936
 937         value = OMAP_HSMMC_READ(host->base, CAPA);
 938         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
 939
 940         /* Set the controller to AUTO IDLE mode */
 941         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
 942         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
 943
 944         /* Set SD bus power bit */
 945         value = OMAP_HSMMC_READ(host->base, HCTL);
 946         OMAP_HSMMC_WRITE(host->base, HCTL, value | SDBP);
 947 }
 948
 949 static struct mmc_host_ops mmc_omap_ops = {
 950         .request = omap_mmc_request,
 951         .set_ios = omap_mmc_set_ios,
 952         .get_cd = omap_hsmmc_get_cd,
 953         .get_ro = omap_hsmmc_get_ro,
 954         /* NYET -- enable_sdio_irq */
 955 };
 956
 957 static int __init omap_mmc_probe(struct platform_device *pdev)
 958 {
 959         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 960         struct mmc_host *mmc;
 961         struct mmc_omap_host *host = NULL;
 962         struct resource *res;
 963         int ret = 0, irq;
 964
 965         if (pdata == NULL) {
 966                 dev_err(&pdev->dev, "Platform Data is missing\n");
 967                 return -ENXIO;
 968         }
 969
 970         if (pdata->nr_slots == 0) {
 971                 dev_err(&pdev->dev, "No Slots\n");
 972                 return -ENXIO;
 973         }
 974
 975         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 976         irq = platform_get_irq(pdev, 0);
 977         if (res == NULL || irq < 0)
 978                 return -ENXIO;
 979
 980         res = request_mem_region(res->start, res->end - res->start + 1,
 981                                                         pdev->name);
 982         if (res == NULL)
 983                 return -EBUSY;
 984
 985         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 986         if (!mmc) {
 987                 ret = -ENOMEM;
 988                 goto err;
 989         }
 990
 991         host            = mmc_priv(mmc);
 992         host->mmc       = mmc;
 993         host->pdata     = pdata;
 994         host->dev       = &pdev->dev;
 995         host->use_dma   = 1;
 996         host->dev->dma_mask = &pdata->dma_mask;
 997         host->dma_ch    = -1;
 998         host->irq       = irq;
 999         host->id        = pdev->id;
1000         host->slot_id   = 0;
1001         host->mapbase   = res->start;
1002         host->base      = ioremap(host->mapbase, SZ_4K);
1003
1004         platform_set_drvdata(pdev, host);
1005         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
1006
1007         mmc->ops        = &mmc_omap_ops;
1008         mmc->f_min      = 400000;
1009         mmc->f_max      = 52000000;
1010
1011         sema_init(&host->sem, 1);
1012
1013         host->iclk = clk_get(&pdev->dev, "mmchs_ick");
1014         if (IS_ERR(host->iclk)) {
1015                 ret = PTR_ERR(host->iclk);
1016                 host->iclk = NULL;
1017                 goto err1;
1018         }
1019         host->fclk = clk_get(&pdev->dev, "mmchs_fck");
1020         if (IS_ERR(host->fclk)) {
1021                 ret = PTR_ERR(host->fclk);
1022                 host->fclk = NULL;
1023                 clk_put(host->iclk);
1024                 goto err1;
1025         }
1026
1027         if (clk_enable(host->fclk) != 0) {
1028                 clk_put(host->iclk);
1029                 clk_put(host->fclk);
1030                 goto err1;
1031         }
1032
1033         if (clk_enable(host->iclk) != 0) {
1034                 clk_disable(host->fclk);
1035                 clk_put(host->iclk);
1036                 clk_put(host->fclk);
1037                 goto err1;
1038         }
1039
1040         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1041         /*
1042          * MMC can still work without debounce clock.
1043          */
1044         if (IS_ERR(host->dbclk))
1045                 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1046         else
1047                 if (clk_enable(host->dbclk) != 0)
1048                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1049                                                         " clk failed\n");
1050                 else
1051                         host->dbclk_enabled = 1;
1052
1053         /* Since we do only SG emulation, we can have as many segs
1054          * as we want. */
1055         mmc->max_phys_segs = 1024;
1056         mmc->max_hw_segs = 1024;
1057
1058         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1059         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1060         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1061         mmc->max_seg_size = mmc->max_req_size;
1062
1063         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1064         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1065
1066         if (pdata->slots[host->slot_id].wires >= 8)
1067                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1068         else if (pdata->slots[host->slot_id].wires >= 4)
1069                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1070
1071         omap_hsmmc_init(host);
1072
1073         /* Select DMA lines */
1074         switch (host->id) {
1075         case OMAP_MMC1_DEVID:
1076                 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1077                 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1078                 break;
1079         case OMAP_MMC2_DEVID:
1080                 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1081                 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1082                 break;
1083         case OMAP_MMC3_DEVID:
1084                 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
1085                 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
1086                 break;
1087         default:
1088                 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
1089                 goto err_irq;
1090         }
1091
1092         /* Request IRQ for MMC operations */
1093         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1094                         mmc_hostname(mmc), host);
1095         if (ret) {
1096                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1097                 goto err_irq;
1098         }
1099
1100         if (pdata->init != NULL) {
1101                 if (pdata->init(&pdev->dev) != 0) {
1102                         dev_dbg(mmc_dev(host->mmc),
1103                                 "Unable to configure MMC IRQs\n");
1104                         goto err_irq_cd_init;
1105                 }
1106         }
1107
1108         /* Request IRQ for card detect */
1109         if ((mmc_slot(host).card_detect_irq)) {
1110                 ret = request_irq(mmc_slot(host).card_detect_irq,
1111                                   omap_mmc_cd_handler,
1112                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1113                                           | IRQF_DISABLED,
1114                                   mmc_hostname(mmc), host);
1115                 if (ret) {
1116                         dev_dbg(mmc_dev(host->mmc),
1117                                 "Unable to grab MMC CD IRQ\n");
1118                         goto err_irq_cd;
1119                 }
1120         }
1121
1122         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1123         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1124
1125         mmc_add_host(mmc);
1126
1127         if (host->pdata->slots[host->slot_id].name != NULL) {
1128                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1129                 if (ret < 0)
1130                         goto err_slot_name;
1131         }
1132         if (mmc_slot(host).card_detect_irq &&
1133             host->pdata->slots[host->slot_id].get_cover_state) {
1134                 ret = device_create_file(&mmc->class_dev,
1135                                         &dev_attr_cover_switch);
1136                 if (ret < 0)
1137                         goto err_cover_switch;
1138         }
1139
1140         return 0;
1141
1142 err_cover_switch:
1143         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1144 err_slot_name:
1145         mmc_remove_host(mmc);
1146 err_irq_cd:
1147         free_irq(mmc_slot(host).card_detect_irq, host);
1148 err_irq_cd_init:
1149         free_irq(host->irq, host);
1150 err_irq:
1151         clk_disable(host->fclk);
1152         clk_disable(host->iclk);
1153         clk_put(host->fclk);
1154         clk_put(host->iclk);
1155         if (host->dbclk_enabled) {
1156                 clk_disable(host->dbclk);
1157                 clk_put(host->dbclk);
1158         }
1159
1160 err1:
1161         iounmap(host->base);
1162 err:
1163         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1164         release_mem_region(res->start, res->end - res->start + 1);
1165         if (host)
1166                 mmc_free_host(mmc);
1167         return ret;
1168 }
1169
1170 static int omap_mmc_remove(struct platform_device *pdev)
1171 {
1172         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1173         struct resource *res;
1174
1175         if (host) {
1176                 mmc_remove_host(host->mmc);
1177                 if (host->pdata->cleanup)
1178                         host->pdata->cleanup(&pdev->dev);
1179                 free_irq(host->irq, host);
1180                 if (mmc_slot(host).card_detect_irq)
1181                         free_irq(mmc_slot(host).card_detect_irq, host);
1182                 flush_scheduled_work();
1183
1184                 clk_disable(host->fclk);
1185                 clk_disable(host->iclk);
1186                 clk_put(host->fclk);
1187                 clk_put(host->iclk);
1188                 if (host->dbclk_enabled) {
1189                         clk_disable(host->dbclk);
1190                         clk_put(host->dbclk);
1191                 }
1192
1193                 mmc_free_host(host->mmc);
1194                 iounmap(host->base);
1195         }
1196
1197         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1198         if (res)
1199                 release_mem_region(res->start, res->end - res->start + 1);
1200         platform_set_drvdata(pdev, NULL);
1201
1202         return 0;
1203 }
1204
1205 #ifdef CONFIG_PM
1206 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1207 {
1208         int ret = 0;
1209         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1210
1211         if (host && host->suspended)
1212                 return 0;
1213
1214         if (host) {
1215                 ret = mmc_suspend_host(host->mmc, state);
1216                 if (ret == 0) {
1217                         host->suspended = 1;
1218
1219                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1220                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1221
1222                         if (host->pdata->suspend) {
1223                                 ret = host->pdata->suspend(&pdev->dev,
1224                                                                 host->slot_id);
1225                                 if (ret)
1226                                         dev_dbg(mmc_dev(host->mmc),
1227                                                 "Unable to handle MMC board"
1228                                                 " level suspend\n");
1229                         }
1230
1231                         OMAP_HSMMC_WRITE(host->base, HCTL,
1232                                          OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
1233                         clk_disable(host->fclk);
1234                         clk_disable(host->iclk);
1235                         clk_disable(host->dbclk);
1236                 }
1237
1238         }
1239         return ret;
1240 }
1241
1242 /* Routine to resume the MMC device */
1243 static int omap_mmc_resume(struct platform_device *pdev)
1244 {
1245         int ret = 0;
1246         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1247
1248         if (host && !host->suspended)
1249                 return 0;
1250
1251         if (host) {
1252
1253                 ret = clk_enable(host->fclk);
1254                 if (ret)
1255                         goto clk_en_err;
1256
1257                 ret = clk_enable(host->iclk);
1258                 if (ret) {
1259                         clk_disable(host->fclk);
1260                         clk_put(host->fclk);
1261                         goto clk_en_err;
1262                 }
1263
1264                 if (clk_enable(host->dbclk) != 0)
1265                         dev_dbg(mmc_dev(host->mmc),
1266                                         "Enabling debounce clk failed\n");
1267
1268                 omap_hsmmc_init(host);
1269
1270                 if (host->pdata->resume) {
1271                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1272                         if (ret)
1273                                 dev_dbg(mmc_dev(host->mmc),
1274                                         "Unmask interrupt failed\n");
1275                 }
1276
1277                 /* Notify the core to resume the host */
1278                 ret = mmc_resume_host(host->mmc);
1279                 if (ret == 0)
1280                         host->suspended = 0;
1281         }
1282
1283         return ret;
1284
1285 clk_en_err:
1286         dev_dbg(mmc_dev(host->mmc),
1287                 "Failed to enable MMC clocks during resume\n");
1288         return ret;
1289 }
1290
1291 #else
1292 #define omap_mmc_suspend        NULL
1293 #define omap_mmc_resume         NULL
1294 #endif
1295
1296 static struct platform_driver omap_mmc_driver = {
1297         .probe          = omap_mmc_probe,
1298         .remove         = omap_mmc_remove,
1299         .suspend        = omap_mmc_suspend,
1300         .resume         = omap_mmc_resume,
1301         .driver         = {
1302                 .name = DRIVER_NAME,
1303                 .owner = THIS_MODULE,
1304         },
1305 };
1306
1307 static int __init omap_mmc_init(void)
1308 {
1309         /* Register the MMC driver */
1310         return platform_driver_register(&omap_mmc_driver);
1311 }
1312
1313 static void __exit omap_mmc_cleanup(void)
1314 {
1315         /* Unregister MMC driver */
1316         platform_driver_unregister(&omap_mmc_driver);
1317 }
1318
1319 module_init(omap_mmc_init);
1320 module_exit(omap_mmc_cleanup);
1321
1322 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1323 MODULE_LICENSE("GPL");
1324 MODULE_ALIAS("platform:" DRIVER_NAME);
1325 MODULE_AUTHOR("Texas Instruments Inc");