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   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/timer.h>
  28 #include <linux/clk.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/io.h>
  31 #include <linux/semaphore.h>
  32 #include <mach/dma.h>
  33 #include <mach/hardware.h>
  34 #include <mach/board.h>
  35 #include <mach/mmc.h>
  36 #include <mach/cpu.h>
  37
  38 /* OMAP HSMMC Host Controller Registers */
  39 #define OMAP_HSMMC_SYSCONFIG    0x0010
  40 #define OMAP_HSMMC_CON          0x002C
  41 #define OMAP_HSMMC_BLK          0x0104
  42 #define OMAP_HSMMC_ARG          0x0108
  43 #define OMAP_HSMMC_CMD          0x010C
  44 #define OMAP_HSMMC_RSP10        0x0110
  45 #define OMAP_HSMMC_RSP32        0x0114
  46 #define OMAP_HSMMC_RSP54        0x0118
  47 #define OMAP_HSMMC_RSP76        0x011C
  48 #define OMAP_HSMMC_DATA         0x0120
  49 #define OMAP_HSMMC_HCTL         0x0128
  50 #define OMAP_HSMMC_SYSCTL       0x012C
  51 #define OMAP_HSMMC_STAT         0x0130
  52 #define OMAP_HSMMC_IE           0x0134
  53 #define OMAP_HSMMC_ISE          0x0138
  54 #define OMAP_HSMMC_CAPA         0x0140
  55
  56 #define VS18                    (1 << 26)
  57 #define VS30                    (1 << 25)
  58 #define SDVS18                  (0x5 << 9)
  59 #define SDVS30                  (0x6 << 9)
  60 #define SDVS33                  (0x7 << 9)
  61 #define SDVS_MASK               0x00000E00
  62 #define SDVSCLR                 0xFFFFF1FF
  63 #define SDVSDET                 0x00000400
  64 #define AUTOIDLE                0x1
  65 #define SDBP                    (1 << 8)
  66 #define DTO                     0xe
  67 #define ICE                     0x1
  68 #define ICS                     0x2
  69 #define CEN                     (1 << 2)
  70 #define CLKD_MASK               0x0000FFC0
  71 #define CLKD_SHIFT              6
  72 #define DTO_MASK                0x000F0000
  73 #define DTO_SHIFT               16
  74 #define INT_EN_MASK             0x307F0033
  75 #define BWR_ENABLE              (1 << 4)
  76 #define BRR_ENABLE              (1 << 5)
  77 #define INIT_STREAM             (1 << 1)
  78 #define DP_SELECT               (1 << 21)
  79 #define DDIR                    (1 << 4)
  80 #define DMA_EN                  0x1
  81 #define MSBS                    (1 << 5)
  82 #define BCE                     (1 << 1)
  83 #define FOUR_BIT                (1 << 1)
  84 #define DW8                     (1 << 5)
  85 #define CC                      0x1
  86 #define TC                      0x02
  87 #define OD                      0x1
  88 #define ERR                     (1 << 15)
  89 #define CMD_TIMEOUT             (1 << 16)
  90 #define DATA_TIMEOUT            (1 << 20)
  91 #define CMD_CRC                 (1 << 17)
  92 #define DATA_CRC                (1 << 21)
  93 #define CARD_ERR                (1 << 28)
  94 #define STAT_CLEAR              0xFFFFFFFF
  95 #define INIT_STREAM_CMD         0x00000000
  96 #define DUAL_VOLT_OCR_BIT       7
  97 #define SRC                     (1 << 25)
  98 #define SRD                     (1 << 26)
  99
 100 /*
 101  * FIXME: Most likely all the data using these _DEVID defines should come
 102  * from the platform_data, or implemented in controller and slot specific
 103  * functions.
 104  */
 105 #define OMAP_MMC1_DEVID         0
 106 #define OMAP_MMC2_DEVID         1
 107 #define OMAP_MMC3_DEVID         2
 108
 109 #define MMC_TIMEOUT_MS          20
 110 #define OMAP_MMC_MASTER_CLOCK   96000000
 111 #define DRIVER_NAME             "mmci-omap-hs"
 112
 113 /*
 114  * One controller can have multiple slots, like on some omap boards using
 115  * omap.c controller driver. Luckily this is not currently done on any known
 116  * omap_hsmmc.c device.
 117  */
 118 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 119
 120 /*
 121  * MMC Host controller read/write API's
 122  */
 123 #define OMAP_HSMMC_READ(base, reg)      \
 124         __raw_readl((base) + OMAP_HSMMC_##reg)
 125
 126 #define OMAP_HSMMC_WRITE(base, reg, val) \
 127         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 128
 129 struct mmc_omap_host {
 130         struct  device          *dev;
 131         struct  mmc_host        *mmc;
 132         struct  mmc_request     *mrq;
 133         struct  mmc_command     *cmd;
 134         struct  mmc_data        *data;
 135         struct  clk             *fclk;
 136         struct  clk             *iclk;
 137         struct  clk             *dbclk;
 138         struct  semaphore       sem;
 139         struct  work_struct     mmc_carddetect_work;
 140         void    __iomem         *base;
 141         resource_size_t         mapbase;
 142         unsigned int            id;
 143         unsigned int            dma_len;
 144         unsigned int            dma_sg_idx;
 145         unsigned char           bus_mode;
 146         u32                     *buffer;
 147         u32                     bytesleft;
 148         int                     suspended;
 149         int                     irq;
 150         int                     carddetect;
 151         int                     use_dma, dma_ch;
 152         int                     dma_line_tx, dma_line_rx;
 153         int                     slot_id;
 154         int                     dbclk_enabled;
 155         int                     response_busy;
 156         struct  omap_mmc_platform_data  *pdata;
 157 };
 158
 159 /*
 160  * Stop clock to the card
 161  */
 162 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 163 {
 164         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 165                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 166         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 167                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 168 }
 169
 170 /*
 171  * Send init stream sequence to card
 172  * before sending IDLE command
 173  */
 174 static void send_init_stream(struct mmc_omap_host *host)
 175 {
 176         int reg = 0;
 177         unsigned long timeout;
 178
 179         disable_irq(host->irq);
 180         OMAP_HSMMC_WRITE(host->base, CON,
 181                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 182         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 183
 184         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 185         while ((reg != CC) && time_before(jiffies, timeout))
 186                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 187
 188         OMAP_HSMMC_WRITE(host->base, CON,
 189                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 190         enable_irq(host->irq);
 191 }
 192
 193 static inline
 194 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
 195 {
 196         int r = 1;
 197
 198         if (host->pdata->slots[host->slot_id].get_cover_state)
 199                 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
 200                         host->slot_id);
 201         return r;
 202 }
 203
 204 static ssize_t
 205 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 206                            char *buf)
 207 {
 208         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 209         struct mmc_omap_host *host = mmc_priv(mmc);
 210
 211         return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
 212                        "open");
 213 }
 214
 215 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 216
 217 static ssize_t
 218 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 219                         char *buf)
 220 {
 221         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 222         struct mmc_omap_host *host = mmc_priv(mmc);
 223         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 224
 225         return sprintf(buf, "%s\n", slot.name);
 226 }
 227
 228 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 229
 230 /*
 231  * Configure the response type and send the cmd.
 232  */
 233 static void
 234 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 235         struct mmc_data *data)
 236 {
 237         int cmdreg = 0, resptype = 0, cmdtype = 0;
 238
 239         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 240                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 241         host->cmd = cmd;
 242
 243         /*
 244          * Clear status bits and enable interrupts
 245          */
 246         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 247         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 248
 249         if (host->use_dma)
 250                 OMAP_HSMMC_WRITE(host->base, IE,
 251                                  INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
 252         else
 253                 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 254
 255         host->response_busy = 0;
 256         if (cmd->flags & MMC_RSP_PRESENT) {
 257                 if (cmd->flags & MMC_RSP_136)
 258                         resptype = 1;
 259                 else if (cmd->flags & MMC_RSP_BUSY) {
 260                         resptype = 3;
 261                         host->response_busy = 1;
 262                 } else
 263                         resptype = 2;
 264         }
 265
 266         /*
 267          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 268          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 269          * a val of 0x3, rest 0x0.
 270          */
 271         if (cmd == host->mrq->stop)
 272                 cmdtype = 0x3;
 273
 274         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 275
 276         if (data) {
 277                 cmdreg |= DP_SELECT | MSBS | BCE;
 278                 if (data->flags & MMC_DATA_READ)
 279                         cmdreg |= DDIR;
 280                 else
 281                         cmdreg &= ~(DDIR);
 282         }
 283
 284         if (host->use_dma)
 285                 cmdreg |= DMA_EN;
 286
 287         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 288         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 289 }
 290
 291 static int
 292 mmc_omap_get_dma_dir(struct mmc_omap_host *host, struct mmc_data *data)
 293 {
 294         if (data->flags & MMC_DATA_WRITE)
 295                 return DMA_TO_DEVICE;
 296         else
 297                 return DMA_FROM_DEVICE;
 298 }
 299
 300 /*
 301  * Notify the transfer complete to MMC core
 302  */
 303 static void
 304 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 305 {
 306         if (!data) {
 307                 struct mmc_request *mrq = host->mrq;
 308
 309                 host->mrq = NULL;
 310                 mmc_request_done(host->mmc, mrq);
 311                 return;
 312         }
 313
 314         host->data = NULL;
 315
 316         if (host->use_dma && host->dma_ch != -1)
 317                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 318                         mmc_omap_get_dma_dir(host, data));
 319
 320         if (!data->error)
 321                 data->bytes_xfered += data->blocks * (data->blksz);
 322         else
 323                 data->bytes_xfered = 0;
 324
 325         if (!data->stop) {
 326                 host->mrq = NULL;
 327                 mmc_request_done(host->mmc, data->mrq);
 328                 return;
 329         }
 330         mmc_omap_start_command(host, data->stop, NULL);
 331 }
 332
 333 /*
 334  * Notify the core about command completion
 335  */
 336 static void
 337 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 338 {
 339         host->cmd = NULL;
 340
 341         if (cmd->flags & MMC_RSP_PRESENT) {
 342                 if (cmd->flags & MMC_RSP_136) {
 343                         /* response type 2 */
 344                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 345                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 346                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 347                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 348                 } else {
 349                         /* response types 1, 1b, 3, 4, 5, 6 */
 350                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 351                 }
 352         }
 353         if ((host->data == NULL && !host->response_busy) || cmd->error) {
 354                 host->mrq = NULL;
 355                 mmc_request_done(host->mmc, cmd->mrq);
 356         }
 357 }
 358
 359 /*
 360  * DMA clean up for command errors
 361  */
 362 static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno)
 363 {
 364         host->data->error = errno;
 365
 366         if (host->use_dma && host->dma_ch != -1) {
 367                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 368                         mmc_omap_get_dma_dir(host, host->data));
 369                 omap_free_dma(host->dma_ch);
 370                 host->dma_ch = -1;
 371                 up(&host->sem);
 372         }
 373         host->data = NULL;
 374 }
 375
 376 /*
 377  * Readable error output
 378  */
 379 #ifdef CONFIG_MMC_DEBUG
 380 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 381 {
 382         /* --- means reserved bit without definition at documentation */
 383         static const char *mmc_omap_status_bits[] = {
 384                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 385                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 386                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 387                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 388         };
 389         char res[256];
 390         char *buf = res;
 391         int len, i;
 392
 393         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 394         buf += len;
 395
 396         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 397                 if (status & (1 << i)) {
 398                         len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
 399                         buf += len;
 400                 }
 401
 402         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
 403 }
 404 #endif  /* CONFIG_MMC_DEBUG */
 405
 406 /*
 407  * MMC controller internal state machines reset
 408  *
 409  * Used to reset command or data internal state machines, using respectively
 410  *  SRC or SRD bit of SYSCTL register
 411  * Can be called from interrupt context
 412  */
 413 static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
 414                 unsigned long bit)
 415 {
 416         unsigned long i = 0;
 417         unsigned long limit = (loops_per_jiffy *
 418                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
 419
 420         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 421                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 422
 423         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 424                 (i++ < limit))
 425                 cpu_relax();
 426
 427         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 428                 dev_err(mmc_dev(host->mmc),
 429                         "Timeout waiting on controller reset in %s\n",
 430                         __func__);
 431 }
 432
 433 /*
 434  * MMC controller IRQ handler
 435  */
 436 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 437 {
 438         struct mmc_omap_host *host = dev_id;
 439         struct mmc_data *data;
 440         int end_cmd = 0, end_trans = 0, status;
 441
 442         if (host->mrq == NULL) {
 443                 OMAP_HSMMC_WRITE(host->base, STAT,
 444                         OMAP_HSMMC_READ(host->base, STAT));
 445                 /* Flush posted write */
 446                 OMAP_HSMMC_READ(host->base, STAT);
 447                 return IRQ_HANDLED;
 448         }
 449
 450         data = host->data;
 451         status = OMAP_HSMMC_READ(host->base, STAT);
 452         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 453
 454         if (status & ERR) {
 455 #ifdef CONFIG_MMC_DEBUG
 456                 mmc_omap_report_irq(host, status);
 457 #endif
 458                 if ((status & CMD_TIMEOUT) ||
 459                         (status & CMD_CRC)) {
 460                         if (host->cmd) {
 461                                 if (status & CMD_TIMEOUT) {
 462                                         mmc_omap_reset_controller_fsm(host, SRC);
 463                                         host->cmd->error = -ETIMEDOUT;
 464                                 } else {
 465                                         host->cmd->error = -EILSEQ;
 466                                 }
 467                                 end_cmd = 1;
 468                         }
 469                         if (host->data || host->response_busy) {
 470                                 if (host->data)
 471                                         mmc_dma_cleanup(host, -ETIMEDOUT);
 472                                 host->response_busy = 0;
 473                                 mmc_omap_reset_controller_fsm(host, SRD);
 474                         }
 475                 }
 476                 if ((status & DATA_TIMEOUT) ||
 477                         (status & DATA_CRC)) {
 478                         if (host->data || host->response_busy) {
 479                                 int err = (status & DATA_TIMEOUT) ?
 480                                                 -ETIMEDOUT : -EILSEQ;
 481
 482                                 if (host->data)
 483                                         mmc_dma_cleanup(host, err);
 484                                 else
 485                                         host->mrq->cmd->error = err;
 486                                 host->response_busy = 0;
 487                                 mmc_omap_reset_controller_fsm(host, SRD);
 488                                 end_trans = 1;
 489                         }
 490                 }
 491                 if (status & CARD_ERR) {
 492                         dev_dbg(mmc_dev(host->mmc),
 493                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 494                         if (host->cmd)
 495                                 end_cmd = 1;
 496                         if (host->data)
 497                                 end_trans = 1;
 498                 }
 499         }
 500
 501         OMAP_HSMMC_WRITE(host->base, STAT, status);
 502         /* Flush posted write */
 503         OMAP_HSMMC_READ(host->base, STAT);
 504
 505         if (end_cmd || ((status & CC) && host->cmd))
 506                 mmc_omap_cmd_done(host, host->cmd);
 507         if (end_trans || (status & TC))
 508                 mmc_omap_xfer_done(host, data);
 509
 510         return IRQ_HANDLED;
 511 }
 512
 513 static void set_sd_bus_power(struct mmc_omap_host *host)
 514 {
 515         unsigned long i;
 516
 517         OMAP_HSMMC_WRITE(host->base, HCTL,
 518                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 519         for (i = 0; i < loops_per_jiffy; i++) {
 520                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
 521                         break;
 522                 cpu_relax();
 523         }
 524 }
 525
 526 /*
 527  * Switch MMC interface voltage ... only relevant for MMC1.
 528  *
 529  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
 530  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
 531  * Some chips, like eMMC ones, use internal transceivers.
 532  */
 533 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 534 {
 535         u32 reg_val = 0;
 536         int ret;
 537
 538         /* Disable the clocks */
 539         clk_disable(host->fclk);
 540         clk_disable(host->iclk);
 541         clk_disable(host->dbclk);
 542
 543         /* Turn the power off */
 544         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 545         if (ret != 0)
 546                 goto err;
 547
 548         /* Turn the power ON with given VDD 1.8 or 3.0v */
 549         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 550         if (ret != 0)
 551                 goto err;
 552
 553         clk_enable(host->fclk);
 554         clk_enable(host->iclk);
 555         clk_enable(host->dbclk);
 556
 557         OMAP_HSMMC_WRITE(host->base, HCTL,
 558                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 559         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 560
 561         /*
 562          * If a MMC dual voltage card is detected, the set_ios fn calls
 563          * this fn with VDD bit set for 1.8V. Upon card removal from the
 564          * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
 565          *
 566          * Cope with a bit of slop in the range ... per data sheets:
 567          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
 568          *    but recommended values are 1.71V to 1.89V
 569          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
 570          *    but recommended values are 2.7V to 3.3V
 571          *
 572          * Board setup code shouldn't permit anything very out-of-range.
 573          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
 574          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
 575          */
 576         if ((1 << vdd) <= MMC_VDD_23_24)
 577                 reg_val |= SDVS18;
 578         else
 579                 reg_val |= SDVS30;
 580
 581         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 582         set_sd_bus_power(host);
 583
 584         return 0;
 585 err:
 586         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 587         return ret;
 588 }
 589
 590 /*
 591  * Work Item to notify the core about card insertion/removal
 592  */
 593 static void mmc_omap_detect(struct work_struct *work)
 594 {
 595         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 596                                                 mmc_carddetect_work);
 597         struct omap_mmc_slot_data *slot = &mmc_slot(host);
 598
 599         if (mmc_slot(host).card_detect)
 600                 host->carddetect = slot->card_detect(slot->card_detect_irq);
 601         else
 602                 host->carddetect = -ENOSYS;
 603
 604         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 605         if (host->carddetect) {
 606                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 607         } else {
 608                 mmc_omap_reset_controller_fsm(host, SRD);
 609                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 610         }
 611 }
 612
 613 /*
 614  * ISR for handling card insertion and removal
 615  */
 616 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 617 {
 618         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 619
 620         schedule_work(&host->mmc_carddetect_work);
 621
 622         return IRQ_HANDLED;
 623 }
 624
 625 static int mmc_omap_get_dma_sync_dev(struct mmc_omap_host *host,
 626                                      struct mmc_data *data)
 627 {
 628         int sync_dev;
 629
 630         if (data->flags & MMC_DATA_WRITE)
 631                 sync_dev = host->dma_line_tx;
 632         else
 633                 sync_dev = host->dma_line_rx;
 634         return sync_dev;
 635 }
 636
 637 static void mmc_omap_config_dma_params(struct mmc_omap_host *host,
 638                                        struct mmc_data *data,
 639                                        struct scatterlist *sgl)
 640 {
 641         int blksz, nblk, dma_ch;
 642
 643         dma_ch = host->dma_ch;
 644         if (data->flags & MMC_DATA_WRITE) {
 645                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 646                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 647                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 648                         sg_dma_address(sgl), 0, 0);
 649         } else {
 650                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 651                                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 652                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 653                         sg_dma_address(sgl), 0, 0);
 654         }
 655
 656         blksz = host->data->blksz;
 657         nblk = sg_dma_len(sgl) / blksz;
 658
 659         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 660                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
 661                         mmc_omap_get_dma_sync_dev(host, data),
 662                         !(data->flags & MMC_DATA_WRITE));
 663
 664         omap_start_dma(dma_ch);
 665 }
 666
 667 /*
 668  * DMA call back function
 669  */
 670 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 671 {
 672         struct mmc_omap_host *host = data;
 673
 674         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 675                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 676
 677         if (host->dma_ch < 0)
 678                 return;
 679
 680         host->dma_sg_idx++;
 681         if (host->dma_sg_idx < host->dma_len) {
 682                 /* Fire up the next transfer. */
 683                 mmc_omap_config_dma_params(host, host->data,
 684                                            host->data->sg + host->dma_sg_idx);
 685                 return;
 686         }
 687
 688         omap_free_dma(host->dma_ch);
 689         host->dma_ch = -1;
 690         /*
 691          * DMA Callback: run in interrupt context.
 692          * mutex_unlock will throw a kernel warning if used.
 693          */
 694         up(&host->sem);
 695 }
 696
 697 /*
 698  * Routine to configure and start DMA for the MMC card
 699  */
 700 static int
 701 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 702 {
 703         int dma_ch = 0, ret = 0, err = 1, i;
 704         struct mmc_data *data = req->data;
 705
 706         /* Sanity check: all the SG entries must be aligned by block size. */
 707         for (i = 0; i < host->dma_len; i++) {
 708                 struct scatterlist *sgl;
 709
 710                 sgl = data->sg + i;
 711                 if (sgl->length % data->blksz)
 712                         return -EINVAL;
 713         }
 714         if ((data->blksz % 4) != 0)
 715                 /* REVISIT: The MMC buffer increments only when MSB is written.
 716                  * Return error for blksz which is non multiple of four.
 717                  */
 718                 return -EINVAL;
 719
 720         /*
 721          * If for some reason the DMA transfer is still active,
 722          * we wait for timeout period and free the dma
 723          */
 724         if (host->dma_ch != -1) {
 725                 set_current_state(TASK_UNINTERRUPTIBLE);
 726                 schedule_timeout(100);
 727                 if (down_trylock(&host->sem)) {
 728                         omap_free_dma(host->dma_ch);
 729                         host->dma_ch = -1;
 730                         up(&host->sem);
 731                         return err;
 732                 }
 733         } else {
 734                 if (down_trylock(&host->sem))
 735                         return err;
 736         }
 737
 738         ret = omap_request_dma(mmc_omap_get_dma_sync_dev(host, data), "MMC/SD",
 739                                mmc_omap_dma_cb,host, &dma_ch);
 740         if (ret != 0) {
 741                 dev_err(mmc_dev(host->mmc),
 742                         "%s: omap_request_dma() failed with %d\n",
 743                         mmc_hostname(host->mmc), ret);
 744                 return ret;
 745         }
 746
 747         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 748                         data->sg_len, mmc_omap_get_dma_dir(host, data));
 749         host->dma_ch = dma_ch;
 750         host->dma_sg_idx = 0;
 751
 752         mmc_omap_config_dma_params(host, data, data->sg);
 753
 754         return 0;
 755 }
 756
 757 static void set_data_timeout(struct mmc_omap_host *host,
 758                              struct mmc_request *req)
 759 {
 760         unsigned int timeout, cycle_ns;
 761         uint32_t reg, clkd, dto = 0;
 762
 763         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
 764         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
 765         if (clkd == 0)
 766                 clkd = 1;
 767
 768         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
 769         timeout = req->data->timeout_ns / cycle_ns;
 770         timeout += req->data->timeout_clks;
 771         if (timeout) {
 772                 while ((timeout & 0x80000000) == 0) {
 773                         dto += 1;
 774                         timeout <<= 1;
 775                 }
 776                 dto = 31 - dto;
 777                 timeout <<= 1;
 778                 if (timeout && dto)
 779                         dto += 1;
 780                 if (dto >= 13)
 781                         dto -= 13;
 782                 else
 783                         dto = 0;
 784                 if (dto > 14)
 785                         dto = 14;
 786         }
 787
 788         reg &= ~DTO_MASK;
 789         reg |= dto << DTO_SHIFT;
 790         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
 791 }
 792
 793 /*
 794  * Configure block length for MMC/SD cards and initiate the transfer.
 795  */
 796 static int
 797 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 798 {
 799         int ret;
 800         host->data = req->data;
 801
 802         if (req->data == NULL) {
 803                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 804                 return 0;
 805         }
 806
 807         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 808                                         | (req->data->blocks << 16));
 809         set_data_timeout(host, req);
 810
 811         if (host->use_dma) {
 812                 ret = mmc_omap_start_dma_transfer(host, req);
 813                 if (ret != 0) {
 814                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 815                         return ret;
 816                 }
 817         }
 818         return 0;
 819 }
 820
 821 /*
 822  * Request function. for read/write operation
 823  */
 824 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 825 {
 826         struct mmc_omap_host *host = mmc_priv(mmc);
 827
 828         WARN_ON(host->mrq != NULL);
 829         host->mrq = req;
 830         mmc_omap_prepare_data(host, req);
 831         mmc_omap_start_command(host, req->cmd, req->data);
 832 }
 833
 834
 835 /* Routine to configure clock values. Exposed API to core */
 836 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 837 {
 838         struct mmc_omap_host *host = mmc_priv(mmc);
 839         u16 dsor = 0;
 840         unsigned long regval;
 841         unsigned long timeout;
 842         u32 con;
 843
 844         switch (ios->power_mode) {
 845         case MMC_POWER_OFF:
 846                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 847                 break;
 848         case MMC_POWER_UP:
 849                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 850                 break;
 851         }
 852
 853         con = OMAP_HSMMC_READ(host->base, CON);
 854         switch (mmc->ios.bus_width) {
 855         case MMC_BUS_WIDTH_8:
 856                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 857                 break;
 858         case MMC_BUS_WIDTH_4:
 859                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 860                 OMAP_HSMMC_WRITE(host->base, HCTL,
 861                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 862                 break;
 863         case MMC_BUS_WIDTH_1:
 864                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 865                 OMAP_HSMMC_WRITE(host->base, HCTL,
 866                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 867                 break;
 868         }
 869
 870         if (host->id == OMAP_MMC1_DEVID) {
 871                 /* Only MMC1 can interface at 3V without some flavor
 872                  * of external transceiver; but they all handle 1.8V.
 873                  */
 874                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 875                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 876                                 /*
 877                                  * The mmc_select_voltage fn of the core does
 878                                  * not seem to set the power_mode to
 879                                  * MMC_POWER_UP upon recalculating the voltage.
 880                                  * vdd 1.8v.
 881                                  */
 882                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 883                                         dev_dbg(mmc_dev(host->mmc),
 884                                                 "Switch operation failed\n");
 885                 }
 886         }
 887
 888         if (ios->clock) {
 889                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 890                 if (dsor < 1)
 891                         dsor = 1;
 892
 893                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 894                         dsor++;
 895
 896                 if (dsor > 250)
 897                         dsor = 250;
 898         }
 899         omap_mmc_stop_clock(host);
 900         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 901         regval = regval & ~(CLKD_MASK);
 902         regval = regval | (dsor << 6) | (DTO << 16);
 903         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 904         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 905                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 906
 907         /* Wait till the ICS bit is set */
 908         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 909         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 910                 && time_before(jiffies, timeout))
 911                 msleep(1);
 912
 913         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 914                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 915
 916         if (ios->power_mode == MMC_POWER_ON)
 917                 send_init_stream(host);
 918
 919         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 920                 OMAP_HSMMC_WRITE(host->base, CON,
 921                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 922 }
 923
 924 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
 925 {
 926         struct mmc_omap_host *host = mmc_priv(mmc);
 927         struct omap_mmc_platform_data *pdata = host->pdata;
 928
 929         if (!pdata->slots[0].card_detect)
 930                 return -ENOSYS;
 931         return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
 932 }
 933
 934 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
 935 {
 936         struct mmc_omap_host *host = mmc_priv(mmc);
 937         struct omap_mmc_platform_data *pdata = host->pdata;
 938
 939         if (!pdata->slots[0].get_ro)
 940                 return -ENOSYS;
 941         return pdata->slots[0].get_ro(host->dev, 0);
 942 }
 943
 944 static void omap_hsmmc_init(struct mmc_omap_host *host)
 945 {
 946         u32 hctl, capa, value;
 947
 948         /* Only MMC1 supports 3.0V */
 949         if (host->id == OMAP_MMC1_DEVID) {
 950                 hctl = SDVS30;
 951                 capa = VS30 | VS18;
 952         } else {
 953                 hctl = SDVS18;
 954                 capa = VS18;
 955         }
 956
 957         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
 958         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
 959
 960         value = OMAP_HSMMC_READ(host->base, CAPA);
 961         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
 962
 963         /* Set the controller to AUTO IDLE mode */
 964         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
 965         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
 966
 967         /* Set SD bus power bit */
 968         set_sd_bus_power(host);
 969 }
 970
 971 static struct mmc_host_ops mmc_omap_ops = {
 972         .request = omap_mmc_request,
 973         .set_ios = omap_mmc_set_ios,
 974         .get_cd = omap_hsmmc_get_cd,
 975         .get_ro = omap_hsmmc_get_ro,
 976         /* NYET -- enable_sdio_irq */
 977 };
 978
 979 #ifdef CONFIG_DEBUG_FS
 980
 981 static int mmc_regs_show(struct seq_file *s, void *data)
 982 {
 983         struct mmc_host *mmc = s->private;
 984         struct mmc_omap_host *host = mmc_priv(mmc);
 985
 986         seq_printf(s, "mmc%d regs:\n", mmc->index);
 987
 988         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
 989                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
 990         seq_printf(s, "CON:\t\t0x%08x\n",
 991                         OMAP_HSMMC_READ(host->base, CON));
 992         seq_printf(s, "HCTL:\t\t0x%08x\n",
 993                         OMAP_HSMMC_READ(host->base, HCTL));
 994         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
 995                         OMAP_HSMMC_READ(host->base, SYSCTL));
 996         seq_printf(s, "IE:\t\t0x%08x\n",
 997                         OMAP_HSMMC_READ(host->base, IE));
 998         seq_printf(s, "ISE:\t\t0x%08x\n",
 999                         OMAP_HSMMC_READ(host->base, ISE));
1000         seq_printf(s, "CAPA:\t\t0x%08x\n",
1001                         OMAP_HSMMC_READ(host->base, CAPA));
1002         return 0;
1003 }
1004
1005 static int mmc_regs_open(struct inode *inode, struct file *file)
1006 {
1007         return single_open(file, mmc_regs_show, inode->i_private);
1008 }
1009
1010 static const struct file_operations mmc_regs_fops = {
1011         .open           = mmc_regs_open,
1012         .read           = seq_read,
1013         .llseek         = seq_lseek,
1014         .release        = single_release,
1015 };
1016
1017 static void omap_mmc_debugfs(struct mmc_host *mmc)
1018 {
1019         if (mmc->debugfs_root)
1020                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1021                         mmc, &mmc_regs_fops);
1022 }
1023
1024 #else
1025
1026 static void omap_mmc_debugfs(struct mmc_host *mmc)
1027 {
1028 }
1029
1030 #endif
1031
1032 static int __init omap_mmc_probe(struct platform_device *pdev)
1033 {
1034         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1035         struct mmc_host *mmc;
1036         struct mmc_omap_host *host = NULL;
1037         struct resource *res;
1038         int ret = 0, irq;
1039
1040         if (pdata == NULL) {
1041                 dev_err(&pdev->dev, "Platform Data is missing\n");
1042                 return -ENXIO;
1043         }
1044
1045         if (pdata->nr_slots == 0) {
1046                 dev_err(&pdev->dev, "No Slots\n");
1047                 return -ENXIO;
1048         }
1049
1050         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1051         irq = platform_get_irq(pdev, 0);
1052         if (res == NULL || irq < 0)
1053                 return -ENXIO;
1054
1055         res = request_mem_region(res->start, res->end - res->start + 1,
1056                                                         pdev->name);
1057         if (res == NULL)
1058                 return -EBUSY;
1059
1060         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1061         if (!mmc) {
1062                 ret = -ENOMEM;
1063                 goto err;
1064         }
1065
1066         host            = mmc_priv(mmc);
1067         host->mmc       = mmc;
1068         host->pdata     = pdata;
1069         host->dev       = &pdev->dev;
1070         host->use_dma   = 1;
1071         host->dev->dma_mask = &pdata->dma_mask;
1072         host->dma_ch    = -1;
1073         host->irq       = irq;
1074         host->id        = pdev->id;
1075         host->slot_id   = 0;
1076         host->mapbase   = res->start;
1077         host->base      = ioremap(host->mapbase, SZ_4K);
1078
1079         platform_set_drvdata(pdev, host);
1080         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
1081
1082         mmc->ops        = &mmc_omap_ops;
1083         mmc->f_min      = 400000;
1084         mmc->f_max      = 52000000;
1085
1086         sema_init(&host->sem, 1);
1087
1088         host->iclk = clk_get(&pdev->dev, "ick");
1089         if (IS_ERR(host->iclk)) {
1090                 ret = PTR_ERR(host->iclk);
1091                 host->iclk = NULL;
1092                 goto err1;
1093         }
1094         host->fclk = clk_get(&pdev->dev, "fck");
1095         if (IS_ERR(host->fclk)) {
1096                 ret = PTR_ERR(host->fclk);
1097                 host->fclk = NULL;
1098                 clk_put(host->iclk);
1099                 goto err1;
1100         }
1101
1102         if (clk_enable(host->fclk) != 0) {
1103                 clk_put(host->iclk);
1104                 clk_put(host->fclk);
1105                 goto err1;
1106         }
1107
1108         if (clk_enable(host->iclk) != 0) {
1109                 clk_disable(host->fclk);
1110                 clk_put(host->iclk);
1111                 clk_put(host->fclk);
1112                 goto err1;
1113         }
1114
1115         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1116         /*
1117          * MMC can still work without debounce clock.
1118          */
1119         if (IS_ERR(host->dbclk))
1120                 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1121         else
1122                 if (clk_enable(host->dbclk) != 0)
1123                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1124                                                         " clk failed\n");
1125                 else
1126                         host->dbclk_enabled = 1;
1127
1128         /* Since we do only SG emulation, we can have as many segs
1129          * as we want. */
1130         mmc->max_phys_segs = 1024;
1131         mmc->max_hw_segs = 1024;
1132
1133         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1134         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1135         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1136         mmc->max_seg_size = mmc->max_req_size;
1137
1138         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1139
1140         if (pdata->slots[host->slot_id].wires >= 8)
1141                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1142         else if (pdata->slots[host->slot_id].wires >= 4)
1143                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1144
1145         omap_hsmmc_init(host);
1146
1147         /* Select DMA lines */
1148         switch (host->id) {
1149         case OMAP_MMC1_DEVID:
1150                 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1151                 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1152                 break;
1153         case OMAP_MMC2_DEVID:
1154                 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1155                 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1156                 break;
1157         case OMAP_MMC3_DEVID:
1158                 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
1159                 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
1160                 break;
1161         default:
1162                 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
1163                 goto err_irq;
1164         }
1165
1166         /* Request IRQ for MMC operations */
1167         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1168                         mmc_hostname(mmc), host);
1169         if (ret) {
1170                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1171                 goto err_irq;
1172         }
1173
1174         /* initialize power supplies, gpios, etc */
1175         if (pdata->init != NULL) {
1176                 if (pdata->init(&pdev->dev) != 0) {
1177                         dev_dbg(mmc_dev(host->mmc), "late init error\n");
1178                         goto err_irq_cd_init;
1179                 }
1180         }
1181         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1182
1183         /* Request IRQ for card detect */
1184         if ((mmc_slot(host).card_detect_irq)) {
1185                 ret = request_irq(mmc_slot(host).card_detect_irq,
1186                                   omap_mmc_cd_handler,
1187                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1188                                           | IRQF_DISABLED,
1189                                   mmc_hostname(mmc), host);
1190                 if (ret) {
1191                         dev_dbg(mmc_dev(host->mmc),
1192                                 "Unable to grab MMC CD IRQ\n");
1193                         goto err_irq_cd;
1194                 }
1195         }
1196
1197         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1198         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1199
1200         mmc_add_host(mmc);
1201
1202         if (host->pdata->slots[host->slot_id].name != NULL) {
1203                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1204                 if (ret < 0)
1205                         goto err_slot_name;
1206         }
1207         if (mmc_slot(host).card_detect_irq &&
1208             host->pdata->slots[host->slot_id].get_cover_state) {
1209                 ret = device_create_file(&mmc->class_dev,
1210                                         &dev_attr_cover_switch);
1211                 if (ret < 0)
1212                         goto err_cover_switch;
1213         }
1214
1215         omap_mmc_debugfs(mmc);
1216
1217         return 0;
1218
1219 err_cover_switch:
1220         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1221 err_slot_name:
1222         mmc_remove_host(mmc);
1223 err_irq_cd:
1224         free_irq(mmc_slot(host).card_detect_irq, host);
1225 err_irq_cd_init:
1226         free_irq(host->irq, host);
1227 err_irq:
1228         clk_disable(host->fclk);
1229         clk_disable(host->iclk);
1230         clk_put(host->fclk);
1231         clk_put(host->iclk);
1232         if (host->dbclk_enabled) {
1233                 clk_disable(host->dbclk);
1234                 clk_put(host->dbclk);
1235         }
1236
1237 err1:
1238         iounmap(host->base);
1239 err:
1240         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1241         release_mem_region(res->start, res->end - res->start + 1);
1242         if (host)
1243                 mmc_free_host(mmc);
1244         return ret;
1245 }
1246
1247 static int omap_mmc_remove(struct platform_device *pdev)
1248 {
1249         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1250         struct resource *res;
1251
1252         if (host) {
1253                 mmc_remove_host(host->mmc);
1254                 if (host->pdata->cleanup)
1255                         host->pdata->cleanup(&pdev->dev);
1256                 free_irq(host->irq, host);
1257                 if (mmc_slot(host).card_detect_irq)
1258                         free_irq(mmc_slot(host).card_detect_irq, host);
1259                 flush_scheduled_work();
1260
1261                 clk_disable(host->fclk);
1262                 clk_disable(host->iclk);
1263                 clk_put(host->fclk);
1264                 clk_put(host->iclk);
1265                 if (host->dbclk_enabled) {
1266                         clk_disable(host->dbclk);
1267                         clk_put(host->dbclk);
1268                 }
1269
1270                 mmc_free_host(host->mmc);
1271                 iounmap(host->base);
1272         }
1273
1274         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1275         if (res)
1276                 release_mem_region(res->start, res->end - res->start + 1);
1277         platform_set_drvdata(pdev, NULL);
1278
1279         return 0;
1280 }
1281
1282 #ifdef CONFIG_PM
1283 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1284 {
1285         int ret = 0;
1286         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1287
1288         if (host && host->suspended)
1289                 return 0;
1290
1291         if (host) {
1292                 ret = mmc_suspend_host(host->mmc, state);
1293                 if (ret == 0) {
1294                         host->suspended = 1;
1295
1296                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1297                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1298
1299                         if (host->pdata->suspend) {
1300                                 ret = host->pdata->suspend(&pdev->dev,
1301                                                                 host->slot_id);
1302                                 if (ret)
1303                                         dev_dbg(mmc_dev(host->mmc),
1304                                                 "Unable to handle MMC board"
1305                                                 " level suspend\n");
1306                         }
1307
1308                         OMAP_HSMMC_WRITE(host->base, HCTL,
1309                                          OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
1310                         clk_disable(host->fclk);
1311                         clk_disable(host->iclk);
1312                         clk_disable(host->dbclk);
1313                 }
1314
1315         }
1316         return ret;
1317 }
1318
1319 /* Routine to resume the MMC device */
1320 static int omap_mmc_resume(struct platform_device *pdev)
1321 {
1322         int ret = 0;
1323         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1324
1325         if (host && !host->suspended)
1326                 return 0;
1327
1328         if (host) {
1329
1330                 ret = clk_enable(host->fclk);
1331                 if (ret)
1332                         goto clk_en_err;
1333
1334                 ret = clk_enable(host->iclk);
1335                 if (ret) {
1336                         clk_disable(host->fclk);
1337                         clk_put(host->fclk);
1338                         goto clk_en_err;
1339                 }
1340
1341                 if (clk_enable(host->dbclk) != 0)
1342                         dev_dbg(mmc_dev(host->mmc),
1343                                         "Enabling debounce clk failed\n");
1344
1345                 omap_hsmmc_init(host);
1346
1347                 if (host->pdata->resume) {
1348                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1349                         if (ret)
1350                                 dev_dbg(mmc_dev(host->mmc),
1351                                         "Unmask interrupt failed\n");
1352                 }
1353
1354                 /* Notify the core to resume the host */
1355                 ret = mmc_resume_host(host->mmc);
1356                 if (ret == 0)
1357                         host->suspended = 0;
1358         }
1359
1360         return ret;
1361
1362 clk_en_err:
1363         dev_dbg(mmc_dev(host->mmc),
1364                 "Failed to enable MMC clocks during resume\n");
1365         return ret;
1366 }
1367
1368 #else
1369 #define omap_mmc_suspend        NULL
1370 #define omap_mmc_resume         NULL
1371 #endif
1372
1373 static struct platform_driver omap_mmc_driver = {
1374         .remove         = omap_mmc_remove,
1375         .suspend        = omap_mmc_suspend,
1376         .resume         = omap_mmc_resume,
1377         .driver         = {
1378                 .name = DRIVER_NAME,
1379                 .owner = THIS_MODULE,
1380         },
1381 };
1382
1383 static int __init omap_mmc_init(void)
1384 {
1385         /* Register the MMC driver */
1386         return platform_driver_probe(&omap_mmc_driver, omap_mmc_probe);
1387 }
1388
1389 static void __exit omap_mmc_cleanup(void)
1390 {
1391         /* Unregister MMC driver */
1392         platform_driver_unregister(&omap_mmc_driver);
1393 }
1394
1395 module_init(omap_mmc_init);
1396 module_exit(omap_mmc_cleanup);
1397
1398 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1399 MODULE_LICENSE("GPL");
1400 MODULE_ALIAS("platform:" DRIVER_NAME);
1401 MODULE_AUTHOR("Texas Instruments Inc");