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   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/timer.h>
  28 #include <linux/clk.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/io.h>
  31 #include <linux/semaphore.h>
  32 #include <mach/dma.h>
  33 #include <mach/hardware.h>
  34 #include <mach/board.h>
  35 #include <mach/mmc.h>
  36 #include <mach/cpu.h>
  37
  38 /* OMAP HSMMC Host Controller Registers */
  39 #define OMAP_HSMMC_SYSCONFIG    0x0010
  40 #define OMAP_HSMMC_SYSSTATUS    0x0014
  41 #define OMAP_HSMMC_CON          0x002C
  42 #define OMAP_HSMMC_BLK          0x0104
  43 #define OMAP_HSMMC_ARG          0x0108
  44 #define OMAP_HSMMC_CMD          0x010C
  45 #define OMAP_HSMMC_RSP10        0x0110
  46 #define OMAP_HSMMC_RSP32        0x0114
  47 #define OMAP_HSMMC_RSP54        0x0118
  48 #define OMAP_HSMMC_RSP76        0x011C
  49 #define OMAP_HSMMC_DATA         0x0120
  50 #define OMAP_HSMMC_HCTL         0x0128
  51 #define OMAP_HSMMC_SYSCTL       0x012C
  52 #define OMAP_HSMMC_STAT         0x0130
  53 #define OMAP_HSMMC_IE           0x0134
  54 #define OMAP_HSMMC_ISE          0x0138
  55 #define OMAP_HSMMC_CAPA         0x0140
  56
  57 #define VS18                    (1 << 26)
  58 #define VS30                    (1 << 25)
  59 #define SDVS18                  (0x5 << 9)
  60 #define SDVS30                  (0x6 << 9)
  61 #define SDVS33                  (0x7 << 9)
  62 #define SDVS_MASK               0x00000E00
  63 #define SDVSCLR                 0xFFFFF1FF
  64 #define SDVSDET                 0x00000400
  65 #define AUTOIDLE                0x1
  66 #define SDBP                    (1 << 8)
  67 #define DTO                     0xe
  68 #define ICE                     0x1
  69 #define ICS                     0x2
  70 #define CEN                     (1 << 2)
  71 #define CLKD_MASK               0x0000FFC0
  72 #define CLKD_SHIFT              6
  73 #define DTO_MASK                0x000F0000
  74 #define DTO_SHIFT               16
  75 #define INT_EN_MASK             0x307F0033
  76 #define BWR_ENABLE              (1 << 4)
  77 #define BRR_ENABLE              (1 << 5)
  78 #define INIT_STREAM             (1 << 1)
  79 #define DP_SELECT               (1 << 21)
  80 #define DDIR                    (1 << 4)
  81 #define DMA_EN                  0x1
  82 #define MSBS                    (1 << 5)
  83 #define BCE                     (1 << 1)
  84 #define FOUR_BIT                (1 << 1)
  85 #define DW8                     (1 << 5)
  86 #define CC                      0x1
  87 #define TC                      0x02
  88 #define OD                      0x1
  89 #define ERR                     (1 << 15)
  90 #define CMD_TIMEOUT             (1 << 16)
  91 #define DATA_TIMEOUT            (1 << 20)
  92 #define CMD_CRC                 (1 << 17)
  93 #define DATA_CRC                (1 << 21)
  94 #define CARD_ERR                (1 << 28)
  95 #define STAT_CLEAR              0xFFFFFFFF
  96 #define INIT_STREAM_CMD         0x00000000
  97 #define DUAL_VOLT_OCR_BIT       7
  98 #define SRC                     (1 << 25)
  99 #define SRD                     (1 << 26)
 100 #define SOFTRESET               (1 << 1)
 101 #define RESETDONE               (1 << 0)
 102
 103 /*
 104  * FIXME: Most likely all the data using these _DEVID defines should come
 105  * from the platform_data, or implemented in controller and slot specific
 106  * functions.
 107  */
 108 #define OMAP_MMC1_DEVID         0
 109 #define OMAP_MMC2_DEVID         1
 110 #define OMAP_MMC3_DEVID         2
 111
 112 #define MMC_TIMEOUT_MS          20
 113 #define OMAP_MMC_MASTER_CLOCK   96000000
 114 #define DRIVER_NAME             "mmci-omap-hs"
 115
 116 /*
 117  * One controller can have multiple slots, like on some omap boards using
 118  * omap.c controller driver. Luckily this is not currently done on any known
 119  * omap_hsmmc.c device.
 120  */
 121 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 122
 123 /*
 124  * MMC Host controller read/write API's
 125  */
 126 #define OMAP_HSMMC_READ(base, reg)      \
 127         __raw_readl((base) + OMAP_HSMMC_##reg)
 128
 129 #define OMAP_HSMMC_WRITE(base, reg, val) \
 130         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 131
 132 struct mmc_omap_host {
 133         struct  device          *dev;
 134         struct  mmc_host        *mmc;
 135         struct  mmc_request     *mrq;
 136         struct  mmc_command     *cmd;
 137         struct  mmc_data        *data;
 138         struct  clk             *fclk;
 139         struct  clk             *iclk;
 140         struct  clk             *dbclk;
 141         struct  semaphore       sem;
 142         struct  work_struct     mmc_carddetect_work;
 143         void    __iomem         *base;
 144         resource_size_t         mapbase;
 145         unsigned int            id;
 146         unsigned int            dma_len;
 147         unsigned int            dma_sg_idx;
 148         unsigned char           bus_mode;
 149         unsigned char           power_mode;
 150         u32                     *buffer;
 151         u32                     bytesleft;
 152         int                     suspended;
 153         int                     irq;
 154         int                     carddetect;
 155         int                     use_dma, dma_ch;
 156         int                     dma_line_tx, dma_line_rx;
 157         int                     slot_id;
 158         int                     dbclk_enabled;
 159         int                     response_busy;
 160         int                     context_loss;
 161
 162         struct  omap_mmc_platform_data  *pdata;
 163 };
 164
 165 /*
 166  * Stop clock to the card
 167  */
 168 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 169 {
 170         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 171                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 172         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 173                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 174 }
 175
 176 #ifdef CONFIG_PM
 177
 178 /*
 179  * Restore the MMC host context, if it was lost as result of a
 180  * power state change.
 181  */
 182 static int omap_mmc_restore_ctx(struct mmc_omap_host *host)
 183 {
 184         struct mmc_ios *ios = &host->mmc->ios;
 185         struct omap_mmc_platform_data *pdata = host->pdata;
 186         int context_loss = 0;
 187         u32 hctl, capa, con;
 188         u16 dsor = 0;
 189         unsigned long timeout;
 190
 191         if (pdata->get_context_loss_count) {
 192                 context_loss = pdata->get_context_loss_count(host->dev);
 193                 if (context_loss < 0)
 194                         return 1;
 195         }
 196
 197         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
 198                 context_loss == host->context_loss ? "not " : "");
 199         if (host->context_loss == context_loss)
 200                 return 1;
 201
 202         /* Wait for hardware reset */
 203         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 204         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 205                 && time_before(jiffies, timeout))
 206                 ;
 207
 208         /* Do software reset */
 209         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
 210         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 211         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 212                 && time_before(jiffies, timeout))
 213                 ;
 214
 215         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 216                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 217
 218         if (host->id == OMAP_MMC1_DEVID) {
 219                 if (host->power_mode != MMC_POWER_OFF &&
 220                     (1 << ios->vdd) <= MMC_VDD_23_24)
 221                         hctl = SDVS18;
 222                 else
 223                         hctl = SDVS30;
 224                 capa = VS30 | VS18;
 225         } else {
 226                 hctl = SDVS18;
 227                 capa = VS18;
 228         }
 229
 230         OMAP_HSMMC_WRITE(host->base, HCTL,
 231                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 232
 233         OMAP_HSMMC_WRITE(host->base, CAPA,
 234                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 235
 236         OMAP_HSMMC_WRITE(host->base, HCTL,
 237                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 238
 239         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 240         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 241                 && time_before(jiffies, timeout))
 242                 ;
 243
 244         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 245         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 246         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 247
 248         /* Do not initialize card-specific things if the power is off */
 249         if (host->power_mode == MMC_POWER_OFF)
 250                 goto out;
 251
 252         con = OMAP_HSMMC_READ(host->base, CON);
 253         switch (ios->bus_width) {
 254         case MMC_BUS_WIDTH_8:
 255                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 256                 break;
 257         case MMC_BUS_WIDTH_4:
 258                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 259                 OMAP_HSMMC_WRITE(host->base, HCTL,
 260                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 261                 break;
 262         case MMC_BUS_WIDTH_1:
 263                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 264                 OMAP_HSMMC_WRITE(host->base, HCTL,
 265                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 266                 break;
 267         }
 268
 269         if (ios->clock) {
 270                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 271                 if (dsor < 1)
 272                         dsor = 1;
 273
 274                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 275                         dsor++;
 276
 277                 if (dsor > 250)
 278                         dsor = 250;
 279         }
 280
 281         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 282                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 283         OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
 284         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 285                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 286
 287         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 288         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 289                 && time_before(jiffies, timeout))
 290                 ;
 291
 292         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 293                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 294
 295         con = OMAP_HSMMC_READ(host->base, CON);
 296         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 297                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 298         else
 299                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 300 out:
 301         host->context_loss = context_loss;
 302
 303         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
 304         return 0;
 305 }
 306
 307 /*
 308  * Save the MMC host context (store the number of power state changes so far).
 309  */
 310 static void omap_mmc_save_ctx(struct mmc_omap_host *host)
 311 {
 312         struct omap_mmc_platform_data *pdata = host->pdata;
 313         int context_loss;
 314
 315         if (pdata->get_context_loss_count) {
 316                 context_loss = pdata->get_context_loss_count(host->dev);
 317                 if (context_loss < 0)
 318                         return;
 319                 host->context_loss = context_loss;
 320         }
 321 }
 322
 323 #else
 324
 325 static int omap_mmc_restore_ctx(struct mmc_omap_host *host)
 326 {
 327         return 0;
 328 }
 329
 330 static void omap_mmc_save_ctx(struct mmc_omap_host *host)
 331 {
 332 }
 333
 334 #endif
 335
 336 /*
 337  * Send init stream sequence to card
 338  * before sending IDLE command
 339  */
 340 static void send_init_stream(struct mmc_omap_host *host)
 341 {
 342         int reg = 0;
 343         unsigned long timeout;
 344
 345         disable_irq(host->irq);
 346         OMAP_HSMMC_WRITE(host->base, CON,
 347                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 348         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 349
 350         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 351         while ((reg != CC) && time_before(jiffies, timeout))
 352                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 353
 354         OMAP_HSMMC_WRITE(host->base, CON,
 355                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 356         enable_irq(host->irq);
 357 }
 358
 359 static inline
 360 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
 361 {
 362         int r = 1;
 363
 364         if (host->pdata->slots[host->slot_id].get_cover_state)
 365                 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
 366                         host->slot_id);
 367         return r;
 368 }
 369
 370 static ssize_t
 371 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 372                            char *buf)
 373 {
 374         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 375         struct mmc_omap_host *host = mmc_priv(mmc);
 376
 377         return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
 378                        "open");
 379 }
 380
 381 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 382
 383 static ssize_t
 384 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 385                         char *buf)
 386 {
 387         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 388         struct mmc_omap_host *host = mmc_priv(mmc);
 389         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 390
 391         return sprintf(buf, "%s\n", slot.name);
 392 }
 393
 394 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 395
 396 /*
 397  * Configure the response type and send the cmd.
 398  */
 399 static void
 400 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 401         struct mmc_data *data)
 402 {
 403         int cmdreg = 0, resptype = 0, cmdtype = 0;
 404
 405         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 406                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 407         host->cmd = cmd;
 408
 409         /*
 410          * Clear status bits and enable interrupts
 411          */
 412         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 413         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 414
 415         if (host->use_dma)
 416                 OMAP_HSMMC_WRITE(host->base, IE,
 417                                  INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
 418         else
 419                 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 420
 421         host->response_busy = 0;
 422         if (cmd->flags & MMC_RSP_PRESENT) {
 423                 if (cmd->flags & MMC_RSP_136)
 424                         resptype = 1;
 425                 else if (cmd->flags & MMC_RSP_BUSY) {
 426                         resptype = 3;
 427                         host->response_busy = 1;
 428                 } else
 429                         resptype = 2;
 430         }
 431
 432         /*
 433          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 434          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 435          * a val of 0x3, rest 0x0.
 436          */
 437         if (cmd == host->mrq->stop)
 438                 cmdtype = 0x3;
 439
 440         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 441
 442         if (data) {
 443                 cmdreg |= DP_SELECT | MSBS | BCE;
 444                 if (data->flags & MMC_DATA_READ)
 445                         cmdreg |= DDIR;
 446                 else
 447                         cmdreg &= ~(DDIR);
 448         }
 449
 450         if (host->use_dma)
 451                 cmdreg |= DMA_EN;
 452
 453         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 454         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 455 }
 456
 457 static int
 458 mmc_omap_get_dma_dir(struct mmc_omap_host *host, struct mmc_data *data)
 459 {
 460         if (data->flags & MMC_DATA_WRITE)
 461                 return DMA_TO_DEVICE;
 462         else
 463                 return DMA_FROM_DEVICE;
 464 }
 465
 466 /*
 467  * Notify the transfer complete to MMC core
 468  */
 469 static void
 470 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 471 {
 472         if (!data) {
 473                 struct mmc_request *mrq = host->mrq;
 474
 475                 host->mrq = NULL;
 476                 mmc_request_done(host->mmc, mrq);
 477                 return;
 478         }
 479
 480         host->data = NULL;
 481
 482         if (host->use_dma && host->dma_ch != -1)
 483                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 484                         mmc_omap_get_dma_dir(host, data));
 485
 486         if (!data->error)
 487                 data->bytes_xfered += data->blocks * (data->blksz);
 488         else
 489                 data->bytes_xfered = 0;
 490
 491         if (!data->stop) {
 492                 host->mrq = NULL;
 493                 mmc_request_done(host->mmc, data->mrq);
 494                 return;
 495         }
 496         mmc_omap_start_command(host, data->stop, NULL);
 497 }
 498
 499 /*
 500  * Notify the core about command completion
 501  */
 502 static void
 503 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 504 {
 505         host->cmd = NULL;
 506
 507         if (cmd->flags & MMC_RSP_PRESENT) {
 508                 if (cmd->flags & MMC_RSP_136) {
 509                         /* response type 2 */
 510                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 511                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 512                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 513                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 514                 } else {
 515                         /* response types 1, 1b, 3, 4, 5, 6 */
 516                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 517                 }
 518         }
 519         if ((host->data == NULL && !host->response_busy) || cmd->error) {
 520                 host->mrq = NULL;
 521                 mmc_request_done(host->mmc, cmd->mrq);
 522         }
 523 }
 524
 525 /*
 526  * DMA clean up for command errors
 527  */
 528 static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno)
 529 {
 530         host->data->error = errno;
 531
 532         if (host->use_dma && host->dma_ch != -1) {
 533                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 534                         mmc_omap_get_dma_dir(host, host->data));
 535                 omap_free_dma(host->dma_ch);
 536                 host->dma_ch = -1;
 537                 up(&host->sem);
 538         }
 539         host->data = NULL;
 540 }
 541
 542 /*
 543  * Readable error output
 544  */
 545 #ifdef CONFIG_MMC_DEBUG
 546 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 547 {
 548         /* --- means reserved bit without definition at documentation */
 549         static const char *mmc_omap_status_bits[] = {
 550                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 551                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 552                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 553                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 554         };
 555         char res[256];
 556         char *buf = res;
 557         int len, i;
 558
 559         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 560         buf += len;
 561
 562         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 563                 if (status & (1 << i)) {
 564                         len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
 565                         buf += len;
 566                 }
 567
 568         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
 569 }
 570 #endif  /* CONFIG_MMC_DEBUG */
 571
 572 /*
 573  * MMC controller internal state machines reset
 574  *
 575  * Used to reset command or data internal state machines, using respectively
 576  *  SRC or SRD bit of SYSCTL register
 577  * Can be called from interrupt context
 578  */
 579 static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
 580                 unsigned long bit)
 581 {
 582         unsigned long i = 0;
 583         unsigned long limit = (loops_per_jiffy *
 584                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
 585
 586         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 587                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 588
 589         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 590                 (i++ < limit))
 591                 cpu_relax();
 592
 593         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 594                 dev_err(mmc_dev(host->mmc),
 595                         "Timeout waiting on controller reset in %s\n",
 596                         __func__);
 597 }
 598
 599 /*
 600  * MMC controller IRQ handler
 601  */
 602 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 603 {
 604         struct mmc_omap_host *host = dev_id;
 605         struct mmc_data *data;
 606         int end_cmd = 0, end_trans = 0, status;
 607
 608         if (host->mrq == NULL) {
 609                 OMAP_HSMMC_WRITE(host->base, STAT,
 610                         OMAP_HSMMC_READ(host->base, STAT));
 611                 /* Flush posted write */
 612                 OMAP_HSMMC_READ(host->base, STAT);
 613                 return IRQ_HANDLED;
 614         }
 615
 616         data = host->data;
 617         status = OMAP_HSMMC_READ(host->base, STAT);
 618         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 619
 620         if (status & ERR) {
 621 #ifdef CONFIG_MMC_DEBUG
 622                 mmc_omap_report_irq(host, status);
 623 #endif
 624                 if ((status & CMD_TIMEOUT) ||
 625                         (status & CMD_CRC)) {
 626                         if (host->cmd) {
 627                                 if (status & CMD_TIMEOUT) {
 628                                         mmc_omap_reset_controller_fsm(host, SRC);
 629                                         host->cmd->error = -ETIMEDOUT;
 630                                 } else {
 631                                         host->cmd->error = -EILSEQ;
 632                                 }
 633                                 end_cmd = 1;
 634                         }
 635                         if (host->data || host->response_busy) {
 636                                 if (host->data)
 637                                         mmc_dma_cleanup(host, -ETIMEDOUT);
 638                                 host->response_busy = 0;
 639                                 mmc_omap_reset_controller_fsm(host, SRD);
 640                         }
 641                 }
 642                 if ((status & DATA_TIMEOUT) ||
 643                         (status & DATA_CRC)) {
 644                         if (host->data || host->response_busy) {
 645                                 int err = (status & DATA_TIMEOUT) ?
 646                                                 -ETIMEDOUT : -EILSEQ;
 647
 648                                 if (host->data)
 649                                         mmc_dma_cleanup(host, err);
 650                                 else
 651                                         host->mrq->cmd->error = err;
 652                                 host->response_busy = 0;
 653                                 mmc_omap_reset_controller_fsm(host, SRD);
 654                                 end_trans = 1;
 655                         }
 656                 }
 657                 if (status & CARD_ERR) {
 658                         dev_dbg(mmc_dev(host->mmc),
 659                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 660                         if (host->cmd)
 661                                 end_cmd = 1;
 662                         if (host->data)
 663                                 end_trans = 1;
 664                 }
 665         }
 666
 667         OMAP_HSMMC_WRITE(host->base, STAT, status);
 668         /* Flush posted write */
 669         OMAP_HSMMC_READ(host->base, STAT);
 670
 671         if (end_cmd || ((status & CC) && host->cmd))
 672                 mmc_omap_cmd_done(host, host->cmd);
 673         if (end_trans || (status & TC))
 674                 mmc_omap_xfer_done(host, data);
 675
 676         return IRQ_HANDLED;
 677 }
 678
 679 static void set_sd_bus_power(struct mmc_omap_host *host)
 680 {
 681         unsigned long i;
 682
 683         OMAP_HSMMC_WRITE(host->base, HCTL,
 684                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 685         for (i = 0; i < loops_per_jiffy; i++) {
 686                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
 687                         break;
 688                 cpu_relax();
 689         }
 690 }
 691
 692 /*
 693  * Switch MMC interface voltage ... only relevant for MMC1.
 694  *
 695  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
 696  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
 697  * Some chips, like eMMC ones, use internal transceivers.
 698  */
 699 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 700 {
 701         u32 reg_val = 0;
 702         int ret;
 703
 704         /* Disable the clocks */
 705         clk_disable(host->fclk);
 706         clk_disable(host->iclk);
 707         clk_disable(host->dbclk);
 708
 709         /* Turn the power off */
 710         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 711         if (ret != 0)
 712                 goto err;
 713
 714         /* Turn the power ON with given VDD 1.8 or 3.0v */
 715         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 716         if (ret != 0)
 717                 goto err;
 718
 719         clk_enable(host->fclk);
 720         clk_enable(host->iclk);
 721         clk_enable(host->dbclk);
 722
 723         OMAP_HSMMC_WRITE(host->base, HCTL,
 724                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 725         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 726
 727         /*
 728          * If a MMC dual voltage card is detected, the set_ios fn calls
 729          * this fn with VDD bit set for 1.8V. Upon card removal from the
 730          * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
 731          *
 732          * Cope with a bit of slop in the range ... per data sheets:
 733          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
 734          *    but recommended values are 1.71V to 1.89V
 735          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
 736          *    but recommended values are 2.7V to 3.3V
 737          *
 738          * Board setup code shouldn't permit anything very out-of-range.
 739          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
 740          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
 741          */
 742         if ((1 << vdd) <= MMC_VDD_23_24)
 743                 reg_val |= SDVS18;
 744         else
 745                 reg_val |= SDVS30;
 746
 747         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 748         set_sd_bus_power(host);
 749
 750         return 0;
 751 err:
 752         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 753         return ret;
 754 }
 755
 756 /*
 757  * Work Item to notify the core about card insertion/removal
 758  */
 759 static void mmc_omap_detect(struct work_struct *work)
 760 {
 761         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 762                                                 mmc_carddetect_work);
 763         struct omap_mmc_slot_data *slot = &mmc_slot(host);
 764
 765         if (mmc_slot(host).card_detect)
 766                 host->carddetect = slot->card_detect(slot->card_detect_irq);
 767         else
 768                 host->carddetect = -ENOSYS;
 769
 770         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 771         if (host->carddetect) {
 772                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 773         } else {
 774                 mmc_host_enable(host->mmc);
 775                 mmc_omap_reset_controller_fsm(host, SRD);
 776                 mmc_host_lazy_disable(host->mmc);
 777                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 778         }
 779 }
 780
 781 /*
 782  * ISR for handling card insertion and removal
 783  */
 784 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 785 {
 786         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 787
 788         schedule_work(&host->mmc_carddetect_work);
 789
 790         return IRQ_HANDLED;
 791 }
 792
 793 static int mmc_omap_get_dma_sync_dev(struct mmc_omap_host *host,
 794                                      struct mmc_data *data)
 795 {
 796         int sync_dev;
 797
 798         if (data->flags & MMC_DATA_WRITE)
 799                 sync_dev = host->dma_line_tx;
 800         else
 801                 sync_dev = host->dma_line_rx;
 802         return sync_dev;
 803 }
 804
 805 static void mmc_omap_config_dma_params(struct mmc_omap_host *host,
 806                                        struct mmc_data *data,
 807                                        struct scatterlist *sgl)
 808 {
 809         int blksz, nblk, dma_ch;
 810
 811         dma_ch = host->dma_ch;
 812         if (data->flags & MMC_DATA_WRITE) {
 813                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 814                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 815                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 816                         sg_dma_address(sgl), 0, 0);
 817         } else {
 818                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 819                                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 820                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 821                         sg_dma_address(sgl), 0, 0);
 822         }
 823
 824         blksz = host->data->blksz;
 825         nblk = sg_dma_len(sgl) / blksz;
 826
 827         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 828                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
 829                         mmc_omap_get_dma_sync_dev(host, data),
 830                         !(data->flags & MMC_DATA_WRITE));
 831
 832         omap_start_dma(dma_ch);
 833 }
 834
 835 /*
 836  * DMA call back function
 837  */
 838 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 839 {
 840         struct mmc_omap_host *host = data;
 841
 842         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 843                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 844
 845         if (host->dma_ch < 0)
 846                 return;
 847
 848         host->dma_sg_idx++;
 849         if (host->dma_sg_idx < host->dma_len) {
 850                 /* Fire up the next transfer. */
 851                 mmc_omap_config_dma_params(host, host->data,
 852                                            host->data->sg + host->dma_sg_idx);
 853                 return;
 854         }
 855
 856         omap_free_dma(host->dma_ch);
 857         host->dma_ch = -1;
 858         /*
 859          * DMA Callback: run in interrupt context.
 860          * mutex_unlock will throw a kernel warning if used.
 861          */
 862         up(&host->sem);
 863 }
 864
 865 /*
 866  * Routine to configure and start DMA for the MMC card
 867  */
 868 static int
 869 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 870 {
 871         int dma_ch = 0, ret = 0, err = 1, i;
 872         struct mmc_data *data = req->data;
 873
 874         /* Sanity check: all the SG entries must be aligned by block size. */
 875         for (i = 0; i < host->dma_len; i++) {
 876                 struct scatterlist *sgl;
 877
 878                 sgl = data->sg + i;
 879                 if (sgl->length % data->blksz)
 880                         return -EINVAL;
 881         }
 882         if ((data->blksz % 4) != 0)
 883                 /* REVISIT: The MMC buffer increments only when MSB is written.
 884                  * Return error for blksz which is non multiple of four.
 885                  */
 886                 return -EINVAL;
 887
 888         /*
 889          * If for some reason the DMA transfer is still active,
 890          * we wait for timeout period and free the dma
 891          */
 892         if (host->dma_ch != -1) {
 893                 set_current_state(TASK_UNINTERRUPTIBLE);
 894                 schedule_timeout(100);
 895                 if (down_trylock(&host->sem)) {
 896                         omap_free_dma(host->dma_ch);
 897                         host->dma_ch = -1;
 898                         up(&host->sem);
 899                         return err;
 900                 }
 901         } else {
 902                 if (down_trylock(&host->sem))
 903                         return err;
 904         }
 905
 906         ret = omap_request_dma(mmc_omap_get_dma_sync_dev(host, data), "MMC/SD",
 907                                mmc_omap_dma_cb,host, &dma_ch);
 908         if (ret != 0) {
 909                 dev_err(mmc_dev(host->mmc),
 910                         "%s: omap_request_dma() failed with %d\n",
 911                         mmc_hostname(host->mmc), ret);
 912                 return ret;
 913         }
 914
 915         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 916                         data->sg_len, mmc_omap_get_dma_dir(host, data));
 917         host->dma_ch = dma_ch;
 918         host->dma_sg_idx = 0;
 919
 920         mmc_omap_config_dma_params(host, data, data->sg);
 921
 922         return 0;
 923 }
 924
 925 static void set_data_timeout(struct mmc_omap_host *host,
 926                              struct mmc_request *req)
 927 {
 928         unsigned int timeout, cycle_ns;
 929         uint32_t reg, clkd, dto = 0;
 930
 931         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
 932         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
 933         if (clkd == 0)
 934                 clkd = 1;
 935
 936         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
 937         timeout = req->data->timeout_ns / cycle_ns;
 938         timeout += req->data->timeout_clks;
 939         if (timeout) {
 940                 while ((timeout & 0x80000000) == 0) {
 941                         dto += 1;
 942                         timeout <<= 1;
 943                 }
 944                 dto = 31 - dto;
 945                 timeout <<= 1;
 946                 if (timeout && dto)
 947                         dto += 1;
 948                 if (dto >= 13)
 949                         dto -= 13;
 950                 else
 951                         dto = 0;
 952                 if (dto > 14)
 953                         dto = 14;
 954         }
 955
 956         reg &= ~DTO_MASK;
 957         reg |= dto << DTO_SHIFT;
 958         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
 959 }
 960
 961 /*
 962  * Configure block length for MMC/SD cards and initiate the transfer.
 963  */
 964 static int
 965 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 966 {
 967         int ret;
 968         host->data = req->data;
 969
 970         if (req->data == NULL) {
 971                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 972                 return 0;
 973         }
 974
 975         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 976                                         | (req->data->blocks << 16));
 977         set_data_timeout(host, req);
 978
 979         if (host->use_dma) {
 980                 ret = mmc_omap_start_dma_transfer(host, req);
 981                 if (ret != 0) {
 982                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 983                         return ret;
 984                 }
 985         }
 986         return 0;
 987 }
 988
 989 static int omap_mmc_enable(struct mmc_host *mmc)
 990 {
 991         struct mmc_omap_host *host = mmc_priv(mmc);
 992         int err;
 993
 994         err = clk_enable(host->fclk);
 995         if (err)
 996                 return err;
 997         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
 998         omap_mmc_restore_ctx(host);
 999         return 0;
1000 }
1001
1002 static int omap_mmc_disable(struct mmc_host *mmc, int lazy)
1003 {
1004         struct mmc_omap_host *host = mmc_priv(mmc);
1005
1006         omap_mmc_save_ctx(host);
1007         clk_disable(host->fclk);
1008         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1009         return 0;
1010 }
1011
1012 /*
1013  * Request function. for read/write operation
1014  */
1015 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
1016 {
1017         struct mmc_omap_host *host = mmc_priv(mmc);
1018
1019         WARN_ON(host->mrq != NULL);
1020         host->mrq = req;
1021         mmc_omap_prepare_data(host, req);
1022         mmc_omap_start_command(host, req->cmd, req->data);
1023 }
1024
1025
1026 /* Routine to configure clock values. Exposed API to core */
1027 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1028 {
1029         struct mmc_omap_host *host = mmc_priv(mmc);
1030         u16 dsor = 0;
1031         unsigned long regval;
1032         unsigned long timeout;
1033         u32 con;
1034         int do_send_init_stream = 0;
1035
1036         mmc_host_enable(host->mmc);
1037
1038         if (ios->power_mode != host->power_mode) {
1039                 switch (ios->power_mode) {
1040                 case MMC_POWER_OFF:
1041                         mmc_slot(host).set_power(host->dev, host->slot_id,
1042                                                  0, 0);
1043                         break;
1044                 case MMC_POWER_UP:
1045                         mmc_slot(host).set_power(host->dev, host->slot_id,
1046                                                  1, ios->vdd);
1047                         break;
1048                 case MMC_POWER_ON:
1049                         do_send_init_stream = 1;
1050                         break;
1051                 }
1052                 host->power_mode = ios->power_mode;
1053         }
1054
1055         con = OMAP_HSMMC_READ(host->base, CON);
1056         switch (mmc->ios.bus_width) {
1057         case MMC_BUS_WIDTH_8:
1058                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1059                 break;
1060         case MMC_BUS_WIDTH_4:
1061                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1062                 OMAP_HSMMC_WRITE(host->base, HCTL,
1063                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1064                 break;
1065         case MMC_BUS_WIDTH_1:
1066                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1067                 OMAP_HSMMC_WRITE(host->base, HCTL,
1068                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1069                 break;
1070         }
1071
1072         if (host->id == OMAP_MMC1_DEVID) {
1073                 /* Only MMC1 can interface at 3V without some flavor
1074                  * of external transceiver; but they all handle 1.8V.
1075                  */
1076                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1077                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1078                                 /*
1079                                  * The mmc_select_voltage fn of the core does
1080                                  * not seem to set the power_mode to
1081                                  * MMC_POWER_UP upon recalculating the voltage.
1082                                  * vdd 1.8v.
1083                                  */
1084                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
1085                                         dev_dbg(mmc_dev(host->mmc),
1086                                                 "Switch operation failed\n");
1087                 }
1088         }
1089
1090         if (ios->clock) {
1091                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1092                 if (dsor < 1)
1093                         dsor = 1;
1094
1095                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1096                         dsor++;
1097
1098                 if (dsor > 250)
1099                         dsor = 250;
1100         }
1101         omap_mmc_stop_clock(host);
1102         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1103         regval = regval & ~(CLKD_MASK);
1104         regval = regval | (dsor << 6) | (DTO << 16);
1105         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1106         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1107                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1108
1109         /* Wait till the ICS bit is set */
1110         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1111         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
1112                 && time_before(jiffies, timeout))
1113                 msleep(1);
1114
1115         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1116                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1117
1118         if (do_send_init_stream)
1119                 send_init_stream(host);
1120
1121         con = OMAP_HSMMC_READ(host->base, CON);
1122         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1123                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1124         else
1125                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
1126
1127         mmc_host_lazy_disable(host->mmc);
1128 }
1129
1130 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1131 {
1132         struct mmc_omap_host *host = mmc_priv(mmc);
1133         struct omap_mmc_platform_data *pdata = host->pdata;
1134
1135         if (!pdata->slots[0].card_detect)
1136                 return -ENOSYS;
1137         return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
1138 }
1139
1140 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1141 {
1142         struct mmc_omap_host *host = mmc_priv(mmc);
1143         struct omap_mmc_platform_data *pdata = host->pdata;
1144
1145         if (!pdata->slots[0].get_ro)
1146                 return -ENOSYS;
1147         return pdata->slots[0].get_ro(host->dev, 0);
1148 }
1149
1150 static void omap_hsmmc_init(struct mmc_omap_host *host)
1151 {
1152         u32 hctl, capa, value;
1153
1154         /* Only MMC1 supports 3.0V */
1155         if (host->id == OMAP_MMC1_DEVID) {
1156                 hctl = SDVS30;
1157                 capa = VS30 | VS18;
1158         } else {
1159                 hctl = SDVS18;
1160                 capa = VS18;
1161         }
1162
1163         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1164         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1165
1166         value = OMAP_HSMMC_READ(host->base, CAPA);
1167         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1168
1169         /* Set the controller to AUTO IDLE mode */
1170         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1171         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1172
1173         /* Set SD bus power bit */
1174         set_sd_bus_power(host);
1175 }
1176
1177 static struct mmc_host_ops mmc_omap_ops = {
1178         .enable = omap_mmc_enable,
1179         .disable = omap_mmc_disable,
1180         .request = omap_mmc_request,
1181         .set_ios = omap_mmc_set_ios,
1182         .get_cd = omap_hsmmc_get_cd,
1183         .get_ro = omap_hsmmc_get_ro,
1184         /* NYET -- enable_sdio_irq */
1185 };
1186
1187 #ifdef CONFIG_DEBUG_FS
1188
1189 static int mmc_regs_show(struct seq_file *s, void *data)
1190 {
1191         struct mmc_host *mmc = s->private;
1192         struct mmc_omap_host *host = mmc_priv(mmc);
1193         struct omap_mmc_platform_data *pdata = host->pdata;
1194         int context_loss = 0;
1195
1196         if (pdata->get_context_loss_count)
1197                 context_loss = pdata->get_context_loss_count(host->dev);
1198
1199         seq_printf(s, "mmc%d:\n"
1200                         " enabled:\t%d\n"
1201                         " nesting_cnt:\t%d\n"
1202                         " ctx_loss:\t%d:%d\n"
1203                         "\nregs:\n",
1204                         mmc->index, mmc->enabled ? 1 : 0, mmc->nesting_cnt,
1205                         host->context_loss, context_loss);
1206
1207         if (clk_enable(host->fclk) != 0) {
1208                 seq_printf(s, "can't read the regs\n");
1209                 goto err;
1210         }
1211
1212         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1213                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1214         seq_printf(s, "CON:\t\t0x%08x\n",
1215                         OMAP_HSMMC_READ(host->base, CON));
1216         seq_printf(s, "HCTL:\t\t0x%08x\n",
1217                         OMAP_HSMMC_READ(host->base, HCTL));
1218         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1219                         OMAP_HSMMC_READ(host->base, SYSCTL));
1220         seq_printf(s, "IE:\t\t0x%08x\n",
1221                         OMAP_HSMMC_READ(host->base, IE));
1222         seq_printf(s, "ISE:\t\t0x%08x\n",
1223                         OMAP_HSMMC_READ(host->base, ISE));
1224         seq_printf(s, "CAPA:\t\t0x%08x\n",
1225                         OMAP_HSMMC_READ(host->base, CAPA));
1226
1227         clk_disable(host->fclk);
1228 err:
1229         return 0;
1230 }
1231
1232 static int mmc_regs_open(struct inode *inode, struct file *file)
1233 {
1234         return single_open(file, mmc_regs_show, inode->i_private);
1235 }
1236
1237 static const struct file_operations mmc_regs_fops = {
1238         .open           = mmc_regs_open,
1239         .read           = seq_read,
1240         .llseek         = seq_lseek,
1241         .release        = single_release,
1242 };
1243
1244 static void omap_mmc_debugfs(struct mmc_host *mmc)
1245 {
1246         if (mmc->debugfs_root)
1247                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1248                         mmc, &mmc_regs_fops);
1249 }
1250
1251 #else
1252
1253 static void omap_mmc_debugfs(struct mmc_host *mmc)
1254 {
1255 }
1256
1257 #endif
1258
1259 static int __init omap_mmc_probe(struct platform_device *pdev)
1260 {
1261         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1262         struct mmc_host *mmc;
1263         struct mmc_omap_host *host = NULL;
1264         struct resource *res;
1265         int ret = 0, irq;
1266
1267         if (pdata == NULL) {
1268                 dev_err(&pdev->dev, "Platform Data is missing\n");
1269                 return -ENXIO;
1270         }
1271
1272         if (pdata->nr_slots == 0) {
1273                 dev_err(&pdev->dev, "No Slots\n");
1274                 return -ENXIO;
1275         }
1276
1277         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1278         irq = platform_get_irq(pdev, 0);
1279         if (res == NULL || irq < 0)
1280                 return -ENXIO;
1281
1282         res = request_mem_region(res->start, res->end - res->start + 1,
1283                                                         pdev->name);
1284         if (res == NULL)
1285                 return -EBUSY;
1286
1287         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1288         if (!mmc) {
1289                 ret = -ENOMEM;
1290                 goto err;
1291         }
1292
1293         host            = mmc_priv(mmc);
1294         host->mmc       = mmc;
1295         host->pdata     = pdata;
1296         host->dev       = &pdev->dev;
1297         host->use_dma   = 1;
1298         host->dev->dma_mask = &pdata->dma_mask;
1299         host->dma_ch    = -1;
1300         host->irq       = irq;
1301         host->id        = pdev->id;
1302         host->slot_id   = 0;
1303         host->mapbase   = res->start;
1304         host->base      = ioremap(host->mapbase, SZ_4K);
1305         host->power_mode = -1;
1306
1307         platform_set_drvdata(pdev, host);
1308         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
1309
1310         mmc->ops        = &mmc_omap_ops;
1311         mmc->f_min      = 400000;
1312         mmc->f_max      = 52000000;
1313
1314         sema_init(&host->sem, 1);
1315
1316         host->iclk = clk_get(&pdev->dev, "ick");
1317         if (IS_ERR(host->iclk)) {
1318                 ret = PTR_ERR(host->iclk);
1319                 host->iclk = NULL;
1320                 goto err1;
1321         }
1322         host->fclk = clk_get(&pdev->dev, "fck");
1323         if (IS_ERR(host->fclk)) {
1324                 ret = PTR_ERR(host->fclk);
1325                 host->fclk = NULL;
1326                 clk_put(host->iclk);
1327                 goto err1;
1328         }
1329
1330         omap_mmc_save_ctx(host);
1331
1332         mmc->caps |= MMC_CAP_DISABLE;
1333         mmc_set_disable_delay(mmc, 100);
1334         if (mmc_host_enable(host->mmc) != 0) {
1335                 clk_put(host->iclk);
1336                 clk_put(host->fclk);
1337                 goto err1;
1338         }
1339
1340         if (clk_enable(host->iclk) != 0) {
1341                 mmc_host_disable(host->mmc);
1342                 clk_put(host->iclk);
1343                 clk_put(host->fclk);
1344                 goto err1;
1345         }
1346
1347         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1348         /*
1349          * MMC can still work without debounce clock.
1350          */
1351         if (IS_ERR(host->dbclk))
1352                 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1353         else
1354                 if (clk_enable(host->dbclk) != 0)
1355                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1356                                                         " clk failed\n");
1357                 else
1358                         host->dbclk_enabled = 1;
1359
1360         /* Since we do only SG emulation, we can have as many segs
1361          * as we want. */
1362         mmc->max_phys_segs = 1024;
1363         mmc->max_hw_segs = 1024;
1364
1365         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1366         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1367         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1368         mmc->max_seg_size = mmc->max_req_size;
1369
1370         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1371
1372         if (pdata->slots[host->slot_id].wires >= 8)
1373                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1374         else if (pdata->slots[host->slot_id].wires >= 4)
1375                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1376
1377         omap_hsmmc_init(host);
1378
1379         /* Select DMA lines */
1380         switch (host->id) {
1381         case OMAP_MMC1_DEVID:
1382                 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1383                 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1384                 break;
1385         case OMAP_MMC2_DEVID:
1386                 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1387                 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1388                 break;
1389         case OMAP_MMC3_DEVID:
1390                 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
1391                 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
1392                 break;
1393         default:
1394                 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
1395                 goto err_irq;
1396         }
1397
1398         /* Request IRQ for MMC operations */
1399         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1400                         mmc_hostname(mmc), host);
1401         if (ret) {
1402                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1403                 goto err_irq;
1404         }
1405
1406         /* initialize power supplies, gpios, etc */
1407         if (pdata->init != NULL) {
1408                 if (pdata->init(&pdev->dev) != 0) {
1409                         dev_dbg(mmc_dev(host->mmc), "late init error\n");
1410                         goto err_irq_cd_init;
1411                 }
1412         }
1413         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1414
1415         /* Request IRQ for card detect */
1416         if ((mmc_slot(host).card_detect_irq)) {
1417                 ret = request_irq(mmc_slot(host).card_detect_irq,
1418                                   omap_mmc_cd_handler,
1419                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1420                                           | IRQF_DISABLED,
1421                                   mmc_hostname(mmc), host);
1422                 if (ret) {
1423                         dev_dbg(mmc_dev(host->mmc),
1424                                 "Unable to grab MMC CD IRQ\n");
1425                         goto err_irq_cd;
1426                 }
1427         }
1428
1429         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1430         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1431
1432         mmc_host_lazy_disable(host->mmc);
1433
1434         mmc_add_host(mmc);
1435
1436         if (host->pdata->slots[host->slot_id].name != NULL) {
1437                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1438                 if (ret < 0)
1439                         goto err_slot_name;
1440         }
1441         if (mmc_slot(host).card_detect_irq &&
1442             host->pdata->slots[host->slot_id].get_cover_state) {
1443                 ret = device_create_file(&mmc->class_dev,
1444                                         &dev_attr_cover_switch);
1445                 if (ret < 0)
1446                         goto err_cover_switch;
1447         }
1448
1449         omap_mmc_debugfs(mmc);
1450
1451         return 0;
1452
1453 err_cover_switch:
1454         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1455 err_slot_name:
1456         mmc_remove_host(mmc);
1457 err_irq_cd:
1458         free_irq(mmc_slot(host).card_detect_irq, host);
1459 err_irq_cd_init:
1460         free_irq(host->irq, host);
1461 err_irq:
1462         mmc_host_disable(host->mmc);
1463         clk_disable(host->iclk);
1464         clk_put(host->fclk);
1465         clk_put(host->iclk);
1466         if (host->dbclk_enabled) {
1467                 clk_disable(host->dbclk);
1468                 clk_put(host->dbclk);
1469         }
1470
1471 err1:
1472         iounmap(host->base);
1473 err:
1474         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1475         release_mem_region(res->start, res->end - res->start + 1);
1476         if (host)
1477                 mmc_free_host(mmc);
1478         return ret;
1479 }
1480
1481 static int omap_mmc_remove(struct platform_device *pdev)
1482 {
1483         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1484         struct resource *res;
1485
1486         if (host) {
1487                 mmc_host_enable(host->mmc);
1488                 mmc_remove_host(host->mmc);
1489                 if (host->pdata->cleanup)
1490                         host->pdata->cleanup(&pdev->dev);
1491                 free_irq(host->irq, host);
1492                 if (mmc_slot(host).card_detect_irq)
1493                         free_irq(mmc_slot(host).card_detect_irq, host);
1494                 flush_scheduled_work();
1495
1496                 mmc_host_disable(host->mmc);
1497                 clk_disable(host->iclk);
1498                 clk_put(host->fclk);
1499                 clk_put(host->iclk);
1500                 if (host->dbclk_enabled) {
1501                         clk_disable(host->dbclk);
1502                         clk_put(host->dbclk);
1503                 }
1504
1505                 mmc_free_host(host->mmc);
1506                 iounmap(host->base);
1507         }
1508
1509         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1510         if (res)
1511                 release_mem_region(res->start, res->end - res->start + 1);
1512         platform_set_drvdata(pdev, NULL);
1513
1514         return 0;
1515 }
1516
1517 #ifdef CONFIG_PM
1518 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1519 {
1520         int ret = 0;
1521         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1522
1523         if (host && host->suspended)
1524                 return 0;
1525
1526         if (host) {
1527                 mmc_host_enable(host->mmc);
1528                 ret = mmc_suspend_host(host->mmc, state);
1529                 if (ret == 0) {
1530                         host->suspended = 1;
1531
1532                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1533                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1534
1535                         if (host->pdata->suspend) {
1536                                 ret = host->pdata->suspend(&pdev->dev,
1537                                                                 host->slot_id);
1538                                 if (ret)
1539                                         dev_dbg(mmc_dev(host->mmc),
1540                                                 "Unable to handle MMC board"
1541                                                 " level suspend\n");
1542                         }
1543
1544                         OMAP_HSMMC_WRITE(host->base, HCTL,
1545                                          OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
1546                         mmc_host_disable(host->mmc);
1547                         clk_disable(host->iclk);
1548                         clk_disable(host->dbclk);
1549                 } else
1550                         mmc_host_disable(host->mmc);
1551
1552         }
1553         return ret;
1554 }
1555
1556 /* Routine to resume the MMC device */
1557 static int omap_mmc_resume(struct platform_device *pdev)
1558 {
1559         int ret = 0;
1560         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1561
1562         if (host && !host->suspended)
1563                 return 0;
1564
1565         if (host) {
1566                 ret = clk_enable(host->iclk);
1567                 if (ret)
1568                         goto clk_en_err;
1569
1570                 if (clk_enable(host->dbclk) != 0)
1571                         dev_dbg(mmc_dev(host->mmc),
1572                                         "Enabling debounce clk failed\n");
1573
1574                 if (mmc_host_enable(host->mmc) != 0) {
1575                         clk_disable(host->iclk);
1576                         goto clk_en_err;
1577                 }
1578
1579                 omap_hsmmc_init(host);
1580
1581                 if (host->pdata->resume) {
1582                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1583                         if (ret)
1584                                 dev_dbg(mmc_dev(host->mmc),
1585                                         "Unmask interrupt failed\n");
1586                 }
1587
1588                 /* Notify the core to resume the host */
1589                 ret = mmc_resume_host(host->mmc);
1590                 if (ret == 0)
1591                         host->suspended = 0;
1592                 mmc_host_lazy_disable(host->mmc);
1593         }
1594
1595         return ret;
1596
1597 clk_en_err:
1598         dev_dbg(mmc_dev(host->mmc),
1599                 "Failed to enable MMC clocks during resume\n");
1600         return ret;
1601 }
1602
1603 #else
1604 #define omap_mmc_suspend        NULL
1605 #define omap_mmc_resume         NULL
1606 #endif
1607
1608 static struct platform_driver omap_mmc_driver = {
1609         .remove         = omap_mmc_remove,
1610         .suspend        = omap_mmc_suspend,
1611         .resume         = omap_mmc_resume,
1612         .driver         = {
1613                 .name = DRIVER_NAME,
1614                 .owner = THIS_MODULE,
1615         },
1616 };
1617
1618 static int __init omap_mmc_init(void)
1619 {
1620         /* Register the MMC driver */
1621         return platform_driver_probe(&omap_mmc_driver, omap_mmc_probe);
1622 }
1623
1624 static void __exit omap_mmc_cleanup(void)
1625 {
1626         /* Unregister MMC driver */
1627         platform_driver_unregister(&omap_mmc_driver);
1628 }
1629
1630 module_init(omap_mmc_init);
1631 module_exit(omap_mmc_cleanup);
1632
1633 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1634 MODULE_LICENSE("GPL");
1635 MODULE_ALIAS("platform:" DRIVER_NAME);
1636 MODULE_AUTHOR("Texas Instruments Inc");