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   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/timer.h>
  28 #include <linux/clk.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/io.h>
  31 #include <linux/semaphore.h>
  32 #include <mach/dma.h>
  33 #include <mach/hardware.h>
  34 #include <mach/board.h>
  35 #include <mach/mmc.h>
  36 #include <mach/cpu.h>
  37
  38 /* OMAP HSMMC Host Controller Registers */
  39 #define OMAP_HSMMC_SYSCONFIG    0x0010
  40 #define OMAP_HSMMC_SYSSTATUS    0x0014
  41 #define OMAP_HSMMC_CON          0x002C
  42 #define OMAP_HSMMC_BLK          0x0104
  43 #define OMAP_HSMMC_ARG          0x0108
  44 #define OMAP_HSMMC_CMD          0x010C
  45 #define OMAP_HSMMC_RSP10        0x0110
  46 #define OMAP_HSMMC_RSP32        0x0114
  47 #define OMAP_HSMMC_RSP54        0x0118
  48 #define OMAP_HSMMC_RSP76        0x011C
  49 #define OMAP_HSMMC_DATA         0x0120
  50 #define OMAP_HSMMC_HCTL         0x0128
  51 #define OMAP_HSMMC_SYSCTL       0x012C
  52 #define OMAP_HSMMC_STAT         0x0130
  53 #define OMAP_HSMMC_IE           0x0134
  54 #define OMAP_HSMMC_ISE          0x0138
  55 #define OMAP_HSMMC_CAPA         0x0140
  56
  57 #define VS18                    (1 << 26)
  58 #define VS30                    (1 << 25)
  59 #define SDVS18                  (0x5 << 9)
  60 #define SDVS30                  (0x6 << 9)
  61 #define SDVS33                  (0x7 << 9)
  62 #define SDVS_MASK               0x00000E00
  63 #define SDVSCLR                 0xFFFFF1FF
  64 #define SDVSDET                 0x00000400
  65 #define AUTOIDLE                0x1
  66 #define SDBP                    (1 << 8)
  67 #define DTO                     0xe
  68 #define ICE                     0x1
  69 #define ICS                     0x2
  70 #define CEN                     (1 << 2)
  71 #define CLKD_MASK               0x0000FFC0
  72 #define CLKD_SHIFT              6
  73 #define DTO_MASK                0x000F0000
  74 #define DTO_SHIFT               16
  75 #define INT_EN_MASK             0x307F0033
  76 #define BWR_ENABLE              (1 << 4)
  77 #define BRR_ENABLE              (1 << 5)
  78 #define INIT_STREAM             (1 << 1)
  79 #define DP_SELECT               (1 << 21)
  80 #define DDIR                    (1 << 4)
  81 #define DMA_EN                  0x1
  82 #define MSBS                    (1 << 5)
  83 #define BCE                     (1 << 1)
  84 #define FOUR_BIT                (1 << 1)
  85 #define DW8                     (1 << 5)
  86 #define CC                      0x1
  87 #define TC                      0x02
  88 #define OD                      0x1
  89 #define ERR                     (1 << 15)
  90 #define CMD_TIMEOUT             (1 << 16)
  91 #define DATA_TIMEOUT            (1 << 20)
  92 #define CMD_CRC                 (1 << 17)
  93 #define DATA_CRC                (1 << 21)
  94 #define CARD_ERR                (1 << 28)
  95 #define STAT_CLEAR              0xFFFFFFFF
  96 #define INIT_STREAM_CMD         0x00000000
  97 #define DUAL_VOLT_OCR_BIT       7
  98 #define SRC                     (1 << 25)
  99 #define SRD                     (1 << 26)
 100 #define SOFTRESET               (1 << 1)
 101 #define RESETDONE               (1 << 0)
 102
 103 /*
 104  * FIXME: Most likely all the data using these _DEVID defines should come
 105  * from the platform_data, or implemented in controller and slot specific
 106  * functions.
 107  */
 108 #define OMAP_MMC1_DEVID         0
 109 #define OMAP_MMC2_DEVID         1
 110 #define OMAP_MMC3_DEVID         2
 111
 112 #define MMC_TIMEOUT_MS          20
 113 #define OMAP_MMC_MASTER_CLOCK   96000000
 114 #define DRIVER_NAME             "mmci-omap-hs"
 115
 116 /* Timeouts for entering power saving states on inactivity, msec */
 117 #define OMAP_MMC_DISABLED_TIMEOUT       100
 118 #define OMAP_MMC_OFF_TIMEOUT            1000
 119
 120 /*
 121  * One controller can have multiple slots, like on some omap boards using
 122  * omap.c controller driver. Luckily this is not currently done on any known
 123  * omap_hsmmc.c device.
 124  */
 125 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 126
 127 /*
 128  * MMC Host controller read/write API's
 129  */
 130 #define OMAP_HSMMC_READ(base, reg)      \
 131         __raw_readl((base) + OMAP_HSMMC_##reg)
 132
 133 #define OMAP_HSMMC_WRITE(base, reg, val) \
 134         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 135
 136 struct mmc_omap_host {
 137         struct  device          *dev;
 138         struct  mmc_host        *mmc;
 139         struct  mmc_request     *mrq;
 140         struct  mmc_command     *cmd;
 141         struct  mmc_data        *data;
 142         struct  clk             *fclk;
 143         struct  clk             *iclk;
 144         struct  clk             *dbclk;
 145         struct  semaphore       sem;
 146         struct  work_struct     mmc_carddetect_work;
 147         void    __iomem         *base;
 148         resource_size_t         mapbase;
 149         unsigned int            id;
 150         unsigned int            dma_len;
 151         unsigned int            dma_sg_idx;
 152         unsigned char           bus_mode;
 153         unsigned char           power_mode;
 154         u32                     *buffer;
 155         u32                     bytesleft;
 156         int                     suspended;
 157         int                     irq;
 158         int                     use_dma, dma_ch;
 159         int                     dma_line_tx, dma_line_rx;
 160         int                     slot_id;
 161         int                     dbclk_enabled;
 162         int                     response_busy;
 163         int                     context_loss;
 164         int                     dpm_state;
 165         int                     vdd;
 166
 167         struct  omap_mmc_platform_data  *pdata;
 168 };
 169
 170 /*
 171  * Stop clock to the card
 172  */
 173 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 174 {
 175         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 176                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 177         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 178                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 179 }
 180
 181 #ifdef CONFIG_PM
 182
 183 /*
 184  * Restore the MMC host context, if it was lost as result of a
 185  * power state change.
 186  */
 187 static int omap_mmc_restore_ctx(struct mmc_omap_host *host)
 188 {
 189         struct mmc_ios *ios = &host->mmc->ios;
 190         struct omap_mmc_platform_data *pdata = host->pdata;
 191         int context_loss = 0;
 192         u32 hctl, capa, con;
 193         u16 dsor = 0;
 194         unsigned long timeout;
 195
 196         if (pdata->get_context_loss_count) {
 197                 context_loss = pdata->get_context_loss_count(host->dev);
 198                 if (context_loss < 0)
 199                         return 1;
 200         }
 201
 202         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
 203                 context_loss == host->context_loss ? "not " : "");
 204         if (host->context_loss == context_loss)
 205                 return 1;
 206
 207         /* Wait for hardware reset */
 208         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 209         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 210                 && time_before(jiffies, timeout))
 211                 ;
 212
 213         /* Do software reset */
 214         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
 215         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 216         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 217                 && time_before(jiffies, timeout))
 218                 ;
 219
 220         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 221                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 222
 223         if (host->id == OMAP_MMC1_DEVID) {
 224                 if (host->power_mode != MMC_POWER_OFF &&
 225                     (1 << ios->vdd) <= MMC_VDD_23_24)
 226                         hctl = SDVS18;
 227                 else
 228                         hctl = SDVS30;
 229                 capa = VS30 | VS18;
 230         } else {
 231                 hctl = SDVS18;
 232                 capa = VS18;
 233         }
 234
 235         OMAP_HSMMC_WRITE(host->base, HCTL,
 236                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 237
 238         OMAP_HSMMC_WRITE(host->base, CAPA,
 239                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 240
 241         OMAP_HSMMC_WRITE(host->base, HCTL,
 242                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 243
 244         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 245         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 246                 && time_before(jiffies, timeout))
 247                 ;
 248
 249         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 250         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 251         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 252
 253         /* Do not initialize card-specific things if the power is off */
 254         if (host->power_mode == MMC_POWER_OFF)
 255                 goto out;
 256
 257         con = OMAP_HSMMC_READ(host->base, CON);
 258         switch (ios->bus_width) {
 259         case MMC_BUS_WIDTH_8:
 260                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 261                 break;
 262         case MMC_BUS_WIDTH_4:
 263                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 264                 OMAP_HSMMC_WRITE(host->base, HCTL,
 265                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 266                 break;
 267         case MMC_BUS_WIDTH_1:
 268                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 269                 OMAP_HSMMC_WRITE(host->base, HCTL,
 270                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 271                 break;
 272         }
 273
 274         if (ios->clock) {
 275                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 276                 if (dsor < 1)
 277                         dsor = 1;
 278
 279                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 280                         dsor++;
 281
 282                 if (dsor > 250)
 283                         dsor = 250;
 284         }
 285
 286         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 287                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 288         OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
 289         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 290                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 291
 292         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 293         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 294                 && time_before(jiffies, timeout))
 295                 ;
 296
 297         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 298                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 299
 300         con = OMAP_HSMMC_READ(host->base, CON);
 301         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 302                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 303         else
 304                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 305 out:
 306         host->context_loss = context_loss;
 307
 308         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
 309         return 0;
 310 }
 311
 312 /*
 313  * Save the MMC host context (store the number of power state changes so far).
 314  */
 315 static void omap_mmc_save_ctx(struct mmc_omap_host *host)
 316 {
 317         struct omap_mmc_platform_data *pdata = host->pdata;
 318         int context_loss;
 319
 320         if (pdata->get_context_loss_count) {
 321                 context_loss = pdata->get_context_loss_count(host->dev);
 322                 if (context_loss < 0)
 323                         return;
 324                 host->context_loss = context_loss;
 325         }
 326 }
 327
 328 #else
 329
 330 static int omap_mmc_restore_ctx(struct mmc_omap_host *host)
 331 {
 332         return 0;
 333 }
 334
 335 static void omap_mmc_save_ctx(struct mmc_omap_host *host)
 336 {
 337 }
 338
 339 #endif
 340
 341 /*
 342  * Send init stream sequence to card
 343  * before sending IDLE command
 344  */
 345 static void send_init_stream(struct mmc_omap_host *host)
 346 {
 347         int reg = 0;
 348         unsigned long timeout;
 349
 350         disable_irq(host->irq);
 351         OMAP_HSMMC_WRITE(host->base, CON,
 352                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 353         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 354
 355         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 356         while ((reg != CC) && time_before(jiffies, timeout))
 357                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 358
 359         OMAP_HSMMC_WRITE(host->base, CON,
 360                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 361         enable_irq(host->irq);
 362 }
 363
 364 static inline
 365 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
 366 {
 367         int r = 1;
 368
 369         if (host->pdata->slots[host->slot_id].get_cover_state)
 370                 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
 371                         host->slot_id);
 372         return r;
 373 }
 374
 375 static ssize_t
 376 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 377                            char *buf)
 378 {
 379         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 380         struct mmc_omap_host *host = mmc_priv(mmc);
 381
 382         return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
 383                        "open");
 384 }
 385
 386 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 387
 388 static ssize_t
 389 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 390                         char *buf)
 391 {
 392         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 393         struct mmc_omap_host *host = mmc_priv(mmc);
 394         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 395
 396         return sprintf(buf, "%s\n", slot.name);
 397 }
 398
 399 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 400
 401 /*
 402  * Configure the response type and send the cmd.
 403  */
 404 static void
 405 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 406         struct mmc_data *data)
 407 {
 408         int cmdreg = 0, resptype = 0, cmdtype = 0;
 409
 410         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 411                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 412         host->cmd = cmd;
 413
 414         /*
 415          * Clear status bits and enable interrupts
 416          */
 417         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 418         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 419
 420         if (host->use_dma)
 421                 OMAP_HSMMC_WRITE(host->base, IE,
 422                                  INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
 423         else
 424                 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 425
 426         host->response_busy = 0;
 427         if (cmd->flags & MMC_RSP_PRESENT) {
 428                 if (cmd->flags & MMC_RSP_136)
 429                         resptype = 1;
 430                 else if (cmd->flags & MMC_RSP_BUSY) {
 431                         resptype = 3;
 432                         host->response_busy = 1;
 433                 } else
 434                         resptype = 2;
 435         }
 436
 437         /*
 438          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 439          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 440          * a val of 0x3, rest 0x0.
 441          */
 442         if (cmd == host->mrq->stop)
 443                 cmdtype = 0x3;
 444
 445         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 446
 447         if (data) {
 448                 cmdreg |= DP_SELECT | MSBS | BCE;
 449                 if (data->flags & MMC_DATA_READ)
 450                         cmdreg |= DDIR;
 451                 else
 452                         cmdreg &= ~(DDIR);
 453         }
 454
 455         if (host->use_dma)
 456                 cmdreg |= DMA_EN;
 457
 458         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 459         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 460 }
 461
 462 static int
 463 mmc_omap_get_dma_dir(struct mmc_omap_host *host, struct mmc_data *data)
 464 {
 465         if (data->flags & MMC_DATA_WRITE)
 466                 return DMA_TO_DEVICE;
 467         else
 468                 return DMA_FROM_DEVICE;
 469 }
 470
 471 /*
 472  * Notify the transfer complete to MMC core
 473  */
 474 static void
 475 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 476 {
 477         if (!data) {
 478                 struct mmc_request *mrq = host->mrq;
 479
 480                 host->mrq = NULL;
 481                 mmc_request_done(host->mmc, mrq);
 482                 return;
 483         }
 484
 485         host->data = NULL;
 486
 487         if (host->use_dma && host->dma_ch != -1)
 488                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 489                         mmc_omap_get_dma_dir(host, data));
 490
 491         if (!data->error)
 492                 data->bytes_xfered += data->blocks * (data->blksz);
 493         else
 494                 data->bytes_xfered = 0;
 495
 496         if (!data->stop) {
 497                 host->mrq = NULL;
 498                 mmc_request_done(host->mmc, data->mrq);
 499                 return;
 500         }
 501         mmc_omap_start_command(host, data->stop, NULL);
 502 }
 503
 504 /*
 505  * Notify the core about command completion
 506  */
 507 static void
 508 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 509 {
 510         host->cmd = NULL;
 511
 512         if (cmd->flags & MMC_RSP_PRESENT) {
 513                 if (cmd->flags & MMC_RSP_136) {
 514                         /* response type 2 */
 515                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 516                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 517                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 518                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 519                 } else {
 520                         /* response types 1, 1b, 3, 4, 5, 6 */
 521                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 522                 }
 523         }
 524         if ((host->data == NULL && !host->response_busy) || cmd->error) {
 525                 host->mrq = NULL;
 526                 mmc_request_done(host->mmc, cmd->mrq);
 527         }
 528 }
 529
 530 /*
 531  * DMA clean up for command errors
 532  */
 533 static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno)
 534 {
 535         host->data->error = errno;
 536
 537         if (host->use_dma && host->dma_ch != -1) {
 538                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 539                         mmc_omap_get_dma_dir(host, host->data));
 540                 omap_free_dma(host->dma_ch);
 541                 host->dma_ch = -1;
 542                 up(&host->sem);
 543         }
 544         host->data = NULL;
 545 }
 546
 547 /*
 548  * Readable error output
 549  */
 550 #ifdef CONFIG_MMC_DEBUG
 551 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 552 {
 553         /* --- means reserved bit without definition at documentation */
 554         static const char *mmc_omap_status_bits[] = {
 555                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 556                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 557                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 558                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 559         };
 560         char res[256];
 561         char *buf = res;
 562         int len, i;
 563
 564         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 565         buf += len;
 566
 567         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 568                 if (status & (1 << i)) {
 569                         len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
 570                         buf += len;
 571                 }
 572
 573         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
 574 }
 575 #endif  /* CONFIG_MMC_DEBUG */
 576
 577 /*
 578  * MMC controller internal state machines reset
 579  *
 580  * Used to reset command or data internal state machines, using respectively
 581  *  SRC or SRD bit of SYSCTL register
 582  * Can be called from interrupt context
 583  */
 584 static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
 585                 unsigned long bit)
 586 {
 587         unsigned long i = 0;
 588         unsigned long limit = (loops_per_jiffy *
 589                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
 590
 591         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 592                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 593
 594         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 595                 (i++ < limit))
 596                 cpu_relax();
 597
 598         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 599                 dev_err(mmc_dev(host->mmc),
 600                         "Timeout waiting on controller reset in %s\n",
 601                         __func__);
 602 }
 603
 604 /*
 605  * MMC controller IRQ handler
 606  */
 607 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 608 {
 609         struct mmc_omap_host *host = dev_id;
 610         struct mmc_data *data;
 611         int end_cmd = 0, end_trans = 0, status;
 612
 613         if (host->mrq == NULL) {
 614                 OMAP_HSMMC_WRITE(host->base, STAT,
 615                         OMAP_HSMMC_READ(host->base, STAT));
 616                 /* Flush posted write */
 617                 OMAP_HSMMC_READ(host->base, STAT);
 618                 return IRQ_HANDLED;
 619         }
 620
 621         data = host->data;
 622         status = OMAP_HSMMC_READ(host->base, STAT);
 623         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 624
 625         if (status & ERR) {
 626 #ifdef CONFIG_MMC_DEBUG
 627                 mmc_omap_report_irq(host, status);
 628 #endif
 629                 if ((status & CMD_TIMEOUT) ||
 630                         (status & CMD_CRC)) {
 631                         if (host->cmd) {
 632                                 if (status & CMD_TIMEOUT) {
 633                                         mmc_omap_reset_controller_fsm(host, SRC);
 634                                         host->cmd->error = -ETIMEDOUT;
 635                                 } else {
 636                                         host->cmd->error = -EILSEQ;
 637                                 }
 638                                 end_cmd = 1;
 639                         }
 640                         if (host->data || host->response_busy) {
 641                                 if (host->data)
 642                                         mmc_dma_cleanup(host, -ETIMEDOUT);
 643                                 host->response_busy = 0;
 644                                 mmc_omap_reset_controller_fsm(host, SRD);
 645                         }
 646                 }
 647                 if ((status & DATA_TIMEOUT) ||
 648                         (status & DATA_CRC)) {
 649                         if (host->data || host->response_busy) {
 650                                 int err = (status & DATA_TIMEOUT) ?
 651                                                 -ETIMEDOUT : -EILSEQ;
 652
 653                                 if (host->data)
 654                                         mmc_dma_cleanup(host, err);
 655                                 else
 656                                         host->mrq->cmd->error = err;
 657                                 host->response_busy = 0;
 658                                 mmc_omap_reset_controller_fsm(host, SRD);
 659                                 end_trans = 1;
 660                         }
 661                 }
 662                 if (status & CARD_ERR) {
 663                         dev_dbg(mmc_dev(host->mmc),
 664                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 665                         if (host->cmd)
 666                                 end_cmd = 1;
 667                         if (host->data)
 668                                 end_trans = 1;
 669                 }
 670         }
 671
 672         OMAP_HSMMC_WRITE(host->base, STAT, status);
 673         /* Flush posted write */
 674         OMAP_HSMMC_READ(host->base, STAT);
 675
 676         if (end_cmd || ((status & CC) && host->cmd))
 677                 mmc_omap_cmd_done(host, host->cmd);
 678         if (end_trans || (status & TC))
 679                 mmc_omap_xfer_done(host, data);
 680
 681         return IRQ_HANDLED;
 682 }
 683
 684 static void set_sd_bus_power(struct mmc_omap_host *host)
 685 {
 686         unsigned long i;
 687
 688         OMAP_HSMMC_WRITE(host->base, HCTL,
 689                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 690         for (i = 0; i < loops_per_jiffy; i++) {
 691                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
 692                         break;
 693                 cpu_relax();
 694         }
 695 }
 696
 697 /*
 698  * Switch MMC interface voltage ... only relevant for MMC1.
 699  *
 700  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
 701  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
 702  * Some chips, like eMMC ones, use internal transceivers.
 703  */
 704 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 705 {
 706         u32 reg_val = 0;
 707         int ret;
 708
 709         /* Disable the clocks */
 710         clk_disable(host->fclk);
 711         clk_disable(host->iclk);
 712         clk_disable(host->dbclk);
 713
 714         /* Turn the power off */
 715         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 716         if (ret != 0)
 717                 goto err;
 718
 719         /* Turn the power ON with given VDD 1.8 or 3.0v */
 720         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 721         if (ret != 0)
 722                 goto err;
 723
 724         clk_enable(host->fclk);
 725         clk_enable(host->iclk);
 726         clk_enable(host->dbclk);
 727
 728         OMAP_HSMMC_WRITE(host->base, HCTL,
 729                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 730         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 731
 732         /*
 733          * If a MMC dual voltage card is detected, the set_ios fn calls
 734          * this fn with VDD bit set for 1.8V. Upon card removal from the
 735          * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
 736          *
 737          * Cope with a bit of slop in the range ... per data sheets:
 738          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
 739          *    but recommended values are 1.71V to 1.89V
 740          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
 741          *    but recommended values are 2.7V to 3.3V
 742          *
 743          * Board setup code shouldn't permit anything very out-of-range.
 744          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
 745          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
 746          */
 747         if ((1 << vdd) <= MMC_VDD_23_24)
 748                 reg_val |= SDVS18;
 749         else
 750                 reg_val |= SDVS30;
 751
 752         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 753         set_sd_bus_power(host);
 754
 755         return 0;
 756 err:
 757         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 758         return ret;
 759 }
 760
 761 /*
 762  * Work Item to notify the core about card insertion/removal
 763  */
 764 static void mmc_omap_detect(struct work_struct *work)
 765 {
 766         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 767                                                 mmc_carddetect_work);
 768         struct omap_mmc_slot_data *slot = &mmc_slot(host);
 769         int carddetect;
 770
 771         if (host->suspended)
 772                 return;
 773
 774         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 775
 776         if (mmc_slot(host).card_detect)
 777                 carddetect = slot->card_detect(slot->card_detect_irq);
 778         else
 779                 carddetect = -ENOSYS;
 780
 781         if (carddetect) {
 782                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 783         } else {
 784                 mmc_host_enable(host->mmc);
 785                 mmc_omap_reset_controller_fsm(host, SRD);
 786                 mmc_host_lazy_disable(host->mmc);
 787                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 788         }
 789 }
 790
 791 /*
 792  * ISR for handling card insertion and removal
 793  */
 794 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 795 {
 796         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 797
 798         if (host->suspended)
 799                 return IRQ_HANDLED;
 800         schedule_work(&host->mmc_carddetect_work);
 801
 802         return IRQ_HANDLED;
 803 }
 804
 805 static int mmc_omap_get_dma_sync_dev(struct mmc_omap_host *host,
 806                                      struct mmc_data *data)
 807 {
 808         int sync_dev;
 809
 810         if (data->flags & MMC_DATA_WRITE)
 811                 sync_dev = host->dma_line_tx;
 812         else
 813                 sync_dev = host->dma_line_rx;
 814         return sync_dev;
 815 }
 816
 817 static void mmc_omap_config_dma_params(struct mmc_omap_host *host,
 818                                        struct mmc_data *data,
 819                                        struct scatterlist *sgl)
 820 {
 821         int blksz, nblk, dma_ch;
 822
 823         dma_ch = host->dma_ch;
 824         if (data->flags & MMC_DATA_WRITE) {
 825                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 826                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 827                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 828                         sg_dma_address(sgl), 0, 0);
 829         } else {
 830                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 831                                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 832                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 833                         sg_dma_address(sgl), 0, 0);
 834         }
 835
 836         blksz = host->data->blksz;
 837         nblk = sg_dma_len(sgl) / blksz;
 838
 839         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 840                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
 841                         mmc_omap_get_dma_sync_dev(host, data),
 842                         !(data->flags & MMC_DATA_WRITE));
 843
 844         omap_start_dma(dma_ch);
 845 }
 846
 847 /*
 848  * DMA call back function
 849  */
 850 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 851 {
 852         struct mmc_omap_host *host = data;
 853
 854         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 855                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 856
 857         if (host->dma_ch < 0)
 858                 return;
 859
 860         host->dma_sg_idx++;
 861         if (host->dma_sg_idx < host->dma_len) {
 862                 /* Fire up the next transfer. */
 863                 mmc_omap_config_dma_params(host, host->data,
 864                                            host->data->sg + host->dma_sg_idx);
 865                 return;
 866         }
 867
 868         omap_free_dma(host->dma_ch);
 869         host->dma_ch = -1;
 870         /*
 871          * DMA Callback: run in interrupt context.
 872          * mutex_unlock will throw a kernel warning if used.
 873          */
 874         up(&host->sem);
 875 }
 876
 877 /*
 878  * Routine to configure and start DMA for the MMC card
 879  */
 880 static int
 881 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 882 {
 883         int dma_ch = 0, ret = 0, err = 1, i;
 884         struct mmc_data *data = req->data;
 885
 886         /* Sanity check: all the SG entries must be aligned by block size. */
 887         for (i = 0; i < data->sg_len; i++) {
 888                 struct scatterlist *sgl;
 889
 890                 sgl = data->sg + i;
 891                 if (sgl->length % data->blksz)
 892                         return -EINVAL;
 893         }
 894         if ((data->blksz % 4) != 0)
 895                 /* REVISIT: The MMC buffer increments only when MSB is written.
 896                  * Return error for blksz which is non multiple of four.
 897                  */
 898                 return -EINVAL;
 899
 900         /*
 901          * If for some reason the DMA transfer is still active,
 902          * we wait for timeout period and free the dma
 903          */
 904         if (host->dma_ch != -1) {
 905                 set_current_state(TASK_UNINTERRUPTIBLE);
 906                 schedule_timeout(100);
 907                 if (down_trylock(&host->sem)) {
 908                         omap_free_dma(host->dma_ch);
 909                         host->dma_ch = -1;
 910                         up(&host->sem);
 911                         return err;
 912                 }
 913         } else {
 914                 if (down_trylock(&host->sem))
 915                         return err;
 916         }
 917
 918         ret = omap_request_dma(mmc_omap_get_dma_sync_dev(host, data), "MMC/SD",
 919                                mmc_omap_dma_cb,host, &dma_ch);
 920         if (ret != 0) {
 921                 dev_err(mmc_dev(host->mmc),
 922                         "%s: omap_request_dma() failed with %d\n",
 923                         mmc_hostname(host->mmc), ret);
 924                 return ret;
 925         }
 926
 927         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 928                         data->sg_len, mmc_omap_get_dma_dir(host, data));
 929         host->dma_ch = dma_ch;
 930         host->dma_sg_idx = 0;
 931
 932         mmc_omap_config_dma_params(host, data, data->sg);
 933
 934         return 0;
 935 }
 936
 937 static void set_data_timeout(struct mmc_omap_host *host,
 938                              struct mmc_request *req)
 939 {
 940         unsigned int timeout, cycle_ns;
 941         uint32_t reg, clkd, dto = 0;
 942
 943         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
 944         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
 945         if (clkd == 0)
 946                 clkd = 1;
 947
 948         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
 949         timeout = req->data->timeout_ns / cycle_ns;
 950         timeout += req->data->timeout_clks;
 951         if (timeout) {
 952                 while ((timeout & 0x80000000) == 0) {
 953                         dto += 1;
 954                         timeout <<= 1;
 955                 }
 956                 dto = 31 - dto;
 957                 timeout <<= 1;
 958                 if (timeout && dto)
 959                         dto += 1;
 960                 if (dto >= 13)
 961                         dto -= 13;
 962                 else
 963                         dto = 0;
 964                 if (dto > 14)
 965                         dto = 14;
 966         }
 967
 968         reg &= ~DTO_MASK;
 969         reg |= dto << DTO_SHIFT;
 970         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
 971 }
 972
 973 /*
 974  * Configure block length for MMC/SD cards and initiate the transfer.
 975  */
 976 static int
 977 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 978 {
 979         int ret;
 980         host->data = req->data;
 981
 982         if (req->data == NULL) {
 983                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 984                 return 0;
 985         }
 986
 987         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 988                                         | (req->data->blocks << 16));
 989         set_data_timeout(host, req);
 990
 991         if (host->use_dma) {
 992                 ret = mmc_omap_start_dma_transfer(host, req);
 993                 if (ret != 0) {
 994                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 995                         return ret;
 996                 }
 997         }
 998         return 0;
 999 }
1000
1001 /*
1002  * Request function. for read/write operation
1003  */
1004 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
1005 {
1006         struct mmc_omap_host *host = mmc_priv(mmc);
1007         int err;
1008
1009         WARN_ON(host->mrq != NULL);
1010         host->mrq = req;
1011         err = mmc_omap_prepare_data(host, req);
1012         if (err) {
1013                 req->cmd->error = err;
1014                 if (req->data)
1015                         req->data->error = err;
1016                 host->mrq = NULL;
1017                 mmc_request_done(mmc, req);
1018                 return;
1019         }
1020
1021         mmc_omap_start_command(host, req->cmd, req->data);
1022 }
1023
1024
1025 /* Routine to configure clock values. Exposed API to core */
1026 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1027 {
1028         struct mmc_omap_host *host = mmc_priv(mmc);
1029         u16 dsor = 0;
1030         unsigned long regval;
1031         unsigned long timeout;
1032         u32 con;
1033         int do_send_init_stream = 0;
1034
1035         mmc_host_enable(host->mmc);
1036
1037         if (ios->power_mode != host->power_mode) {
1038                 switch (ios->power_mode) {
1039                 case MMC_POWER_OFF:
1040                         mmc_slot(host).set_power(host->dev, host->slot_id,
1041                                                  0, 0);
1042                         host->vdd = 0;
1043                         break;
1044                 case MMC_POWER_UP:
1045                         mmc_slot(host).set_power(host->dev, host->slot_id,
1046                                                  1, ios->vdd);
1047                         host->vdd = ios->vdd;
1048                         break;
1049                 case MMC_POWER_ON:
1050                         do_send_init_stream = 1;
1051                         break;
1052                 }
1053                 host->power_mode = ios->power_mode;
1054         }
1055
1056         /* FIXME: set registers based only on changes to ios */
1057
1058         con = OMAP_HSMMC_READ(host->base, CON);
1059         switch (mmc->ios.bus_width) {
1060         case MMC_BUS_WIDTH_8:
1061                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1062                 break;
1063         case MMC_BUS_WIDTH_4:
1064                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1065                 OMAP_HSMMC_WRITE(host->base, HCTL,
1066                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1067                 break;
1068         case MMC_BUS_WIDTH_1:
1069                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1070                 OMAP_HSMMC_WRITE(host->base, HCTL,
1071                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1072                 break;
1073         }
1074
1075         if (host->id == OMAP_MMC1_DEVID) {
1076                 /* Only MMC1 can interface at 3V without some flavor
1077                  * of external transceiver; but they all handle 1.8V.
1078                  */
1079                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1080                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1081                                 /*
1082                                  * The mmc_select_voltage fn of the core does
1083                                  * not seem to set the power_mode to
1084                                  * MMC_POWER_UP upon recalculating the voltage.
1085                                  * vdd 1.8v.
1086                                  */
1087                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
1088                                         dev_dbg(mmc_dev(host->mmc),
1089                                                 "Switch operation failed\n");
1090                 }
1091         }
1092
1093         if (ios->clock) {
1094                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1095                 if (dsor < 1)
1096                         dsor = 1;
1097
1098                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1099                         dsor++;
1100
1101                 if (dsor > 250)
1102                         dsor = 250;
1103         }
1104         omap_mmc_stop_clock(host);
1105         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1106         regval = regval & ~(CLKD_MASK);
1107         regval = regval | (dsor << 6) | (DTO << 16);
1108         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1109         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1110                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1111
1112         /* Wait till the ICS bit is set */
1113         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1114         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
1115                 && time_before(jiffies, timeout))
1116                 msleep(1);
1117
1118         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1119                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1120
1121         if (do_send_init_stream)
1122                 send_init_stream(host);
1123
1124         con = OMAP_HSMMC_READ(host->base, CON);
1125         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1126                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1127         else
1128                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
1129
1130         if (host->power_mode == MMC_POWER_OFF)
1131                 mmc_host_disable(host->mmc);
1132         else
1133                 mmc_host_lazy_disable(host->mmc);
1134 }
1135
1136 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1137 {
1138         struct mmc_omap_host *host = mmc_priv(mmc);
1139         struct omap_mmc_platform_data *pdata = host->pdata;
1140
1141         if (!pdata->slots[0].card_detect)
1142                 return -ENOSYS;
1143         return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
1144 }
1145
1146 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1147 {
1148         struct mmc_omap_host *host = mmc_priv(mmc);
1149         struct omap_mmc_platform_data *pdata = host->pdata;
1150
1151         if (!pdata->slots[0].get_ro)
1152                 return -ENOSYS;
1153         return pdata->slots[0].get_ro(host->dev, 0);
1154 }
1155
1156 static void omap_hsmmc_init(struct mmc_omap_host *host)
1157 {
1158         u32 hctl, capa, value;
1159
1160         /* Only MMC1 supports 3.0V */
1161         if (host->id == OMAP_MMC1_DEVID) {
1162                 hctl = SDVS30;
1163                 capa = VS30 | VS18;
1164         } else {
1165                 hctl = SDVS18;
1166                 capa = VS18;
1167         }
1168
1169         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1170         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1171
1172         value = OMAP_HSMMC_READ(host->base, CAPA);
1173         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1174
1175         /* Set the controller to AUTO IDLE mode */
1176         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1177         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1178
1179         /* Set SD bus power bit */
1180         set_sd_bus_power(host);
1181 }
1182
1183 /*
1184  * Dynamic power saving handling, FSM:
1185  *   ENABLED -> DISABLED -> OFF / REGSLEEP
1186  *     ^___________|          |
1187  *     |______________________|
1188  *
1189  * ENABLED:   mmc host is fully functional
1190  * DISABLED:  fclk is off
1191  * OFF:       fclk is off,voltage regulator is off
1192  * REGSLEEP:  fclk is off,voltage regulator is asleep
1193  *
1194  * Transition handlers return the timeout for the next state transition
1195  * or negative error.
1196  */
1197
1198 enum {ENABLED = 0, DISABLED, REGSLEEP, OFF};
1199
1200 /* Handler for [ENABLED -> DISABLED] transition */
1201 static int omap_mmc_enabled_to_disabled(struct mmc_omap_host *host)
1202 {
1203         omap_mmc_save_ctx(host);
1204         clk_disable(host->fclk);
1205         host->dpm_state = DISABLED;
1206
1207         dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1208
1209         if (host->power_mode == MMC_POWER_OFF)
1210                 return 0;
1211
1212         return msecs_to_jiffies(OMAP_MMC_OFF_TIMEOUT);
1213 }
1214
1215 /* Handler for [DISABLED -> OFF] transition */
1216 static int omap_mmc_disabled_to_off(struct mmc_omap_host *host)
1217 {
1218         int new_state;
1219
1220         dev_dbg(mmc_dev(host->mmc), "DISABLED -> OFF\n");
1221
1222         if (!mmc_try_claim_host(host->mmc))
1223                 return 0;
1224
1225         clk_enable(host->fclk);
1226
1227         omap_mmc_restore_ctx(host);
1228
1229         if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1230             mmc_slot(host).card_detect ||
1231             (mmc_slot(host).get_cover_state &&
1232              mmc_slot(host).get_cover_state(host->dev, host->slot_id))) {
1233                 mmc_power_save_host(host->mmc);
1234                 new_state = OFF;
1235         } else {
1236                 if (mmc_slot(host).set_sleep)
1237                         mmc_slot(host).set_sleep(host->dev, host->slot_id,
1238                                                  1, 0, 0);
1239                 new_state = REGSLEEP;
1240         }
1241
1242         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1243         OMAP_HSMMC_WRITE(host->base, IE, 0);
1244         OMAP_HSMMC_WRITE(host->base, HCTL,
1245                  OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
1246
1247         clk_disable(host->fclk);
1248         clk_disable(host->iclk);
1249         clk_disable(host->dbclk);
1250
1251         host->dpm_state = new_state;
1252
1253         mmc_release_host(host->mmc);
1254
1255         return 0;
1256 }
1257
1258 /* Handler for [DISABLED -> ENABLED] transition */
1259 static int omap_mmc_disabled_to_enabled(struct mmc_omap_host *host)
1260 {
1261         int err;
1262
1263         err = clk_enable(host->fclk);
1264         if (err < 0)
1265                 return err;
1266
1267         omap_mmc_restore_ctx(host);
1268
1269         host->dpm_state = ENABLED;
1270
1271         dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1272
1273         return 0;
1274 }
1275
1276 /* Handler for [OFF -> ENABLED] transition */
1277 static int omap_mmc_off_to_enabled(struct mmc_omap_host *host)
1278 {
1279         clk_enable(host->fclk);
1280         clk_enable(host->iclk);
1281
1282         if (clk_enable(host->dbclk))
1283                 dev_dbg(mmc_dev(host->mmc),
1284                         "Enabling debounce clk failed\n");
1285
1286         omap_mmc_restore_ctx(host);
1287         omap_hsmmc_init(host);
1288         mmc_power_restore_host(host->mmc);
1289
1290         host->dpm_state = ENABLED;
1291
1292         dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1293
1294         return 0;
1295 }
1296
1297 /* Handler for [REGSLEEP -> ENABLED] transition */
1298 static int omap_mmc_regsleep_to_enabled(struct mmc_omap_host *host)
1299 {
1300         unsigned long timeout;
1301
1302         dev_dbg(mmc_dev(host->mmc), "REGSLEEP -> ENABLED\n");
1303
1304         clk_enable(host->fclk);
1305         clk_enable(host->iclk);
1306
1307         if (clk_enable(host->dbclk))
1308                 dev_dbg(mmc_dev(host->mmc),
1309                         "Enabling debounce clk failed\n");
1310
1311         omap_mmc_restore_ctx(host);
1312
1313         /*
1314          * We turned off interrupts and bus power.  Interrupts
1315          * are turned on by 'mmc_omap_start_command()' so we
1316          * just need to turn on the bus power here.
1317          */
1318         OMAP_HSMMC_WRITE(host->base, HCTL,
1319                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1320
1321         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1322         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP &&
1323                time_before(jiffies, timeout))
1324                 ;
1325
1326         if (mmc_slot(host).set_sleep)
1327                 mmc_slot(host).set_sleep(host->dev, host->slot_id,
1328                                          0, host->vdd, 0);
1329
1330         host->dpm_state = ENABLED;
1331
1332         return 0;
1333 }
1334
1335 /*
1336  * Bring MMC host to ENABLED from any other PM state.
1337  */
1338 static int omap_mmc_enable(struct mmc_host *mmc)
1339 {
1340         struct mmc_omap_host *host = mmc_priv(mmc);
1341
1342         switch (host->dpm_state) {
1343         case DISABLED:
1344                 return omap_mmc_disabled_to_enabled(host);
1345         case REGSLEEP:
1346                 return omap_mmc_regsleep_to_enabled(host);
1347         case OFF:
1348                 return omap_mmc_off_to_enabled(host);
1349         default:
1350                 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1351                 return -EINVAL;
1352         }
1353 }
1354
1355 /*
1356  * Bring MMC host in PM state (one level deeper).
1357  */
1358 static int omap_mmc_disable(struct mmc_host *mmc, int lazy)
1359 {
1360         struct mmc_omap_host *host = mmc_priv(mmc);
1361
1362         switch (host->dpm_state) {
1363         case ENABLED: {
1364                 int delay;
1365
1366                 delay = omap_mmc_enabled_to_disabled(host);
1367                 if (lazy || delay < 0)
1368                         return delay;
1369                 return 0;
1370         }
1371         case DISABLED:
1372                 return omap_mmc_disabled_to_off(host);
1373         default:
1374                 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1375                 return -EINVAL;
1376         }
1377 }
1378
1379 static int omap_mmc_enable_fclk(struct mmc_host *mmc)
1380 {
1381         struct mmc_omap_host *host = mmc_priv(mmc);
1382         int err;
1383
1384         err = clk_enable(host->fclk);
1385         if (err)
1386                 return err;
1387         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
1388         omap_mmc_restore_ctx(host);
1389         return 0;
1390 }
1391
1392 static int omap_mmc_disable_fclk(struct mmc_host *mmc, int lazy)
1393 {
1394         struct mmc_omap_host *host = mmc_priv(mmc);
1395
1396         omap_mmc_save_ctx(host);
1397         clk_disable(host->fclk);
1398         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1399         return 0;
1400 }
1401
1402 static const struct mmc_host_ops mmc_omap_ops = {
1403         .enable = omap_mmc_enable_fclk,
1404         .disable = omap_mmc_disable_fclk,
1405         .request = omap_mmc_request,
1406         .set_ios = omap_mmc_set_ios,
1407         .get_cd = omap_hsmmc_get_cd,
1408         .get_ro = omap_hsmmc_get_ro,
1409         /* NYET -- enable_sdio_irq */
1410 };
1411
1412 static const struct mmc_host_ops mmc_omap_ps_ops = {
1413         .enable = omap_mmc_enable,
1414         .disable = omap_mmc_disable,
1415         .request = omap_mmc_request,
1416         .set_ios = omap_mmc_set_ios,
1417         .get_cd = omap_hsmmc_get_cd,
1418         .get_ro = omap_hsmmc_get_ro,
1419         /* NYET -- enable_sdio_irq */
1420 };
1421
1422 #ifdef CONFIG_DEBUG_FS
1423
1424 static int mmc_regs_show(struct seq_file *s, void *data)
1425 {
1426         struct mmc_host *mmc = s->private;
1427         struct mmc_omap_host *host = mmc_priv(mmc);
1428         struct omap_mmc_platform_data *pdata = host->pdata;
1429         int context_loss = 0;
1430
1431         if (pdata->get_context_loss_count)
1432                 context_loss = pdata->get_context_loss_count(host->dev);
1433
1434         seq_printf(s, "mmc%d:\n"
1435                         " enabled:\t%d\n"
1436                         " dpm_state:\t%d\n"
1437                         " nesting_cnt:\t%d\n"
1438                         " ctx_loss:\t%d:%d\n"
1439                         "\nregs:\n",
1440                         mmc->index, mmc->enabled ? 1 : 0,
1441                         host->dpm_state, mmc->nesting_cnt,
1442                         host->context_loss, context_loss);
1443
1444         if (host->suspended || host->dpm_state == OFF ||
1445             host->dpm_state == REGSLEEP) {
1446                 seq_printf(s, "host suspended, can't read registers\n");
1447                 return 0;
1448         }
1449
1450         if (clk_enable(host->fclk) != 0) {
1451                 seq_printf(s, "can't read the regs\n");
1452                 return 0;
1453         }
1454
1455         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1456                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1457         seq_printf(s, "CON:\t\t0x%08x\n",
1458                         OMAP_HSMMC_READ(host->base, CON));
1459         seq_printf(s, "HCTL:\t\t0x%08x\n",
1460                         OMAP_HSMMC_READ(host->base, HCTL));
1461         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1462                         OMAP_HSMMC_READ(host->base, SYSCTL));
1463         seq_printf(s, "IE:\t\t0x%08x\n",
1464                         OMAP_HSMMC_READ(host->base, IE));
1465         seq_printf(s, "ISE:\t\t0x%08x\n",
1466                         OMAP_HSMMC_READ(host->base, ISE));
1467         seq_printf(s, "CAPA:\t\t0x%08x\n",
1468                         OMAP_HSMMC_READ(host->base, CAPA));
1469
1470         clk_disable(host->fclk);
1471
1472         return 0;
1473 }
1474
1475 static int mmc_regs_open(struct inode *inode, struct file *file)
1476 {
1477         return single_open(file, mmc_regs_show, inode->i_private);
1478 }
1479
1480 static const struct file_operations mmc_regs_fops = {
1481         .open           = mmc_regs_open,
1482         .read           = seq_read,
1483         .llseek         = seq_lseek,
1484         .release        = single_release,
1485 };
1486
1487 static void omap_mmc_debugfs(struct mmc_host *mmc)
1488 {
1489         if (mmc->debugfs_root)
1490                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1491                         mmc, &mmc_regs_fops);
1492 }
1493
1494 #else
1495
1496 static void omap_mmc_debugfs(struct mmc_host *mmc)
1497 {
1498 }
1499
1500 #endif
1501
1502 static int __init omap_mmc_probe(struct platform_device *pdev)
1503 {
1504         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1505         struct mmc_host *mmc;
1506         struct mmc_omap_host *host = NULL;
1507         struct resource *res;
1508         int ret = 0, irq;
1509
1510         if (pdata == NULL) {
1511                 dev_err(&pdev->dev, "Platform Data is missing\n");
1512                 return -ENXIO;
1513         }
1514
1515         if (pdata->nr_slots == 0) {
1516                 dev_err(&pdev->dev, "No Slots\n");
1517                 return -ENXIO;
1518         }
1519
1520         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1521         irq = platform_get_irq(pdev, 0);
1522         if (res == NULL || irq < 0)
1523                 return -ENXIO;
1524
1525         res = request_mem_region(res->start, res->end - res->start + 1,
1526                                                         pdev->name);
1527         if (res == NULL)
1528                 return -EBUSY;
1529
1530         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1531         if (!mmc) {
1532                 ret = -ENOMEM;
1533                 goto err;
1534         }
1535
1536         host            = mmc_priv(mmc);
1537         host->mmc       = mmc;
1538         host->pdata     = pdata;
1539         host->dev       = &pdev->dev;
1540         host->use_dma   = 1;
1541         host->dev->dma_mask = &pdata->dma_mask;
1542         host->dma_ch    = -1;
1543         host->irq       = irq;
1544         host->id        = pdev->id;
1545         host->slot_id   = 0;
1546         host->mapbase   = res->start;
1547         host->base      = ioremap(host->mapbase, SZ_4K);
1548         host->power_mode = -1;
1549
1550         platform_set_drvdata(pdev, host);
1551         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
1552
1553         if (pdata->slots[host->slot_id].power_saving)
1554                 mmc->ops        = &mmc_omap_ps_ops;
1555         else
1556                 mmc->ops        = &mmc_omap_ops;
1557
1558         mmc->f_min      = 400000;
1559         mmc->f_max      = 52000000;
1560
1561         sema_init(&host->sem, 1);
1562
1563         host->iclk = clk_get(&pdev->dev, "ick");
1564         if (IS_ERR(host->iclk)) {
1565                 ret = PTR_ERR(host->iclk);
1566                 host->iclk = NULL;
1567                 goto err1;
1568         }
1569         host->fclk = clk_get(&pdev->dev, "fck");
1570         if (IS_ERR(host->fclk)) {
1571                 ret = PTR_ERR(host->fclk);
1572                 host->fclk = NULL;
1573                 clk_put(host->iclk);
1574                 goto err1;
1575         }
1576
1577         omap_mmc_save_ctx(host);
1578
1579         mmc->caps |= MMC_CAP_DISABLE;
1580         mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
1581         /* we start off in DISABLED state */
1582         host->dpm_state = DISABLED;
1583
1584         if (mmc_host_enable(host->mmc) != 0) {
1585                 clk_put(host->iclk);
1586                 clk_put(host->fclk);
1587                 goto err1;
1588         }
1589
1590         if (clk_enable(host->iclk) != 0) {
1591                 mmc_host_disable(host->mmc);
1592                 clk_put(host->iclk);
1593                 clk_put(host->fclk);
1594                 goto err1;
1595         }
1596
1597         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1598         /*
1599          * MMC can still work without debounce clock.
1600          */
1601         if (IS_ERR(host->dbclk))
1602                 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1603         else
1604                 if (clk_enable(host->dbclk) != 0)
1605                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1606                                                         " clk failed\n");
1607                 else
1608                         host->dbclk_enabled = 1;
1609
1610         /* Since we do only SG emulation, we can have as many segs
1611          * as we want. */
1612         mmc->max_phys_segs = 1024;
1613         mmc->max_hw_segs = 1024;
1614
1615         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1616         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1617         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1618         mmc->max_seg_size = mmc->max_req_size;
1619
1620         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1621
1622         if (pdata->slots[host->slot_id].wires >= 8)
1623                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1624         else if (pdata->slots[host->slot_id].wires >= 4)
1625                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1626
1627         if (pdata->slots[host->slot_id].nonremovable)
1628                 mmc->caps |= MMC_CAP_NONREMOVABLE;
1629
1630         omap_hsmmc_init(host);
1631
1632         /* Select DMA lines */
1633         switch (host->id) {
1634         case OMAP_MMC1_DEVID:
1635                 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1636                 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1637                 break;
1638         case OMAP_MMC2_DEVID:
1639                 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1640                 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1641                 break;
1642         case OMAP_MMC3_DEVID:
1643                 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
1644                 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
1645                 break;
1646         default:
1647                 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
1648                 goto err_irq;
1649         }
1650
1651         /* Request IRQ for MMC operations */
1652         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1653                         mmc_hostname(mmc), host);
1654         if (ret) {
1655                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1656                 goto err_irq;
1657         }
1658
1659         /* initialize power supplies, gpios, etc */
1660         if (pdata->init != NULL) {
1661                 if (pdata->init(&pdev->dev) != 0) {
1662                         dev_dbg(mmc_dev(host->mmc), "late init error\n");
1663                         goto err_irq_cd_init;
1664                 }
1665         }
1666         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1667
1668         /* Request IRQ for card detect */
1669         if ((mmc_slot(host).card_detect_irq)) {
1670                 ret = request_irq(mmc_slot(host).card_detect_irq,
1671                                   omap_mmc_cd_handler,
1672                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1673                                           | IRQF_DISABLED,
1674                                   mmc_hostname(mmc), host);
1675                 if (ret) {
1676                         dev_dbg(mmc_dev(host->mmc),
1677                                 "Unable to grab MMC CD IRQ\n");
1678                         goto err_irq_cd;
1679                 }
1680         }
1681
1682         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1683         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1684
1685         mmc_host_lazy_disable(host->mmc);
1686
1687         mmc_add_host(mmc);
1688
1689         if (host->pdata->slots[host->slot_id].name != NULL) {
1690                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1691                 if (ret < 0)
1692                         goto err_slot_name;
1693         }
1694         if (mmc_slot(host).card_detect_irq &&
1695             host->pdata->slots[host->slot_id].get_cover_state) {
1696                 ret = device_create_file(&mmc->class_dev,
1697                                         &dev_attr_cover_switch);
1698                 if (ret < 0)
1699                         goto err_cover_switch;
1700         }
1701
1702         omap_mmc_debugfs(mmc);
1703
1704         return 0;
1705
1706 err_cover_switch:
1707         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1708 err_slot_name:
1709         mmc_remove_host(mmc);
1710 err_irq_cd:
1711         free_irq(mmc_slot(host).card_detect_irq, host);
1712 err_irq_cd_init:
1713         free_irq(host->irq, host);
1714 err_irq:
1715         mmc_host_disable(host->mmc);
1716         clk_disable(host->iclk);
1717         clk_put(host->fclk);
1718         clk_put(host->iclk);
1719         if (host->dbclk_enabled) {
1720                 clk_disable(host->dbclk);
1721                 clk_put(host->dbclk);
1722         }
1723
1724 err1:
1725         iounmap(host->base);
1726 err:
1727         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1728         release_mem_region(res->start, res->end - res->start + 1);
1729         if (host)
1730                 mmc_free_host(mmc);
1731         return ret;
1732 }
1733
1734 static int omap_mmc_remove(struct platform_device *pdev)
1735 {
1736         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1737         struct resource *res;
1738
1739         if (host) {
1740                 mmc_host_enable(host->mmc);
1741                 mmc_remove_host(host->mmc);
1742                 if (host->pdata->cleanup)
1743                         host->pdata->cleanup(&pdev->dev);
1744                 free_irq(host->irq, host);
1745                 if (mmc_slot(host).card_detect_irq)
1746                         free_irq(mmc_slot(host).card_detect_irq, host);
1747                 flush_scheduled_work();
1748
1749                 mmc_host_disable(host->mmc);
1750                 clk_disable(host->iclk);
1751                 clk_put(host->fclk);
1752                 clk_put(host->iclk);
1753                 if (host->dbclk_enabled) {
1754                         clk_disable(host->dbclk);
1755                         clk_put(host->dbclk);
1756                 }
1757
1758                 mmc_free_host(host->mmc);
1759                 iounmap(host->base);
1760         }
1761
1762         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1763         if (res)
1764                 release_mem_region(res->start, res->end - res->start + 1);
1765         platform_set_drvdata(pdev, NULL);
1766
1767         return 0;
1768 }
1769
1770 #ifdef CONFIG_PM
1771 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1772 {
1773         int ret = 0;
1774         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1775
1776         if (host && host->suspended)
1777                 return 0;
1778
1779         if (host) {
1780                 host->suspended = 1;
1781                 if (host->pdata->suspend) {
1782                         ret = host->pdata->suspend(&pdev->dev,
1783                                                         host->slot_id);
1784                         if (ret) {
1785                                 dev_dbg(mmc_dev(host->mmc),
1786                                         "Unable to handle MMC board"
1787                                         " level suspend\n");
1788                                 host->suspended = 0;
1789                                 return ret;
1790                         }
1791                 }
1792                 cancel_work_sync(&host->mmc_carddetect_work);
1793                 mmc_host_enable(host->mmc);
1794                 ret = mmc_suspend_host(host->mmc, state);
1795                 if (ret == 0) {
1796                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1797                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1798
1799
1800                         OMAP_HSMMC_WRITE(host->base, HCTL,
1801                                          OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
1802                         mmc_host_disable(host->mmc);
1803                         clk_disable(host->iclk);
1804                         clk_disable(host->dbclk);
1805                 } else {
1806                         host->suspended = 0;
1807                         if (host->pdata->resume) {
1808                                 ret = host->pdata->resume(&pdev->dev,
1809                                                           host->slot_id);
1810                                 if (ret)
1811                                         dev_dbg(mmc_dev(host->mmc),
1812                                                 "Unmask interrupt failed\n");
1813                         }
1814                         mmc_host_disable(host->mmc);
1815                 }
1816
1817         }
1818         return ret;
1819 }
1820
1821 /* Routine to resume the MMC device */
1822 static int omap_mmc_resume(struct platform_device *pdev)
1823 {
1824         int ret = 0;
1825         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1826
1827         if (host && !host->suspended)
1828                 return 0;
1829
1830         if (host) {
1831                 ret = clk_enable(host->iclk);
1832                 if (ret)
1833                         goto clk_en_err;
1834
1835                 if (clk_enable(host->dbclk) != 0)
1836                         dev_dbg(mmc_dev(host->mmc),
1837                                         "Enabling debounce clk failed\n");
1838
1839                 if (mmc_host_enable(host->mmc) != 0) {
1840                         clk_disable(host->iclk);
1841                         goto clk_en_err;
1842                 }
1843
1844                 omap_hsmmc_init(host);
1845
1846                 if (host->pdata->resume) {
1847                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1848                         if (ret)
1849                                 dev_dbg(mmc_dev(host->mmc),
1850                                         "Unmask interrupt failed\n");
1851                 }
1852
1853                 /* Notify the core to resume the host */
1854                 ret = mmc_resume_host(host->mmc);
1855                 if (ret == 0)
1856                         host->suspended = 0;
1857                 mmc_host_lazy_disable(host->mmc);
1858         }
1859
1860         return ret;
1861
1862 clk_en_err:
1863         dev_dbg(mmc_dev(host->mmc),
1864                 "Failed to enable MMC clocks during resume\n");
1865         return ret;
1866 }
1867
1868 #else
1869 #define omap_mmc_suspend        NULL
1870 #define omap_mmc_resume         NULL
1871 #endif
1872
1873 static struct platform_driver omap_mmc_driver = {
1874         .remove         = omap_mmc_remove,
1875         .suspend        = omap_mmc_suspend,
1876         .resume         = omap_mmc_resume,
1877         .driver         = {
1878                 .name = DRIVER_NAME,
1879                 .owner = THIS_MODULE,
1880         },
1881 };
1882
1883 static int __init omap_mmc_init(void)
1884 {
1885         /* Register the MMC driver */
1886         return platform_driver_probe(&omap_mmc_driver, omap_mmc_probe);
1887 }
1888
1889 static void __exit omap_mmc_cleanup(void)
1890 {
1891         /* Unregister MMC driver */
1892         platform_driver_unregister(&omap_mmc_driver);
1893 }
1894
1895 module_init(omap_mmc_init);
1896 module_exit(omap_mmc_cleanup);
1897
1898 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1899 MODULE_LICENSE("GPL");
1900 MODULE_ALIAS("platform:" DRIVER_NAME);
1901 MODULE_AUTHOR("Texas Instruments Inc");