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   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/timer.h>
  26 #include <linux/clk.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/io.h>
  29 #include <linux/semaphore.h>
  30 #include <mach/dma.h>
  31 #include <mach/hardware.h>
  32 #include <mach/board.h>
  33 #include <mach/mmc.h>
  34 #include <mach/cpu.h>
  35
  36 /* OMAP HSMMC Host Controller Registers */
  37 #define OMAP_HSMMC_SYSCONFIG    0x0010
  38 #define OMAP_HSMMC_CON          0x002C
  39 #define OMAP_HSMMC_BLK          0x0104
  40 #define OMAP_HSMMC_ARG          0x0108
  41 #define OMAP_HSMMC_CMD          0x010C
  42 #define OMAP_HSMMC_RSP10        0x0110
  43 #define OMAP_HSMMC_RSP32        0x0114
  44 #define OMAP_HSMMC_RSP54        0x0118
  45 #define OMAP_HSMMC_RSP76        0x011C
  46 #define OMAP_HSMMC_DATA         0x0120
  47 #define OMAP_HSMMC_HCTL         0x0128
  48 #define OMAP_HSMMC_SYSCTL       0x012C
  49 #define OMAP_HSMMC_STAT         0x0130
  50 #define OMAP_HSMMC_IE           0x0134
  51 #define OMAP_HSMMC_ISE          0x0138
  52 #define OMAP_HSMMC_CAPA         0x0140
  53
  54 #define VS18                    (1 << 26)
  55 #define VS30                    (1 << 25)
  56 #define SDVS18                  (0x5 << 9)
  57 #define SDVS30                  (0x6 << 9)
  58 #define SDVSCLR                 0xFFFFF1FF
  59 #define SDVSDET                 0x00000400
  60 #define AUTOIDLE                0x1
  61 #define SDBP                    (1 << 8)
  62 #define DTO                     0xe
  63 #define ICE                     0x1
  64 #define ICS                     0x2
  65 #define CEN                     (1 << 2)
  66 #define CLKD_MASK               0x0000FFC0
  67 #define CLKD_SHIFT              6
  68 #define DTO_MASK                0x000F0000
  69 #define DTO_SHIFT               16
  70 #define INT_EN_MASK             0x307F0033
  71 #define INIT_STREAM             (1 << 1)
  72 #define DP_SELECT               (1 << 21)
  73 #define DDIR                    (1 << 4)
  74 #define DMA_EN                  0x1
  75 #define MSBS                    (1 << 5)
  76 #define BCE                     (1 << 1)
  77 #define FOUR_BIT                (1 << 1)
  78 #define CC                      0x1
  79 #define TC                      0x02
  80 #define OD                      0x1
  81 #define ERR                     (1 << 15)
  82 #define CMD_TIMEOUT             (1 << 16)
  83 #define DATA_TIMEOUT            (1 << 20)
  84 #define CMD_CRC                 (1 << 17)
  85 #define DATA_CRC                (1 << 21)
  86 #define CARD_ERR                (1 << 28)
  87 #define STAT_CLEAR              0xFFFFFFFF
  88 #define INIT_STREAM_CMD         0x00000000
  89 #define DUAL_VOLT_OCR_BIT       7
  90 #define SRC                     (1 << 25)
  91 #define SRD                     (1 << 26)
  92
  93 /*
  94  * FIXME: Most likely all the data using these _DEVID defines should come
  95  * from the platform_data, or implemented in controller and slot specific
  96  * functions.
  97  */
  98 #define OMAP_MMC1_DEVID         0
  99 #define OMAP_MMC2_DEVID         1
 100
 101 #define OMAP_MMC_DATADIR_NONE   0
 102 #define OMAP_MMC_DATADIR_READ   1
 103 #define OMAP_MMC_DATADIR_WRITE  2
 104 #define MMC_TIMEOUT_MS          20
 105 #define OMAP_MMC_MASTER_CLOCK   96000000
 106 #define DRIVER_NAME             "mmci-omap-hs"
 107
 108 /*
 109  * One controller can have multiple slots, like on some omap boards using
 110  * omap.c controller driver. Luckily this is not currently done on any known
 111  * omap_hsmmc.c device.
 112  */
 113 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 114
 115 /*
 116  * MMC Host controller read/write API's
 117  */
 118 #define OMAP_HSMMC_READ(base, reg)      \
 119         __raw_readl((base) + OMAP_HSMMC_##reg)
 120
 121 #define OMAP_HSMMC_WRITE(base, reg, val) \
 122         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 123
 124 struct mmc_omap_host {
 125         struct  device          *dev;
 126         struct  mmc_host        *mmc;
 127         struct  mmc_request     *mrq;
 128         struct  mmc_command     *cmd;
 129         struct  mmc_data        *data;
 130         struct  clk             *fclk;
 131         struct  clk             *iclk;
 132         struct  clk             *dbclk;
 133         struct  semaphore       sem;
 134         struct  work_struct     mmc_carddetect_work;
 135         void    __iomem         *base;
 136         resource_size_t         mapbase;
 137         unsigned int            id;
 138         unsigned int            dma_len;
 139         unsigned int            dma_dir;
 140         unsigned char           bus_mode;
 141         unsigned char           datadir;
 142         u32                     *buffer;
 143         u32                     bytesleft;
 144         int                     suspended;
 145         int                     irq;
 146         int                     carddetect;
 147         int                     use_dma, dma_ch;
 148         int                     initstr;
 149         int                     slot_id;
 150         int                     dbclk_enabled;
 151         struct  omap_mmc_platform_data  *pdata;
 152 };
 153
 154 /*
 155  * Stop clock to the card
 156  */
 157 static void omap_mmc_stop_clock(struct mmc_omap_host *host)
 158 {
 159         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 160                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 161         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 162                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 163 }
 164
 165 /*
 166  * Send init stream sequence to card
 167  * before sending IDLE command
 168  */
 169 static void send_init_stream(struct mmc_omap_host *host)
 170 {
 171         int reg = 0;
 172         unsigned long timeout;
 173
 174         disable_irq(host->irq);
 175         OMAP_HSMMC_WRITE(host->base, CON,
 176                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 177         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 178
 179         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 180         while ((reg != CC) && time_before(jiffies, timeout))
 181                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 182
 183         OMAP_HSMMC_WRITE(host->base, CON,
 184                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 185         enable_irq(host->irq);
 186 }
 187
 188 static inline
 189 int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
 190 {
 191         int r = 1;
 192
 193         if (host->pdata->slots[host->slot_id].get_cover_state)
 194                 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
 195                         host->slot_id);
 196         return r;
 197 }
 198
 199 static ssize_t
 200 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 201                            char *buf)
 202 {
 203         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 204         struct mmc_omap_host *host = mmc_priv(mmc);
 205
 206         return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
 207                        "open");
 208 }
 209
 210 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 211
 212 static ssize_t
 213 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 214                         char *buf)
 215 {
 216         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 217         struct mmc_omap_host *host = mmc_priv(mmc);
 218         struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
 219
 220         return sprintf(buf, "slot:%s\n", slot.name);
 221 }
 222
 223 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 224
 225 /*
 226  * Configure the response type and send the cmd.
 227  */
 228 static void
 229 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
 230         struct mmc_data *data)
 231 {
 232         int cmdreg = 0, resptype = 0, cmdtype = 0;
 233
 234         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 235                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 236         host->cmd = cmd;
 237
 238         /*
 239          * Clear status bits and enable interrupts
 240          */
 241         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 242         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 243         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 244
 245         if (cmd->flags & MMC_RSP_PRESENT) {
 246                 if (cmd->flags & MMC_RSP_136)
 247                         resptype = 1;
 248                 else
 249                         resptype = 2;
 250         }
 251
 252         /*
 253          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 254          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 255          * a val of 0x3, rest 0x0.
 256          */
 257         if (cmd == host->mrq->stop)
 258                 cmdtype = 0x3;
 259
 260         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 261
 262         if (data) {
 263                 cmdreg |= DP_SELECT | MSBS | BCE;
 264                 if (data->flags & MMC_DATA_READ)
 265                         cmdreg |= DDIR;
 266                 else
 267                         cmdreg &= ~(DDIR);
 268         }
 269
 270         if (host->use_dma)
 271                 cmdreg |= DMA_EN;
 272
 273         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 274         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 275 }
 276
 277 /*
 278  * Notify the transfer complete to MMC core
 279  */
 280 static void
 281 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 282 {
 283         host->data = NULL;
 284
 285         if (host->use_dma && host->dma_ch != -1)
 286                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 287                         host->dma_dir);
 288
 289         host->datadir = OMAP_MMC_DATADIR_NONE;
 290
 291         if (!data->error)
 292                 data->bytes_xfered += data->blocks * (data->blksz);
 293         else
 294                 data->bytes_xfered = 0;
 295
 296         if (!data->stop) {
 297                 host->mrq = NULL;
 298                 mmc_request_done(host->mmc, data->mrq);
 299                 return;
 300         }
 301         mmc_omap_start_command(host, data->stop, NULL);
 302 }
 303
 304 /*
 305  * Notify the core about command completion
 306  */
 307 static void
 308 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 309 {
 310         host->cmd = NULL;
 311
 312         if (cmd->flags & MMC_RSP_PRESENT) {
 313                 if (cmd->flags & MMC_RSP_136) {
 314                         /* response type 2 */
 315                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 316                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 317                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 318                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 319                 } else {
 320                         /* response types 1, 1b, 3, 4, 5, 6 */
 321                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 322                 }
 323         }
 324         if (host->data == NULL || cmd->error) {
 325                 host->mrq = NULL;
 326                 mmc_request_done(host->mmc, cmd->mrq);
 327         }
 328 }
 329
 330 /*
 331  * DMA clean up for command errors
 332  */
 333 static void mmc_dma_cleanup(struct mmc_omap_host *host)
 334 {
 335         host->data->error = -ETIMEDOUT;
 336
 337         if (host->use_dma && host->dma_ch != -1) {
 338                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 339                         host->dma_dir);
 340                 omap_free_dma(host->dma_ch);
 341                 host->dma_ch = -1;
 342                 up(&host->sem);
 343         }
 344         host->data = NULL;
 345         host->datadir = OMAP_MMC_DATADIR_NONE;
 346 }
 347
 348 /*
 349  * Readable error output
 350  */
 351 #ifdef CONFIG_MMC_DEBUG
 352 static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
 353 {
 354         /* --- means reserved bit without definition at documentation */
 355         static const char *mmc_omap_status_bits[] = {
 356                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 357                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 358                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 359                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 360         };
 361         char res[256];
 362         char *buf = res;
 363         int len, i;
 364
 365         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 366         buf += len;
 367
 368         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 369                 if (status & (1 << i)) {
 370                         len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
 371                         buf += len;
 372                 }
 373
 374         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
 375 }
 376 #endif  /* CONFIG_MMC_DEBUG */
 377
 378
 379 /*
 380  * MMC controller IRQ handler
 381  */
 382 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 383 {
 384         struct mmc_omap_host *host = dev_id;
 385         struct mmc_data *data;
 386         int end_cmd = 0, end_trans = 0, status;
 387
 388         if (host->cmd == NULL && host->data == NULL) {
 389                 OMAP_HSMMC_WRITE(host->base, STAT,
 390                         OMAP_HSMMC_READ(host->base, STAT));
 391                 return IRQ_HANDLED;
 392         }
 393
 394         data = host->data;
 395         status = OMAP_HSMMC_READ(host->base, STAT);
 396         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 397
 398         if (status & ERR) {
 399 #ifdef CONFIG_MMC_DEBUG
 400                 mmc_omap_report_irq(host, status);
 401 #endif
 402                 if ((status & CMD_TIMEOUT) ||
 403                         (status & CMD_CRC)) {
 404                         if (host->cmd) {
 405                                 if (status & CMD_TIMEOUT) {
 406                                         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 407                                                 OMAP_HSMMC_READ(host->base,
 408                                                                 SYSCTL) | SRC);
 409                                         while (OMAP_HSMMC_READ(host->base,
 410                                                         SYSCTL) & SRC)
 411                                                 ;
 412
 413                                         host->cmd->error = -ETIMEDOUT;
 414                                 } else {
 415                                         host->cmd->error = -EILSEQ;
 416                                 }
 417                                 end_cmd = 1;
 418                         }
 419                         if (host->data)
 420                                 mmc_dma_cleanup(host);
 421                 }
 422                 if ((status & DATA_TIMEOUT) ||
 423                         (status & DATA_CRC)) {
 424                         if (host->data) {
 425                                 if (status & DATA_TIMEOUT)
 426                                         mmc_dma_cleanup(host);
 427                                 else
 428                                         host->data->error = -EILSEQ;
 429                                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 430                                         OMAP_HSMMC_READ(host->base,
 431                                                         SYSCTL) | SRD);
 432                                 while (OMAP_HSMMC_READ(host->base,
 433                                                 SYSCTL) & SRD)
 434                                         ;
 435                                 end_trans = 1;
 436                         }
 437                 }
 438                 if (status & CARD_ERR) {
 439                         dev_dbg(mmc_dev(host->mmc),
 440                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 441                         if (host->cmd)
 442                                 end_cmd = 1;
 443                         if (host->data)
 444                                 end_trans = 1;
 445                 }
 446         }
 447
 448         OMAP_HSMMC_WRITE(host->base, STAT, status);
 449
 450         if (end_cmd || (status & CC))
 451                 mmc_omap_cmd_done(host, host->cmd);
 452         if (end_trans || (status & TC))
 453                 mmc_omap_xfer_done(host, data);
 454
 455         return IRQ_HANDLED;
 456 }
 457
 458 /*
 459  * Switch MMC operating voltage
 460  */
 461 static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
 462 {
 463         u32 reg_val = 0;
 464         int ret;
 465
 466         /* Disable the clocks */
 467         clk_disable(host->fclk);
 468         clk_disable(host->iclk);
 469         clk_disable(host->dbclk);
 470
 471         /* Turn the power off */
 472         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 473         if (ret != 0)
 474                 goto err;
 475
 476         /* Turn the power ON with given VDD 1.8 or 3.0v */
 477         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
 478         if (ret != 0)
 479                 goto err;
 480
 481         clk_enable(host->fclk);
 482         clk_enable(host->iclk);
 483         clk_enable(host->dbclk);
 484
 485         OMAP_HSMMC_WRITE(host->base, HCTL,
 486                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 487         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 488         /*
 489          * If a MMC dual voltage card is detected, the set_ios fn calls
 490          * this fn with VDD bit set for 1.8V. Upon card removal from the
 491          * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
 492          *
 493          * Only MMC1 supports 3.0V.  MMC2 will not function if SDVS30 is
 494          * set in HCTL.
 495          */
 496         if (host->id == OMAP_MMC1_DEVID && (((1 << vdd) == MMC_VDD_32_33) ||
 497                                 ((1 << vdd) == MMC_VDD_33_34)))
 498                 reg_val |= SDVS30;
 499         if ((1 << vdd) == MMC_VDD_165_195)
 500                 reg_val |= SDVS18;
 501
 502         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 503
 504         OMAP_HSMMC_WRITE(host->base, HCTL,
 505                 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 506
 507         return 0;
 508 err:
 509         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 510         return ret;
 511 }
 512
 513 /*
 514  * Work Item to notify the core about card insertion/removal
 515  */
 516 static void mmc_omap_detect(struct work_struct *work)
 517 {
 518         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 519                                                 mmc_carddetect_work);
 520         struct omap_mmc_slot_data *slot = &mmc_slot(host);
 521
 522         host->carddetect = slot->card_detect(slot->card_detect_irq);
 523
 524         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 525         if (host->carddetect) {
 526                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 527         } else {
 528                 OMAP_HSMMC_WRITE(host->base, SYSCTL,
 529                         OMAP_HSMMC_READ(host->base, SYSCTL) | SRD);
 530                 while (OMAP_HSMMC_READ(host->base, SYSCTL) & SRD)
 531                         ;
 532
 533                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 534         }
 535 }
 536
 537 /*
 538  * ISR for handling card insertion and removal
 539  */
 540 static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
 541 {
 542         struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
 543
 544         schedule_work(&host->mmc_carddetect_work);
 545
 546         return IRQ_HANDLED;
 547 }
 548
 549 /*
 550  * DMA call back function
 551  */
 552 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 553 {
 554         struct mmc_omap_host *host = data;
 555
 556         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 557                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 558
 559         if (host->dma_ch < 0)
 560                 return;
 561
 562         omap_free_dma(host->dma_ch);
 563         host->dma_ch = -1;
 564         /*
 565          * DMA Callback: run in interrupt context.
 566          * mutex_unlock will through a kernel warning if used.
 567          */
 568         up(&host->sem);
 569 }
 570
 571 /*
 572  * Configure dma src and destination parameters
 573  */
 574 static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host,
 575                                 struct mmc_data *data)
 576 {
 577         if (sync_dir == 0) {
 578                 omap_set_dma_dest_params(host->dma_ch, 0,
 579                         OMAP_DMA_AMODE_CONSTANT,
 580                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 581                 omap_set_dma_src_params(host->dma_ch, 0,
 582                         OMAP_DMA_AMODE_POST_INC,
 583                         sg_dma_address(&data->sg[0]), 0, 0);
 584         } else {
 585                 omap_set_dma_src_params(host->dma_ch, 0,
 586                         OMAP_DMA_AMODE_CONSTANT,
 587                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 588                 omap_set_dma_dest_params(host->dma_ch, 0,
 589                         OMAP_DMA_AMODE_POST_INC,
 590                         sg_dma_address(&data->sg[0]), 0, 0);
 591         }
 592         return 0;
 593 }
 594 /*
 595  * Routine to configure and start DMA for the MMC card
 596  */
 597 static int
 598 mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
 599 {
 600         int sync_dev, sync_dir = 0;
 601         int dma_ch = 0, ret = 0, err = 1;
 602         struct mmc_data *data = req->data;
 603
 604         /*
 605          * If for some reason the DMA transfer is still active,
 606          * we wait for timeout period and free the dma
 607          */
 608         if (host->dma_ch != -1) {
 609                 set_current_state(TASK_UNINTERRUPTIBLE);
 610                 schedule_timeout(100);
 611                 if (down_trylock(&host->sem)) {
 612                         omap_free_dma(host->dma_ch);
 613                         host->dma_ch = -1;
 614                         up(&host->sem);
 615                         return err;
 616                 }
 617         } else {
 618                 if (down_trylock(&host->sem))
 619                         return err;
 620         }
 621
 622         if (!(data->flags & MMC_DATA_WRITE)) {
 623                 host->dma_dir = DMA_FROM_DEVICE;
 624                 if (host->id == OMAP_MMC1_DEVID)
 625                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 626                 else
 627                         sync_dev = OMAP24XX_DMA_MMC2_RX;
 628         } else {
 629                 host->dma_dir = DMA_TO_DEVICE;
 630                 if (host->id == OMAP_MMC1_DEVID)
 631                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 632                 else
 633                         sync_dev = OMAP24XX_DMA_MMC2_TX;
 634         }
 635
 636         ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb,
 637                         host, &dma_ch);
 638         if (ret != 0) {
 639                 dev_dbg(mmc_dev(host->mmc),
 640                         "%s: omap_request_dma() failed with %d\n",
 641                         mmc_hostname(host->mmc), ret);
 642                 return ret;
 643         }
 644
 645         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 646                         data->sg_len, host->dma_dir);
 647         host->dma_ch = dma_ch;
 648
 649         if (!(data->flags & MMC_DATA_WRITE))
 650                 mmc_omap_config_dma_param(1, host, data);
 651         else
 652                 mmc_omap_config_dma_param(0, host, data);
 653
 654         if ((data->blksz % 4) == 0)
 655                 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 656                         (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME,
 657                         sync_dev, sync_dir);
 658         else
 659                 /* REVISIT: The MMC buffer increments only when MSB is written.
 660                  * Return error for blksz which is non multiple of four.
 661                  */
 662                 return -EINVAL;
 663
 664         omap_start_dma(dma_ch);
 665         return 0;
 666 }
 667
 668 static void set_data_timeout(struct mmc_omap_host *host,
 669                              struct mmc_request *req)
 670 {
 671         unsigned int timeout, cycle_ns;
 672         uint32_t reg, clkd, dto = 0;
 673
 674         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
 675         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
 676         if (clkd == 0)
 677                 clkd = 1;
 678
 679         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
 680         timeout = req->data->timeout_ns / cycle_ns;
 681         timeout += req->data->timeout_clks;
 682         if (timeout) {
 683                 while ((timeout & 0x80000000) == 0) {
 684                         dto += 1;
 685                         timeout <<= 1;
 686                 }
 687                 dto = 31 - dto;
 688                 timeout <<= 1;
 689                 if (timeout && dto)
 690                         dto += 1;
 691                 if (dto >= 13)
 692                         dto -= 13;
 693                 else
 694                         dto = 0;
 695                 if (dto > 14)
 696                         dto = 14;
 697         }
 698
 699         reg &= ~DTO_MASK;
 700         reg |= dto << DTO_SHIFT;
 701         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
 702 }
 703
 704 /*
 705  * Configure block length for MMC/SD cards and initiate the transfer.
 706  */
 707 static int
 708 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 709 {
 710         int ret;
 711         host->data = req->data;
 712
 713         if (req->data == NULL) {
 714                 host->datadir = OMAP_MMC_DATADIR_NONE;
 715                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
 716                 return 0;
 717         }
 718
 719         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
 720                                         | (req->data->blocks << 16));
 721         set_data_timeout(host, req);
 722
 723         host->datadir = (req->data->flags & MMC_DATA_WRITE) ?
 724                         OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ;
 725
 726         if (host->use_dma) {
 727                 ret = mmc_omap_start_dma_transfer(host, req);
 728                 if (ret != 0) {
 729                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
 730                         return ret;
 731                 }
 732         }
 733         return 0;
 734 }
 735
 736 /*
 737  * Request function. for read/write operation
 738  */
 739 static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 740 {
 741         struct mmc_omap_host *host = mmc_priv(mmc);
 742
 743         WARN_ON(host->mrq != NULL);
 744         host->mrq = req;
 745         mmc_omap_prepare_data(host, req);
 746         mmc_omap_start_command(host, req->cmd, req->data);
 747 }
 748
 749
 750 /* Routine to configure clock values. Exposed API to core */
 751 static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 752 {
 753         struct mmc_omap_host *host = mmc_priv(mmc);
 754         u16 dsor = 0;
 755         unsigned long regval;
 756         unsigned long timeout;
 757
 758         switch (ios->power_mode) {
 759         case MMC_POWER_OFF:
 760                 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 761                 /*
 762                  * Reset bus voltage to 3V if it got set to 1.8V earlier.
 763                  * REVISIT: If we are able to detect cards after unplugging
 764                  * a 1.8V card, this code should not be needed.
 765                  */
 766                 if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
 767                         int vdd = fls(host->mmc->ocr_avail) - 1;
 768                         if (omap_mmc_switch_opcond(host, vdd) != 0)
 769                                 host->mmc->ios.vdd = vdd;
 770                 }
 771                 break;
 772         case MMC_POWER_UP:
 773                 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
 774                 break;
 775         }
 776
 777         switch (mmc->ios.bus_width) {
 778         case MMC_BUS_WIDTH_4:
 779                 OMAP_HSMMC_WRITE(host->base, HCTL,
 780                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 781                 break;
 782         case MMC_BUS_WIDTH_1:
 783                 OMAP_HSMMC_WRITE(host->base, HCTL,
 784                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 785                 break;
 786         }
 787
 788         if (host->id == OMAP_MMC1_DEVID) {
 789                 /* Only MMC1 can operate at 3V/1.8V */
 790                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
 791                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
 792                                 /*
 793                                  * The mmc_select_voltage fn of the core does
 794                                  * not seem to set the power_mode to
 795                                  * MMC_POWER_UP upon recalculating the voltage.
 796                                  * vdd 1.8v.
 797                                  */
 798                                 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
 799                                         dev_dbg(mmc_dev(host->mmc),
 800                                                 "Switch operation failed\n");
 801                 }
 802         }
 803
 804         if (ios->clock) {
 805                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 806                 if (dsor < 1)
 807                         dsor = 1;
 808
 809                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 810                         dsor++;
 811
 812                 if (dsor > 250)
 813                         dsor = 250;
 814         }
 815         omap_mmc_stop_clock(host);
 816         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 817         regval = regval & ~(CLKD_MASK);
 818         regval = regval | (dsor << 6) | (DTO << 16);
 819         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 820         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 821                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 822
 823         /* Wait till the ICS bit is set */
 824         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 825         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
 826                 && time_before(jiffies, timeout))
 827                 msleep(1);
 828
 829         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 830                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 831
 832         if (ios->power_mode == MMC_POWER_ON)
 833                 send_init_stream(host);
 834
 835         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 836                 OMAP_HSMMC_WRITE(host->base, CON,
 837                                 OMAP_HSMMC_READ(host->base, CON) | OD);
 838 }
 839
 840 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
 841 {
 842         struct mmc_omap_host *host = mmc_priv(mmc);
 843         struct omap_mmc_platform_data *pdata = host->pdata;
 844
 845         if (!pdata->slots[0].card_detect)
 846                 return -ENOSYS;
 847         return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
 848 }
 849
 850 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
 851 {
 852         struct mmc_omap_host *host = mmc_priv(mmc);
 853         struct omap_mmc_platform_data *pdata = host->pdata;
 854
 855         if (!pdata->slots[0].get_ro)
 856                 return -ENOSYS;
 857         return pdata->slots[0].get_ro(host->dev, 0);
 858 }
 859
 860 static struct mmc_host_ops mmc_omap_ops = {
 861         .request = omap_mmc_request,
 862         .set_ios = omap_mmc_set_ios,
 863         .get_cd = omap_hsmmc_get_cd,
 864         .get_ro = omap_hsmmc_get_ro,
 865         /* NYET -- enable_sdio_irq */
 866 };
 867
 868 static int __init omap_mmc_probe(struct platform_device *pdev)
 869 {
 870         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
 871         struct mmc_host *mmc;
 872         struct mmc_omap_host *host = NULL;
 873         struct resource *res;
 874         int ret = 0, irq;
 875         u32 hctl, capa;
 876
 877         if (pdata == NULL) {
 878                 dev_err(&pdev->dev, "Platform Data is missing\n");
 879                 return -ENXIO;
 880         }
 881
 882         if (pdata->nr_slots == 0) {
 883                 dev_err(&pdev->dev, "No Slots\n");
 884                 return -ENXIO;
 885         }
 886
 887         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 888         irq = platform_get_irq(pdev, 0);
 889         if (res == NULL || irq < 0)
 890                 return -ENXIO;
 891
 892         res = request_mem_region(res->start, res->end - res->start + 1,
 893                                                         pdev->name);
 894         if (res == NULL)
 895                 return -EBUSY;
 896
 897         mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
 898         if (!mmc) {
 899                 ret = -ENOMEM;
 900                 goto err;
 901         }
 902
 903         host            = mmc_priv(mmc);
 904         host->mmc       = mmc;
 905         host->pdata     = pdata;
 906         host->dev       = &pdev->dev;
 907         host->use_dma   = 1;
 908         host->dev->dma_mask = &pdata->dma_mask;
 909         host->dma_ch    = -1;
 910         host->irq       = irq;
 911         host->id        = pdev->id;
 912         host->slot_id   = 0;
 913         host->mapbase   = res->start;
 914         host->base      = ioremap(host->mapbase, SZ_4K);
 915
 916         platform_set_drvdata(pdev, host);
 917         INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
 918
 919         mmc->ops        = &mmc_omap_ops;
 920         mmc->f_min      = 400000;
 921         mmc->f_max      = 52000000;
 922
 923         sema_init(&host->sem, 1);
 924
 925         host->iclk = clk_get(&pdev->dev, "mmchs_ick");
 926         if (IS_ERR(host->iclk)) {
 927                 ret = PTR_ERR(host->iclk);
 928                 host->iclk = NULL;
 929                 goto err1;
 930         }
 931         host->fclk = clk_get(&pdev->dev, "mmchs_fck");
 932         if (IS_ERR(host->fclk)) {
 933                 ret = PTR_ERR(host->fclk);
 934                 host->fclk = NULL;
 935                 clk_put(host->iclk);
 936                 goto err1;
 937         }
 938
 939         if (clk_enable(host->fclk) != 0) {
 940                 clk_put(host->iclk);
 941                 clk_put(host->fclk);
 942                 goto err1;
 943         }
 944
 945         if (clk_enable(host->iclk) != 0) {
 946                 clk_disable(host->fclk);
 947                 clk_put(host->iclk);
 948                 clk_put(host->fclk);
 949                 goto err1;
 950         }
 951
 952         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
 953         /*
 954          * MMC can still work without debounce clock.
 955          */
 956         if (IS_ERR(host->dbclk))
 957                 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
 958         else
 959                 if (clk_enable(host->dbclk) != 0)
 960                         dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
 961                                                         " clk failed\n");
 962                 else
 963                         host->dbclk_enabled = 1;
 964
 965 #ifdef CONFIG_MMC_BLOCK_BOUNCE
 966         mmc->max_phys_segs = 1;
 967         mmc->max_hw_segs = 1;
 968 #endif
 969         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
 970         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
 971         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
 972         mmc->max_seg_size = mmc->max_req_size;
 973
 974         mmc->ocr_avail = mmc_slot(host).ocr_mask;
 975         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
 976
 977         if (pdata->slots[host->slot_id].wires >= 4)
 978                 mmc->caps |= MMC_CAP_4_BIT_DATA;
 979
 980         /* Only MMC1 supports 3.0V */
 981         if (host->id == OMAP_MMC1_DEVID) {
 982                 hctl = SDVS30;
 983                 capa = VS30 | VS18;
 984         } else {
 985                 hctl = SDVS18;
 986                 capa = VS18;
 987         }
 988
 989         OMAP_HSMMC_WRITE(host->base, HCTL,
 990                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 991
 992         OMAP_HSMMC_WRITE(host->base, CAPA,
 993                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 994
 995         /* Set the controller to AUTO IDLE mode */
 996         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 997                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 998
 999         /* Set SD bus power bit */
1000         OMAP_HSMMC_WRITE(host->base, HCTL,
1001                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1002
1003         /* Request IRQ for MMC operations */
1004         ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1005                         mmc_hostname(mmc), host);
1006         if (ret) {
1007                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1008                 goto err_irq;
1009         }
1010
1011         if (pdata->init != NULL) {
1012                 if (pdata->init(&pdev->dev) != 0) {
1013                         dev_dbg(mmc_dev(host->mmc),
1014                                 "Unable to configure MMC IRQs\n");
1015                         goto err_irq_cd_init;
1016                 }
1017         }
1018
1019         /* Request IRQ for card detect */
1020         if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) {
1021                 ret = request_irq(mmc_slot(host).card_detect_irq,
1022                                   omap_mmc_cd_handler,
1023                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1024                                           | IRQF_DISABLED,
1025                                   mmc_hostname(mmc), host);
1026                 if (ret) {
1027                         dev_dbg(mmc_dev(host->mmc),
1028                                 "Unable to grab MMC CD IRQ\n");
1029                         goto err_irq_cd;
1030                 }
1031         }
1032
1033         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1034         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1035
1036         mmc_add_host(mmc);
1037
1038         if (host->pdata->slots[host->slot_id].name != NULL) {
1039                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1040                 if (ret < 0)
1041                         goto err_slot_name;
1042         }
1043         if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect &&
1044                         host->pdata->slots[host->slot_id].get_cover_state) {
1045                 ret = device_create_file(&mmc->class_dev,
1046                                         &dev_attr_cover_switch);
1047                 if (ret < 0)
1048                         goto err_cover_switch;
1049         }
1050
1051         return 0;
1052
1053 err_cover_switch:
1054         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1055 err_slot_name:
1056         mmc_remove_host(mmc);
1057 err_irq_cd:
1058         free_irq(mmc_slot(host).card_detect_irq, host);
1059 err_irq_cd_init:
1060         free_irq(host->irq, host);
1061 err_irq:
1062         clk_disable(host->fclk);
1063         clk_disable(host->iclk);
1064         clk_put(host->fclk);
1065         clk_put(host->iclk);
1066         if (host->dbclk_enabled) {
1067                 clk_disable(host->dbclk);
1068                 clk_put(host->dbclk);
1069         }
1070
1071 err1:
1072         iounmap(host->base);
1073 err:
1074         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1075         release_mem_region(res->start, res->end - res->start + 1);
1076         if (host)
1077                 mmc_free_host(mmc);
1078         return ret;
1079 }
1080
1081 static int omap_mmc_remove(struct platform_device *pdev)
1082 {
1083         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1084         struct resource *res;
1085
1086         if (host) {
1087                 mmc_remove_host(host->mmc);
1088                 if (host->pdata->cleanup)
1089                         host->pdata->cleanup(&pdev->dev);
1090                 free_irq(host->irq, host);
1091                 if (mmc_slot(host).card_detect_irq)
1092                         free_irq(mmc_slot(host).card_detect_irq, host);
1093                 flush_scheduled_work();
1094
1095                 clk_disable(host->fclk);
1096                 clk_disable(host->iclk);
1097                 clk_put(host->fclk);
1098                 clk_put(host->iclk);
1099                 if (host->dbclk_enabled) {
1100                         clk_disable(host->dbclk);
1101                         clk_put(host->dbclk);
1102                 }
1103
1104                 mmc_free_host(host->mmc);
1105                 iounmap(host->base);
1106         }
1107
1108         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1109         if (res)
1110                 release_mem_region(res->start, res->end - res->start + 1);
1111         platform_set_drvdata(pdev, NULL);
1112
1113         return 0;
1114 }
1115
1116 #ifdef CONFIG_PM
1117 static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1118 {
1119         int ret = 0;
1120         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1121
1122         if (host && host->suspended)
1123                 return 0;
1124
1125         if (host) {
1126                 ret = mmc_suspend_host(host->mmc, state);
1127                 if (ret == 0) {
1128                         host->suspended = 1;
1129
1130                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1131                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1132
1133                         if (host->pdata->suspend) {
1134                                 ret = host->pdata->suspend(&pdev->dev,
1135                                                                 host->slot_id);
1136                                 if (ret)
1137                                         dev_dbg(mmc_dev(host->mmc),
1138                                                 "Unable to handle MMC board"
1139                                                 " level suspend\n");
1140                         }
1141
1142                         if (!(OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET)) {
1143                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1144                                         OMAP_HSMMC_READ(host->base, HCTL)
1145                                         & SDVSCLR);
1146                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1147                                         OMAP_HSMMC_READ(host->base, HCTL)
1148                                         | SDVS30);
1149                                 OMAP_HSMMC_WRITE(host->base, HCTL,
1150                                         OMAP_HSMMC_READ(host->base, HCTL)
1151                                         | SDBP);
1152                         }
1153
1154                         clk_disable(host->fclk);
1155                         clk_disable(host->iclk);
1156                         clk_disable(host->dbclk);
1157                 }
1158
1159         }
1160         return ret;
1161 }
1162
1163 /* Routine to resume the MMC device */
1164 static int omap_mmc_resume(struct platform_device *pdev)
1165 {
1166         int ret = 0;
1167         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1168
1169         if (host && !host->suspended)
1170                 return 0;
1171
1172         if (host) {
1173
1174                 ret = clk_enable(host->fclk);
1175                 if (ret)
1176                         goto clk_en_err;
1177
1178                 ret = clk_enable(host->iclk);
1179                 if (ret) {
1180                         clk_disable(host->fclk);
1181                         clk_put(host->fclk);
1182                         goto clk_en_err;
1183                 }
1184
1185                 if (clk_enable(host->dbclk) != 0)
1186                         dev_dbg(mmc_dev(host->mmc),
1187                                         "Enabling debounce clk failed\n");
1188
1189                 if (host->pdata->resume) {
1190                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1191                         if (ret)
1192                                 dev_dbg(mmc_dev(host->mmc),
1193                                         "Unmask interrupt failed\n");
1194                 }
1195
1196                 /* Notify the core to resume the host */
1197                 ret = mmc_resume_host(host->mmc);
1198                 if (ret == 0)
1199                         host->suspended = 0;
1200         }
1201
1202         return ret;
1203
1204 clk_en_err:
1205         dev_dbg(mmc_dev(host->mmc),
1206                 "Failed to enable MMC clocks during resume\n");
1207         return ret;
1208 }
1209
1210 #else
1211 #define omap_mmc_suspend        NULL
1212 #define omap_mmc_resume         NULL
1213 #endif
1214
1215 static struct platform_driver omap_mmc_driver = {
1216         .probe          = omap_mmc_probe,
1217         .remove         = omap_mmc_remove,
1218         .suspend        = omap_mmc_suspend,
1219         .resume         = omap_mmc_resume,
1220         .driver         = {
1221                 .name = DRIVER_NAME,
1222                 .owner = THIS_MODULE,
1223         },
1224 };
1225
1226 static int __init omap_mmc_init(void)
1227 {
1228         /* Register the MMC driver */
1229         return platform_driver_register(&omap_mmc_driver);
1230 }
1231
1232 static void __exit omap_mmc_cleanup(void)
1233 {
1234         /* Unregister MMC driver */
1235         platform_driver_unregister(&omap_mmc_driver);
1236 }
1237
1238 module_init(omap_mmc_init);
1239 module_exit(omap_mmc_cleanup);
1240
1241 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1242 MODULE_LICENSE("GPL");
1243 MODULE_ALIAS("platform:" DRIVER_NAME);
1244 MODULE_AUTHOR("Texas Instruments Inc");