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   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/debugfs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/timer.h>
  28 #include <linux/clk.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/core.h>
  31 #include <linux/io.h>
  32 #include <linux/semaphore.h>
  33 #include <mach/dma.h>
  34 #include <mach/hardware.h>
  35 #include <mach/board.h>
  36 #include <mach/mmc.h>
  37 #include <mach/cpu.h>
  38
  39 /* OMAP HSMMC Host Controller Registers */
  40 #define OMAP_HSMMC_SYSCONFIG    0x0010
  41 #define OMAP_HSMMC_SYSSTATUS    0x0014
  42 #define OMAP_HSMMC_CON          0x002C
  43 #define OMAP_HSMMC_BLK          0x0104
  44 #define OMAP_HSMMC_ARG          0x0108
  45 #define OMAP_HSMMC_CMD          0x010C
  46 #define OMAP_HSMMC_RSP10        0x0110
  47 #define OMAP_HSMMC_RSP32        0x0114
  48 #define OMAP_HSMMC_RSP54        0x0118
  49 #define OMAP_HSMMC_RSP76        0x011C
  50 #define OMAP_HSMMC_DATA         0x0120
  51 #define OMAP_HSMMC_HCTL         0x0128
  52 #define OMAP_HSMMC_SYSCTL       0x012C
  53 #define OMAP_HSMMC_STAT         0x0130
  54 #define OMAP_HSMMC_IE           0x0134
  55 #define OMAP_HSMMC_ISE          0x0138
  56 #define OMAP_HSMMC_CAPA         0x0140
  57
  58 #define VS18                    (1 << 26)
  59 #define VS30                    (1 << 25)
  60 #define SDVS18                  (0x5 << 9)
  61 #define SDVS30                  (0x6 << 9)
  62 #define SDVS33                  (0x7 << 9)
  63 #define SDVS_MASK               0x00000E00
  64 #define SDVSCLR                 0xFFFFF1FF
  65 #define SDVSDET                 0x00000400
  66 #define AUTOIDLE                0x1
  67 #define SDBP                    (1 << 8)
  68 #define DTO                     0xe
  69 #define ICE                     0x1
  70 #define ICS                     0x2
  71 #define CEN                     (1 << 2)
  72 #define CLKD_MASK               0x0000FFC0
  73 #define CLKD_SHIFT              6
  74 #define DTO_MASK                0x000F0000
  75 #define DTO_SHIFT               16
  76 #define INT_EN_MASK             0x307F0033
  77 #define BWR_ENABLE              (1 << 4)
  78 #define BRR_ENABLE              (1 << 5)
  79 #define INIT_STREAM             (1 << 1)
  80 #define DP_SELECT               (1 << 21)
  81 #define DDIR                    (1 << 4)
  82 #define DMA_EN                  0x1
  83 #define MSBS                    (1 << 5)
  84 #define BCE                     (1 << 1)
  85 #define FOUR_BIT                (1 << 1)
  86 #define DW8                     (1 << 5)
  87 #define CC                      0x1
  88 #define TC                      0x02
  89 #define OD                      0x1
  90 #define ERR                     (1 << 15)
  91 #define CMD_TIMEOUT             (1 << 16)
  92 #define DATA_TIMEOUT            (1 << 20)
  93 #define CMD_CRC                 (1 << 17)
  94 #define DATA_CRC                (1 << 21)
  95 #define CARD_ERR                (1 << 28)
  96 #define STAT_CLEAR              0xFFFFFFFF
  97 #define INIT_STREAM_CMD         0x00000000
  98 #define DUAL_VOLT_OCR_BIT       7
  99 #define SRC                     (1 << 25)
 100 #define SRD                     (1 << 26)
 101 #define SOFTRESET               (1 << 1)
 102 #define RESETDONE               (1 << 0)
 103
 104 /*
 105  * FIXME: Most likely all the data using these _DEVID defines should come
 106  * from the platform_data, or implemented in controller and slot specific
 107  * functions.
 108  */
 109 #define OMAP_MMC1_DEVID         0
 110 #define OMAP_MMC2_DEVID         1
 111 #define OMAP_MMC3_DEVID         2
 112
 113 #define MMC_TIMEOUT_MS          20
 114 #define OMAP_MMC_MASTER_CLOCK   96000000
 115 #define DRIVER_NAME             "mmci-omap-hs"
 116
 117 /* Timeouts for entering power saving states on inactivity, msec */
 118 #define OMAP_MMC_DISABLED_TIMEOUT       100
 119 #define OMAP_MMC_SLEEP_TIMEOUT          1000
 120 #define OMAP_MMC_OFF_TIMEOUT            8000
 121
 122 /*
 123  * One controller can have multiple slots, like on some omap boards using
 124  * omap.c controller driver. Luckily this is not currently done on any known
 125  * omap_hsmmc.c device.
 126  */
 127 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 128
 129 /*
 130  * MMC Host controller read/write API's
 131  */
 132 #define OMAP_HSMMC_READ(base, reg)      \
 133         __raw_readl((base) + OMAP_HSMMC_##reg)
 134
 135 #define OMAP_HSMMC_WRITE(base, reg, val) \
 136         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 137
 138 struct omap_hsmmc_host {
 139         struct  device          *dev;
 140         struct  mmc_host        *mmc;
 141         struct  mmc_request     *mrq;
 142         struct  mmc_command     *cmd;
 143         struct  mmc_data        *data;
 144         struct  clk             *fclk;
 145         struct  clk             *iclk;
 146         struct  clk             *dbclk;
 147         struct  semaphore       sem;
 148         struct  work_struct     mmc_carddetect_work;
 149         void    __iomem         *base;
 150         resource_size_t         mapbase;
 151         spinlock_t              irq_lock; /* Prevent races with irq handler */
 152         unsigned long           flags;
 153         unsigned int            id;
 154         unsigned int            dma_len;
 155         unsigned int            dma_sg_idx;
 156         unsigned char           bus_mode;
 157         unsigned char           power_mode;
 158         u32                     *buffer;
 159         u32                     bytesleft;
 160         int                     suspended;
 161         int                     irq;
 162         int                     use_dma, dma_ch;
 163         int                     dma_line_tx, dma_line_rx;
 164         int                     slot_id;
 165         int                     got_dbclk;
 166         int                     response_busy;
 167         int                     context_loss;
 168         int                     dpm_state;
 169         int                     vdd;
 170         int                     protect_card;
 171         int                     reqs_blocked;
 172
 173         struct  omap_mmc_platform_data  *pdata;
 174 };
 175
 176 /*
 177  * Stop clock to the card
 178  */
 179 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 180 {
 181         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 182                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 183         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 184                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 185 }
 186
 187 #ifdef CONFIG_PM
 188
 189 /*
 190  * Restore the MMC host context, if it was lost as result of a
 191  * power state change.
 192  */
 193 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 194 {
 195         struct mmc_ios *ios = &host->mmc->ios;
 196         struct omap_mmc_platform_data *pdata = host->pdata;
 197         int context_loss = 0;
 198         u32 hctl, capa, con;
 199         u16 dsor = 0;
 200         unsigned long timeout;
 201
 202         if (pdata->get_context_loss_count) {
 203                 context_loss = pdata->get_context_loss_count(host->dev);
 204                 if (context_loss < 0)
 205                         return 1;
 206         }
 207
 208         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
 209                 context_loss == host->context_loss ? "not " : "");
 210         if (host->context_loss == context_loss)
 211                 return 1;
 212
 213         /* Wait for hardware reset */
 214         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 215         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 216                 && time_before(jiffies, timeout))
 217                 ;
 218
 219         /* Do software reset */
 220         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
 221         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 222         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 223                 && time_before(jiffies, timeout))
 224                 ;
 225
 226         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 227                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 228
 229         if (host->id == OMAP_MMC1_DEVID) {
 230                 if (host->power_mode != MMC_POWER_OFF &&
 231                     (1 << ios->vdd) <= MMC_VDD_23_24)
 232                         hctl = SDVS18;
 233                 else
 234                         hctl = SDVS30;
 235                 capa = VS30 | VS18;
 236         } else {
 237                 hctl = SDVS18;
 238                 capa = VS18;
 239         }
 240
 241         OMAP_HSMMC_WRITE(host->base, HCTL,
 242                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 243
 244         OMAP_HSMMC_WRITE(host->base, CAPA,
 245                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 246
 247         OMAP_HSMMC_WRITE(host->base, HCTL,
 248                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 249
 250         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 251         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 252                 && time_before(jiffies, timeout))
 253                 ;
 254
 255         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 256         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 257         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 258
 259         /* Do not initialize card-specific things if the power is off */
 260         if (host->power_mode == MMC_POWER_OFF)
 261                 goto out;
 262
 263         con = OMAP_HSMMC_READ(host->base, CON);
 264         switch (ios->bus_width) {
 265         case MMC_BUS_WIDTH_8:
 266                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 267                 break;
 268         case MMC_BUS_WIDTH_4:
 269                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 270                 OMAP_HSMMC_WRITE(host->base, HCTL,
 271                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 272                 break;
 273         case MMC_BUS_WIDTH_1:
 274                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 275                 OMAP_HSMMC_WRITE(host->base, HCTL,
 276                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 277                 break;
 278         }
 279
 280         if (ios->clock) {
 281                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
 282                 if (dsor < 1)
 283                         dsor = 1;
 284
 285                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
 286                         dsor++;
 287
 288                 if (dsor > 250)
 289                         dsor = 250;
 290         }
 291
 292         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 293                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 294         OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
 295         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 296                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 297
 298         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 299         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 300                 && time_before(jiffies, timeout))
 301                 ;
 302
 303         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 304                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 305
 306         con = OMAP_HSMMC_READ(host->base, CON);
 307         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 308                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 309         else
 310                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 311 out:
 312         host->context_loss = context_loss;
 313
 314         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
 315         return 0;
 316 }
 317
 318 /*
 319  * Save the MMC host context (store the number of power state changes so far).
 320  */
 321 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 322 {
 323         struct omap_mmc_platform_data *pdata = host->pdata;
 324         int context_loss;
 325
 326         if (pdata->get_context_loss_count) {
 327                 context_loss = pdata->get_context_loss_count(host->dev);
 328                 if (context_loss < 0)
 329                         return;
 330                 host->context_loss = context_loss;
 331         }
 332 }
 333
 334 #else
 335
 336 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 337 {
 338         return 0;
 339 }
 340
 341 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 342 {
 343 }
 344
 345 #endif
 346
 347 /*
 348  * Send init stream sequence to card
 349  * before sending IDLE command
 350  */
 351 static void send_init_stream(struct omap_hsmmc_host *host)
 352 {
 353         int reg = 0;
 354         unsigned long timeout;
 355
 356         if (host->protect_card)
 357                 return;
 358
 359         disable_irq(host->irq);
 360         OMAP_HSMMC_WRITE(host->base, CON,
 361                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 362         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 363
 364         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 365         while ((reg != CC) && time_before(jiffies, timeout))
 366                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 367
 368         OMAP_HSMMC_WRITE(host->base, CON,
 369                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 370
 371         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 372         OMAP_HSMMC_READ(host->base, STAT);
 373
 374         enable_irq(host->irq);
 375 }
 376
 377 static inline
 378 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 379 {
 380         int r = 1;
 381
 382         if (mmc_slot(host).get_cover_state)
 383                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
 384         return r;
 385 }
 386
 387 static ssize_t
 388 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 389                            char *buf)
 390 {
 391         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 392         struct omap_hsmmc_host *host = mmc_priv(mmc);
 393
 394         return sprintf(buf, "%s\n",
 395                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 396 }
 397
 398 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 399
 400 static ssize_t
 401 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 402                         char *buf)
 403 {
 404         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 405         struct omap_hsmmc_host *host = mmc_priv(mmc);
 406
 407         return sprintf(buf, "%s\n", mmc_slot(host).name);
 408 }
 409
 410 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 411
 412 /*
 413  * Configure the response type and send the cmd.
 414  */
 415 static void
 416 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 417         struct mmc_data *data)
 418 {
 419         int cmdreg = 0, resptype = 0, cmdtype = 0;
 420
 421         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 422                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 423         host->cmd = cmd;
 424
 425         /*
 426          * Clear status bits and enable interrupts
 427          */
 428         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 429         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
 430
 431         if (host->use_dma)
 432                 OMAP_HSMMC_WRITE(host->base, IE,
 433                                  INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
 434         else
 435                 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 436
 437         host->response_busy = 0;
 438         if (cmd->flags & MMC_RSP_PRESENT) {
 439                 if (cmd->flags & MMC_RSP_136)
 440                         resptype = 1;
 441                 else if (cmd->flags & MMC_RSP_BUSY) {
 442                         resptype = 3;
 443                         host->response_busy = 1;
 444                 } else
 445                         resptype = 2;
 446         }
 447
 448         /*
 449          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 450          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 451          * a val of 0x3, rest 0x0.
 452          */
 453         if (cmd == host->mrq->stop)
 454                 cmdtype = 0x3;
 455
 456         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 457
 458         if (data) {
 459                 cmdreg |= DP_SELECT | MSBS | BCE;
 460                 if (data->flags & MMC_DATA_READ)
 461                         cmdreg |= DDIR;
 462                 else
 463                         cmdreg &= ~(DDIR);
 464         }
 465
 466         if (host->use_dma)
 467                 cmdreg |= DMA_EN;
 468
 469         /*
 470          * In an interrupt context (i.e. STOP command), the spinlock is unlocked
 471          * by the interrupt handler, otherwise (i.e. for a new request) it is
 472          * unlocked here.
 473          */
 474         if (!in_interrupt())
 475                 spin_unlock_irqrestore(&host->irq_lock, host->flags);
 476
 477         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 478         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 479 }
 480
 481 static int
 482 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 483 {
 484         if (data->flags & MMC_DATA_WRITE)
 485                 return DMA_TO_DEVICE;
 486         else
 487                 return DMA_FROM_DEVICE;
 488 }
 489
 490 /*
 491  * Notify the transfer complete to MMC core
 492  */
 493 static void
 494 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 495 {
 496         if (!data) {
 497                 struct mmc_request *mrq = host->mrq;
 498
 499                 /* TC before CC from CMD6 - don't know why, but it happens */
 500                 if (host->cmd && host->cmd->opcode == 6 &&
 501                     host->response_busy) {
 502                         host->response_busy = 0;
 503                         return;
 504                 }
 505
 506                 host->mrq = NULL;
 507                 mmc_request_done(host->mmc, mrq);
 508                 return;
 509         }
 510
 511         host->data = NULL;
 512
 513         if (host->use_dma && host->dma_ch != -1)
 514                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
 515                         omap_hsmmc_get_dma_dir(host, data));
 516
 517         if (!data->error)
 518                 data->bytes_xfered += data->blocks * (data->blksz);
 519         else
 520                 data->bytes_xfered = 0;
 521
 522         if (!data->stop) {
 523                 host->mrq = NULL;
 524                 mmc_request_done(host->mmc, data->mrq);
 525                 return;
 526         }
 527         omap_hsmmc_start_command(host, data->stop, NULL);
 528 }
 529
 530 /*
 531  * Notify the core about command completion
 532  */
 533 static void
 534 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 535 {
 536         host->cmd = NULL;
 537
 538         if (cmd->flags & MMC_RSP_PRESENT) {
 539                 if (cmd->flags & MMC_RSP_136) {
 540                         /* response type 2 */
 541                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 542                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 543                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 544                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 545                 } else {
 546                         /* response types 1, 1b, 3, 4, 5, 6 */
 547                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 548                 }
 549         }
 550         if ((host->data == NULL && !host->response_busy) || cmd->error) {
 551                 host->mrq = NULL;
 552                 mmc_request_done(host->mmc, cmd->mrq);
 553         }
 554 }
 555
 556 /*
 557  * DMA clean up for command errors
 558  */
 559 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
 560 {
 561         host->data->error = errno;
 562
 563         if (host->use_dma && host->dma_ch != -1) {
 564                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
 565                         omap_hsmmc_get_dma_dir(host, host->data));
 566                 omap_free_dma(host->dma_ch);
 567                 host->dma_ch = -1;
 568                 up(&host->sem);
 569         }
 570         host->data = NULL;
 571 }
 572
 573 /*
 574  * Readable error output
 575  */
 576 #ifdef CONFIG_MMC_DEBUG
 577 static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
 578 {
 579         /* --- means reserved bit without definition at documentation */
 580         static const char *omap_hsmmc_status_bits[] = {
 581                 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
 582                 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
 583                 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
 584                 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
 585         };
 586         char res[256];
 587         char *buf = res;
 588         int len, i;
 589
 590         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 591         buf += len;
 592
 593         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
 594                 if (status & (1 << i)) {
 595                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
 596                         buf += len;
 597                 }
 598
 599         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
 600 }
 601 #endif  /* CONFIG_MMC_DEBUG */
 602
 603 /*
 604  * MMC controller internal state machines reset
 605  *
 606  * Used to reset command or data internal state machines, using respectively
 607  *  SRC or SRD bit of SYSCTL register
 608  * Can be called from interrupt context
 609  */
 610 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
 611                                                    unsigned long bit)
 612 {
 613         unsigned long i = 0;
 614         unsigned long limit = (loops_per_jiffy *
 615                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
 616
 617         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 618                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 619
 620         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 621                 (i++ < limit))
 622                 cpu_relax();
 623
 624         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 625                 dev_err(mmc_dev(host->mmc),
 626                         "Timeout waiting on controller reset in %s\n",
 627                         __func__);
 628 }
 629
 630 /*
 631  * MMC controller IRQ handler
 632  */
 633 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
 634 {
 635         struct omap_hsmmc_host *host = dev_id;
 636         struct mmc_data *data;
 637         int end_cmd = 0, end_trans = 0, status;
 638
 639         spin_lock(&host->irq_lock);
 640
 641         if (host->mrq == NULL) {
 642                 OMAP_HSMMC_WRITE(host->base, STAT,
 643                         OMAP_HSMMC_READ(host->base, STAT));
 644                 /* Flush posted write */
 645                 OMAP_HSMMC_READ(host->base, STAT);
 646                 spin_unlock(&host->irq_lock);
 647                 return IRQ_HANDLED;
 648         }
 649
 650         data = host->data;
 651         status = OMAP_HSMMC_READ(host->base, STAT);
 652         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 653
 654         if (status & ERR) {
 655 #ifdef CONFIG_MMC_DEBUG
 656                 omap_hsmmc_report_irq(host, status);
 657 #endif
 658                 if ((status & CMD_TIMEOUT) ||
 659                         (status & CMD_CRC)) {
 660                         if (host->cmd) {
 661                                 if (status & CMD_TIMEOUT) {
 662                                         omap_hsmmc_reset_controller_fsm(host,
 663                                                                         SRC);
 664                                         host->cmd->error = -ETIMEDOUT;
 665                                 } else {
 666                                         host->cmd->error = -EILSEQ;
 667                                 }
 668                                 end_cmd = 1;
 669                         }
 670                         if (host->data || host->response_busy) {
 671                                 if (host->data)
 672                                         omap_hsmmc_dma_cleanup(host,
 673                                                                 -ETIMEDOUT);
 674                                 host->response_busy = 0;
 675                                 omap_hsmmc_reset_controller_fsm(host, SRD);
 676                         }
 677                 }
 678                 if ((status & DATA_TIMEOUT) ||
 679                         (status & DATA_CRC)) {
 680                         if (host->data || host->response_busy) {
 681                                 int err = (status & DATA_TIMEOUT) ?
 682                                                 -ETIMEDOUT : -EILSEQ;
 683
 684                                 if (host->data)
 685                                         omap_hsmmc_dma_cleanup(host, err);
 686                                 else
 687                                         host->mrq->cmd->error = err;
 688                                 host->response_busy = 0;
 689                                 omap_hsmmc_reset_controller_fsm(host, SRD);
 690                                 end_trans = 1;
 691                         }
 692                 }
 693                 if (status & CARD_ERR) {
 694                         dev_dbg(mmc_dev(host->mmc),
 695                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
 696                         if (host->cmd)
 697                                 end_cmd = 1;
 698                         if (host->data)
 699                                 end_trans = 1;
 700                 }
 701         }
 702
 703         OMAP_HSMMC_WRITE(host->base, STAT, status);
 704         /* Flush posted write */
 705         OMAP_HSMMC_READ(host->base, STAT);
 706
 707         if (end_cmd || ((status & CC) && host->cmd))
 708                 omap_hsmmc_cmd_done(host, host->cmd);
 709         if ((end_trans || (status & TC)) && host->mrq)
 710                 omap_hsmmc_xfer_done(host, data);
 711
 712         spin_unlock(&host->irq_lock);
 713
 714         return IRQ_HANDLED;
 715 }
 716
 717 static void set_sd_bus_power(struct omap_hsmmc_host *host)
 718 {
 719         unsigned long i;
 720
 721         OMAP_HSMMC_WRITE(host->base, HCTL,
 722                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 723         for (i = 0; i < loops_per_jiffy; i++) {
 724                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
 725                         break;
 726                 cpu_relax();
 727         }
 728 }
 729
 730 /*
 731  * Switch MMC interface voltage ... only relevant for MMC1.
 732  *
 733  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
 734  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
 735  * Some chips, like eMMC ones, use internal transceivers.
 736  */
 737 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
 738 {
 739         u32 reg_val = 0;
 740         int ret;
 741
 742         /* Disable the clocks */
 743         clk_disable(host->fclk);
 744         clk_disable(host->iclk);
 745         if (host->got_dbclk)
 746                 clk_disable(host->dbclk);
 747
 748         /* Turn the power off */
 749         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
 750
 751         /* Turn the power ON with given VDD 1.8 or 3.0v */
 752         if (!ret)
 753                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
 754                                                vdd);
 755         clk_enable(host->iclk);
 756         clk_enable(host->fclk);
 757         if (host->got_dbclk)
 758                 clk_enable(host->dbclk);
 759
 760         if (ret != 0)
 761                 goto err;
 762
 763         OMAP_HSMMC_WRITE(host->base, HCTL,
 764                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
 765         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
 766
 767         /*
 768          * If a MMC dual voltage card is detected, the set_ios fn calls
 769          * this fn with VDD bit set for 1.8V. Upon card removal from the
 770          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
 771          *
 772          * Cope with a bit of slop in the range ... per data sheets:
 773          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
 774          *    but recommended values are 1.71V to 1.89V
 775          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
 776          *    but recommended values are 2.7V to 3.3V
 777          *
 778          * Board setup code shouldn't permit anything very out-of-range.
 779          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
 780          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
 781          */
 782         if ((1 << vdd) <= MMC_VDD_23_24)
 783                 reg_val |= SDVS18;
 784         else
 785                 reg_val |= SDVS30;
 786
 787         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
 788         set_sd_bus_power(host);
 789
 790         return 0;
 791 err:
 792         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
 793         return ret;
 794 }
 795
 796 /* Protect the card while the cover is open */
 797 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
 798 {
 799         if (!mmc_slot(host).get_cover_state)
 800                 return;
 801
 802         host->reqs_blocked = 0;
 803         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
 804                 if (host->protect_card) {
 805                         printk(KERN_INFO "%s: cover is closed, "
 806                                          "card is now accessible\n",
 807                                          mmc_hostname(host->mmc));
 808                         host->protect_card = 0;
 809                 }
 810         } else {
 811                 if (!host->protect_card) {
 812                         printk(KERN_INFO "%s: cover is open, "
 813                                          "card is now inaccessible\n",
 814                                          mmc_hostname(host->mmc));
 815                         host->protect_card = 1;
 816                 }
 817         }
 818 }
 819
 820 /*
 821  * Work Item to notify the core about card insertion/removal
 822  */
 823 static void omap_hsmmc_detect(struct work_struct *work)
 824 {
 825         struct omap_hsmmc_host *host =
 826                 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
 827         struct omap_mmc_slot_data *slot = &mmc_slot(host);
 828         int carddetect;
 829
 830         if (host->suspended)
 831                 return;
 832
 833         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
 834
 835         if (slot->card_detect)
 836                 carddetect = slot->card_detect(slot->card_detect_irq);
 837         else {
 838                 omap_hsmmc_protect_card(host);
 839                 carddetect = -ENOSYS;
 840         }
 841
 842         if (carddetect) {
 843                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
 844         } else {
 845                 mmc_host_enable(host->mmc);
 846                 omap_hsmmc_reset_controller_fsm(host, SRD);
 847                 mmc_host_lazy_disable(host->mmc);
 848
 849                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
 850         }
 851 }
 852
 853 /*
 854  * ISR for handling card insertion and removal
 855  */
 856 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
 857 {
 858         struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
 859
 860         if (host->suspended)
 861                 return IRQ_HANDLED;
 862         schedule_work(&host->mmc_carddetect_work);
 863
 864         return IRQ_HANDLED;
 865 }
 866
 867 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
 868                                      struct mmc_data *data)
 869 {
 870         int sync_dev;
 871
 872         if (data->flags & MMC_DATA_WRITE)
 873                 sync_dev = host->dma_line_tx;
 874         else
 875                 sync_dev = host->dma_line_rx;
 876         return sync_dev;
 877 }
 878
 879 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
 880                                        struct mmc_data *data,
 881                                        struct scatterlist *sgl)
 882 {
 883         int blksz, nblk, dma_ch;
 884
 885         dma_ch = host->dma_ch;
 886         if (data->flags & MMC_DATA_WRITE) {
 887                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 888                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 889                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 890                         sg_dma_address(sgl), 0, 0);
 891         } else {
 892                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 893                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
 894                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 895                         sg_dma_address(sgl), 0, 0);
 896         }
 897
 898         blksz = host->data->blksz;
 899         nblk = sg_dma_len(sgl) / blksz;
 900
 901         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
 902                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
 903                         omap_hsmmc_get_dma_sync_dev(host, data),
 904                         !(data->flags & MMC_DATA_WRITE));
 905
 906         omap_start_dma(dma_ch);
 907 }
 908
 909 /*
 910  * DMA call back function
 911  */
 912 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *data)
 913 {
 914         struct omap_hsmmc_host *host = data;
 915
 916         if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
 917                 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
 918
 919         if (host->dma_ch < 0)
 920                 return;
 921
 922         host->dma_sg_idx++;
 923         if (host->dma_sg_idx < host->dma_len) {
 924                 /* Fire up the next transfer. */
 925                 omap_hsmmc_config_dma_params(host, host->data,
 926                                            host->data->sg + host->dma_sg_idx);
 927                 return;
 928         }
 929
 930         omap_free_dma(host->dma_ch);
 931         host->dma_ch = -1;
 932         /*
 933          * DMA Callback: run in interrupt context.
 934          * mutex_unlock will throw a kernel warning if used.
 935          */
 936         up(&host->sem);
 937 }
 938
 939 /*
 940  * Routine to configure and start DMA for the MMC card
 941  */
 942 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
 943                                         struct mmc_request *req)
 944 {
 945         int dma_ch = 0, ret = 0, err = 1, i;
 946         struct mmc_data *data = req->data;
 947
 948         /* Sanity check: all the SG entries must be aligned by block size. */
 949         for (i = 0; i < data->sg_len; i++) {
 950                 struct scatterlist *sgl;
 951
 952                 sgl = data->sg + i;
 953                 if (sgl->length % data->blksz)
 954                         return -EINVAL;
 955         }
 956         if ((data->blksz % 4) != 0)
 957                 /* REVISIT: The MMC buffer increments only when MSB is written.
 958                  * Return error for blksz which is non multiple of four.
 959                  */
 960                 return -EINVAL;
 961
 962         /*
 963          * If for some reason the DMA transfer is still active,
 964          * we wait for timeout period and free the dma
 965          */
 966         if (host->dma_ch != -1) {
 967                 set_current_state(TASK_UNINTERRUPTIBLE);
 968                 schedule_timeout(100);
 969                 if (down_trylock(&host->sem)) {
 970                         omap_free_dma(host->dma_ch);
 971                         host->dma_ch = -1;
 972                         up(&host->sem);
 973                         return err;
 974                 }
 975         } else {
 976                 if (down_trylock(&host->sem))
 977                         return err;
 978         }
 979
 980         ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
 981                                "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
 982         if (ret != 0) {
 983                 dev_err(mmc_dev(host->mmc),
 984                         "%s: omap_request_dma() failed with %d\n",
 985                         mmc_hostname(host->mmc), ret);
 986                 return ret;
 987         }
 988
 989         host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 990                         data->sg_len, omap_hsmmc_get_dma_dir(host, data));
 991         host->dma_ch = dma_ch;
 992         host->dma_sg_idx = 0;
 993
 994         omap_hsmmc_config_dma_params(host, data, data->sg);
 995
 996         return 0;
 997 }
 998
 999 static void set_data_timeout(struct omap_hsmmc_host *host,
1000                              struct mmc_request *req)
1001 {
1002         unsigned int timeout, cycle_ns;
1003         uint32_t reg, clkd, dto = 0;
1004
1005         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1006         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1007         if (clkd == 0)
1008                 clkd = 1;
1009
1010         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1011         timeout = req->data->timeout_ns / cycle_ns;
1012         timeout += req->data->timeout_clks;
1013         if (timeout) {
1014                 while ((timeout & 0x80000000) == 0) {
1015                         dto += 1;
1016                         timeout <<= 1;
1017                 }
1018                 dto = 31 - dto;
1019                 timeout <<= 1;
1020                 if (timeout && dto)
1021                         dto += 1;
1022                 if (dto >= 13)
1023                         dto -= 13;
1024                 else
1025                         dto = 0;
1026                 if (dto > 14)
1027                         dto = 14;
1028         }
1029
1030         reg &= ~DTO_MASK;
1031         reg |= dto << DTO_SHIFT;
1032         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1033 }
1034
1035 /*
1036  * Configure block length for MMC/SD cards and initiate the transfer.
1037  */
1038 static int
1039 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1040 {
1041         int ret;
1042         host->data = req->data;
1043
1044         if (req->data == NULL) {
1045                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1046                 return 0;
1047         }
1048
1049         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1050                                         | (req->data->blocks << 16));
1051         set_data_timeout(host, req);
1052
1053         if (host->use_dma) {
1054                 ret = omap_hsmmc_start_dma_transfer(host, req);
1055                 if (ret != 0) {
1056                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1057                         return ret;
1058                 }
1059         }
1060         return 0;
1061 }
1062
1063 /*
1064  * Request function. for read/write operation
1065  */
1066 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1067 {
1068         struct omap_hsmmc_host *host = mmc_priv(mmc);
1069         int err;
1070
1071         /*
1072          * Prevent races with the interrupt handler because of unexpected
1073          * interrupts, but not if we are already in interrupt context i.e.
1074          * retries.
1075          */
1076         if (!in_interrupt()) {
1077                 spin_lock_irqsave(&host->irq_lock, host->flags);
1078                 /*
1079                  * Protect the card from I/O if there is a possibility
1080                  * it can be removed.
1081                  */
1082                 if (host->protect_card) {
1083                         if (host->reqs_blocked < 3) {
1084                                 /*
1085                                  * Ensure the controller is left in a consistent
1086                                  * state by resetting the command and data state
1087                                  * machines.
1088                                  */
1089                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1090                                 omap_hsmmc_reset_controller_fsm(host, SRC);
1091                                 host->reqs_blocked += 1;
1092                         }
1093                         req->cmd->error = -EBADF;
1094                         if (req->data)
1095                                 req->data->error = -EBADF;
1096                         spin_unlock_irqrestore(&host->irq_lock, host->flags);
1097                         mmc_request_done(mmc, req);
1098                         return;
1099                 } else if (host->reqs_blocked)
1100                         host->reqs_blocked = 0;
1101         }
1102         WARN_ON(host->mrq != NULL);
1103         host->mrq = req;
1104         err = omap_hsmmc_prepare_data(host, req);
1105         if (err) {
1106                 req->cmd->error = err;
1107                 if (req->data)
1108                         req->data->error = err;
1109                 host->mrq = NULL;
1110                 if (!in_interrupt())
1111                         spin_unlock_irqrestore(&host->irq_lock, host->flags);
1112                 mmc_request_done(mmc, req);
1113                 return;
1114         }
1115
1116         omap_hsmmc_start_command(host, req->cmd, req->data);
1117 }
1118
1119 /* Routine to configure clock values. Exposed API to core */
1120 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1121 {
1122         struct omap_hsmmc_host *host = mmc_priv(mmc);
1123         u16 dsor = 0;
1124         unsigned long regval;
1125         unsigned long timeout;
1126         u32 con;
1127         int do_send_init_stream = 0;
1128
1129         mmc_host_enable(host->mmc);
1130
1131         if (ios->power_mode != host->power_mode) {
1132                 switch (ios->power_mode) {
1133                 case MMC_POWER_OFF:
1134                         mmc_slot(host).set_power(host->dev, host->slot_id,
1135                                                  0, 0);
1136                         host->vdd = 0;
1137                         break;
1138                 case MMC_POWER_UP:
1139                         mmc_slot(host).set_power(host->dev, host->slot_id,
1140                                                  1, ios->vdd);
1141                         host->vdd = ios->vdd;
1142                         break;
1143                 case MMC_POWER_ON:
1144                         do_send_init_stream = 1;
1145                         break;
1146                 }
1147                 host->power_mode = ios->power_mode;
1148         }
1149
1150         /* FIXME: set registers based only on changes to ios */
1151
1152         con = OMAP_HSMMC_READ(host->base, CON);
1153         switch (mmc->ios.bus_width) {
1154         case MMC_BUS_WIDTH_8:
1155                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1156                 break;
1157         case MMC_BUS_WIDTH_4:
1158                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1159                 OMAP_HSMMC_WRITE(host->base, HCTL,
1160                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1161                 break;
1162         case MMC_BUS_WIDTH_1:
1163                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1164                 OMAP_HSMMC_WRITE(host->base, HCTL,
1165                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1166                 break;
1167         }
1168
1169         if (host->id == OMAP_MMC1_DEVID) {
1170                 /* Only MMC1 can interface at 3V without some flavor
1171                  * of external transceiver; but they all handle 1.8V.
1172                  */
1173                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1174                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1175                                 /*
1176                                  * The mmc_select_voltage fn of the core does
1177                                  * not seem to set the power_mode to
1178                                  * MMC_POWER_UP upon recalculating the voltage.
1179                                  * vdd 1.8v.
1180                                  */
1181                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1182                                 dev_dbg(mmc_dev(host->mmc),
1183                                                 "Switch operation failed\n");
1184                 }
1185         }
1186
1187         if (ios->clock) {
1188                 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1189                 if (dsor < 1)
1190                         dsor = 1;
1191
1192                 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1193                         dsor++;
1194
1195                 if (dsor > 250)
1196                         dsor = 250;
1197         }
1198         omap_hsmmc_stop_clock(host);
1199         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1200         regval = regval & ~(CLKD_MASK);
1201         regval = regval | (dsor << 6) | (DTO << 16);
1202         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1203         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1204                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1205
1206         /* Wait till the ICS bit is set */
1207         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1208         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
1209                 && time_before(jiffies, timeout))
1210                 msleep(1);
1211
1212         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1213                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1214
1215         if (do_send_init_stream)
1216                 send_init_stream(host);
1217
1218         con = OMAP_HSMMC_READ(host->base, CON);
1219         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1220                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1221         else
1222                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
1223
1224         if (host->power_mode == MMC_POWER_OFF)
1225                 mmc_host_disable(host->mmc);
1226         else
1227                 mmc_host_lazy_disable(host->mmc);
1228 }
1229
1230 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1231 {
1232         struct omap_hsmmc_host *host = mmc_priv(mmc);
1233
1234         if (!mmc_slot(host).card_detect)
1235                 return -ENOSYS;
1236         return mmc_slot(host).card_detect(mmc_slot(host).card_detect_irq);
1237 }
1238
1239 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1240 {
1241         struct omap_hsmmc_host *host = mmc_priv(mmc);
1242
1243         if (!mmc_slot(host).get_ro)
1244                 return -ENOSYS;
1245         return mmc_slot(host).get_ro(host->dev, 0);
1246 }
1247
1248 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1249 {
1250         u32 hctl, capa, value;
1251
1252         /* Only MMC1 supports 3.0V */
1253         if (host->id == OMAP_MMC1_DEVID) {
1254                 hctl = SDVS30;
1255                 capa = VS30 | VS18;
1256         } else {
1257                 hctl = SDVS18;
1258                 capa = VS18;
1259         }
1260
1261         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1262         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1263
1264         value = OMAP_HSMMC_READ(host->base, CAPA);
1265         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1266
1267         /* Set the controller to AUTO IDLE mode */
1268         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1269         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1270
1271         /* Set SD bus power bit */
1272         set_sd_bus_power(host);
1273 }
1274
1275 /*
1276  * Dynamic power saving handling, FSM:
1277  *   ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1278  *     ^___________|          |                      |
1279  *     |______________________|______________________|
1280  *
1281  * ENABLED:   mmc host is fully functional
1282  * DISABLED:  fclk is off
1283  * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1284  * REGSLEEP:  fclk is off, voltage regulator is asleep
1285  * OFF:       fclk is off, voltage regulator is off
1286  *
1287  * Transition handlers return the timeout for the next state transition
1288  * or negative error.
1289  */
1290
1291 enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
1292
1293 /* Handler for [ENABLED -> DISABLED] transition */
1294 static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
1295 {
1296         omap_hsmmc_context_save(host);
1297         clk_disable(host->fclk);
1298         host->dpm_state = DISABLED;
1299
1300         dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1301
1302         if (host->power_mode == MMC_POWER_OFF)
1303                 return 0;
1304
1305         return msecs_to_jiffies(OMAP_MMC_SLEEP_TIMEOUT);
1306 }
1307
1308 /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
1309 static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
1310 {
1311         int err, new_state;
1312
1313         if (!mmc_try_claim_host(host->mmc))
1314                 return 0;
1315
1316         clk_enable(host->fclk);
1317         omap_hsmmc_context_restore(host);
1318         if (mmc_card_can_sleep(host->mmc)) {
1319                 err = mmc_card_sleep(host->mmc);
1320                 if (err < 0) {
1321                         clk_disable(host->fclk);
1322                         mmc_release_host(host->mmc);
1323                         return err;
1324                 }
1325                 new_state = CARDSLEEP;
1326         } else {
1327                 new_state = REGSLEEP;
1328         }
1329         if (mmc_slot(host).set_sleep)
1330                 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1331                                          new_state == CARDSLEEP);
1332         /* FIXME: turn off bus power and perhaps interrupts too */
1333         clk_disable(host->fclk);
1334         host->dpm_state = new_state;
1335
1336         mmc_release_host(host->mmc);
1337
1338         dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1339                 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1340
1341         if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1342             mmc_slot(host).card_detect ||
1343             (mmc_slot(host).get_cover_state &&
1344              mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
1345                 return msecs_to_jiffies(OMAP_MMC_OFF_TIMEOUT);
1346
1347         return 0;
1348 }
1349
1350 /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
1351 static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
1352 {
1353         if (!mmc_try_claim_host(host->mmc))
1354                 return 0;
1355
1356         if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1357               mmc_slot(host).card_detect ||
1358               (mmc_slot(host).get_cover_state &&
1359                mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1360                 mmc_release_host(host->mmc);
1361                 return 0;
1362         }
1363
1364         mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1365         host->vdd = 0;
1366         host->power_mode = MMC_POWER_OFF;
1367
1368         dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1369                 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1370
1371         host->dpm_state = OFF;
1372
1373         mmc_release_host(host->mmc);
1374
1375         return 0;
1376 }
1377
1378 /* Handler for [DISABLED -> ENABLED] transition */
1379 static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host)
1380 {
1381         int err;
1382
1383         err = clk_enable(host->fclk);
1384         if (err < 0)
1385                 return err;
1386
1387         omap_hsmmc_context_restore(host);
1388         host->dpm_state = ENABLED;
1389
1390         dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1391
1392         return 0;
1393 }
1394
1395 /* Handler for [SLEEP -> ENABLED] transition */
1396 static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
1397 {
1398         if (!mmc_try_claim_host(host->mmc))
1399                 return 0;
1400
1401         clk_enable(host->fclk);
1402         omap_hsmmc_context_restore(host);
1403         if (mmc_slot(host).set_sleep)
1404                 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1405                          host->vdd, host->dpm_state == CARDSLEEP);
1406         if (mmc_card_can_sleep(host->mmc))
1407                 mmc_card_awake(host->mmc);
1408
1409         dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1410                 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1411
1412         host->dpm_state = ENABLED;
1413
1414         mmc_release_host(host->mmc);
1415
1416         return 0;
1417 }
1418
1419 /* Handler for [OFF -> ENABLED] transition */
1420 static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host)
1421 {
1422         clk_enable(host->fclk);
1423
1424         omap_hsmmc_context_restore(host);
1425         omap_hsmmc_conf_bus_power(host);
1426         mmc_power_restore_host(host->mmc);
1427
1428         host->dpm_state = ENABLED;
1429
1430         dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1431
1432         return 0;
1433 }
1434
1435 /*
1436  * Bring MMC host to ENABLED from any other PM state.
1437  */
1438 static int omap_hsmmc_enable(struct mmc_host *mmc)
1439 {
1440         struct omap_hsmmc_host *host = mmc_priv(mmc);
1441
1442         switch (host->dpm_state) {
1443         case DISABLED:
1444                 return omap_hsmmc_disabled_to_enabled(host);
1445         case CARDSLEEP:
1446         case REGSLEEP:
1447                 return omap_hsmmc_sleep_to_enabled(host);
1448         case OFF:
1449                 return omap_hsmmc_off_to_enabled(host);
1450         default:
1451                 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1452                 return -EINVAL;
1453         }
1454 }
1455
1456 /*
1457  * Bring MMC host in PM state (one level deeper).
1458  */
1459 static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy)
1460 {
1461         struct omap_hsmmc_host *host = mmc_priv(mmc);
1462
1463         switch (host->dpm_state) {
1464         case ENABLED: {
1465                 int delay;
1466
1467                 delay = omap_hsmmc_enabled_to_disabled(host);
1468                 if (lazy || delay < 0)
1469                         return delay;
1470                 return 0;
1471         }
1472         case DISABLED:
1473                 return omap_hsmmc_disabled_to_sleep(host);
1474         case CARDSLEEP:
1475         case REGSLEEP:
1476                 return omap_hsmmc_sleep_to_off(host);
1477         default:
1478                 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1479                 return -EINVAL;
1480         }
1481 }
1482
1483 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1484 {
1485         struct omap_hsmmc_host *host = mmc_priv(mmc);
1486         int err;
1487
1488         err = clk_enable(host->fclk);
1489         if (err)
1490                 return err;
1491         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
1492         omap_hsmmc_context_restore(host);
1493         return 0;
1494 }
1495
1496 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1497 {
1498         struct omap_hsmmc_host *host = mmc_priv(mmc);
1499
1500         omap_hsmmc_context_save(host);
1501         clk_disable(host->fclk);
1502         dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1503         return 0;
1504 }
1505
1506 static const struct mmc_host_ops omap_hsmmc_ops = {
1507         .enable = omap_hsmmc_enable_fclk,
1508         .disable = omap_hsmmc_disable_fclk,
1509         .request = omap_hsmmc_request,
1510         .set_ios = omap_hsmmc_set_ios,
1511         .get_cd = omap_hsmmc_get_cd,
1512         .get_ro = omap_hsmmc_get_ro,
1513         /* NYET -- enable_sdio_irq */
1514 };
1515
1516 static const struct mmc_host_ops omap_hsmmc_ps_ops = {
1517         .enable = omap_hsmmc_enable,
1518         .disable = omap_hsmmc_disable,
1519         .request = omap_hsmmc_request,
1520         .set_ios = omap_hsmmc_set_ios,
1521         .get_cd = omap_hsmmc_get_cd,
1522         .get_ro = omap_hsmmc_get_ro,
1523         /* NYET -- enable_sdio_irq */
1524 };
1525
1526 #ifdef CONFIG_DEBUG_FS
1527
1528 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1529 {
1530         struct mmc_host *mmc = s->private;
1531         struct omap_hsmmc_host *host = mmc_priv(mmc);
1532         int context_loss = 0;
1533
1534         if (host->pdata->get_context_loss_count)
1535                 context_loss = host->pdata->get_context_loss_count(host->dev);
1536
1537         seq_printf(s, "mmc%d:\n"
1538                         " enabled:\t%d\n"
1539                         " dpm_state:\t%d\n"
1540                         " nesting_cnt:\t%d\n"
1541                         " ctx_loss:\t%d:%d\n"
1542                         "\nregs:\n",
1543                         mmc->index, mmc->enabled ? 1 : 0,
1544                         host->dpm_state, mmc->nesting_cnt,
1545                         host->context_loss, context_loss);
1546
1547         if (host->suspended || host->dpm_state == OFF) {
1548                 seq_printf(s, "host suspended, can't read registers\n");
1549                 return 0;
1550         }
1551
1552         if (clk_enable(host->fclk) != 0) {
1553                 seq_printf(s, "can't read the regs\n");
1554                 return 0;
1555         }
1556
1557         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1558                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1559         seq_printf(s, "CON:\t\t0x%08x\n",
1560                         OMAP_HSMMC_READ(host->base, CON));
1561         seq_printf(s, "HCTL:\t\t0x%08x\n",
1562                         OMAP_HSMMC_READ(host->base, HCTL));
1563         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1564                         OMAP_HSMMC_READ(host->base, SYSCTL));
1565         seq_printf(s, "IE:\t\t0x%08x\n",
1566                         OMAP_HSMMC_READ(host->base, IE));
1567         seq_printf(s, "ISE:\t\t0x%08x\n",
1568                         OMAP_HSMMC_READ(host->base, ISE));
1569         seq_printf(s, "CAPA:\t\t0x%08x\n",
1570                         OMAP_HSMMC_READ(host->base, CAPA));
1571
1572         clk_disable(host->fclk);
1573
1574         return 0;
1575 }
1576
1577 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1578 {
1579         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1580 }
1581
1582 static const struct file_operations mmc_regs_fops = {
1583         .open           = omap_hsmmc_regs_open,
1584         .read           = seq_read,
1585         .llseek         = seq_lseek,
1586         .release        = single_release,
1587 };
1588
1589 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1590 {
1591         if (mmc->debugfs_root)
1592                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1593                         mmc, &mmc_regs_fops);
1594 }
1595
1596 #else
1597
1598 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1599 {
1600 }
1601
1602 #endif
1603
1604 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1605 {
1606         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1607         struct mmc_host *mmc;
1608         struct omap_hsmmc_host *host = NULL;
1609         struct resource *res;
1610         int ret = 0, irq;
1611
1612         if (pdata == NULL) {
1613                 dev_err(&pdev->dev, "Platform Data is missing\n");
1614                 return -ENXIO;
1615         }
1616
1617         if (pdata->nr_slots == 0) {
1618                 dev_err(&pdev->dev, "No Slots\n");
1619                 return -ENXIO;
1620         }
1621
1622         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1623         irq = platform_get_irq(pdev, 0);
1624         if (res == NULL || irq < 0)
1625                 return -ENXIO;
1626
1627         res = request_mem_region(res->start, res->end - res->start + 1,
1628                                                         pdev->name);
1629         if (res == NULL)
1630                 return -EBUSY;
1631
1632         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1633         if (!mmc) {
1634                 ret = -ENOMEM;
1635                 goto err;
1636         }
1637
1638         host            = mmc_priv(mmc);
1639         host->mmc       = mmc;
1640         host->pdata     = pdata;
1641         host->dev       = &pdev->dev;
1642         host->use_dma   = 1;
1643         host->dev->dma_mask = &pdata->dma_mask;
1644         host->dma_ch    = -1;
1645         host->irq       = irq;
1646         host->id        = pdev->id;
1647         host->slot_id   = 0;
1648         host->mapbase   = res->start;
1649         host->base      = ioremap(host->mapbase, SZ_4K);
1650         host->power_mode = -1;
1651
1652         platform_set_drvdata(pdev, host);
1653         INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
1654
1655         if (mmc_slot(host).power_saving)
1656                 mmc->ops        = &omap_hsmmc_ps_ops;
1657         else
1658                 mmc->ops        = &omap_hsmmc_ops;
1659
1660         mmc->f_min      = 400000;
1661         mmc->f_max      = 52000000;
1662
1663         sema_init(&host->sem, 1);
1664         spin_lock_init(&host->irq_lock);
1665
1666         host->iclk = clk_get(&pdev->dev, "ick");
1667         if (IS_ERR(host->iclk)) {
1668                 ret = PTR_ERR(host->iclk);
1669                 host->iclk = NULL;
1670                 goto err1;
1671         }
1672         host->fclk = clk_get(&pdev->dev, "fck");
1673         if (IS_ERR(host->fclk)) {
1674                 ret = PTR_ERR(host->fclk);
1675                 host->fclk = NULL;
1676                 clk_put(host->iclk);
1677                 goto err1;
1678         }
1679
1680         omap_hsmmc_context_save(host);
1681
1682         mmc->caps |= MMC_CAP_DISABLE;
1683         mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
1684         /* we start off in DISABLED state */
1685         host->dpm_state = DISABLED;
1686
1687         if (mmc_host_enable(host->mmc) != 0) {
1688                 clk_put(host->iclk);
1689                 clk_put(host->fclk);
1690                 goto err1;
1691         }
1692
1693         if (clk_enable(host->iclk) != 0) {
1694                 mmc_host_disable(host->mmc);
1695                 clk_put(host->iclk);
1696                 clk_put(host->fclk);
1697                 goto err1;
1698         }
1699
1700         if (cpu_is_omap2430()) {
1701                 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1702                 /*
1703                  * MMC can still work without debounce clock.
1704                  */
1705                 if (IS_ERR(host->dbclk))
1706                         dev_warn(mmc_dev(host->mmc),
1707                                 "Failed to get debounce clock\n");
1708                 else
1709                         host->got_dbclk = 1;
1710
1711                 if (host->got_dbclk)
1712                         if (clk_enable(host->dbclk) != 0)
1713                                 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1714                                                         " clk failed\n");
1715         }
1716
1717         /* Since we do only SG emulation, we can have as many segs
1718          * as we want. */
1719         mmc->max_phys_segs = 1024;
1720         mmc->max_hw_segs = 1024;
1721
1722         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1723         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1724         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1725         mmc->max_seg_size = mmc->max_req_size;
1726
1727         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1728                      MMC_CAP_WAIT_WHILE_BUSY;
1729
1730         if (mmc_slot(host).wires >= 8)
1731                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1732         else if (mmc_slot(host).wires >= 4)
1733                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1734
1735         if (mmc_slot(host).nonremovable)
1736                 mmc->caps |= MMC_CAP_NONREMOVABLE;
1737
1738         omap_hsmmc_conf_bus_power(host);
1739
1740         /* Select DMA lines */
1741         switch (host->id) {
1742         case OMAP_MMC1_DEVID:
1743                 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1744                 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1745                 break;
1746         case OMAP_MMC2_DEVID:
1747                 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1748                 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1749                 break;
1750         case OMAP_MMC3_DEVID:
1751                 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
1752                 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
1753                 break;
1754         default:
1755                 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
1756                 goto err_irq;
1757         }
1758
1759         /* Request IRQ for MMC operations */
1760         ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
1761                         mmc_hostname(mmc), host);
1762         if (ret) {
1763                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1764                 goto err_irq;
1765         }
1766
1767         /* initialize power supplies, gpios, etc */
1768         if (pdata->init != NULL) {
1769                 if (pdata->init(&pdev->dev) != 0) {
1770                         dev_dbg(mmc_dev(host->mmc),
1771                                 "Unable to configure MMC IRQs\n");
1772                         goto err_irq_cd_init;
1773                 }
1774         }
1775         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1776
1777         /* Request IRQ for card detect */
1778         if ((mmc_slot(host).card_detect_irq)) {
1779                 ret = request_irq(mmc_slot(host).card_detect_irq,
1780                                   omap_hsmmc_cd_handler,
1781                                   IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1782                                           | IRQF_DISABLED,
1783                                   mmc_hostname(mmc), host);
1784                 if (ret) {
1785                         dev_dbg(mmc_dev(host->mmc),
1786                                 "Unable to grab MMC CD IRQ\n");
1787                         goto err_irq_cd;
1788                 }
1789         }
1790
1791         OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1792         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1793
1794         mmc_host_lazy_disable(host->mmc);
1795
1796         omap_hsmmc_protect_card(host);
1797
1798         mmc_add_host(mmc);
1799
1800         if (mmc_slot(host).name != NULL) {
1801                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1802                 if (ret < 0)
1803                         goto err_slot_name;
1804         }
1805         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
1806                 ret = device_create_file(&mmc->class_dev,
1807                                         &dev_attr_cover_switch);
1808                 if (ret < 0)
1809                         goto err_cover_switch;
1810         }
1811
1812         omap_hsmmc_debugfs(mmc);
1813
1814         return 0;
1815
1816 err_cover_switch:
1817         device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1818 err_slot_name:
1819         mmc_remove_host(mmc);
1820 err_irq_cd:
1821         free_irq(mmc_slot(host).card_detect_irq, host);
1822 err_irq_cd_init:
1823         free_irq(host->irq, host);
1824 err_irq:
1825         mmc_host_disable(host->mmc);
1826         clk_disable(host->iclk);
1827         clk_put(host->fclk);
1828         clk_put(host->iclk);
1829         if (host->got_dbclk) {
1830                 clk_disable(host->dbclk);
1831                 clk_put(host->dbclk);
1832         }
1833
1834 err1:
1835         iounmap(host->base);
1836 err:
1837         dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1838         release_mem_region(res->start, res->end - res->start + 1);
1839         if (host)
1840                 mmc_free_host(mmc);
1841         return ret;
1842 }
1843
1844 static int omap_hsmmc_remove(struct platform_device *pdev)
1845 {
1846         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1847         struct resource *res;
1848
1849         if (host) {
1850                 mmc_host_enable(host->mmc);
1851                 mmc_remove_host(host->mmc);
1852                 if (host->pdata->cleanup)
1853                         host->pdata->cleanup(&pdev->dev);
1854                 free_irq(host->irq, host);
1855                 if (mmc_slot(host).card_detect_irq)
1856                         free_irq(mmc_slot(host).card_detect_irq, host);
1857                 flush_scheduled_work();
1858
1859                 mmc_host_disable(host->mmc);
1860                 clk_disable(host->iclk);
1861                 clk_put(host->fclk);
1862                 clk_put(host->iclk);
1863                 if (host->got_dbclk) {
1864                         clk_disable(host->dbclk);
1865                         clk_put(host->dbclk);
1866                 }
1867
1868                 mmc_free_host(host->mmc);
1869                 iounmap(host->base);
1870         }
1871
1872         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1873         if (res)
1874                 release_mem_region(res->start, res->end - res->start + 1);
1875         platform_set_drvdata(pdev, NULL);
1876
1877         return 0;
1878 }
1879
1880 #ifdef CONFIG_PM
1881 static int omap_hsmmc_suspend(struct platform_device *pdev, pm_message_t state)
1882 {
1883         int ret = 0;
1884         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1885
1886         if (host && host->suspended)
1887                 return 0;
1888
1889         if (host) {
1890                 host->suspended = 1;
1891                 if (host->pdata->suspend) {
1892                         ret = host->pdata->suspend(&pdev->dev,
1893                                                         host->slot_id);
1894                         if (ret) {
1895                                 dev_dbg(mmc_dev(host->mmc),
1896                                         "Unable to handle MMC board"
1897                                         " level suspend\n");
1898                                 host->suspended = 0;
1899                                 return ret;
1900                         }
1901                 }
1902                 cancel_work_sync(&host->mmc_carddetect_work);
1903                 mmc_host_enable(host->mmc);
1904                 ret = mmc_suspend_host(host->mmc, state);
1905                 if (ret == 0) {
1906                         OMAP_HSMMC_WRITE(host->base, ISE, 0);
1907                         OMAP_HSMMC_WRITE(host->base, IE, 0);
1908
1909
1910                         OMAP_HSMMC_WRITE(host->base, HCTL,
1911                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
1912                         mmc_host_disable(host->mmc);
1913                         clk_disable(host->iclk);
1914                         if (host->got_dbclk)
1915                                 clk_disable(host->dbclk);
1916                 } else {
1917                         host->suspended = 0;
1918                         if (host->pdata->resume) {
1919                                 ret = host->pdata->resume(&pdev->dev,
1920                                                           host->slot_id);
1921                                 if (ret)
1922                                         dev_dbg(mmc_dev(host->mmc),
1923                                                 "Unmask interrupt failed\n");
1924                         }
1925                         mmc_host_disable(host->mmc);
1926                 }
1927
1928         }
1929         return ret;
1930 }
1931
1932 /* Routine to resume the MMC device */
1933 static int omap_hsmmc_resume(struct platform_device *pdev)
1934 {
1935         int ret = 0;
1936         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1937
1938         if (host && !host->suspended)
1939                 return 0;
1940
1941         if (host) {
1942                 ret = clk_enable(host->iclk);
1943                 if (ret)
1944                         goto clk_en_err;
1945
1946                 if (mmc_host_enable(host->mmc) != 0) {
1947                         clk_disable(host->iclk);
1948                         goto clk_en_err;
1949                 }
1950
1951                 if (host->got_dbclk)
1952                         clk_enable(host->dbclk);
1953
1954                 omap_hsmmc_conf_bus_power(host);
1955
1956                 if (host->pdata->resume) {
1957                         ret = host->pdata->resume(&pdev->dev, host->slot_id);
1958                         if (ret)
1959                                 dev_dbg(mmc_dev(host->mmc),
1960                                         "Unmask interrupt failed\n");
1961                 }
1962
1963                 omap_hsmmc_protect_card(host);
1964
1965                 /* Notify the core to resume the host */
1966                 ret = mmc_resume_host(host->mmc);
1967                 if (ret == 0)
1968                         host->suspended = 0;
1969
1970                 mmc_host_lazy_disable(host->mmc);
1971         }
1972
1973         return ret;
1974
1975 clk_en_err:
1976         dev_dbg(mmc_dev(host->mmc),
1977                 "Failed to enable MMC clocks during resume\n");
1978         return ret;
1979 }
1980
1981 #else
1982 #define omap_hsmmc_suspend      NULL
1983 #define omap_hsmmc_resume               NULL
1984 #endif
1985
1986 static struct platform_driver omap_hsmmc_driver = {
1987         .remove         = omap_hsmmc_remove,
1988         .suspend        = omap_hsmmc_suspend,
1989         .resume         = omap_hsmmc_resume,
1990         .driver         = {
1991                 .name = DRIVER_NAME,
1992                 .owner = THIS_MODULE,
1993         },
1994 };
1995
1996 static int __init omap_hsmmc_init(void)
1997 {
1998         /* Register the MMC driver */
1999         return platform_driver_register(&omap_hsmmc_driver);
2000 }
2001
2002 static void __exit omap_hsmmc_cleanup(void)
2003 {
2004         /* Unregister MMC driver */
2005         platform_driver_unregister(&omap_hsmmc_driver);
2006 }
2007
2008 module_init(omap_hsmmc_init);
2009 module_exit(omap_hsmmc_cleanup);
2010
2011 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2012 MODULE_LICENSE("GPL");
2013 MODULE_ALIAS("platform:" DRIVER_NAME);
2014 MODULE_AUTHOR("Texas Instruments Inc");