SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/delay.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/timer.h>
  24 #include <linux/mmc/host.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/clk.h>
  27 #include <linux/scatterlist.h>
  28 #include <linux/i2c/tps65010.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/mach-types.h>
  33
  34 #include <asm/arch/board.h>
  35 #include <asm/arch/mmc.h>
  36 #include <asm/arch/gpio.h>
  37 #include <asm/arch/dma.h>
  38 #include <asm/arch/mux.h>
  39 #include <asm/arch/fpga.h>
  40
  41 #define OMAP_MMC_REG_CMD        0x00
  42 #define OMAP_MMC_REG_ARGL       0x04
  43 #define OMAP_MMC_REG_ARGH       0x08
  44 #define OMAP_MMC_REG_CON        0x0c
  45 #define OMAP_MMC_REG_STAT       0x10
  46 #define OMAP_MMC_REG_IE         0x14
  47 #define OMAP_MMC_REG_CTO        0x18
  48 #define OMAP_MMC_REG_DTO        0x1c
  49 #define OMAP_MMC_REG_DATA       0x20
  50 #define OMAP_MMC_REG_BLEN       0x24
  51 #define OMAP_MMC_REG_NBLK       0x28
  52 #define OMAP_MMC_REG_BUF        0x2c
  53 #define OMAP_MMC_REG_SDIO       0x34
  54 #define OMAP_MMC_REG_REV        0x3c
  55 #define OMAP_MMC_REG_RSP0       0x40
  56 #define OMAP_MMC_REG_RSP1       0x44
  57 #define OMAP_MMC_REG_RSP2       0x48
  58 #define OMAP_MMC_REG_RSP3       0x4c
  59 #define OMAP_MMC_REG_RSP4       0x50
  60 #define OMAP_MMC_REG_RSP5       0x54
  61 #define OMAP_MMC_REG_RSP6       0x58
  62 #define OMAP_MMC_REG_RSP7       0x5c
  63 #define OMAP_MMC_REG_IOSR       0x60
  64 #define OMAP_MMC_REG_SYSC       0x64
  65 #define OMAP_MMC_REG_SYSS       0x68
  66
  67 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  68 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  69 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  70 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  71 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  72 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  73 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  74 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  75 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  76 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  77 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  78 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  79 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  80
  81 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
  82 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
  83
  84 /*
  85  * Command types
  86  */
  87 #define OMAP_MMC_CMDTYPE_BC     0
  88 #define OMAP_MMC_CMDTYPE_BCR    1
  89 #define OMAP_MMC_CMDTYPE_AC     2
  90 #define OMAP_MMC_CMDTYPE_ADTC   3
  91
  92
  93 #define DRIVER_NAME "mmci-omap"
  94
  95 /* Specifies how often in millisecs to poll for card status changes
  96  * when the cover switch is open */
  97 #define OMAP_MMC_COVER_POLL_DELAY       500
  98
  99 struct mmc_omap_host;
 100
 101 struct mmc_omap_slot {
 102         int                     id;
 103         unsigned int            vdd;
 104         u16                     saved_con;
 105         u16                     bus_mode;
 106         unsigned int            fclk_freq;
 107         unsigned                powered:1;
 108
 109         struct tasklet_struct   cover_tasklet;
 110         struct timer_list       cover_timer;
 111         unsigned                cover_open;
 112
 113         struct mmc_request      *mrq;
 114         struct mmc_omap_host    *host;
 115         struct mmc_host         *mmc;
 116         struct omap_mmc_slot_data *pdata;
 117 };
 118
 119 struct mmc_omap_host {
 120         int                     initialized;
 121         int                     suspended;
 122         struct mmc_request *    mrq;
 123         struct mmc_command *    cmd;
 124         struct mmc_data *       data;
 125         struct mmc_host *       mmc;
 126         struct device *         dev;
 127         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 128         struct clk *            iclk;
 129         struct clk *            fclk;
 130         struct resource         *mem_res;
 131         void __iomem            *virt_base;
 132         unsigned int            phys_base;
 133         int                     irq;
 134         unsigned char           bus_mode;
 135         unsigned char           hw_bus_mode;
 136
 137         struct work_struct      cmd_abort;
 138         struct timer_list       cmd_timer;
 139
 140         unsigned int            sg_len;
 141         int                     sg_idx;
 142         u16 *                   buffer;
 143         u32                     buffer_bytes_left;
 144         u32                     total_bytes_left;
 145
 146         unsigned                use_dma:1;
 147         unsigned                brs_received:1, dma_done:1;
 148         unsigned                dma_is_read:1;
 149         unsigned                dma_in_use:1;
 150         int                     dma_ch;
 151         spinlock_t              dma_lock;
 152         struct timer_list       dma_timer;
 153         unsigned                dma_len;
 154
 155         short                   power_pin;
 156
 157         struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
 158         struct mmc_omap_slot    *current_slot;
 159         spinlock_t              slot_lock;
 160         wait_queue_head_t       slot_wq;
 161         int                     nr_slots;
 162
 163         struct omap_mmc_platform_data *pdata;
 164 };
 165
 166 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
 167 {
 168         struct mmc_omap_host *host = slot->host;
 169         unsigned long flags;
 170
 171         if (claimed)
 172                 goto no_claim;
 173         spin_lock_irqsave(&host->slot_lock, flags);
 174         while (host->mmc != NULL) {
 175                 spin_unlock_irqrestore(&host->slot_lock, flags);
 176                 wait_event(host->slot_wq, host->mmc == NULL);
 177                 spin_lock_irqsave(&host->slot_lock, flags);
 178         }
 179         host->mmc = slot->mmc;
 180         spin_unlock_irqrestore(&host->slot_lock, flags);
 181 no_claim:
 182         clk_enable(host->fclk);
 183         if (host->current_slot != slot) {
 184                 if (host->pdata->switch_slot != NULL)
 185                         host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
 186                 host->current_slot = slot;
 187         }
 188
 189         /* Doing the dummy read here seems to work around some bug
 190          * at least in OMAP24xx silicon where the command would not
 191          * start after writing the CMD register. Sigh. */
 192         OMAP_MMC_READ(host, CON);
 193
 194         OMAP_MMC_WRITE(host, CON, slot->saved_con);
 195 }
 196
 197 static void mmc_omap_start_request(struct mmc_omap_host *host,
 198                                    struct mmc_request *req);
 199
 200 static void mmc_omap_release_slot(struct mmc_omap_slot *slot)
 201 {
 202         struct mmc_omap_host *host = slot->host;
 203         unsigned long flags;
 204         int i;
 205
 206         BUG_ON(slot == NULL || host->mmc == NULL);
 207         clk_disable(host->fclk);
 208
 209         spin_lock_irqsave(&host->slot_lock, flags);
 210         /* Check for any pending requests */
 211         for (i = 0; i < host->nr_slots; i++) {
 212                 struct mmc_omap_slot *new_slot;
 213                 struct mmc_request *rq;
 214
 215                 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
 216                         continue;
 217
 218                 new_slot = host->slots[i];
 219                 /* The current slot should not have a request in queue */
 220                 BUG_ON(new_slot == host->current_slot);
 221
 222                 host->mmc = new_slot->mmc;
 223                 spin_unlock_irqrestore(&host->slot_lock, flags);
 224                 mmc_omap_select_slot(new_slot, 1);
 225                 rq = new_slot->mrq;
 226                 new_slot->mrq = NULL;
 227                 mmc_omap_start_request(host, rq);
 228                 return;
 229         }
 230
 231         host->mmc = NULL;
 232         wake_up(&host->slot_wq);
 233         spin_unlock_irqrestore(&host->slot_lock, flags);
 234 }
 235
 236 static inline
 237 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
 238 {
 239         if (slot->pdata->get_cover_state)
 240                 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
 241                                                     slot->id);
 242         return 0;
 243 }
 244
 245 static ssize_t
 246 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 247                            char *buf)
 248 {
 249         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 250         struct mmc_omap_slot *slot = mmc_priv(mmc);
 251
 252         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
 253                        "closed");
 254 }
 255
 256 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 257
 258 static ssize_t
 259 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 260                         char *buf)
 261 {
 262         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 263         struct mmc_omap_slot *slot = mmc_priv(mmc);
 264
 265         return sprintf(buf, "%s\n", slot->pdata->name);
 266 }
 267
 268 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 269
 270 static void
 271 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 272 {
 273         u32 cmdreg;
 274         u32 resptype;
 275         u32 cmdtype;
 276
 277         host->cmd = cmd;
 278
 279         resptype = 0;
 280         cmdtype = 0;
 281
 282         /* Our hardware needs to know exact type */
 283         switch (mmc_resp_type(cmd)) {
 284         case MMC_RSP_NONE:
 285                 break;
 286         case MMC_RSP_R1:
 287         case MMC_RSP_R1B:
 288                 /* resp 1, 1b, 6, 7 */
 289                 resptype = 1;
 290                 break;
 291         case MMC_RSP_R2:
 292                 resptype = 2;
 293                 break;
 294         case MMC_RSP_R3:
 295                 resptype = 3;
 296                 break;
 297         default:
 298                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 299                 break;
 300         }
 301
 302         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 303                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 304         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 305                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 306         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 307                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 308         } else {
 309                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 310         }
 311
 312         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 313
 314         if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
 315                 cmdreg |= 1 << 6;
 316
 317         if (cmd->flags & MMC_RSP_BUSY)
 318                 cmdreg |= 1 << 11;
 319
 320         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 321                 cmdreg |= 1 << 15;
 322
 323         mod_timer(&host->cmd_timer, jiffies + HZ/2);
 324
 325         OMAP_MMC_WRITE(host, CTO, 200);
 326         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 327         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 328         OMAP_MMC_WRITE(host, IE,
 329                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 330                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 331                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 332                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 333                        OMAP_MMC_STAT_END_OF_DATA);
 334         OMAP_MMC_WRITE(host, CMD, cmdreg);
 335 }
 336
 337 static void
 338 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
 339                      int abort)
 340 {
 341         enum dma_data_direction dma_data_dir;
 342
 343         BUG_ON(host->dma_ch < 0);
 344         if (data->error)
 345                 omap_stop_dma(host->dma_ch);
 346         /* Release DMA channel lazily */
 347         mod_timer(&host->dma_timer, jiffies + HZ);
 348         if (data->flags & MMC_DATA_WRITE)
 349                 dma_data_dir = DMA_TO_DEVICE;
 350         else
 351                 dma_data_dir = DMA_FROM_DEVICE;
 352         dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
 353                      dma_data_dir);
 354 }
 355
 356 static void
 357 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 358 {
 359         if (host->dma_in_use)
 360                 mmc_omap_release_dma(host, data, data->error);
 361
 362         host->data = NULL;
 363         host->sg_len = 0;
 364
 365         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 366          * dozens of requests until the card finishes writing data.
 367          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 368          */
 369
 370         if (!data->stop) {
 371                 struct mmc_host *mmc;
 372
 373                 host->mrq = NULL;
 374                 mmc = host->mmc;
 375                 mmc_omap_release_slot(host->current_slot);
 376                 mmc_request_done(mmc, data->mrq);
 377                 return;
 378         }
 379
 380         mmc_omap_start_command(host, data->stop);
 381 }
 382
 383 static void
 384 mmc_omap_send_abort(struct mmc_omap_host *host)
 385 {
 386         struct mmc_omap_slot *slot = host->current_slot;
 387         unsigned int restarts, passes, timeout;
 388         u16 stat = 0;
 389
 390         /* Sending abort takes 80 clocks. Have some extra and round up */
 391         timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
 392         restarts = 0;
 393         while (restarts < 10000) {
 394                 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
 395                 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
 396
 397                 passes = 0;
 398                 while (passes < timeout) {
 399                         stat = OMAP_MMC_READ(host, STAT);
 400                         if (stat & OMAP_MMC_STAT_END_OF_CMD)
 401                                 goto out;
 402                         udelay(1);
 403                         passes++;
 404                 }
 405
 406                 restarts++;
 407         }
 408 out:
 409         OMAP_MMC_WRITE(host, STAT, stat);
 410 }
 411
 412 static void
 413 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
 414 {
 415         u16 ie;
 416
 417         if (host->dma_in_use)
 418                 mmc_omap_release_dma(host, data, 1);
 419
 420         host->data = NULL;
 421         host->sg_len = 0;
 422
 423         ie = OMAP_MMC_READ(host, IE);
 424         OMAP_MMC_WRITE(host, IE, 0);
 425         OMAP_MMC_WRITE(host, IE, ie);
 426         mmc_omap_send_abort(host);
 427 }
 428
 429 static void
 430 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 431 {
 432         unsigned long flags;
 433         int done;
 434
 435         if (!host->dma_in_use) {
 436                 mmc_omap_xfer_done(host, data);
 437                 return;
 438         }
 439         done = 0;
 440         spin_lock_irqsave(&host->dma_lock, flags);
 441         if (host->dma_done)
 442                 done = 1;
 443         else
 444                 host->brs_received = 1;
 445         spin_unlock_irqrestore(&host->dma_lock, flags);
 446         if (done)
 447                 mmc_omap_xfer_done(host, data);
 448 }
 449
 450 static void
 451 mmc_omap_dma_timer(unsigned long data)
 452 {
 453         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 454
 455         BUG_ON(host->dma_ch < 0);
 456         omap_free_dma(host->dma_ch);
 457         host->dma_ch = -1;
 458 }
 459
 460 static void
 461 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 462 {
 463         unsigned long flags;
 464         int done;
 465
 466         done = 0;
 467         spin_lock_irqsave(&host->dma_lock, flags);
 468         if (host->brs_received)
 469                 done = 1;
 470         else
 471                 host->dma_done = 1;
 472         spin_unlock_irqrestore(&host->dma_lock, flags);
 473         if (done)
 474                 mmc_omap_xfer_done(host, data);
 475 }
 476
 477 static void
 478 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 479 {
 480         host->cmd = NULL;
 481
 482         del_timer(&host->cmd_timer);
 483
 484         if (cmd->flags & MMC_RSP_PRESENT) {
 485                 if (cmd->flags & MMC_RSP_136) {
 486                         /* response type 2 */
 487                         cmd->resp[3] =
 488                                 OMAP_MMC_READ(host, RSP0) |
 489                                 (OMAP_MMC_READ(host, RSP1) << 16);
 490                         cmd->resp[2] =
 491                                 OMAP_MMC_READ(host, RSP2) |
 492                                 (OMAP_MMC_READ(host, RSP3) << 16);
 493                         cmd->resp[1] =
 494                                 OMAP_MMC_READ(host, RSP4) |
 495                                 (OMAP_MMC_READ(host, RSP5) << 16);
 496                         cmd->resp[0] =
 497                                 OMAP_MMC_READ(host, RSP6) |
 498                                 (OMAP_MMC_READ(host, RSP7) << 16);
 499                 } else {
 500                         /* response types 1, 1b, 3, 4, 5, 6 */
 501                         cmd->resp[0] =
 502                                 OMAP_MMC_READ(host, RSP6) |
 503                                 (OMAP_MMC_READ(host, RSP7) << 16);
 504                 }
 505         }
 506
 507         if (host->data == NULL || cmd->error) {
 508                 struct mmc_host *mmc;
 509
 510                 if (host->data != NULL)
 511                         mmc_omap_abort_xfer(host, host->data);
 512                 host->mrq = NULL;
 513                 mmc = host->mmc;
 514                 mmc_omap_release_slot(host->current_slot);
 515                 mmc_request_done(mmc, cmd->mrq);
 516         }
 517 }
 518
 519 /*
 520  * Abort stuck command. Can occur when card is removed while it is being
 521  * read.
 522  */
 523 static void mmc_omap_abort_command(struct work_struct *work)
 524 {
 525         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 526                                                   cmd_abort);
 527         u16 ie;
 528
 529         ie = OMAP_MMC_READ(host, IE);
 530         OMAP_MMC_WRITE(host, IE, 0);
 531
 532         if (!host->cmd) {
 533                 OMAP_MMC_WRITE(host, IE, ie);
 534                 return;
 535         }
 536
 537         dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
 538                 host->cmd->opcode);
 539
 540         if (host->data && host->dma_in_use)
 541                 mmc_omap_release_dma(host, host->data, 1);
 542
 543         host->data = NULL;
 544         host->sg_len = 0;
 545
 546         mmc_omap_send_abort(host);
 547         host->cmd->error = -ETIMEDOUT;
 548         mmc_omap_cmd_done(host, host->cmd);
 549         OMAP_MMC_WRITE(host, IE, ie);
 550 }
 551
 552 static void
 553 mmc_omap_cmd_timer(unsigned long data)
 554 {
 555         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 556
 557         schedule_work(&host->cmd_abort);
 558 }
 559
 560 /* PIO only */
 561 static void
 562 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 563 {
 564         struct scatterlist *sg;
 565
 566         sg = host->data->sg + host->sg_idx;
 567         host->buffer_bytes_left = sg->length;
 568         host->buffer = sg_virt(sg);
 569         if (host->buffer_bytes_left > host->total_bytes_left)
 570                 host->buffer_bytes_left = host->total_bytes_left;
 571 }
 572
 573 /* PIO only */
 574 static void
 575 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 576 {
 577         int n;
 578
 579         if (host->buffer_bytes_left == 0) {
 580                 host->sg_idx++;
 581                 BUG_ON(host->sg_idx == host->sg_len);
 582                 mmc_omap_sg_to_buf(host);
 583         }
 584         n = 64;
 585         if (n > host->buffer_bytes_left)
 586                 n = host->buffer_bytes_left;
 587         host->buffer_bytes_left -= n;
 588         host->total_bytes_left -= n;
 589         host->data->bytes_xfered += n;
 590
 591         if (write) {
 592                 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 593         } else {
 594                 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
 595         }
 596 }
 597
 598 static inline void mmc_omap_report_irq(u16 status)
 599 {
 600         static const char *mmc_omap_status_bits[] = {
 601                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 602                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 603         };
 604         int i, c = 0;
 605
 606         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 607                 if (status & (1 << i)) {
 608                         if (c)
 609                                 printk(" ");
 610                         printk("%s", mmc_omap_status_bits[i]);
 611                         c++;
 612                 }
 613 }
 614
 615 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 616 {
 617         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 618         u16 status;
 619         int end_command;
 620         int end_transfer;
 621         int transfer_error, cmd_error;
 622
 623         if (host->cmd == NULL && host->data == NULL) {
 624                 status = OMAP_MMC_READ(host, STAT);
 625                 dev_info(mmc_dev(host->slots[0]->mmc),
 626                          "Spurious IRQ 0x%04x\n", status);
 627                 if (status != 0) {
 628                         OMAP_MMC_WRITE(host, STAT, status);
 629                         OMAP_MMC_WRITE(host, IE, 0);
 630                 }
 631                 return IRQ_HANDLED;
 632         }
 633
 634         end_command = 0;
 635         end_transfer = 0;
 636         transfer_error = 0;
 637         cmd_error = 0;
 638
 639         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 640                 int cmd;
 641
 642                 OMAP_MMC_WRITE(host, STAT, status);
 643                 if (host->cmd != NULL)
 644                         cmd = host->cmd->opcode;
 645                 else
 646                         cmd = -1;
 647 #ifdef CONFIG_MMC_DEBUG
 648                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 649                         status, cmd);
 650                 mmc_omap_report_irq(status);
 651                 printk("\n");
 652 #endif
 653                 if (host->total_bytes_left) {
 654                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 655                             (status & OMAP_MMC_STAT_END_OF_DATA))
 656                                 mmc_omap_xfer_data(host, 0);
 657                         if (status & OMAP_MMC_STAT_A_EMPTY)
 658                                 mmc_omap_xfer_data(host, 1);
 659                 }
 660
 661                 if (status & OMAP_MMC_STAT_END_OF_DATA)
 662                         end_transfer = 1;
 663
 664                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 665                         dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
 666                                 cmd);
 667                         if (host->data) {
 668                                 host->data->error = -ETIMEDOUT;
 669                                 transfer_error = 1;
 670                         }
 671                 }
 672
 673                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 674                         if (host->data) {
 675                                 host->data->error = -EILSEQ;
 676                                 dev_dbg(mmc_dev(host->mmc),
 677                                          "data CRC error, bytes left %d\n",
 678                                         host->total_bytes_left);
 679                                 transfer_error = 1;
 680                         } else {
 681                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 682                         }
 683                 }
 684
 685                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 686                         /* Timeouts are routine with some commands */
 687                         if (host->cmd) {
 688                                 struct mmc_omap_slot *slot =
 689                                         host->current_slot;
 690                                 if (slot == NULL ||
 691                                     !mmc_omap_cover_is_open(slot))
 692                                         dev_err(mmc_dev(host->mmc),
 693                                                 "command timeout (CMD%d)\n",
 694                                                 cmd);
 695                                 host->cmd->error = -ETIMEDOUT;
 696                                 end_command = 1;
 697                                 cmd_error = 1;
 698                         }
 699                 }
 700
 701                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 702                         if (host->cmd) {
 703                                 dev_err(mmc_dev(host->mmc),
 704                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 705                                         cmd, host->cmd->arg);
 706                                 host->cmd->error = -EILSEQ;
 707                                 end_command = 1;
 708                                 cmd_error = 1;
 709                         } else
 710                                 dev_err(mmc_dev(host->mmc),
 711                                         "command CRC error without cmd?\n");
 712                 }
 713
 714                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 715                         dev_dbg(mmc_dev(host->mmc),
 716                                 "ignoring card status error (CMD%d)\n",
 717                                 cmd);
 718                         end_command = 1;
 719                 }
 720
 721                 /*
 722                  * NOTE: On 1610 the END_OF_CMD may come too early when
 723                  * starting a write
 724                  */
 725                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 726                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 727                         end_command = 1;
 728                 }
 729         }
 730
 731         if (end_command)
 732                 mmc_omap_cmd_done(host, host->cmd);
 733         if (host->data != NULL) {
 734                 if (transfer_error)
 735                         mmc_omap_xfer_done(host, host->data);
 736                 else if (end_transfer)
 737                         mmc_omap_end_of_data(host, host->data);
 738         }
 739
 740         return IRQ_HANDLED;
 741 }
 742
 743 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
 744 {
 745         int cover_open;
 746         struct mmc_omap_host *host = dev_get_drvdata(dev);
 747         struct mmc_omap_slot *slot = host->slots[num];
 748
 749         BUG_ON(num >= host->nr_slots);
 750
 751         /* Other subsystems can call in here before we're initialised. */
 752         if (host->nr_slots == 0 || !host->slots[num])
 753                 return;
 754
 755         cover_open = mmc_omap_cover_is_open(slot);
 756         if (cover_open != slot->cover_open) {
 757                 slot->cover_open = cover_open;
 758                 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
 759         }
 760
 761         tasklet_hi_schedule(&slot->cover_tasklet);
 762 }
 763
 764 static void mmc_omap_cover_timer(unsigned long arg)
 765 {
 766         struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
 767         tasklet_schedule(&slot->cover_tasklet);
 768 }
 769
 770 static void mmc_omap_cover_handler(unsigned long param)
 771 {
 772         struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
 773         int cover_open = mmc_omap_cover_is_open(slot);
 774
 775         mmc_detect_change(slot->mmc, 0);
 776         if (!cover_open)
 777                 return;
 778
 779         /*
 780          * If no card is inserted, we postpone polling until
 781          * the cover has been closed.
 782          */
 783         if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
 784                 return;
 785
 786         mod_timer(&slot->cover_timer,
 787                   jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
 788 }
 789
 790 /* Prepare to transfer the next segment of a scatterlist */
 791 static void
 792 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
 793 {
 794         int dma_ch = host->dma_ch;
 795         unsigned long data_addr;
 796         u16 buf, frame;
 797         u32 count;
 798         struct scatterlist *sg = &data->sg[host->sg_idx];
 799         int src_port = 0;
 800         int dst_port = 0;
 801         int sync_dev = 0;
 802
 803         data_addr = host->phys_base + OMAP_MMC_REG_DATA;
 804         frame = data->blksz;
 805         count = sg_dma_len(sg);
 806
 807         if ((data->blocks == 1) && (count > data->blksz))
 808                 count = frame;
 809
 810         host->dma_len = count;
 811
 812         /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
 813          * Use 16 or 32 word frames when the blocksize is at least that large.
 814          * Blocksize is usually 512 bytes; but not for some SD reads.
 815          */
 816         if (cpu_is_omap15xx() && frame > 32)
 817                 frame = 32;
 818         else if (frame > 64)
 819                 frame = 64;
 820         count /= frame;
 821         frame >>= 1;
 822
 823         if (!(data->flags & MMC_DATA_WRITE)) {
 824                 buf = 0x800f | ((frame - 1) << 8);
 825
 826                 if (cpu_class_is_omap1()) {
 827                         src_port = OMAP_DMA_PORT_TIPB;
 828                         dst_port = OMAP_DMA_PORT_EMIFF;
 829                 }
 830                 if (cpu_is_omap24xx())
 831                         sync_dev = OMAP24XX_DMA_MMC1_RX;
 832
 833                 omap_set_dma_src_params(dma_ch, src_port,
 834                                         OMAP_DMA_AMODE_CONSTANT,
 835                                         data_addr, 0, 0);
 836                 omap_set_dma_dest_params(dma_ch, dst_port,
 837                                          OMAP_DMA_AMODE_POST_INC,
 838                                          sg_dma_address(sg), 0, 0);
 839                 omap_set_dma_dest_data_pack(dma_ch, 1);
 840                 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 841         } else {
 842                 buf = 0x0f80 | ((frame - 1) << 0);
 843
 844                 if (cpu_class_is_omap1()) {
 845                         src_port = OMAP_DMA_PORT_EMIFF;
 846                         dst_port = OMAP_DMA_PORT_TIPB;
 847                 }
 848                 if (cpu_is_omap24xx())
 849                         sync_dev = OMAP24XX_DMA_MMC1_TX;
 850
 851                 omap_set_dma_dest_params(dma_ch, dst_port,
 852                                          OMAP_DMA_AMODE_CONSTANT,
 853                                          data_addr, 0, 0);
 854                 omap_set_dma_src_params(dma_ch, src_port,
 855                                         OMAP_DMA_AMODE_POST_INC,
 856                                         sg_dma_address(sg), 0, 0);
 857                 omap_set_dma_src_data_pack(dma_ch, 1);
 858                 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
 859         }
 860
 861         /* Max limit for DMA frame count is 0xffff */
 862         BUG_ON(count > 0xffff);
 863
 864         OMAP_MMC_WRITE(host, BUF, buf);
 865         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
 866                                      frame, count, OMAP_DMA_SYNC_FRAME,
 867                                      sync_dev, 0);
 868 }
 869
 870 /* A scatterlist segment completed */
 871 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
 872 {
 873         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 874         struct mmc_data *mmcdat = host->data;
 875
 876         if (unlikely(host->dma_ch < 0)) {
 877                 dev_err(mmc_dev(host->mmc),
 878                         "DMA callback while DMA not enabled\n");
 879                 return;
 880         }
 881         /* FIXME: We really should do something to _handle_ the errors */
 882         if (ch_status & OMAP1_DMA_TOUT_IRQ) {
 883                 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
 884                 return;
 885         }
 886         if (ch_status & OMAP_DMA_DROP_IRQ) {
 887                 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
 888                 return;
 889         }
 890         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
 891                 return;
 892         }
 893         mmcdat->bytes_xfered += host->dma_len;
 894         host->sg_idx++;
 895         if (host->sg_idx < host->sg_len) {
 896                 mmc_omap_prepare_dma(host, host->data);
 897                 omap_start_dma(host->dma_ch);
 898         } else
 899                 mmc_omap_dma_done(host, host->data);
 900 }
 901
 902 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
 903 {
 904         const char *dev_name;
 905         int sync_dev, dma_ch, is_read, r;
 906
 907         is_read = !(data->flags & MMC_DATA_WRITE);
 908         del_timer_sync(&host->dma_timer);
 909         if (host->dma_ch >= 0) {
 910                 if (is_read == host->dma_is_read)
 911                         return 0;
 912                 omap_free_dma(host->dma_ch);
 913                 host->dma_ch = -1;
 914         }
 915
 916         if (is_read) {
 917                 if (host->id == 1) {
 918                         sync_dev = OMAP_DMA_MMC_RX;
 919                         dev_name = "MMC1 read";
 920                 } else {
 921                         sync_dev = OMAP_DMA_MMC2_RX;
 922                         dev_name = "MMC2 read";
 923                 }
 924         } else {
 925                 if (host->id == 1) {
 926                         sync_dev = OMAP_DMA_MMC_TX;
 927                         dev_name = "MMC1 write";
 928                 } else {
 929                         sync_dev = OMAP_DMA_MMC2_TX;
 930                         dev_name = "MMC2 write";
 931                 }
 932         }
 933         r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
 934                              host, &dma_ch);
 935         if (r != 0) {
 936                 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
 937                 return r;
 938         }
 939         host->dma_ch = dma_ch;
 940         host->dma_is_read = is_read;
 941
 942         return 0;
 943 }
 944
 945 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 946 {
 947         u16 reg;
 948
 949         reg = OMAP_MMC_READ(host, SDIO);
 950         reg &= ~(1 << 5);
 951         OMAP_MMC_WRITE(host, SDIO, reg);
 952         /* Set maximum timeout */
 953         OMAP_MMC_WRITE(host, CTO, 0xff);
 954 }
 955
 956 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 957 {
 958         unsigned int timeout, cycle_ns;
 959         u16 reg;
 960
 961         cycle_ns = 1000000000 / host->current_slot->fclk_freq;
 962         timeout = req->data->timeout_ns / cycle_ns;
 963         timeout += req->data->timeout_clks;
 964
 965         /* Check if we need to use timeout multiplier register */
 966         reg = OMAP_MMC_READ(host, SDIO);
 967         if (timeout > 0xffff) {
 968                 reg |= (1 << 5);
 969                 timeout /= 1024;
 970         } else
 971                 reg &= ~(1 << 5);
 972         OMAP_MMC_WRITE(host, SDIO, reg);
 973         OMAP_MMC_WRITE(host, DTO, timeout);
 974 }
 975
 976 static void
 977 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 978 {
 979         struct mmc_data *data = req->data;
 980         int i, use_dma, block_size;
 981         unsigned sg_len;
 982
 983         host->data = data;
 984         if (data == NULL) {
 985                 OMAP_MMC_WRITE(host, BLEN, 0);
 986                 OMAP_MMC_WRITE(host, NBLK, 0);
 987                 OMAP_MMC_WRITE(host, BUF, 0);
 988                 host->dma_in_use = 0;
 989                 set_cmd_timeout(host, req);
 990                 return;
 991         }
 992
 993         block_size = data->blksz;
 994
 995         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 996         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 997         set_data_timeout(host, req);
 998
 999         /* cope with calling layer confusion; it issues "single
1000          * block" writes using multi-block scatterlists.
1001          */
1002         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
1003
1004         /* Only do DMA for entire blocks */
1005         use_dma = host->use_dma;
1006         if (use_dma) {
1007                 for (i = 0; i < sg_len; i++) {
1008                         if ((data->sg[i].length % block_size) != 0) {
1009                                 use_dma = 0;
1010                                 break;
1011                         }
1012                 }
1013         }
1014
1015         host->sg_idx = 0;
1016         if (use_dma) {
1017                 if (mmc_omap_get_dma_channel(host, data) == 0) {
1018                         enum dma_data_direction dma_data_dir;
1019
1020                         if (data->flags & MMC_DATA_WRITE)
1021                                 dma_data_dir = DMA_TO_DEVICE;
1022                         else
1023                                 dma_data_dir = DMA_FROM_DEVICE;
1024
1025                         host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1026                                                 sg_len, dma_data_dir);
1027                         host->total_bytes_left = 0;
1028                         mmc_omap_prepare_dma(host, req->data);
1029                         host->brs_received = 0;
1030                         host->dma_done = 0;
1031                         host->dma_in_use = 1;
1032                 } else
1033                         use_dma = 0;
1034         }
1035
1036         /* Revert to PIO? */
1037         if (!use_dma) {
1038                 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1039                 host->total_bytes_left = data->blocks * block_size;
1040                 host->sg_len = sg_len;
1041                 mmc_omap_sg_to_buf(host);
1042                 host->dma_in_use = 0;
1043         }
1044 }
1045
1046 static void mmc_omap_start_request(struct mmc_omap_host *host,
1047                                    struct mmc_request *req)
1048 {
1049         BUG_ON(host->mrq != NULL);
1050
1051         host->mrq = req;
1052
1053         /* only touch fifo AFTER the controller readies it */
1054         mmc_omap_prepare_data(host, req);
1055         mmc_omap_start_command(host, req->cmd);
1056         if (host->dma_in_use)
1057                 omap_start_dma(host->dma_ch);
1058         BUG_ON(irqs_disabled());
1059 }
1060
1061 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1062 {
1063         struct mmc_omap_slot *slot = mmc_priv(mmc);
1064         struct mmc_omap_host *host = slot->host;
1065         unsigned long flags;
1066
1067         spin_lock_irqsave(&host->slot_lock, flags);
1068         if (host->mmc != NULL) {
1069                 BUG_ON(slot->mrq != NULL);
1070                 slot->mrq = req;
1071                 spin_unlock_irqrestore(&host->slot_lock, flags);
1072                 return;
1073         } else
1074                 host->mmc = mmc;
1075         spin_unlock_irqrestore(&host->slot_lock, flags);
1076         mmc_omap_select_slot(slot, 1);
1077         mmc_omap_start_request(host, req);
1078 }
1079
1080 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1081                                 int vdd)
1082 {
1083         struct mmc_omap_host *host;
1084
1085         host = slot->host;
1086
1087         if (slot->pdata->set_power != NULL)
1088                 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1089                                         vdd);
1090
1091         if (cpu_is_omap24xx()) {
1092                 u16 w;
1093
1094                 if (power_on) {
1095                         w = OMAP_MMC_READ(host, CON);
1096                         OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1097                 } else {
1098                         w = OMAP_MMC_READ(host, CON);
1099                         OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1100                 }
1101         }
1102 }
1103
1104 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1105 {
1106         struct mmc_omap_slot *slot = mmc_priv(mmc);
1107         struct mmc_omap_host *host = slot->host;
1108         int func_clk_rate = clk_get_rate(host->fclk);
1109         int dsor;
1110
1111         if (ios->clock == 0)
1112                 return 0;
1113
1114         dsor = func_clk_rate / ios->clock;
1115         if (dsor < 1)
1116                 dsor = 1;
1117
1118         if (func_clk_rate / dsor > ios->clock)
1119                 dsor++;
1120
1121         if (dsor > 250)
1122                 dsor = 250;
1123
1124         slot->fclk_freq = func_clk_rate / dsor;
1125
1126         if (ios->bus_width == MMC_BUS_WIDTH_4)
1127                 dsor |= 1 << 15;
1128
1129         return dsor;
1130 }
1131
1132 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1133 {
1134         struct mmc_omap_slot *slot = mmc_priv(mmc);
1135         struct mmc_omap_host *host = slot->host;
1136         int i, dsor;
1137
1138         dsor = mmc_omap_calc_divisor(mmc, ios);
1139
1140         mmc_omap_select_slot(slot, 0);
1141
1142         if (ios->vdd != slot->vdd)
1143                 slot->vdd = ios->vdd;
1144
1145         switch (ios->power_mode) {
1146         case MMC_POWER_OFF:
1147                 mmc_omap_set_power(slot, 0, ios->vdd);
1148                 break;
1149         case MMC_POWER_UP:
1150                 /* Cannot touch dsor yet, just power up MMC */
1151                 mmc_omap_set_power(slot, 1, ios->vdd);
1152                 goto exit;
1153         case MMC_POWER_ON:
1154                 dsor |= 1 << 11;
1155                 break;
1156         }
1157
1158         if (slot->bus_mode != ios->bus_mode) {
1159                 if (slot->pdata->set_bus_mode != NULL)
1160                         slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1161                                                   ios->bus_mode);
1162                 slot->bus_mode = ios->bus_mode;
1163         }
1164
1165         /* On insanely high arm_per frequencies something sometimes
1166          * goes somehow out of sync, and the POW bit is not being set,
1167          * which results in the while loop below getting stuck.
1168          * Writing to the CON register twice seems to do the trick. */
1169         for (i = 0; i < 2; i++)
1170                 OMAP_MMC_WRITE(host, CON, dsor);
1171         slot->saved_con = dsor;
1172         if (ios->power_mode == MMC_POWER_ON) {
1173                 /* Send clock cycles, poll completion */
1174                 OMAP_MMC_WRITE(host, IE, 0);
1175                 OMAP_MMC_WRITE(host, STAT, 0xffff);
1176                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1177                 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
1178                 OMAP_MMC_WRITE(host, STAT, 1);
1179         }
1180
1181 exit:
1182         mmc_omap_release_slot(slot);
1183 }
1184
1185 static const struct mmc_host_ops mmc_omap_ops = {
1186         .request        = mmc_omap_request,
1187         .set_ios        = mmc_omap_set_ios,
1188 };
1189
1190 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1191 {
1192         struct mmc_omap_slot *slot = NULL;
1193         struct mmc_host *mmc;
1194         int r;
1195
1196         mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1197         if (mmc == NULL)
1198                 return -ENOMEM;
1199
1200         slot = mmc_priv(mmc);
1201         slot->host = host;
1202         slot->mmc = mmc;
1203         slot->id = id;
1204         slot->pdata = &host->pdata->slots[id];
1205
1206         host->slots[id] = slot;
1207
1208         mmc->caps = MMC_CAP_MULTIWRITE;
1209         if (host->pdata->conf.wire4)
1210                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1211
1212         mmc->ops = &mmc_omap_ops;
1213         mmc->f_min = 400000;
1214
1215         if (cpu_class_is_omap2())
1216                 mmc->f_max = 48000000;
1217         else
1218                 mmc->f_max = 24000000;
1219         if (host->pdata->max_freq)
1220                 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1221         mmc->ocr_avail = slot->pdata->ocr_mask;
1222
1223         /* Use scatterlist DMA to reduce per-transfer costs.
1224          * NOTE max_seg_size assumption that small blocks aren't
1225          * normally used (except e.g. for reading SD registers).
1226          */
1227         mmc->max_phys_segs = 32;
1228         mmc->max_hw_segs = 32;
1229         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1230         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1231         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1232         mmc->max_seg_size = mmc->max_req_size;
1233
1234         r = mmc_add_host(mmc);
1235         if (r < 0)
1236                 goto err_remove_host;
1237
1238         if (slot->pdata->name != NULL) {
1239                 r = device_create_file(&mmc->class_dev,
1240                                         &dev_attr_slot_name);
1241                 if (r < 0)
1242                         goto err_remove_host;
1243         }
1244
1245         if (slot->pdata->get_cover_state != NULL) {
1246                 r = device_create_file(&mmc->class_dev,
1247                                         &dev_attr_cover_switch);
1248                 if (r < 0)
1249                         goto err_remove_slot_name;
1250
1251                 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1252                             (unsigned long)slot);
1253                 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1254                              (unsigned long)slot);
1255                 tasklet_schedule(&slot->cover_tasklet);
1256         }
1257
1258         return 0;
1259
1260 err_remove_slot_name:
1261         if (slot->pdata->name != NULL)
1262                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1263 err_remove_host:
1264         mmc_remove_host(mmc);
1265         mmc_free_host(mmc);
1266         return r;
1267 }
1268
1269 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1270 {
1271         struct mmc_host *mmc = slot->mmc;
1272
1273         if (slot->pdata->name != NULL)
1274                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1275         if (slot->pdata->get_cover_state != NULL)
1276                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1277
1278         tasklet_kill(&slot->cover_tasklet);
1279         del_timer_sync(&slot->cover_timer);
1280         flush_scheduled_work();
1281
1282         mmc_remove_host(mmc);
1283         mmc_free_host(mmc);
1284 }
1285
1286 static int __init mmc_omap_probe(struct platform_device *pdev)
1287 {
1288         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1289         struct mmc_omap_host *host = NULL;
1290         struct resource *res;
1291         int i, ret = 0;
1292         int irq;
1293
1294         if (pdata == NULL) {
1295                 dev_err(&pdev->dev, "platform data missing\n");
1296                 return -ENXIO;
1297         }
1298         if (pdata->nr_slots == 0) {
1299                 dev_err(&pdev->dev, "no slots\n");
1300                 return -ENXIO;
1301         }
1302
1303         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1304         irq = platform_get_irq(pdev, 0);
1305         if (res == NULL || irq < 0)
1306                 return -ENXIO;
1307
1308         res = request_mem_region(res->start, res->end - res->start + 1,
1309                                  pdev->name);
1310         if (res == NULL)
1311                 return -EBUSY;
1312
1313         host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1314         if (host == NULL) {
1315                 ret = -ENOMEM;
1316                 goto err_free_mem_region;
1317         }
1318
1319         INIT_WORK(&host->cmd_abort, mmc_omap_abort_command);
1320         setup_timer(&host->cmd_timer, mmc_omap_cmd_timer, (unsigned long) host);
1321
1322         spin_lock_init(&host->dma_lock);
1323         setup_timer(&host->dma_timer, mmc_omap_dma_timer, (unsigned long) host);
1324         spin_lock_init(&host->slot_lock);
1325         init_waitqueue_head(&host->slot_wq);
1326
1327         host->pdata = pdata;
1328         host->dev = &pdev->dev;
1329         platform_set_drvdata(pdev, host);
1330
1331         host->id = pdev->id;
1332         host->mem_res = res;
1333         host->irq = irq;
1334
1335         host->use_dma = 1;
1336         host->dma_ch = -1;
1337
1338         host->irq = irq;
1339         host->phys_base = host->mem_res->start;
1340         host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1341
1342         if (cpu_is_omap24xx()) {
1343                 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1344                 if (IS_ERR(host->iclk))
1345                         goto err_free_mmc_host;
1346                 clk_enable(host->iclk);
1347         }
1348
1349         if (!cpu_is_omap24xx())
1350                 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1351         else
1352                 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1353
1354         if (IS_ERR(host->fclk)) {
1355                 ret = PTR_ERR(host->fclk);
1356                 goto err_free_iclk;
1357         }
1358
1359         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1360         if (ret)
1361                 goto err_free_fclk;
1362
1363         if (pdata->init != NULL) {
1364                 ret = pdata->init(&pdev->dev);
1365                 if (ret < 0)
1366                         goto err_free_irq;
1367         }
1368
1369         host->nr_slots = pdata->nr_slots;
1370         for (i = 0; i < pdata->nr_slots; i++) {
1371                 ret = mmc_omap_new_slot(host, i);
1372                 if (ret < 0) {
1373                         while (--i >= 0)
1374                                 mmc_omap_remove_slot(host->slots[i]);
1375
1376                         goto err_plat_cleanup;
1377                 }
1378         }
1379
1380         return 0;
1381
1382 err_plat_cleanup:
1383         if (pdata->cleanup)
1384                 pdata->cleanup(&pdev->dev);
1385 err_free_irq:
1386         free_irq(host->irq, host);
1387 err_free_fclk:
1388         clk_put(host->fclk);
1389 err_free_iclk:
1390         if (host->iclk != NULL) {
1391                 clk_disable(host->iclk);
1392                 clk_put(host->iclk);
1393         }
1394 err_free_mmc_host:
1395         kfree(host);
1396 err_free_mem_region:
1397         release_mem_region(res->start, res->end - res->start + 1);
1398         return ret;
1399 }
1400
1401 static int mmc_omap_remove(struct platform_device *pdev)
1402 {
1403         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1404         int i;
1405
1406         platform_set_drvdata(pdev, NULL);
1407
1408         BUG_ON(host == NULL);
1409
1410         for (i = 0; i < host->nr_slots; i++)
1411                 mmc_omap_remove_slot(host->slots[i]);
1412
1413         if (host->pdata->cleanup)
1414                 host->pdata->cleanup(&pdev->dev);
1415
1416         if (host->iclk && !IS_ERR(host->iclk))
1417                 clk_put(host->iclk);
1418         if (host->fclk && !IS_ERR(host->fclk))
1419                 clk_put(host->fclk);
1420
1421         release_mem_region(pdev->resource[0].start,
1422                            pdev->resource[0].end - pdev->resource[0].start + 1);
1423
1424         kfree(host);
1425
1426         return 0;
1427 }
1428
1429 #ifdef CONFIG_PM
1430 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1431 {
1432         int i, ret = 0;
1433         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1434
1435         if (host == NULL || host->suspended)
1436                 return 0;
1437
1438         for (i = 0; i < host->nr_slots; i++) {
1439                 struct mmc_omap_slot *slot;
1440
1441                 slot = host->slots[i];
1442                 ret = mmc_suspend_host(slot->mmc, mesg);
1443                 if (ret < 0) {
1444                         while (--i >= 0) {
1445                                 slot = host->slots[i];
1446                                 mmc_resume_host(slot->mmc);
1447                         }
1448                         return ret;
1449                 }
1450         }
1451         host->suspended = 1;
1452         return 0;
1453 }
1454
1455 static int mmc_omap_resume(struct platform_device *pdev)
1456 {
1457         int i, ret = 0;
1458         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1459
1460         if (host == NULL || !host->suspended)
1461                 return 0;
1462
1463         for (i = 0; i < host->nr_slots; i++) {
1464                 struct mmc_omap_slot *slot;
1465                 slot = host->slots[i];
1466                 ret = mmc_resume_host(slot->mmc);
1467                 if (ret < 0)
1468                         return ret;
1469
1470                 host->suspended = 0;
1471         }
1472         return 0;
1473 }
1474 #else
1475 #define mmc_omap_suspend        NULL
1476 #define mmc_omap_resume         NULL
1477 #endif
1478
1479 static struct platform_driver mmc_omap_driver = {
1480         .probe          = mmc_omap_probe,
1481         .remove         = mmc_omap_remove,
1482         .suspend        = mmc_omap_suspend,
1483         .resume         = mmc_omap_resume,
1484         .driver         = {
1485                 .name   = DRIVER_NAME,
1486                 .owner  = THIS_MODULE,
1487         },
1488 };
1489
1490 static int __init mmc_omap_init(void)
1491 {
1492         return platform_driver_register(&mmc_omap_driver);
1493 }
1494
1495 static void __exit mmc_omap_exit(void)
1496 {
1497         platform_driver_unregister(&mmc_omap_driver);
1498 }
1499
1500 module_init(mmc_omap_init);
1501 module_exit(mmc_omap_exit);
1502
1503 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1504 MODULE_LICENSE("GPL");
1505 MODULE_ALIAS("platform:" DRIVER_NAME);
1506 MODULE_AUTHOR("Juha Yrjölä");