2 * linux/drivers/mmc/host/omap.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/delay.h>
22 #include <linux/spinlock.h>
23 #include <linux/timer.h>
24 #include <linux/mmc/host.h>
25 #include <linux/mmc/card.h>
26 #include <linux/clk.h>
27 #include <linux/scatterlist.h>
28 #include <linux/i2c/tps65010.h>
32 #include <asm/mach-types.h>
34 #include <asm/arch/board.h>
35 #include <asm/arch/gpio.h>
36 #include <asm/arch/dma.h>
37 #include <asm/arch/mux.h>
38 #include <asm/arch/fpga.h>
40 #define OMAP_MMC_REG_CMD 0x00
41 #define OMAP_MMC_REG_ARGL 0x04
42 #define OMAP_MMC_REG_ARGH 0x08
43 #define OMAP_MMC_REG_CON 0x0c
44 #define OMAP_MMC_REG_STAT 0x10
45 #define OMAP_MMC_REG_IE 0x14
46 #define OMAP_MMC_REG_CTO 0x18
47 #define OMAP_MMC_REG_DTO 0x1c
48 #define OMAP_MMC_REG_DATA 0x20
49 #define OMAP_MMC_REG_BLEN 0x24
50 #define OMAP_MMC_REG_NBLK 0x28
51 #define OMAP_MMC_REG_BUF 0x2c
52 #define OMAP_MMC_REG_SDIO 0x34
53 #define OMAP_MMC_REG_REV 0x3c
54 #define OMAP_MMC_REG_RSP0 0x40
55 #define OMAP_MMC_REG_RSP1 0x44
56 #define OMAP_MMC_REG_RSP2 0x48
57 #define OMAP_MMC_REG_RSP3 0x4c
58 #define OMAP_MMC_REG_RSP4 0x50
59 #define OMAP_MMC_REG_RSP5 0x54
60 #define OMAP_MMC_REG_RSP6 0x58
61 #define OMAP_MMC_REG_RSP7 0x5c
62 #define OMAP_MMC_REG_IOSR 0x60
63 #define OMAP_MMC_REG_SYSC 0x64
64 #define OMAP_MMC_REG_SYSS 0x68
66 #define OMAP_MMC_STAT_CARD_ERR (1 << 14)
67 #define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
68 #define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
69 #define OMAP_MMC_STAT_A_EMPTY (1 << 11)
70 #define OMAP_MMC_STAT_A_FULL (1 << 10)
71 #define OMAP_MMC_STAT_CMD_CRC (1 << 8)
72 #define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
73 #define OMAP_MMC_STAT_DATA_CRC (1 << 6)
74 #define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
75 #define OMAP_MMC_STAT_END_BUSY (1 << 4)
76 #define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
77 #define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
78 #define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
80 #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
81 #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
86 #define OMAP_MMC_CMDTYPE_BC 0
87 #define OMAP_MMC_CMDTYPE_BCR 1
88 #define OMAP_MMC_CMDTYPE_AC 2
89 #define OMAP_MMC_CMDTYPE_ADTC 3
92 #define DRIVER_NAME "mmci-omap"
94 /* Specifies how often in millisecs to poll for card status changes
95 * when the cover switch is open */
96 #define OMAP_MMC_SWITCH_POLL_DELAY 500
98 static int mmc_omap_enable_poll = 1;
100 struct mmc_omap_host {
103 struct mmc_request * mrq;
104 struct mmc_command * cmd;
105 struct mmc_data * data;
106 struct mmc_host * mmc;
108 unsigned char id; /* 16xx chips have 2 MMC blocks */
111 struct resource *mem_res;
112 void __iomem *virt_base;
113 unsigned int phys_base;
115 unsigned char bus_mode;
116 unsigned char hw_bus_mode;
121 u32 buffer_bytes_left;
122 u32 total_bytes_left;
125 unsigned brs_received:1, dma_done:1;
126 unsigned dma_is_read:1;
127 unsigned dma_in_use:1;
130 struct timer_list dma_timer;
137 struct work_struct switch_work;
138 struct timer_list switch_timer;
139 int switch_last_state;
143 mmc_omap_cover_is_open(struct mmc_omap_host *host)
145 if (host->switch_pin < 0)
147 return omap_get_gpio_datain(host->switch_pin);
151 mmc_omap_show_cover_switch(struct device *dev,
152 struct device_attribute *attr, char *buf)
154 struct mmc_omap_host *host = dev_get_drvdata(dev);
156 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(host) ? "open" :
160 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
163 mmc_omap_show_enable_poll(struct device *dev,
164 struct device_attribute *attr, char *buf)
166 return snprintf(buf, PAGE_SIZE, "%d\n", mmc_omap_enable_poll);
170 mmc_omap_store_enable_poll(struct device *dev,
171 struct device_attribute *attr, const char *buf,
176 if (sscanf(buf, "%10d", &enable_poll) != 1)
179 if (enable_poll != mmc_omap_enable_poll) {
180 struct mmc_omap_host *host = dev_get_drvdata(dev);
182 mmc_omap_enable_poll = enable_poll;
183 if (enable_poll && host->switch_pin >= 0)
184 schedule_work(&host->switch_work);
189 static DEVICE_ATTR(enable_poll, 0664,
190 mmc_omap_show_enable_poll, mmc_omap_store_enable_poll);
193 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
204 /* Our hardware needs to know exact type */
205 switch (mmc_resp_type(cmd)) {
210 /* resp 1, 1b, 6, 7 */
220 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
224 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
225 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
226 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
227 cmdtype = OMAP_MMC_CMDTYPE_BC;
228 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
229 cmdtype = OMAP_MMC_CMDTYPE_BCR;
231 cmdtype = OMAP_MMC_CMDTYPE_AC;
234 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
236 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
239 if (cmd->flags & MMC_RSP_BUSY)
242 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
245 clk_enable(host->fclk);
247 OMAP_MMC_WRITE(host, CTO, 200);
248 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
249 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
250 OMAP_MMC_WRITE(host, IE,
251 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
252 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
253 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
254 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
255 OMAP_MMC_STAT_END_OF_DATA);
256 OMAP_MMC_WRITE(host, CMD, cmdreg);
260 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
262 if (host->dma_in_use) {
263 enum dma_data_direction dma_data_dir;
265 BUG_ON(host->dma_ch < 0);
267 omap_stop_dma(host->dma_ch);
268 /* Release DMA channel lazily */
269 mod_timer(&host->dma_timer, jiffies + HZ);
270 if (data->flags & MMC_DATA_WRITE)
271 dma_data_dir = DMA_TO_DEVICE;
273 dma_data_dir = DMA_FROM_DEVICE;
274 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
279 clk_disable(host->fclk);
281 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
282 * dozens of requests until the card finishes writing data.
283 * It'd be cheaper to just wait till an EOFB interrupt arrives...
288 mmc_request_done(host->mmc, data->mrq);
292 mmc_omap_start_command(host, data->stop);
296 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
301 if (!host->dma_in_use) {
302 mmc_omap_xfer_done(host, data);
306 spin_lock_irqsave(&host->dma_lock, flags);
310 host->brs_received = 1;
311 spin_unlock_irqrestore(&host->dma_lock, flags);
313 mmc_omap_xfer_done(host, data);
317 mmc_omap_dma_timer(unsigned long data)
319 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
321 BUG_ON(host->dma_ch < 0);
322 omap_free_dma(host->dma_ch);
327 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
333 spin_lock_irqsave(&host->dma_lock, flags);
334 if (host->brs_received)
338 spin_unlock_irqrestore(&host->dma_lock, flags);
340 mmc_omap_xfer_done(host, data);
344 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
348 if (cmd->flags & MMC_RSP_PRESENT) {
349 if (cmd->flags & MMC_RSP_136) {
350 /* response type 2 */
352 OMAP_MMC_READ(host, RSP0) |
353 (OMAP_MMC_READ(host, RSP1) << 16);
355 OMAP_MMC_READ(host, RSP2) |
356 (OMAP_MMC_READ(host, RSP3) << 16);
358 OMAP_MMC_READ(host, RSP4) |
359 (OMAP_MMC_READ(host, RSP5) << 16);
361 OMAP_MMC_READ(host, RSP6) |
362 (OMAP_MMC_READ(host, RSP7) << 16);
364 /* response types 1, 1b, 3, 4, 5, 6 */
366 OMAP_MMC_READ(host, RSP6) |
367 (OMAP_MMC_READ(host, RSP7) << 16);
371 if (host->data == NULL || cmd->error) {
373 clk_disable(host->fclk);
374 mmc_request_done(host->mmc, cmd->mrq);
380 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
382 struct scatterlist *sg;
384 sg = host->data->sg + host->sg_idx;
385 host->buffer_bytes_left = sg->length;
386 host->buffer = sg_virt(sg);
387 if (host->buffer_bytes_left > host->total_bytes_left)
388 host->buffer_bytes_left = host->total_bytes_left;
393 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
397 if (host->buffer_bytes_left == 0) {
399 BUG_ON(host->sg_idx == host->sg_len);
400 mmc_omap_sg_to_buf(host);
403 if (n > host->buffer_bytes_left)
404 n = host->buffer_bytes_left;
405 host->buffer_bytes_left -= n;
406 host->total_bytes_left -= n;
407 host->data->bytes_xfered += n;
410 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
412 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
416 static inline void mmc_omap_report_irq(u16 status)
418 static const char *mmc_omap_status_bits[] = {
419 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
420 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
424 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
425 if (status & (1 << i)) {
428 printk("%s", mmc_omap_status_bits[i]);
433 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
435 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
441 if (host->cmd == NULL && host->data == NULL) {
442 status = OMAP_MMC_READ(host, STAT);
443 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
445 OMAP_MMC_WRITE(host, STAT, status);
446 OMAP_MMC_WRITE(host, IE, 0);
455 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
456 OMAP_MMC_WRITE(host, STAT, status);
457 #ifdef CONFIG_MMC_DEBUG
458 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
459 status, host->cmd != NULL ? host->cmd->opcode : -1);
460 mmc_omap_report_irq(status);
463 if (host->total_bytes_left) {
464 if ((status & OMAP_MMC_STAT_A_FULL) ||
465 (status & OMAP_MMC_STAT_END_OF_DATA))
466 mmc_omap_xfer_data(host, 0);
467 if (status & OMAP_MMC_STAT_A_EMPTY)
468 mmc_omap_xfer_data(host, 1);
471 if (status & OMAP_MMC_STAT_END_OF_DATA) {
475 if (status & OMAP_MMC_STAT_DATA_TOUT) {
476 dev_dbg(mmc_dev(host->mmc), "data timeout\n");
478 host->data->error = -ETIMEDOUT;
483 if (status & OMAP_MMC_STAT_DATA_CRC) {
485 host->data->error = -EILSEQ;
486 dev_dbg(mmc_dev(host->mmc),
487 "data CRC error, bytes left %d\n",
488 host->total_bytes_left);
491 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
495 if (status & OMAP_MMC_STAT_CMD_TOUT) {
496 /* Timeouts are routine with some commands */
498 if (!mmc_omap_cover_is_open(host))
499 dev_err(mmc_dev(host->mmc),
500 "command timeout, CMD %d\n",
502 host->cmd->error = -ETIMEDOUT;
507 if (status & OMAP_MMC_STAT_CMD_CRC) {
509 dev_err(mmc_dev(host->mmc),
510 "command CRC error (CMD%d, arg 0x%08x)\n",
511 host->cmd->opcode, host->cmd->arg);
512 host->cmd->error = -EILSEQ;
515 dev_err(mmc_dev(host->mmc),
516 "command CRC error without cmd?\n");
519 if (status & OMAP_MMC_STAT_CARD_ERR) {
520 dev_dbg(mmc_dev(host->mmc),
521 "ignoring card status error (CMD%d)\n",
527 * NOTE: On 1610 the END_OF_CMD may come too early when
530 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
531 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
537 mmc_omap_cmd_done(host, host->cmd);
540 mmc_omap_xfer_done(host, host->data);
541 else if (end_transfer)
542 mmc_omap_end_of_data(host, host->data);
547 static irqreturn_t mmc_omap_switch_irq(int irq, void *dev_id)
549 struct mmc_omap_host *host = (struct mmc_omap_host *) dev_id;
551 schedule_work(&host->switch_work);
556 static void mmc_omap_switch_timer(unsigned long arg)
558 struct mmc_omap_host *host = (struct mmc_omap_host *) arg;
560 schedule_work(&host->switch_work);
563 static void mmc_omap_switch_handler(struct work_struct *work)
565 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, switch_work);
566 struct mmc_card *card;
567 static int complained = 0;
568 int cards = 0, cover_open;
570 if (host->switch_pin == -1)
572 cover_open = mmc_omap_cover_is_open(host);
573 if (cover_open != host->switch_last_state) {
574 kobject_uevent(&host->dev->kobj, KOBJ_CHANGE);
575 host->switch_last_state = cover_open;
577 mmc_detect_change(host->mmc, 0);
578 list_for_each_entry(card, &host->mmc->cards, node) {
579 if (mmc_card_present(card))
582 if (mmc_omap_cover_is_open(host)) {
584 dev_info(mmc_dev(host->mmc), "cover is open\n");
587 if (mmc_omap_enable_poll)
588 mod_timer(&host->switch_timer, jiffies +
589 msecs_to_jiffies(OMAP_MMC_SWITCH_POLL_DELAY));
595 /* Prepare to transfer the next segment of a scatterlist */
597 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
599 int dma_ch = host->dma_ch;
600 unsigned long data_addr;
603 struct scatterlist *sg = &data->sg[host->sg_idx];
608 data_addr = host->phys_base + OMAP_MMC_REG_DATA;
610 count = sg_dma_len(sg);
612 if ((data->blocks == 1) && (count > data->blksz))
615 host->dma_len = count;
617 /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
618 * Use 16 or 32 word frames when the blocksize is at least that large.
619 * Blocksize is usually 512 bytes; but not for some SD reads.
621 if (cpu_is_omap15xx() && frame > 32)
628 if (!(data->flags & MMC_DATA_WRITE)) {
629 buf = 0x800f | ((frame - 1) << 8);
631 if (cpu_class_is_omap1()) {
632 src_port = OMAP_DMA_PORT_TIPB;
633 dst_port = OMAP_DMA_PORT_EMIFF;
635 if (cpu_is_omap24xx())
636 sync_dev = OMAP24XX_DMA_MMC1_RX;
638 omap_set_dma_src_params(dma_ch, src_port,
639 OMAP_DMA_AMODE_CONSTANT,
641 omap_set_dma_dest_params(dma_ch, dst_port,
642 OMAP_DMA_AMODE_POST_INC,
643 sg_dma_address(sg), 0, 0);
644 omap_set_dma_dest_data_pack(dma_ch, 1);
645 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
647 buf = 0x0f80 | ((frame - 1) << 0);
649 if (cpu_class_is_omap1()) {
650 src_port = OMAP_DMA_PORT_EMIFF;
651 dst_port = OMAP_DMA_PORT_TIPB;
653 if (cpu_is_omap24xx())
654 sync_dev = OMAP24XX_DMA_MMC1_TX;
656 omap_set_dma_dest_params(dma_ch, dst_port,
657 OMAP_DMA_AMODE_CONSTANT,
659 omap_set_dma_src_params(dma_ch, src_port,
660 OMAP_DMA_AMODE_POST_INC,
661 sg_dma_address(sg), 0, 0);
662 omap_set_dma_src_data_pack(dma_ch, 1);
663 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
666 /* Max limit for DMA frame count is 0xffff */
667 BUG_ON(count > 0xffff);
669 OMAP_MMC_WRITE(host, BUF, buf);
670 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
671 frame, count, OMAP_DMA_SYNC_FRAME,
675 /* A scatterlist segment completed */
676 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
678 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
679 struct mmc_data *mmcdat = host->data;
681 if (unlikely(host->dma_ch < 0)) {
682 dev_err(mmc_dev(host->mmc),
683 "DMA callback while DMA not enabled\n");
686 /* FIXME: We really should do something to _handle_ the errors */
687 if (ch_status & OMAP1_DMA_TOUT_IRQ) {
688 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
691 if (ch_status & OMAP_DMA_DROP_IRQ) {
692 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
695 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
698 mmcdat->bytes_xfered += host->dma_len;
700 if (host->sg_idx < host->sg_len) {
701 mmc_omap_prepare_dma(host, host->data);
702 omap_start_dma(host->dma_ch);
704 mmc_omap_dma_done(host, host->data);
707 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
709 const char *dev_name;
710 int sync_dev, dma_ch, is_read, r;
712 is_read = !(data->flags & MMC_DATA_WRITE);
713 del_timer_sync(&host->dma_timer);
714 if (host->dma_ch >= 0) {
715 if (is_read == host->dma_is_read)
717 omap_free_dma(host->dma_ch);
723 sync_dev = OMAP_DMA_MMC_RX;
724 dev_name = "MMC1 read";
726 sync_dev = OMAP_DMA_MMC2_RX;
727 dev_name = "MMC2 read";
731 sync_dev = OMAP_DMA_MMC_TX;
732 dev_name = "MMC1 write";
734 sync_dev = OMAP_DMA_MMC2_TX;
735 dev_name = "MMC2 write";
738 r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
741 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
744 host->dma_ch = dma_ch;
745 host->dma_is_read = is_read;
750 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
754 reg = OMAP_MMC_READ(host, SDIO);
756 OMAP_MMC_WRITE(host, SDIO, reg);
757 /* Set maximum timeout */
758 OMAP_MMC_WRITE(host, CTO, 0xff);
761 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
766 /* Convert ns to clock cycles by assuming 20MHz frequency
767 * 1 cycle at 20MHz = 500 ns
769 timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
771 /* Check if we need to use timeout multiplier register */
772 reg = OMAP_MMC_READ(host, SDIO);
773 if (timeout > 0xffff) {
778 OMAP_MMC_WRITE(host, SDIO, reg);
779 OMAP_MMC_WRITE(host, DTO, timeout);
783 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
785 struct mmc_data *data = req->data;
786 int i, use_dma, block_size;
791 OMAP_MMC_WRITE(host, BLEN, 0);
792 OMAP_MMC_WRITE(host, NBLK, 0);
793 OMAP_MMC_WRITE(host, BUF, 0);
794 host->dma_in_use = 0;
795 set_cmd_timeout(host, req);
799 block_size = data->blksz;
801 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
802 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
803 set_data_timeout(host, req);
805 /* cope with calling layer confusion; it issues "single
806 * block" writes using multi-block scatterlists.
808 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
810 /* Only do DMA for entire blocks */
811 use_dma = host->use_dma;
813 for (i = 0; i < sg_len; i++) {
814 if ((data->sg[i].length % block_size) != 0) {
823 if (mmc_omap_get_dma_channel(host, data) == 0) {
824 enum dma_data_direction dma_data_dir;
826 if (data->flags & MMC_DATA_WRITE)
827 dma_data_dir = DMA_TO_DEVICE;
829 dma_data_dir = DMA_FROM_DEVICE;
831 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
832 sg_len, dma_data_dir);
833 host->total_bytes_left = 0;
834 mmc_omap_prepare_dma(host, req->data);
835 host->brs_received = 0;
837 host->dma_in_use = 1;
844 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
845 host->total_bytes_left = data->blocks * block_size;
846 host->sg_len = sg_len;
847 mmc_omap_sg_to_buf(host);
848 host->dma_in_use = 0;
852 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
854 struct mmc_omap_host *host = mmc_priv(mmc);
856 WARN_ON(host->mrq != NULL);
860 /* only touch fifo AFTER the controller readies it */
861 mmc_omap_prepare_data(host, req);
862 mmc_omap_start_command(host, req->cmd);
863 if (host->dma_in_use)
864 omap_start_dma(host->dma_ch);
867 static void innovator_fpga_socket_power(int on)
869 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
871 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
872 OMAP1510_FPGA_POWER);
874 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
875 OMAP1510_FPGA_POWER);
881 * Turn the socket power on/off. Innovator uses FPGA, most boards
884 static void mmc_omap_power(struct mmc_omap_host *host, int on)
887 if (machine_is_omap_innovator())
888 innovator_fpga_socket_power(1);
889 else if (machine_is_omap_h2())
890 tps65010_set_gpio_out_value(GPIO3, HIGH);
891 else if (machine_is_omap_h3())
892 /* GPIO 4 of TPS65010 sends SD_EN signal */
893 tps65010_set_gpio_out_value(GPIO4, HIGH);
894 else if (cpu_is_omap24xx()) {
895 u16 reg = OMAP_MMC_READ(host, CON);
896 OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
898 if (host->power_pin >= 0)
899 omap_set_gpio_dataout(host->power_pin, 1);
901 if (machine_is_omap_innovator())
902 innovator_fpga_socket_power(0);
903 else if (machine_is_omap_h2())
904 tps65010_set_gpio_out_value(GPIO3, LOW);
905 else if (machine_is_omap_h3())
906 tps65010_set_gpio_out_value(GPIO4, LOW);
907 else if (cpu_is_omap24xx()) {
908 u16 reg = OMAP_MMC_READ(host, CON);
909 OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
911 if (host->power_pin >= 0)
912 omap_set_gpio_dataout(host->power_pin, 0);
916 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
918 struct mmc_omap_host *host = mmc_priv(mmc);
919 int func_clk_rate = clk_get_rate(host->fclk);
925 dsor = func_clk_rate / ios->clock;
929 if (func_clk_rate / dsor > ios->clock)
935 if (ios->bus_width == MMC_BUS_WIDTH_4)
941 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
943 struct mmc_omap_host *host = mmc_priv(mmc);
947 dsor = mmc_omap_calc_divisor(mmc, ios);
948 host->bus_mode = ios->bus_mode;
949 host->hw_bus_mode = host->bus_mode;
951 switch (ios->power_mode) {
953 mmc_omap_power(host, 0);
956 /* Cannot touch dsor yet, just power up MMC */
957 mmc_omap_power(host, 1);
964 clk_enable(host->fclk);
966 /* On insanely high arm_per frequencies something sometimes
967 * goes somehow out of sync, and the POW bit is not being set,
968 * which results in the while loop below getting stuck.
969 * Writing to the CON register twice seems to do the trick. */
970 for (i = 0; i < 2; i++)
971 OMAP_MMC_WRITE(host, CON, dsor);
972 if (ios->power_mode == MMC_POWER_ON) {
973 /* Send clock cycles, poll completion */
974 OMAP_MMC_WRITE(host, IE, 0);
975 OMAP_MMC_WRITE(host, STAT, 0xffff);
976 OMAP_MMC_WRITE(host, CMD, 1 << 7);
977 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
978 OMAP_MMC_WRITE(host, STAT, 1);
980 clk_disable(host->fclk);
983 static int mmc_omap_get_ro(struct mmc_host *mmc)
985 struct mmc_omap_host *host = mmc_priv(mmc);
987 return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
990 static const struct mmc_host_ops mmc_omap_ops = {
991 .request = mmc_omap_request,
992 .set_ios = mmc_omap_set_ios,
993 .get_ro = mmc_omap_get_ro,
996 static int __init mmc_omap_probe(struct platform_device *pdev)
998 struct omap_mmc_conf *minfo = pdev->dev.platform_data;
999 struct mmc_host *mmc;
1000 struct mmc_omap_host *host = NULL;
1001 struct resource *res;
1005 if (minfo == NULL) {
1006 dev_err(&pdev->dev, "platform data missing\n");
1010 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1011 irq = platform_get_irq(pdev, 0);
1012 if (res == NULL || irq < 0)
1015 res = request_mem_region(res->start, res->end - res->start + 1,
1020 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1023 goto err_free_mem_region;
1026 host = mmc_priv(mmc);
1029 spin_lock_init(&host->dma_lock);
1030 init_timer(&host->dma_timer);
1031 host->dma_timer.function = mmc_omap_dma_timer;
1032 host->dma_timer.data = (unsigned long) host;
1034 host->id = pdev->id;
1035 host->mem_res = res;
1038 if (cpu_is_omap24xx()) {
1039 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1040 if (IS_ERR(host->iclk))
1041 goto err_free_mmc_host;
1042 clk_enable(host->iclk);
1045 if (!cpu_is_omap24xx())
1046 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1048 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1050 if (IS_ERR(host->fclk)) {
1051 ret = PTR_ERR(host->fclk);
1056 * Also, use minfo->cover to decide how to manage
1057 * the card detect sensing.
1059 host->power_pin = minfo->power_pin;
1060 host->switch_pin = minfo->switch_pin;
1061 host->wp_pin = minfo->wp_pin;
1066 host->phys_base = host->mem_res->start;
1067 host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1069 mmc->ops = &mmc_omap_ops;
1070 mmc->f_min = 400000;
1071 mmc->f_max = 24000000;
1072 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1073 mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
1076 mmc->caps |= MMC_CAP_4_BIT_DATA;
1078 /* Use scatterlist DMA to reduce per-transfer costs.
1079 * NOTE max_seg_size assumption that small blocks aren't
1080 * normally used (except e.g. for reading SD registers).
1082 mmc->max_phys_segs = 32;
1083 mmc->max_hw_segs = 32;
1084 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1085 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1086 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1087 mmc->max_seg_size = mmc->max_req_size;
1089 if (host->power_pin >= 0) {
1090 if ((ret = omap_request_gpio(host->power_pin)) != 0) {
1091 dev_err(mmc_dev(host->mmc),
1092 "Unable to get GPIO pin for MMC power\n");
1095 omap_set_gpio_direction(host->power_pin, 0);
1098 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1100 goto err_free_power_gpio;
1102 host->dev = &pdev->dev;
1103 platform_set_drvdata(pdev, host);
1105 if (host->switch_pin >= 0) {
1106 INIT_WORK(&host->switch_work, mmc_omap_switch_handler);
1107 init_timer(&host->switch_timer);
1108 host->switch_timer.function = mmc_omap_switch_timer;
1109 host->switch_timer.data = (unsigned long) host;
1110 if (omap_request_gpio(host->switch_pin) != 0) {
1111 dev_warn(mmc_dev(host->mmc), "Unable to get GPIO pin for MMC cover switch\n");
1112 host->switch_pin = -1;
1116 omap_set_gpio_direction(host->switch_pin, 1);
1117 ret = request_irq(OMAP_GPIO_IRQ(host->switch_pin),
1118 mmc_omap_switch_irq, IRQF_TRIGGER_RISING, DRIVER_NAME, host);
1120 dev_warn(mmc_dev(host->mmc), "Unable to get IRQ for MMC cover switch\n");
1121 omap_free_gpio(host->switch_pin);
1122 host->switch_pin = -1;
1125 ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
1127 ret = device_create_file(&pdev->dev, &dev_attr_enable_poll);
1129 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1132 dev_warn(mmc_dev(host->mmc), "Unable to create sysfs attributes\n");
1133 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1134 omap_free_gpio(host->switch_pin);
1135 host->switch_pin = -1;
1138 if (mmc_omap_enable_poll && mmc_omap_cover_is_open(host))
1139 schedule_work(&host->switch_work);
1147 /* FIXME: Free other resources too. */
1149 if (host->iclk && !IS_ERR(host->iclk))
1150 clk_put(host->iclk);
1151 if (host->fclk && !IS_ERR(host->fclk))
1152 clk_put(host->fclk);
1153 mmc_free_host(host->mmc);
1155 err_free_power_gpio:
1156 if (host->power_pin >= 0)
1157 omap_free_gpio(host->power_pin);
1159 clk_put(host->fclk);
1161 if (host->iclk != NULL) {
1162 clk_disable(host->iclk);
1163 clk_put(host->iclk);
1166 mmc_free_host(host->mmc);
1167 err_free_mem_region:
1168 release_mem_region(res->start, res->end - res->start + 1);
1172 static int mmc_omap_remove(struct platform_device *pdev)
1174 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1176 platform_set_drvdata(pdev, NULL);
1178 BUG_ON(host == NULL);
1180 mmc_remove_host(host->mmc);
1181 free_irq(host->irq, host);
1183 if (host->power_pin >= 0)
1184 omap_free_gpio(host->power_pin);
1185 if (host->switch_pin >= 0) {
1186 device_remove_file(&pdev->dev, &dev_attr_enable_poll);
1187 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1188 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1189 omap_free_gpio(host->switch_pin);
1190 host->switch_pin = -1;
1191 del_timer_sync(&host->switch_timer);
1192 flush_scheduled_work();
1194 if (host->iclk && !IS_ERR(host->iclk))
1195 clk_put(host->iclk);
1196 if (host->fclk && !IS_ERR(host->fclk))
1197 clk_put(host->fclk);
1199 release_mem_region(pdev->resource[0].start,
1200 pdev->resource[0].end - pdev->resource[0].start + 1);
1202 mmc_free_host(host->mmc);
1208 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1211 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1213 if (host && host->suspended)
1217 ret = mmc_suspend_host(host->mmc, mesg);
1219 host->suspended = 1;
1224 static int mmc_omap_resume(struct platform_device *pdev)
1227 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1229 if (host && !host->suspended)
1233 ret = mmc_resume_host(host->mmc);
1235 host->suspended = 0;
1241 #define mmc_omap_suspend NULL
1242 #define mmc_omap_resume NULL
1245 static struct platform_driver mmc_omap_driver = {
1246 .probe = mmc_omap_probe,
1247 .remove = mmc_omap_remove,
1248 .suspend = mmc_omap_suspend,
1249 .resume = mmc_omap_resume,
1251 .name = DRIVER_NAME,
1252 .owner = THIS_MODULE,
1256 static int __init mmc_omap_init(void)
1258 return platform_driver_register(&mmc_omap_driver);
1261 static void __exit mmc_omap_exit(void)
1263 platform_driver_unregister(&mmc_omap_driver);
1266 module_init(mmc_omap_init);
1267 module_exit(mmc_omap_exit);
1269 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1270 MODULE_LICENSE("GPL");
1271 MODULE_ALIAS("platform:" DRIVER_NAME);
1272 MODULE_AUTHOR("Juha Yrjölä");