2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
7 * not need all the quirks found in imxmmc.c, hence the separate driver.
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
12 * derived from pxamci.c by Russell King
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/platform_device.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/blkdev.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/card.h>
30 #include <linux/delay.h>
31 #include <linux/clk.h>
33 #include <linux/gpio.h>
37 #include <asm/sizes.h>
40 #ifdef CONFIG_ARCH_MX2
41 #include <mach/dma-mx1-mx2.h>
45 #define DRIVER_NAME "mxc-mmc"
47 #define MMC_REG_STR_STP_CLK 0x00
48 #define MMC_REG_STATUS 0x04
49 #define MMC_REG_CLK_RATE 0x08
50 #define MMC_REG_CMD_DAT_CONT 0x0C
51 #define MMC_REG_RES_TO 0x10
52 #define MMC_REG_READ_TO 0x14
53 #define MMC_REG_BLK_LEN 0x18
54 #define MMC_REG_NOB 0x1C
55 #define MMC_REG_REV_NO 0x20
56 #define MMC_REG_INT_CNTR 0x24
57 #define MMC_REG_CMD 0x28
58 #define MMC_REG_ARG 0x2C
59 #define MMC_REG_RES_FIFO 0x34
60 #define MMC_REG_BUFFER_ACCESS 0x38
62 #define STR_STP_CLK_RESET (1 << 3)
63 #define STR_STP_CLK_START_CLK (1 << 1)
64 #define STR_STP_CLK_STOP_CLK (1 << 0)
66 #define STATUS_CARD_INSERTION (1 << 31)
67 #define STATUS_CARD_REMOVAL (1 << 30)
68 #define STATUS_YBUF_EMPTY (1 << 29)
69 #define STATUS_XBUF_EMPTY (1 << 28)
70 #define STATUS_YBUF_FULL (1 << 27)
71 #define STATUS_XBUF_FULL (1 << 26)
72 #define STATUS_BUF_UND_RUN (1 << 25)
73 #define STATUS_BUF_OVFL (1 << 24)
74 #define STATUS_SDIO_INT_ACTIVE (1 << 14)
75 #define STATUS_END_CMD_RESP (1 << 13)
76 #define STATUS_WRITE_OP_DONE (1 << 12)
77 #define STATUS_DATA_TRANS_DONE (1 << 11)
78 #define STATUS_READ_OP_DONE (1 << 11)
79 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
80 #define STATUS_CARD_BUS_CLK_RUN (1 << 8)
81 #define STATUS_BUF_READ_RDY (1 << 7)
82 #define STATUS_BUF_WRITE_RDY (1 << 6)
83 #define STATUS_RESP_CRC_ERR (1 << 5)
84 #define STATUS_CRC_READ_ERR (1 << 3)
85 #define STATUS_CRC_WRITE_ERR (1 << 2)
86 #define STATUS_TIME_OUT_RESP (1 << 1)
87 #define STATUS_TIME_OUT_READ (1 << 0)
88 #define STATUS_ERR_MASK 0x2f
90 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
91 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
92 #define CMD_DAT_CONT_START_READWAIT (1 << 10)
93 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
94 #define CMD_DAT_CONT_INIT (1 << 7)
95 #define CMD_DAT_CONT_WRITE (1 << 4)
96 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
97 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
98 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
99 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
101 #define INT_SDIO_INT_WKP_EN (1 << 18)
102 #define INT_CARD_INSERTION_WKP_EN (1 << 17)
103 #define INT_CARD_REMOVAL_WKP_EN (1 << 16)
104 #define INT_CARD_INSERTION_EN (1 << 15)
105 #define INT_CARD_REMOVAL_EN (1 << 14)
106 #define INT_SDIO_IRQ_EN (1 << 13)
107 #define INT_DAT0_EN (1 << 12)
108 #define INT_BUF_READ_EN (1 << 4)
109 #define INT_BUF_WRITE_EN (1 << 3)
110 #define INT_END_CMD_RES_EN (1 << 2)
111 #define INT_WRITE_OP_DONE_EN (1 << 1)
112 #define INT_READ_OP_EN (1 << 0)
115 struct mmc_host *mmc;
116 struct resource *res;
122 unsigned int power_mode;
123 struct imxmmc_platform_data *pdata;
125 struct mmc_request *req;
126 struct mmc_command *cmd;
127 struct mmc_data *data;
129 unsigned int dma_nents;
130 unsigned int datasize;
131 unsigned int dma_dir;
140 struct work_struct datawork;
143 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
145 static inline int mxcmci_use_dma(struct mxcmci_host *host)
150 static void mxcmci_softreset(struct mxcmci_host *host)
154 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
157 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK);
158 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
159 host->base + MMC_REG_STR_STP_CLK);
161 for (i = 0; i < 8; i++)
162 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
164 writew(0xff, host->base + MMC_REG_RES_TO);
167 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
169 unsigned int nob = data->blocks;
170 unsigned int blksz = data->blksz;
171 unsigned int datasize = nob * blksz;
173 struct scatterlist *sg;
177 if (data->flags & MMC_DATA_STREAM)
181 data->bytes_xfered = 0;
183 writew(nob, host->base + MMC_REG_NOB);
184 writew(blksz, host->base + MMC_REG_BLK_LEN);
185 host->datasize = datasize;
188 for_each_sg(data->sg, sg, data->sg_len, i) {
189 if (sg->offset & 3 || sg->length & 3) {
195 if (data->flags & MMC_DATA_READ) {
196 host->dma_dir = DMA_FROM_DEVICE;
197 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
198 data->sg_len, host->dma_dir);
200 ret = imx_dma_setup_sg(host->dma, data->sg, host->dma_nents,
202 host->res->start + MMC_REG_BUFFER_ACCESS,
205 host->dma_dir = DMA_TO_DEVICE;
206 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
207 data->sg_len, host->dma_dir);
209 ret = imx_dma_setup_sg(host->dma, data->sg, host->dma_nents,
211 host->res->start + MMC_REG_BUFFER_ACCESS,
216 dev_err(mmc_dev(host->mmc), "failed to setup DMA : %d\n", ret);
221 imx_dma_enable(host->dma);
226 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
229 WARN_ON(host->cmd != NULL);
232 switch (mmc_resp_type(cmd)) {
233 case MMC_RSP_R1: /* short CRC, OPCODE */
234 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
235 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
237 case MMC_RSP_R2: /* long 136 bit + CRC */
238 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
240 case MMC_RSP_R3: /* short */
241 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
246 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
248 cmd->error = -EINVAL;
252 if (mxcmci_use_dma(host))
253 writel(INT_READ_OP_EN | INT_WRITE_OP_DONE_EN |
255 host->base + MMC_REG_INT_CNTR);
257 writel(INT_END_CMD_RES_EN, host->base + MMC_REG_INT_CNTR);
259 writew(cmd->opcode, host->base + MMC_REG_CMD);
260 writel(cmd->arg, host->base + MMC_REG_ARG);
261 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
266 static void mxcmci_finish_request(struct mxcmci_host *host,
267 struct mmc_request *req)
269 writel(0, host->base + MMC_REG_INT_CNTR);
275 mmc_request_done(host->mmc, req);
278 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
280 struct mmc_data *data = host->data;
284 if (mxcmci_use_dma(host)) {
285 imx_dma_disable(host->dma);
286 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
291 if (stat & STATUS_ERR_MASK) {
292 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
294 if (stat & STATUS_CRC_READ_ERR) {
295 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
296 data->error = -EILSEQ;
297 } else if (stat & STATUS_CRC_WRITE_ERR) {
298 u32 err_code = (stat >> 9) & 0x3;
299 if (err_code == 2) { /* No CRC response */
300 dev_err(mmc_dev(host->mmc),
301 "%s: No CRC -ETIMEDOUT\n", __func__);
302 data->error = -ETIMEDOUT;
304 dev_err(mmc_dev(host->mmc),
305 "%s: -EILSEQ\n", __func__);
306 data->error = -EILSEQ;
308 } else if (stat & STATUS_TIME_OUT_READ) {
309 dev_err(mmc_dev(host->mmc),
310 "%s: read -ETIMEDOUT\n", __func__);
311 data->error = -ETIMEDOUT;
313 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
317 data->bytes_xfered = host->datasize;
320 data_error = data->error;
327 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
329 struct mmc_command *cmd = host->cmd;
336 if (stat & STATUS_TIME_OUT_RESP) {
337 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
338 cmd->error = -ETIMEDOUT;
339 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
340 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
341 cmd->error = -EILSEQ;
344 if (cmd->flags & MMC_RSP_PRESENT) {
345 if (cmd->flags & MMC_RSP_136) {
346 for (i = 0; i < 4; i++) {
347 a = readw(host->base + MMC_REG_RES_FIFO);
348 b = readw(host->base + MMC_REG_RES_FIFO);
349 cmd->resp[i] = a << 16 | b;
352 a = readw(host->base + MMC_REG_RES_FIFO);
353 b = readw(host->base + MMC_REG_RES_FIFO);
354 c = readw(host->base + MMC_REG_RES_FIFO);
355 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
360 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
363 unsigned long timeout = jiffies + HZ;
366 stat = readl(host->base + MMC_REG_STATUS);
367 if (stat & STATUS_ERR_MASK)
369 if (time_after(jiffies, timeout)) {
370 mxcmci_softreset(host);
371 mxcmci_set_clk_rate(host, host->clock);
372 return STATUS_TIME_OUT_READ;
380 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
386 stat = mxcmci_poll_status(host,
387 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
390 *buf++ = readl(host->base + MMC_REG_BUFFER_ACCESS);
398 stat = mxcmci_poll_status(host,
399 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
402 tmp = readl(host->base + MMC_REG_BUFFER_ACCESS);
403 memcpy(b, &tmp, bytes);
409 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
415 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
418 writel(*buf++, host->base + MMC_REG_BUFFER_ACCESS);
426 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
430 memcpy(&tmp, b, bytes);
431 writel(tmp, host->base + MMC_REG_BUFFER_ACCESS);
434 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
441 static int mxcmci_transfer_data(struct mxcmci_host *host)
443 struct mmc_data *data = host->req->data;
444 struct scatterlist *sg;
450 if (data->flags & MMC_DATA_READ) {
451 for_each_sg(data->sg, sg, data->sg_len, i) {
452 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
455 host->datasize += sg->length;
458 for_each_sg(data->sg, sg, data->sg_len, i) {
459 stat = mxcmci_push(host, sg_virt(sg), sg->length);
462 host->datasize += sg->length;
464 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
471 static void mxcmci_datawork(struct work_struct *work)
473 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
475 int datastat = mxcmci_transfer_data(host);
476 mxcmci_finish_data(host, datastat);
478 if (host->req->stop) {
479 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
480 mxcmci_finish_request(host, host->req);
484 mxcmci_finish_request(host, host->req);
489 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
491 struct mmc_data *data = host->data;
497 data_error = mxcmci_finish_data(host, stat);
499 mxcmci_read_response(host, stat);
502 if (host->req->stop) {
503 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
504 mxcmci_finish_request(host, host->req);
508 mxcmci_finish_request(host, host->req);
513 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
515 mxcmci_read_response(host, stat);
518 if (!host->data && host->req) {
519 mxcmci_finish_request(host, host->req);
523 /* For the DMA case the DMA engine handles the data transfer
524 * automatically. For non DMA we have to do it ourselves.
525 * Don't do it in interrupt context though.
527 if (!mxcmci_use_dma(host) && host->data)
528 schedule_work(&host->datawork);
532 static irqreturn_t mxcmci_irq(int irq, void *devid)
534 struct mxcmci_host *host = devid;
537 stat = readl(host->base + MMC_REG_STATUS);
538 writel(stat, host->base + MMC_REG_STATUS);
540 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
542 if (stat & STATUS_END_CMD_RESP)
543 mxcmci_cmd_done(host, stat);
545 if (mxcmci_use_dma(host) &&
546 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE)))
547 mxcmci_data_done(host, stat);
552 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
554 struct mxcmci_host *host = mmc_priv(mmc);
555 unsigned int cmdat = host->cmdat;
558 WARN_ON(host->req != NULL);
561 host->cmdat &= ~CMD_DAT_CONT_INIT;
566 error = mxcmci_setup_data(host, req->data);
568 req->cmd->error = error;
573 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
575 if (req->data->flags & MMC_DATA_WRITE)
576 cmdat |= CMD_DAT_CONT_WRITE;
579 error = mxcmci_start_cmd(host, req->cmd, cmdat);
582 mxcmci_finish_request(host, req);
585 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
587 unsigned int divider;
589 unsigned int clk_in = clk_get_rate(host->clk);
591 while (prescaler <= 0x800) {
592 for (divider = 1; divider <= 0xF; divider++) {
595 x = (clk_in / (divider + 1));
598 x /= (prescaler * 2);
612 writew((prescaler << 4) | divider, host->base + MMC_REG_CLK_RATE);
614 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
615 prescaler, divider, clk_in, clk_ios);
618 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
620 struct mxcmci_host *host = mmc_priv(mmc);
624 * use burstlen of 64 in 4 bit mode (--> reg value 0)
625 * use burstlen of 16 in 1 bit mode (--> reg value 16)
627 if (ios->bus_width == MMC_BUS_WIDTH_4)
632 imx_dma_config_burstlen(host->dma, blen);
634 if (ios->bus_width == MMC_BUS_WIDTH_4)
635 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
637 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
639 if (host->power_mode != ios->power_mode) {
640 if (host->pdata && host->pdata->setpower)
641 host->pdata->setpower(mmc_dev(mmc), ios->vdd);
642 host->power_mode = ios->power_mode;
643 if (ios->power_mode == MMC_POWER_ON)
644 host->cmdat |= CMD_DAT_CONT_INIT;
648 mxcmci_set_clk_rate(host, ios->clock);
649 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
651 writew(STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
654 host->clock = ios->clock;
657 static irqreturn_t mxcmci_detect_irq(int irq, void *data)
659 struct mmc_host *mmc = data;
661 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
663 mmc_detect_change(mmc, msecs_to_jiffies(250));
667 static int mxcmci_get_ro(struct mmc_host *mmc)
669 struct mxcmci_host *host = mmc_priv(mmc);
671 if (host->pdata && host->pdata->get_ro)
672 return !!host->pdata->get_ro(mmc_dev(mmc));
674 * Board doesn't support read only detection; let the mmc core
681 static const struct mmc_host_ops mxcmci_ops = {
682 .request = mxcmci_request,
683 .set_ios = mxcmci_set_ios,
684 .get_ro = mxcmci_get_ro,
687 static int mxcmci_probe(struct platform_device *pdev)
689 struct mmc_host *mmc;
690 struct mxcmci_host *host = NULL;
691 struct resource *iores, *r;
694 printk(KERN_INFO "i.MX SDHC driver\n");
696 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
697 irq = platform_get_irq(pdev, 0);
698 if (!iores || irq < 0)
701 r = request_mem_region(iores->start, resource_size(iores), pdev->name);
705 mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev);
708 goto out_release_mem;
711 mmc->ops = &mxcmci_ops;
712 mmc->caps = MMC_CAP_4_BIT_DATA;
714 /* MMC core transfer sizes tunable parameters */
715 mmc->max_hw_segs = 64;
716 mmc->max_phys_segs = 64;
717 mmc->max_blk_size = 2048;
718 mmc->max_blk_count = 65535;
719 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
720 mmc->max_seg_size = mmc->max_req_size;
722 host = mmc_priv(mmc);
723 host->base = ioremap(r->start, resource_size(r));
730 host->pdata = pdev->dev.platform_data;
732 if (host->pdata && host->pdata->ocr_avail)
733 mmc->ocr_avail = host->pdata->ocr_avail;
735 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
740 host->clk = clk_get(&pdev->dev, NULL);
741 if (IS_ERR(host->clk)) {
742 ret = PTR_ERR(host->clk);
745 clk_enable(host->clk);
747 mxcmci_softreset(host);
749 host->rev_no = readw(host->base + MMC_REG_REV_NO);
750 if (host->rev_no != 0x400) {
752 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
757 mmc->f_min = clk_get_rate(host->clk) >> 16;
758 mmc->f_max = clk_get_rate(host->clk) >> 1;
760 /* recommended in data sheet */
761 writew(0x2db4, host->base + MMC_REG_READ_TO);
763 writel(0, host->base + MMC_REG_INT_CNTR);
766 host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
768 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
773 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
779 ret = imx_dma_config_channel(host->dma,
780 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO,
781 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
784 dev_err(mmc_dev(host->mmc), "failed to config DMA channel\n");
788 INIT_WORK(&host->datawork, mxcmci_datawork);
790 ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host);
794 platform_set_drvdata(pdev, mmc);
796 if (host->pdata && host->pdata->init) {
797 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
808 free_irq(host->irq, host);
811 imx_dma_free(host->dma);
814 clk_disable(host->clk);
821 release_mem_region(iores->start, resource_size(iores));
825 static int mxcmci_remove(struct platform_device *pdev)
827 struct mmc_host *mmc = platform_get_drvdata(pdev);
828 struct mxcmci_host *host = mmc_priv(mmc);
830 platform_set_drvdata(pdev, NULL);
832 mmc_remove_host(mmc);
834 if (host->pdata && host->pdata->exit)
835 host->pdata->exit(&pdev->dev, mmc);
837 free_irq(host->irq, host);
840 imx_dma_free(host->dma);
842 clk_disable(host->clk);
845 release_mem_region(host->res->start, resource_size(host->res));
846 release_resource(host->res);
854 static int mxcmci_suspend(struct platform_device *dev, pm_message_t state)
856 struct mmc_host *mmc = platform_get_drvdata(dev);
860 ret = mmc_suspend_host(mmc, state);
865 static int mxcmci_resume(struct platform_device *dev)
867 struct mmc_host *mmc = platform_get_drvdata(dev);
868 struct mxcmci_host *host;
872 host = mmc_priv(mmc);
873 ret = mmc_resume_host(mmc);
879 #define mxcmci_suspend NULL
880 #define mxcmci_resume NULL
881 #endif /* CONFIG_PM */
883 static struct platform_driver mxcmci_driver = {
884 .probe = mxcmci_probe,
885 .remove = mxcmci_remove,
886 .suspend = mxcmci_suspend,
887 .resume = mxcmci_resume,
890 .owner = THIS_MODULE,
894 static int __init mxcmci_init(void)
896 return platform_driver_register(&mxcmci_driver);
899 static void __exit mxcmci_exit(void)
901 platform_driver_unregister(&mxcmci_driver);
904 module_init(mxcmci_init);
905 module_exit(mxcmci_exit);
907 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
908 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
909 MODULE_LICENSE("GPL");
910 MODULE_ALIAS("platform:imx-mmc");