2 * SN Platform GRU Driver
4 * FAULT HANDLER FOR GRU DETECTED TLB MISSES
6 * This file contains code that handles TLB misses within the GRU.
7 * These misses are reported either via interrupts or user polling of
10 * Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 #include <linux/kernel.h>
28 #include <linux/errno.h>
29 #include <linux/spinlock.h>
31 #include <linux/hugetlb.h>
32 #include <linux/device.h>
34 #include <linux/uaccess.h>
35 #include <linux/security.h>
36 #include <asm/pgtable.h>
38 #include "grutables.h"
40 #include "gru_instructions.h"
41 #include <asm/uv/uv_hub.h>
44 * Test if a physical address is a valid GRU GSEG address
46 static inline int is_gru_paddr(unsigned long paddr)
48 return paddr >= gru_start_paddr && paddr < gru_end_paddr;
52 * Find the vma of a GRU segment. Caller must hold mmap_sem.
54 struct vm_area_struct *gru_find_vma(unsigned long vaddr)
56 struct vm_area_struct *vma;
58 vma = find_vma(current->mm, vaddr);
59 if (vma && vma->vm_start <= vaddr && vma->vm_ops == &gru_vm_ops)
65 * Find and lock the gts that contains the specified user vaddr.
68 * - *gts with the mmap_sem locked for read and the GTS locked.
69 * - NULL if vaddr invalid OR is not a valid GSEG vaddr.
72 static struct gru_thread_state *gru_find_lock_gts(unsigned long vaddr)
74 struct mm_struct *mm = current->mm;
75 struct vm_area_struct *vma;
76 struct gru_thread_state *gts = NULL;
78 down_read(&mm->mmap_sem);
79 vma = gru_find_vma(vaddr);
81 gts = gru_find_thread_state(vma, TSID(vaddr, vma));
83 mutex_lock(>s->ts_ctxlock);
85 up_read(&mm->mmap_sem);
89 static struct gru_thread_state *gru_alloc_locked_gts(unsigned long vaddr)
91 struct mm_struct *mm = current->mm;
92 struct vm_area_struct *vma;
93 struct gru_thread_state *gts = ERR_PTR(-EINVAL);
95 down_write(&mm->mmap_sem);
96 vma = gru_find_vma(vaddr);
100 gts = gru_alloc_thread_state(vma, TSID(vaddr, vma));
103 mutex_lock(>s->ts_ctxlock);
104 downgrade_write(&mm->mmap_sem);
108 up_write(&mm->mmap_sem);
113 * Unlock a GTS that was previously locked with gru_find_lock_gts().
115 static void gru_unlock_gts(struct gru_thread_state *gts)
117 mutex_unlock(>s->ts_ctxlock);
118 up_read(¤t->mm->mmap_sem);
122 * Set a CB.istatus to active using a user virtual address. This must be done
123 * just prior to a TFH RESTART. The new cb.istatus is an in-cache status ONLY.
124 * If the line is evicted, the status may be lost. The in-cache update
125 * is necessary to prevent the user from seeing a stale cb.istatus that will
126 * change as soon as the TFH restart is complete. Races may cause an
127 * occasional failure to clear the cb.istatus, but that is ok.
129 static void gru_cb_set_istatus_active(struct gru_instruction_bits *cbk)
132 cbk->istatus = CBS_ACTIVE;
139 * The GRU has an array of fault maps. A map is private to a cpu
140 * Only one cpu will be accessing a cpu's fault map.
142 * This function scans the cpu-private fault map & clears all bits that
143 * are set. The function returns a bitmap that indicates the bits that
144 * were cleared. Note that sense the maps may be updated asynchronously by
145 * the GRU, atomic operations must be used to clear bits.
147 static void get_clear_fault_map(struct gru_state *gru,
148 struct gru_tlb_fault_map *imap,
149 struct gru_tlb_fault_map *dmap)
152 struct gru_tlb_fault_map *tfm;
154 tfm = get_tfm_for_cpu(gru, gru_cpu_fault_map_id());
155 prefetchw(tfm); /* Helps on hardware, required for emulator */
156 for (i = 0; i < BITS_TO_LONGS(GRU_NUM_CBE); i++) {
157 k = tfm->fault_bits[i];
159 k = xchg(&tfm->fault_bits[i], 0UL);
160 imap->fault_bits[i] = k;
161 k = tfm->done_bits[i];
163 k = xchg(&tfm->done_bits[i], 0UL);
164 dmap->fault_bits[i] = k;
168 * Not functionally required but helps performance. (Required
171 gru_flush_cache(tfm);
175 * Atomic (interrupt context) & non-atomic (user context) functions to
176 * convert a vaddr into a physical address. The size of the page
177 * is returned in pageshift.
181 * 1 - (atomic only) try again in non-atomic context
183 static int non_atomic_pte_lookup(struct vm_area_struct *vma,
184 unsigned long vaddr, int write,
185 unsigned long *paddr, int *pageshift)
189 /* ZZZ Need to handle HUGE pages */
190 if (is_vm_hugetlb_page(vma))
192 *pageshift = PAGE_SHIFT;
194 (current, current->mm, vaddr, 1, write, 0, &page, NULL) <= 0)
196 *paddr = page_to_phys(page);
204 * Convert a user virtual address to a physical address
205 * Only supports Intel large pages (2MB only) on x86_64.
206 * ZZZ - hugepage support is incomplete
208 * NOTE: mmap_sem is already held on entry to this function. This
209 * guarantees existence of the page tables.
211 static int atomic_pte_lookup(struct vm_area_struct *vma, unsigned long vaddr,
212 int write, unsigned long *paddr, int *pageshift)
219 pgdp = pgd_offset(vma->vm_mm, vaddr);
220 if (unlikely(pgd_none(*pgdp)))
223 pudp = pud_offset(pgdp, vaddr);
224 if (unlikely(pud_none(*pudp)))
227 pmdp = pmd_offset(pudp, vaddr);
228 if (unlikely(pmd_none(*pmdp)))
231 if (unlikely(pmd_large(*pmdp)))
232 pte = *(pte_t *) pmdp;
235 pte = *pte_offset_kernel(pmdp, vaddr);
237 if (unlikely(!pte_present(pte) ||
238 (write && (!pte_write(pte) || !pte_dirty(pte)))))
241 *paddr = pte_pfn(pte) << PAGE_SHIFT;
242 #ifdef CONFIG_HUGETLB_PAGE
243 *pageshift = is_vm_hugetlb_page(vma) ? HPAGE_SHIFT : PAGE_SHIFT;
245 *pageshift = PAGE_SHIFT;
254 static int gru_vtop(struct gru_thread_state *gts, unsigned long vaddr,
255 int write, int atomic, unsigned long *gpa, int *pageshift)
257 struct mm_struct *mm = gts->ts_mm;
258 struct vm_area_struct *vma;
262 vma = find_vma(mm, vaddr);
267 * Atomic lookup is faster & usually works even if called in non-atomic
270 rmb(); /* Must/check ms_range_active before loading PTEs */
271 ret = atomic_pte_lookup(vma, vaddr, write, &paddr, &ps);
275 if (non_atomic_pte_lookup(vma, vaddr, write, &paddr, &ps))
278 if (is_gru_paddr(paddr))
280 paddr = paddr & ~((1UL << ps) - 1);
281 *gpa = uv_soc_phys_ram_to_gpa(paddr);
293 * Flush a CBE from cache. The CBE is clean in the cache. Dirty the
294 * CBE cacheline so that the line will be written back to home agent.
295 * Otherwise the line may be silently dropped. This has no impact
296 * except on performance.
298 static void gru_flush_cache_cbe(struct gru_control_block_extended *cbe)
301 cbe->cbrexecstatus = 0; /* make CL dirty */
302 gru_flush_cache(cbe);
307 * Preload the TLB with entries that may be required. Currently, preloading
308 * is implemented only for BCOPY. Preload <tlb_preload_count> pages OR to
309 * the end of the bcopy tranfer, whichever is smaller.
311 static void gru_preload_tlb(struct gru_state *gru,
312 struct gru_thread_state *gts, int atomic,
313 unsigned long fault_vaddr, int asid, int write,
314 unsigned char tlb_preload_count,
315 struct gru_tlb_fault_handle *tfh,
316 struct gru_control_block_extended *cbe)
318 unsigned long vaddr = 0, gpa;
321 if (cbe->opccpy != OP_BCOPY)
324 if (fault_vaddr == cbe->cbe_baddr0)
325 vaddr = fault_vaddr + GRU_CACHE_LINE_BYTES * cbe->cbe_src_cl - 1;
326 else if (fault_vaddr == cbe->cbe_baddr1)
327 vaddr = fault_vaddr + (1 << cbe->xtypecpy) * cbe->cbe_nelemcur - 1;
329 fault_vaddr &= PAGE_MASK;
331 vaddr = min(vaddr, fault_vaddr + tlb_preload_count * PAGE_SIZE);
333 while (vaddr > fault_vaddr) {
334 ret = gru_vtop(gts, vaddr, write, atomic, &gpa, &pageshift);
335 if (ret || tfh_write_only(tfh, gpa, GAA_RAM, vaddr, asid, write,
336 GRU_PAGESIZE(pageshift)))
339 "%s: gid %d, gts 0x%p, tfh 0x%p, vaddr 0x%lx, asid 0x%x, rw %d, ps %d, gpa 0x%lx\n",
340 atomic ? "atomic" : "non-atomic", gru->gs_gid, gts, tfh,
341 vaddr, asid, write, pageshift, gpa);
343 STAT(tlb_preload_page);
348 * Drop a TLB entry into the GRU. The fault is described by info in an TFH.
350 * cb Address of user CBR. Null if not running in user context
352 * 0 = dropin, exception, or switch to UPM successful
353 * 1 = range invalidate active
357 static int gru_try_dropin(struct gru_thread_state *gts,
358 struct gru_tlb_fault_handle *tfh,
359 struct gru_instruction_bits *cbk)
361 struct gru_control_block_extended *cbe = NULL;
362 unsigned char tlb_preload_count = gts->ts_tlb_preload_count;
363 int pageshift = 0, asid, write, ret, atomic = !cbk, indexway;
364 unsigned long gpa = 0, vaddr = 0;
367 * NOTE: The GRU contains magic hardware that eliminates races between
368 * TLB invalidates and TLB dropins. If an invalidate occurs
369 * in the window between reading the TFH and the subsequent TLB dropin,
370 * the dropin is ignored. This eliminates the need for additional locks.
374 * Prefetch the CBE if doing TLB preloading
376 if (unlikely(tlb_preload_count)) {
377 cbe = gru_tfh_to_cbe(tfh);
382 * Error if TFH state is IDLE or FMM mode & the user issuing a UPM call.
383 * Might be a hardware race OR a stupid user. Ignore FMM because FMM
384 * is a transient state.
386 if (tfh->status != TFHSTATUS_EXCEPTION) {
387 gru_flush_cache(tfh);
389 if (tfh->status != TFHSTATUS_EXCEPTION)
390 goto failnoexception;
391 STAT(tfh_stale_on_fault);
393 if (tfh->state == TFHSTATE_IDLE)
395 if (tfh->state == TFHSTATE_MISS_FMM && cbk)
398 write = (tfh->cause & TFHCAUSE_TLB_MOD) != 0;
399 vaddr = tfh->missvaddr;
400 asid = tfh->missasid;
401 indexway = tfh->indexway;
405 rmb(); /* TFH must be cache resident before reading ms_range_active */
408 * TFH is cache resident - at least briefly. Fail the dropin
409 * if a range invalidate is active.
411 if (atomic_read(>s->ts_gms->ms_range_active))
414 ret = gru_vtop(gts, vaddr, write, atomic, &gpa, &pageshift);
420 if (!(gts->ts_sizeavail & GRU_SIZEAVAIL(pageshift))) {
421 gts->ts_sizeavail |= GRU_SIZEAVAIL(pageshift);
422 if (atomic || !gru_update_cch(gts)) {
423 gts->ts_force_cch_reload = 1;
428 if (unlikely(cbe) && pageshift == PAGE_SHIFT) {
429 gru_preload_tlb(gts->ts_gru, gts, atomic, vaddr, asid, write, tlb_preload_count, tfh, cbe);
430 gru_flush_cache_cbe(cbe);
433 gru_cb_set_istatus_active(cbk);
434 tfh_write_restart(tfh, gpa, GAA_RAM, vaddr, asid, write,
435 GRU_PAGESIZE(pageshift));
437 "%s: gid %d, gts 0x%p, tfh 0x%p, vaddr 0x%lx, asid 0x%x, indexway 0x%x,"
438 " rw %d, ps %d, gpa 0x%lx\n",
439 atomic ? "atomic" : "non-atomic", gts->ts_gru->gs_gid, gts, tfh, vaddr, asid,
440 indexway, write, pageshift, gpa);
445 /* No asid (delayed unload). */
446 STAT(tlb_dropin_fail_no_asid);
447 gru_dbg(grudev, "FAILED no_asid tfh: 0x%p, vaddr 0x%lx\n", tfh, vaddr);
449 tfh_user_polling_mode(tfh);
451 gru_flush_cache(tfh);
452 gru_flush_cache_cbe(cbe);
456 /* Atomic failure switch CBR to UPM */
457 tfh_user_polling_mode(tfh);
458 gru_flush_cache_cbe(cbe);
459 STAT(tlb_dropin_fail_upm);
460 gru_dbg(grudev, "FAILED upm tfh: 0x%p, vaddr 0x%lx\n", tfh, vaddr);
464 /* FMM state on UPM call */
465 gru_flush_cache(tfh);
466 gru_flush_cache_cbe(cbe);
467 STAT(tlb_dropin_fail_fmm);
468 gru_dbg(grudev, "FAILED fmm tfh: 0x%p, state %d\n", tfh, tfh->state);
472 /* TFH status did not show exception pending */
473 gru_flush_cache(tfh);
474 gru_flush_cache_cbe(cbe);
476 gru_flush_cache(cbk);
477 STAT(tlb_dropin_fail_no_exception);
478 gru_dbg(grudev, "FAILED non-exception tfh: 0x%p, status %d, state %d\n",
479 tfh, tfh->status, tfh->state);
483 /* TFH state was idle - no miss pending */
484 gru_flush_cache(tfh);
485 gru_flush_cache_cbe(cbe);
487 gru_flush_cache(cbk);
488 STAT(tlb_dropin_fail_idle);
489 gru_dbg(grudev, "FAILED idle tfh: 0x%p, state %d\n", tfh, tfh->state);
493 /* All errors (atomic & non-atomic) switch CBR to EXCEPTION state */
495 gru_flush_cache_cbe(cbe);
496 STAT(tlb_dropin_fail_invalid);
497 gru_dbg(grudev, "FAILED inval tfh: 0x%p, vaddr 0x%lx\n", tfh, vaddr);
501 /* Range invalidate active. Switch to UPM iff atomic */
503 tfh_user_polling_mode(tfh);
505 gru_flush_cache(tfh);
506 gru_flush_cache_cbe(cbe);
507 STAT(tlb_dropin_fail_range_active);
508 gru_dbg(grudev, "FAILED range active: tfh 0x%p, vaddr 0x%lx\n",
514 * Process an external interrupt from the GRU. This interrupt is
515 * caused by a TLB miss.
516 * Note that this is the interrupt handler that is registered with linux
517 * interrupt handlers.
519 static irqreturn_t gru_intr(int chiplet, int blade)
521 struct gru_state *gru;
522 struct gru_tlb_fault_map imap, dmap;
523 struct gru_thread_state *gts;
524 struct gru_tlb_fault_handle *tfh = NULL;
529 gru = &gru_base[blade]->bs_grus[chiplet];
531 dev_err(grudev, "GRU: invalid interrupt: cpu %d, chiplet %d\n",
532 raw_smp_processor_id(), chiplet);
535 get_clear_fault_map(gru, &imap, &dmap);
537 "cpu %d, chiplet %d, gid %d, imap %016lx %016lx, dmap %016lx %016lx\n",
538 smp_processor_id(), chiplet, gru->gs_gid,
539 imap.fault_bits[0], imap.fault_bits[1],
540 dmap.fault_bits[0], dmap.fault_bits[1]);
542 for_each_cbr_in_tfm(cbrnum, dmap.fault_bits) {
544 complete(gru->gs_blade->bs_async_wq);
545 gru_dbg(grudev, "gid %d, cbr_done %d, done %d\n",
546 gru->gs_gid, cbrnum, gru->gs_blade->bs_async_wq->done);
549 for_each_cbr_in_tfm(cbrnum, imap.fault_bits) {
551 tfh = get_tfh_by_index(gru, cbrnum);
552 prefetchw(tfh); /* Helps on hdw, required for emulator */
555 * When hardware sets a bit in the faultmap, it implicitly
556 * locks the GRU context so that it cannot be unloaded.
557 * The gts cannot change until a TFH start/writestart command
560 ctxnum = tfh->ctxnum;
561 gts = gru->gs_gts[ctxnum];
564 * This is running in interrupt context. Trylock the mmap_sem.
565 * If it fails, retry the fault in user context.
567 if (!gts->ts_force_cch_reload &&
568 down_read_trylock(>s->ts_mm->mmap_sem)) {
569 gts->ustats.fmm_tlbdropin++;
570 gru_try_dropin(gts, tfh, NULL);
571 up_read(>s->ts_mm->mmap_sem);
573 tfh_user_polling_mode(tfh);
574 STAT(intr_mm_lock_failed);
580 irqreturn_t gru0_intr(int irq, void *dev_id)
582 return gru_intr(0, uv_numa_blade_id());
585 irqreturn_t gru1_intr(int irq, void *dev_id)
587 return gru_intr(1, uv_numa_blade_id());
590 irqreturn_t gru_intr_mblade(int irq, void *dev_id)
594 for_each_possible_blade(blade) {
595 if (uv_blade_nr_possible_cpus(blade))
604 static int gru_user_dropin(struct gru_thread_state *gts,
605 struct gru_tlb_fault_handle *tfh,
608 struct gru_mm_struct *gms = gts->ts_gms;
611 gts->ustats.upm_tlbdropin++;
613 wait_event(gms->ms_wait_queue,
614 atomic_read(&gms->ms_range_active) == 0);
615 prefetchw(tfh); /* Helps on hdw, required for emulator */
616 ret = gru_try_dropin(gts, tfh, cb);
619 STAT(call_os_wait_queue);
624 * This interface is called as a result of a user detecting a "call OS" bit
625 * in a user CB. Normally means that a TLB fault has occurred.
626 * cb - user virtual address of the CB
628 int gru_handle_user_call_os(unsigned long cb)
630 struct gru_tlb_fault_handle *tfh;
631 struct gru_thread_state *gts;
633 int ucbnum, cbrnum, ret = -EINVAL;
637 /* sanity check the cb pointer */
638 ucbnum = get_cb_number((void *)cb);
639 if ((cb & (GRU_HANDLE_STRIDE - 1)) || ucbnum >= GRU_NUM_CB)
642 gts = gru_find_lock_gts(cb);
645 gru_dbg(grudev, "address 0x%lx, gid %d, gts 0x%p\n", cb, gts->ts_gru ? gts->ts_gru->gs_gid : -1, gts);
647 if (ucbnum >= gts->ts_cbr_au_count * GRU_CBR_AU_SIZE)
650 gru_check_context_placement(gts);
653 * CCH may contain stale data if ts_force_cch_reload is set.
655 if (gts->ts_gru && gts->ts_force_cch_reload) {
656 gts->ts_force_cch_reload = 0;
661 cbrnum = thread_cbr_number(gts, ucbnum);
663 tfh = get_tfh_by_index(gts->ts_gru, cbrnum);
664 cbk = get_gseg_base_address_cb(gts->ts_gru->gs_gru_base_vaddr,
665 gts->ts_ctxnum, ucbnum);
666 ret = gru_user_dropin(gts, tfh, cbk);
674 * Fetch the exception detail information for a CB that terminated with
677 int gru_get_exception_detail(unsigned long arg)
679 struct control_block_extended_exc_detail excdet;
680 struct gru_control_block_extended *cbe;
681 struct gru_thread_state *gts;
682 int ucbnum, cbrnum, ret;
684 STAT(user_exception);
685 if (copy_from_user(&excdet, (void __user *)arg, sizeof(excdet)))
688 gts = gru_find_lock_gts(excdet.cb);
692 gru_dbg(grudev, "address 0x%lx, gid %d, gts 0x%p\n", excdet.cb, gts->ts_gru ? gts->ts_gru->gs_gid : -1, gts);
693 ucbnum = get_cb_number((void *)excdet.cb);
694 if (ucbnum >= gts->ts_cbr_au_count * GRU_CBR_AU_SIZE) {
696 } else if (gts->ts_gru) {
697 cbrnum = thread_cbr_number(gts, ucbnum);
698 cbe = get_cbe_by_index(gts->ts_gru, cbrnum);
699 gru_flush_cache(cbe); /* CBE not coherent */
700 sync_core(); /* make sure we are have current data */
701 excdet.opc = cbe->opccpy;
702 excdet.exopc = cbe->exopccpy;
703 excdet.ecause = cbe->ecause;
704 excdet.exceptdet0 = cbe->idef1upd;
705 excdet.exceptdet1 = cbe->idef3upd;
706 excdet.cbrstate = cbe->cbrstate;
707 excdet.cbrexecstatus = cbe->cbrexecstatus;
708 gru_flush_cache_cbe(cbe);
716 "cb 0x%lx, op %d, exopc %d, cbrstate %d, cbrexecstatus 0x%x, ecause 0x%x, "
717 "exdet0 0x%lx, exdet1 0x%x\n",
718 excdet.cb, excdet.opc, excdet.exopc, excdet.cbrstate, excdet.cbrexecstatus,
719 excdet.ecause, excdet.exceptdet0, excdet.exceptdet1);
720 if (!ret && copy_to_user((void __user *)arg, &excdet, sizeof(excdet)))
726 * User request to unload a context. Content is saved for possible reload.
728 static int gru_unload_all_contexts(void)
730 struct gru_thread_state *gts;
731 struct gru_state *gru;
734 if (!capable(CAP_SYS_ADMIN))
737 gru = GID_TO_GRU(gid);
738 spin_lock(&gru->gs_lock);
739 for (ctxnum = 0; ctxnum < GRU_NUM_CCH; ctxnum++) {
740 gts = gru->gs_gts[ctxnum];
741 if (gts && mutex_trylock(>s->ts_ctxlock)) {
742 spin_unlock(&gru->gs_lock);
743 gru_unload_context(gts, 1);
744 mutex_unlock(>s->ts_ctxlock);
745 spin_lock(&gru->gs_lock);
748 spin_unlock(&gru->gs_lock);
753 int gru_user_unload_context(unsigned long arg)
755 struct gru_thread_state *gts;
756 struct gru_unload_context_req req;
758 STAT(user_unload_context);
759 if (copy_from_user(&req, (void __user *)arg, sizeof(req)))
762 gru_dbg(grudev, "gseg 0x%lx\n", req.gseg);
765 return gru_unload_all_contexts();
767 gts = gru_find_lock_gts(req.gseg);
772 gru_unload_context(gts, 1);
779 * User request to flush a range of virtual addresses from the GRU TLB
780 * (Mainly for testing).
782 int gru_user_flush_tlb(unsigned long arg)
784 struct gru_thread_state *gts;
785 struct gru_flush_tlb_req req;
786 struct gru_mm_struct *gms;
788 STAT(user_flush_tlb);
789 if (copy_from_user(&req, (void __user *)arg, sizeof(req)))
792 gru_dbg(grudev, "gseg 0x%lx, vaddr 0x%lx, len 0x%lx\n", req.gseg,
795 gts = gru_find_lock_gts(req.gseg);
801 gru_flush_tlb_range(gms, req.vaddr, req.len);
807 * Fetch GSEG statisticss
809 long gru_get_gseg_statistics(unsigned long arg)
811 struct gru_thread_state *gts;
812 struct gru_get_gseg_statistics_req req;
814 if (copy_from_user(&req, (void __user *)arg, sizeof(req)))
818 * The library creates arrays of contexts for threaded programs.
819 * If no gts exists in the array, the context has never been used & all
820 * statistics are implicitly 0.
822 gts = gru_find_lock_gts(req.gseg);
824 memcpy(&req.stats, >s->ustats, sizeof(gts->ustats));
827 memset(&req.stats, 0, sizeof(gts->ustats));
830 if (copy_to_user((void __user *)arg, &req, sizeof(req)))
837 * Register the current task as the user of the GSEG slice.
838 * Needed for TLB fault interrupt targeting.
840 int gru_set_context_option(unsigned long arg)
842 struct gru_thread_state *gts;
843 struct gru_set_context_option_req req;
846 STAT(set_context_option);
847 if (copy_from_user(&req, (void __user *)arg, sizeof(req)))
849 gru_dbg(grudev, "op %d, gseg 0x%lx, value1 0x%lx\n", req.op, req.gseg, req.val1);
851 gts = gru_find_lock_gts(req.gseg);
853 gts = gru_alloc_locked_gts(req.gseg);
859 case sco_blade_chiplet:
860 /* Select blade/chiplet for GRU context */
861 if (req.val1 < -1 || req.val1 >= GRU_MAX_BLADES || !gru_base[req.val1] ||
862 req.val0 < -1 || req.val0 >= GRU_CHIPLETS_PER_HUB) {
865 gts->ts_user_blade_id = req.val1;
866 gts->ts_user_chiplet_id = req.val0;
867 gru_check_context_placement(gts);
871 /* Register the current task as the GSEG owner */
872 gts->ts_tgid_owner = current->tgid;
874 case sco_cch_req_slice:
875 /* Set the CCH slice option */
876 gts->ts_cch_req_slice = req.val1 & 3;