2 * wm8350-core.c -- Device access for Wolfson WM8350
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
6 * Author: Liam Girdwood, Mark Brown
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/bug.h>
19 #include <linux/device.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/workqueue.h>
24 #include <linux/mfd/wm8350/core.h>
25 #include <linux/mfd/wm8350/audio.h>
26 #include <linux/mfd/wm8350/comparator.h>
27 #include <linux/mfd/wm8350/gpio.h>
28 #include <linux/mfd/wm8350/pmic.h>
29 #include <linux/mfd/wm8350/rtc.h>
30 #include <linux/mfd/wm8350/supply.h>
31 #include <linux/mfd/wm8350/wdt.h>
33 #define WM8350_UNLOCK_KEY 0x0013
34 #define WM8350_LOCK_KEY 0x0000
36 #define WM8350_CLOCK_CONTROL_1 0x28
37 #define WM8350_AIF_TEST 0x74
40 #define WM8350_BUS_DEBUG 0
42 #define dump(regs, src) do { \
46 for (i_ = 0; i_ < regs; i_++) \
47 printk(" 0x%4.4x", *src_++); \
51 #define dump(bytes, src)
54 #define WM8350_LOCK_DEBUG 0
56 #define ldbg(format, arg...) printk(format, ## arg)
58 #define ldbg(format, arg...)
64 static DEFINE_MUTEX(io_mutex);
65 static DEFINE_MUTEX(reg_lock_mutex);
66 static DEFINE_MUTEX(auxadc_mutex);
68 /* Perform a physical read from the device.
70 static int wm8350_phys_read(struct wm8350 *wm8350, u8 reg, int num_regs,
74 int bytes = num_regs * 2;
76 dev_dbg(wm8350->dev, "volatile read\n");
77 ret = wm8350->read_dev(wm8350, reg, bytes, (char *)dest);
79 for (i = reg; i < reg + num_regs; i++) {
80 /* Cache is CPU endian */
81 dest[i - reg] = be16_to_cpu(dest[i - reg]);
83 /* Satisfy non-volatile bits from cache */
84 dest[i - reg] &= wm8350_reg_io_map[i].vol;
85 dest[i - reg] |= wm8350->reg_cache[i];
87 /* Mask out non-readable bits */
88 dest[i - reg] &= wm8350_reg_io_map[i].readable;
96 static int wm8350_read(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *dest)
99 int end = reg + num_regs;
101 int bytes = num_regs * 2;
103 if (wm8350->read_dev == NULL)
106 if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
107 dev_err(wm8350->dev, "invalid reg %x\n",
113 "%s R%d(0x%2.2x) %d regs\n", __func__, reg, reg, num_regs);
116 /* we can _safely_ read any register, but warn if read not supported */
117 for (i = reg; i < end; i++) {
118 if (!wm8350_reg_io_map[i].readable)
119 dev_warn(wm8350->dev,
120 "reg R%d is not readable\n", i);
124 /* if any volatile registers are required, then read back all */
125 for (i = reg; i < end; i++)
126 if (wm8350_reg_io_map[i].vol)
127 return wm8350_phys_read(wm8350, reg, num_regs, dest);
129 /* no volatiles, then cache is good */
130 dev_dbg(wm8350->dev, "cache read\n");
131 memcpy(dest, &wm8350->reg_cache[reg], bytes);
132 dump(num_regs, dest);
136 static inline int is_reg_locked(struct wm8350 *wm8350, u8 reg)
138 if (reg == WM8350_SECURITY ||
139 wm8350->reg_cache[WM8350_SECURITY] == WM8350_UNLOCK_KEY)
142 if ((reg == WM8350_GPIO_CONFIGURATION_I_O) ||
143 (reg >= WM8350_GPIO_FUNCTION_SELECT_1 &&
144 reg <= WM8350_GPIO_FUNCTION_SELECT_4) ||
145 (reg >= WM8350_BATTERY_CHARGER_CONTROL_1 &&
146 reg <= WM8350_BATTERY_CHARGER_CONTROL_3))
151 static int wm8350_write(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *src)
154 int end = reg + num_regs;
155 int bytes = num_regs * 2;
157 if (wm8350->write_dev == NULL)
160 if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
161 dev_err(wm8350->dev, "invalid reg %x\n",
166 /* it's generally not a good idea to write to RO or locked registers */
167 for (i = reg; i < end; i++) {
168 if (!wm8350_reg_io_map[i].writable) {
170 "attempted write to read only reg R%d\n", i);
174 if (is_reg_locked(wm8350, i)) {
176 "attempted write to locked reg R%d\n", i);
180 src[i - reg] &= wm8350_reg_io_map[i].writable;
182 wm8350->reg_cache[i] =
183 (wm8350->reg_cache[i] & ~wm8350_reg_io_map[i].writable)
186 /* Don't store volatile bits */
187 wm8350->reg_cache[i] &= ~wm8350_reg_io_map[i].vol;
189 src[i - reg] = cpu_to_be16(src[i - reg]);
192 /* Actually write it out */
193 return wm8350->write_dev(wm8350, reg, bytes, (char *)src);
197 * Safe read, modify, write methods
199 int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
204 mutex_lock(&io_mutex);
205 err = wm8350_read(wm8350, reg, 1, &data);
207 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
212 err = wm8350_write(wm8350, reg, 1, &data);
214 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
216 mutex_unlock(&io_mutex);
219 EXPORT_SYMBOL_GPL(wm8350_clear_bits);
221 int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
226 mutex_lock(&io_mutex);
227 err = wm8350_read(wm8350, reg, 1, &data);
229 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
234 err = wm8350_write(wm8350, reg, 1, &data);
236 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
238 mutex_unlock(&io_mutex);
241 EXPORT_SYMBOL_GPL(wm8350_set_bits);
243 u16 wm8350_reg_read(struct wm8350 *wm8350, int reg)
248 mutex_lock(&io_mutex);
249 err = wm8350_read(wm8350, reg, 1, &data);
251 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
253 mutex_unlock(&io_mutex);
256 EXPORT_SYMBOL_GPL(wm8350_reg_read);
258 int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val)
263 mutex_lock(&io_mutex);
264 ret = wm8350_write(wm8350, reg, 1, &data);
266 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
267 mutex_unlock(&io_mutex);
270 EXPORT_SYMBOL_GPL(wm8350_reg_write);
272 int wm8350_block_read(struct wm8350 *wm8350, int start_reg, int regs,
277 mutex_lock(&io_mutex);
278 err = wm8350_read(wm8350, start_reg, regs, dest);
280 dev_err(wm8350->dev, "block read starting from R%d failed\n",
282 mutex_unlock(&io_mutex);
285 EXPORT_SYMBOL_GPL(wm8350_block_read);
287 int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs,
292 mutex_lock(&io_mutex);
293 ret = wm8350_write(wm8350, start_reg, regs, src);
295 dev_err(wm8350->dev, "block write starting at R%d failed\n",
297 mutex_unlock(&io_mutex);
300 EXPORT_SYMBOL_GPL(wm8350_block_write);
305 * The WM8350 has a hardware lock which can be used to prevent writes to
306 * some registers (generally those which can cause particularly serious
307 * problems if misused). This function enables that lock.
309 int wm8350_reg_lock(struct wm8350 *wm8350)
311 u16 key = WM8350_LOCK_KEY;
315 mutex_lock(&io_mutex);
316 ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
318 dev_err(wm8350->dev, "lock failed\n");
319 mutex_unlock(&io_mutex);
322 EXPORT_SYMBOL_GPL(wm8350_reg_lock);
325 * wm8350_reg_unlock()
327 * The WM8350 has a hardware lock which can be used to prevent writes to
328 * some registers (generally those which can cause particularly serious
329 * problems if misused). This function disables that lock so updates
330 * can be performed. For maximum safety this should be done only when
333 int wm8350_reg_unlock(struct wm8350 *wm8350)
335 u16 key = WM8350_UNLOCK_KEY;
339 mutex_lock(&io_mutex);
340 ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
342 dev_err(wm8350->dev, "unlock failed\n");
343 mutex_unlock(&io_mutex);
346 EXPORT_SYMBOL_GPL(wm8350_reg_unlock);
348 static void wm8350_irq_call_handler(struct wm8350 *wm8350, int irq)
350 mutex_lock(&wm8350->irq_mutex);
352 if (wm8350->irq[irq].handler)
353 wm8350->irq[irq].handler(wm8350, irq, wm8350->irq[irq].data);
355 dev_err(wm8350->dev, "irq %d nobody cared. now masked.\n",
357 wm8350_mask_irq(wm8350, irq);
360 mutex_unlock(&wm8350->irq_mutex);
364 * wm8350_irq_worker actually handles the interrupts. Since all
365 * interrupts are clear on read the IRQ line will be reasserted and
366 * the physical IRQ will be handled again if another interrupt is
367 * asserted while we run - in the normal course of events this is a
368 * rare occurrence so we save I2C/SPI reads.
370 static void wm8350_irq_worker(struct work_struct *work)
372 struct wm8350 *wm8350 = container_of(work, struct wm8350, irq_work);
373 u16 level_one, status1, status2, comp;
375 /* TODO: Use block reads to improve performance? */
376 level_one = wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS)
377 & ~wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK);
378 status1 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_1)
379 & ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_1_MASK);
380 status2 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_2)
381 & ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_2_MASK);
382 comp = wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS)
383 & ~wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS_MASK);
386 if (level_one & WM8350_OC_INT) {
389 oc = wm8350_reg_read(wm8350, WM8350_OVER_CURRENT_INT_STATUS);
390 oc &= ~wm8350_reg_read(wm8350,
391 WM8350_OVER_CURRENT_INT_STATUS_MASK);
393 if (oc & WM8350_OC_LS_EINT) /* limit switch */
394 wm8350_irq_call_handler(wm8350, WM8350_IRQ_OC_LS);
398 if (level_one & WM8350_UV_INT) {
401 uv = wm8350_reg_read(wm8350, WM8350_UNDER_VOLTAGE_INT_STATUS);
402 uv &= ~wm8350_reg_read(wm8350,
403 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK);
405 if (uv & WM8350_UV_DC1_EINT)
406 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC1);
407 if (uv & WM8350_UV_DC2_EINT)
408 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC2);
409 if (uv & WM8350_UV_DC3_EINT)
410 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC3);
411 if (uv & WM8350_UV_DC4_EINT)
412 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC4);
413 if (uv & WM8350_UV_DC5_EINT)
414 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC5);
415 if (uv & WM8350_UV_DC6_EINT)
416 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC6);
417 if (uv & WM8350_UV_LDO1_EINT)
418 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO1);
419 if (uv & WM8350_UV_LDO2_EINT)
420 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO2);
421 if (uv & WM8350_UV_LDO3_EINT)
422 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO3);
423 if (uv & WM8350_UV_LDO4_EINT)
424 wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO4);
429 if (status1 & WM8350_CHG_BAT_HOT_EINT)
430 wm8350_irq_call_handler(wm8350,
431 WM8350_IRQ_CHG_BAT_HOT);
432 if (status1 & WM8350_CHG_BAT_COLD_EINT)
433 wm8350_irq_call_handler(wm8350,
434 WM8350_IRQ_CHG_BAT_COLD);
435 if (status1 & WM8350_CHG_BAT_FAIL_EINT)
436 wm8350_irq_call_handler(wm8350,
437 WM8350_IRQ_CHG_BAT_FAIL);
438 if (status1 & WM8350_CHG_TO_EINT)
439 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_TO);
440 if (status1 & WM8350_CHG_END_EINT)
441 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_END);
442 if (status1 & WM8350_CHG_START_EINT)
443 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_START);
444 if (status1 & WM8350_CHG_FAST_RDY_EINT)
445 wm8350_irq_call_handler(wm8350,
446 WM8350_IRQ_CHG_FAST_RDY);
447 if (status1 & WM8350_CHG_VBATT_LT_3P9_EINT)
448 wm8350_irq_call_handler(wm8350,
449 WM8350_IRQ_CHG_VBATT_LT_3P9);
450 if (status1 & WM8350_CHG_VBATT_LT_3P1_EINT)
451 wm8350_irq_call_handler(wm8350,
452 WM8350_IRQ_CHG_VBATT_LT_3P1);
453 if (status1 & WM8350_CHG_VBATT_LT_2P85_EINT)
454 wm8350_irq_call_handler(wm8350,
455 WM8350_IRQ_CHG_VBATT_LT_2P85);
456 if (status1 & WM8350_RTC_ALM_EINT)
457 wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_ALM);
458 if (status1 & WM8350_RTC_SEC_EINT)
459 wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_SEC);
460 if (status1 & WM8350_RTC_PER_EINT)
461 wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_PER);
464 /* current sink, system, aux adc */
466 if (status2 & WM8350_CS1_EINT)
467 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS1);
468 if (status2 & WM8350_CS2_EINT)
469 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS2);
471 if (status2 & WM8350_SYS_HYST_COMP_FAIL_EINT)
472 wm8350_irq_call_handler(wm8350,
473 WM8350_IRQ_SYS_HYST_COMP_FAIL);
474 if (status2 & WM8350_SYS_CHIP_GT115_EINT)
475 wm8350_irq_call_handler(wm8350,
476 WM8350_IRQ_SYS_CHIP_GT115);
477 if (status2 & WM8350_SYS_CHIP_GT140_EINT)
478 wm8350_irq_call_handler(wm8350,
479 WM8350_IRQ_SYS_CHIP_GT140);
480 if (status2 & WM8350_SYS_WDOG_TO_EINT)
481 wm8350_irq_call_handler(wm8350,
482 WM8350_IRQ_SYS_WDOG_TO);
484 if (status2 & WM8350_AUXADC_DATARDY_EINT)
485 wm8350_irq_call_handler(wm8350,
486 WM8350_IRQ_AUXADC_DATARDY);
487 if (status2 & WM8350_AUXADC_DCOMP4_EINT)
488 wm8350_irq_call_handler(wm8350,
489 WM8350_IRQ_AUXADC_DCOMP4);
490 if (status2 & WM8350_AUXADC_DCOMP3_EINT)
491 wm8350_irq_call_handler(wm8350,
492 WM8350_IRQ_AUXADC_DCOMP3);
493 if (status2 & WM8350_AUXADC_DCOMP2_EINT)
494 wm8350_irq_call_handler(wm8350,
495 WM8350_IRQ_AUXADC_DCOMP2);
496 if (status2 & WM8350_AUXADC_DCOMP1_EINT)
497 wm8350_irq_call_handler(wm8350,
498 WM8350_IRQ_AUXADC_DCOMP1);
500 if (status2 & WM8350_USB_LIMIT_EINT)
501 wm8350_irq_call_handler(wm8350, WM8350_IRQ_USB_LIMIT);
504 /* wake, codec, ext */
506 if (comp & WM8350_WKUP_OFF_STATE_EINT)
507 wm8350_irq_call_handler(wm8350,
508 WM8350_IRQ_WKUP_OFF_STATE);
509 if (comp & WM8350_WKUP_HIB_STATE_EINT)
510 wm8350_irq_call_handler(wm8350,
511 WM8350_IRQ_WKUP_HIB_STATE);
512 if (comp & WM8350_WKUP_CONV_FAULT_EINT)
513 wm8350_irq_call_handler(wm8350,
514 WM8350_IRQ_WKUP_CONV_FAULT);
515 if (comp & WM8350_WKUP_WDOG_RST_EINT)
516 wm8350_irq_call_handler(wm8350,
517 WM8350_IRQ_WKUP_WDOG_RST);
518 if (comp & WM8350_WKUP_GP_PWR_ON_EINT)
519 wm8350_irq_call_handler(wm8350,
520 WM8350_IRQ_WKUP_GP_PWR_ON);
521 if (comp & WM8350_WKUP_ONKEY_EINT)
522 wm8350_irq_call_handler(wm8350, WM8350_IRQ_WKUP_ONKEY);
523 if (comp & WM8350_WKUP_GP_WAKEUP_EINT)
524 wm8350_irq_call_handler(wm8350,
525 WM8350_IRQ_WKUP_GP_WAKEUP);
527 if (comp & WM8350_CODEC_JCK_DET_L_EINT)
528 wm8350_irq_call_handler(wm8350,
529 WM8350_IRQ_CODEC_JCK_DET_L);
530 if (comp & WM8350_CODEC_JCK_DET_R_EINT)
531 wm8350_irq_call_handler(wm8350,
532 WM8350_IRQ_CODEC_JCK_DET_R);
533 if (comp & WM8350_CODEC_MICSCD_EINT)
534 wm8350_irq_call_handler(wm8350,
535 WM8350_IRQ_CODEC_MICSCD);
536 if (comp & WM8350_CODEC_MICD_EINT)
537 wm8350_irq_call_handler(wm8350, WM8350_IRQ_CODEC_MICD);
539 if (comp & WM8350_EXT_USB_FB_EINT)
540 wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_USB_FB);
541 if (comp & WM8350_EXT_WALL_FB_EINT)
542 wm8350_irq_call_handler(wm8350,
543 WM8350_IRQ_EXT_WALL_FB);
544 if (comp & WM8350_EXT_BAT_FB_EINT)
545 wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_BAT_FB);
548 if (level_one & WM8350_GP_INT) {
552 gpio = wm8350_reg_read(wm8350, WM8350_GPIO_INT_STATUS);
553 gpio &= ~wm8350_reg_read(wm8350,
554 WM8350_GPIO_INT_STATUS_MASK);
556 for (i = 0; i < 12; i++) {
558 wm8350_irq_call_handler(wm8350,
563 enable_irq(wm8350->chip_irq);
566 static irqreturn_t wm8350_irq(int irq, void *data)
568 struct wm8350 *wm8350 = data;
570 disable_irq_nosync(irq);
571 schedule_work(&wm8350->irq_work);
576 int wm8350_register_irq(struct wm8350 *wm8350, int irq,
577 void (*handler) (struct wm8350 *, int, void *),
580 if (irq < 0 || irq > WM8350_NUM_IRQ || !handler)
583 if (wm8350->irq[irq].handler)
586 mutex_lock(&wm8350->irq_mutex);
587 wm8350->irq[irq].handler = handler;
588 wm8350->irq[irq].data = data;
589 mutex_unlock(&wm8350->irq_mutex);
593 EXPORT_SYMBOL_GPL(wm8350_register_irq);
595 int wm8350_free_irq(struct wm8350 *wm8350, int irq)
597 if (irq < 0 || irq > WM8350_NUM_IRQ)
600 mutex_lock(&wm8350->irq_mutex);
601 wm8350->irq[irq].handler = NULL;
602 mutex_unlock(&wm8350->irq_mutex);
605 EXPORT_SYMBOL_GPL(wm8350_free_irq);
607 int wm8350_mask_irq(struct wm8350 *wm8350, int irq)
610 case WM8350_IRQ_CHG_BAT_HOT:
611 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
612 WM8350_IM_CHG_BAT_HOT_EINT);
613 case WM8350_IRQ_CHG_BAT_COLD:
614 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
615 WM8350_IM_CHG_BAT_COLD_EINT);
616 case WM8350_IRQ_CHG_BAT_FAIL:
617 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
618 WM8350_IM_CHG_BAT_FAIL_EINT);
619 case WM8350_IRQ_CHG_TO:
620 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
621 WM8350_IM_CHG_TO_EINT);
622 case WM8350_IRQ_CHG_END:
623 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
624 WM8350_IM_CHG_END_EINT);
625 case WM8350_IRQ_CHG_START:
626 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
627 WM8350_IM_CHG_START_EINT);
628 case WM8350_IRQ_CHG_FAST_RDY:
629 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
630 WM8350_IM_CHG_FAST_RDY_EINT);
631 case WM8350_IRQ_RTC_PER:
632 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
633 WM8350_IM_RTC_PER_EINT);
634 case WM8350_IRQ_RTC_SEC:
635 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
636 WM8350_IM_RTC_SEC_EINT);
637 case WM8350_IRQ_RTC_ALM:
638 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
639 WM8350_IM_RTC_ALM_EINT);
640 case WM8350_IRQ_CHG_VBATT_LT_3P9:
641 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
642 WM8350_IM_CHG_VBATT_LT_3P9_EINT);
643 case WM8350_IRQ_CHG_VBATT_LT_3P1:
644 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
645 WM8350_IM_CHG_VBATT_LT_3P1_EINT);
646 case WM8350_IRQ_CHG_VBATT_LT_2P85:
647 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
648 WM8350_IM_CHG_VBATT_LT_2P85_EINT);
650 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
653 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
655 case WM8350_IRQ_USB_LIMIT:
656 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
657 WM8350_IM_USB_LIMIT_EINT);
658 case WM8350_IRQ_AUXADC_DATARDY:
659 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
660 WM8350_IM_AUXADC_DATARDY_EINT);
661 case WM8350_IRQ_AUXADC_DCOMP4:
662 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
663 WM8350_IM_AUXADC_DCOMP4_EINT);
664 case WM8350_IRQ_AUXADC_DCOMP3:
665 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
666 WM8350_IM_AUXADC_DCOMP3_EINT);
667 case WM8350_IRQ_AUXADC_DCOMP2:
668 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
669 WM8350_IM_AUXADC_DCOMP2_EINT);
670 case WM8350_IRQ_AUXADC_DCOMP1:
671 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
672 WM8350_IM_AUXADC_DCOMP1_EINT);
673 case WM8350_IRQ_SYS_HYST_COMP_FAIL:
674 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
675 WM8350_IM_SYS_HYST_COMP_FAIL_EINT);
676 case WM8350_IRQ_SYS_CHIP_GT115:
677 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
678 WM8350_IM_SYS_CHIP_GT115_EINT);
679 case WM8350_IRQ_SYS_CHIP_GT140:
680 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
681 WM8350_IM_SYS_CHIP_GT140_EINT);
682 case WM8350_IRQ_SYS_WDOG_TO:
683 return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
684 WM8350_IM_SYS_WDOG_TO_EINT);
685 case WM8350_IRQ_UV_LDO4:
686 return wm8350_set_bits(wm8350,
687 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
688 WM8350_IM_UV_LDO4_EINT);
689 case WM8350_IRQ_UV_LDO3:
690 return wm8350_set_bits(wm8350,
691 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
692 WM8350_IM_UV_LDO3_EINT);
693 case WM8350_IRQ_UV_LDO2:
694 return wm8350_set_bits(wm8350,
695 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
696 WM8350_IM_UV_LDO2_EINT);
697 case WM8350_IRQ_UV_LDO1:
698 return wm8350_set_bits(wm8350,
699 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
700 WM8350_IM_UV_LDO1_EINT);
701 case WM8350_IRQ_UV_DC6:
702 return wm8350_set_bits(wm8350,
703 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
704 WM8350_IM_UV_DC6_EINT);
705 case WM8350_IRQ_UV_DC5:
706 return wm8350_set_bits(wm8350,
707 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
708 WM8350_IM_UV_DC5_EINT);
709 case WM8350_IRQ_UV_DC4:
710 return wm8350_set_bits(wm8350,
711 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
712 WM8350_IM_UV_DC4_EINT);
713 case WM8350_IRQ_UV_DC3:
714 return wm8350_set_bits(wm8350,
715 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
716 WM8350_IM_UV_DC3_EINT);
717 case WM8350_IRQ_UV_DC2:
718 return wm8350_set_bits(wm8350,
719 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
720 WM8350_IM_UV_DC2_EINT);
721 case WM8350_IRQ_UV_DC1:
722 return wm8350_set_bits(wm8350,
723 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
724 WM8350_IM_UV_DC1_EINT);
725 case WM8350_IRQ_OC_LS:
726 return wm8350_set_bits(wm8350,
727 WM8350_OVER_CURRENT_INT_STATUS_MASK,
728 WM8350_IM_OC_LS_EINT);
729 case WM8350_IRQ_EXT_USB_FB:
730 return wm8350_set_bits(wm8350,
731 WM8350_COMPARATOR_INT_STATUS_MASK,
732 WM8350_IM_EXT_USB_FB_EINT);
733 case WM8350_IRQ_EXT_WALL_FB:
734 return wm8350_set_bits(wm8350,
735 WM8350_COMPARATOR_INT_STATUS_MASK,
736 WM8350_IM_EXT_WALL_FB_EINT);
737 case WM8350_IRQ_EXT_BAT_FB:
738 return wm8350_set_bits(wm8350,
739 WM8350_COMPARATOR_INT_STATUS_MASK,
740 WM8350_IM_EXT_BAT_FB_EINT);
741 case WM8350_IRQ_CODEC_JCK_DET_L:
742 return wm8350_set_bits(wm8350,
743 WM8350_COMPARATOR_INT_STATUS_MASK,
744 WM8350_IM_CODEC_JCK_DET_L_EINT);
745 case WM8350_IRQ_CODEC_JCK_DET_R:
746 return wm8350_set_bits(wm8350,
747 WM8350_COMPARATOR_INT_STATUS_MASK,
748 WM8350_IM_CODEC_JCK_DET_R_EINT);
749 case WM8350_IRQ_CODEC_MICSCD:
750 return wm8350_set_bits(wm8350,
751 WM8350_COMPARATOR_INT_STATUS_MASK,
752 WM8350_IM_CODEC_MICSCD_EINT);
753 case WM8350_IRQ_CODEC_MICD:
754 return wm8350_set_bits(wm8350,
755 WM8350_COMPARATOR_INT_STATUS_MASK,
756 WM8350_IM_CODEC_MICD_EINT);
757 case WM8350_IRQ_WKUP_OFF_STATE:
758 return wm8350_set_bits(wm8350,
759 WM8350_COMPARATOR_INT_STATUS_MASK,
760 WM8350_IM_WKUP_OFF_STATE_EINT);
761 case WM8350_IRQ_WKUP_HIB_STATE:
762 return wm8350_set_bits(wm8350,
763 WM8350_COMPARATOR_INT_STATUS_MASK,
764 WM8350_IM_WKUP_HIB_STATE_EINT);
765 case WM8350_IRQ_WKUP_CONV_FAULT:
766 return wm8350_set_bits(wm8350,
767 WM8350_COMPARATOR_INT_STATUS_MASK,
768 WM8350_IM_WKUP_CONV_FAULT_EINT);
769 case WM8350_IRQ_WKUP_WDOG_RST:
770 return wm8350_set_bits(wm8350,
771 WM8350_COMPARATOR_INT_STATUS_MASK,
772 WM8350_IM_WKUP_OFF_STATE_EINT);
773 case WM8350_IRQ_WKUP_GP_PWR_ON:
774 return wm8350_set_bits(wm8350,
775 WM8350_COMPARATOR_INT_STATUS_MASK,
776 WM8350_IM_WKUP_GP_PWR_ON_EINT);
777 case WM8350_IRQ_WKUP_ONKEY:
778 return wm8350_set_bits(wm8350,
779 WM8350_COMPARATOR_INT_STATUS_MASK,
780 WM8350_IM_WKUP_ONKEY_EINT);
781 case WM8350_IRQ_WKUP_GP_WAKEUP:
782 return wm8350_set_bits(wm8350,
783 WM8350_COMPARATOR_INT_STATUS_MASK,
784 WM8350_IM_WKUP_GP_WAKEUP_EINT);
785 case WM8350_IRQ_GPIO(0):
786 return wm8350_set_bits(wm8350,
787 WM8350_GPIO_INT_STATUS_MASK,
789 case WM8350_IRQ_GPIO(1):
790 return wm8350_set_bits(wm8350,
791 WM8350_GPIO_INT_STATUS_MASK,
793 case WM8350_IRQ_GPIO(2):
794 return wm8350_set_bits(wm8350,
795 WM8350_GPIO_INT_STATUS_MASK,
797 case WM8350_IRQ_GPIO(3):
798 return wm8350_set_bits(wm8350,
799 WM8350_GPIO_INT_STATUS_MASK,
801 case WM8350_IRQ_GPIO(4):
802 return wm8350_set_bits(wm8350,
803 WM8350_GPIO_INT_STATUS_MASK,
805 case WM8350_IRQ_GPIO(5):
806 return wm8350_set_bits(wm8350,
807 WM8350_GPIO_INT_STATUS_MASK,
809 case WM8350_IRQ_GPIO(6):
810 return wm8350_set_bits(wm8350,
811 WM8350_GPIO_INT_STATUS_MASK,
813 case WM8350_IRQ_GPIO(7):
814 return wm8350_set_bits(wm8350,
815 WM8350_GPIO_INT_STATUS_MASK,
817 case WM8350_IRQ_GPIO(8):
818 return wm8350_set_bits(wm8350,
819 WM8350_GPIO_INT_STATUS_MASK,
821 case WM8350_IRQ_GPIO(9):
822 return wm8350_set_bits(wm8350,
823 WM8350_GPIO_INT_STATUS_MASK,
825 case WM8350_IRQ_GPIO(10):
826 return wm8350_set_bits(wm8350,
827 WM8350_GPIO_INT_STATUS_MASK,
828 WM8350_IM_GP10_EINT);
829 case WM8350_IRQ_GPIO(11):
830 return wm8350_set_bits(wm8350,
831 WM8350_GPIO_INT_STATUS_MASK,
832 WM8350_IM_GP11_EINT);
833 case WM8350_IRQ_GPIO(12):
834 return wm8350_set_bits(wm8350,
835 WM8350_GPIO_INT_STATUS_MASK,
836 WM8350_IM_GP12_EINT);
838 dev_warn(wm8350->dev, "Attempting to mask unknown IRQ %d\n",
844 EXPORT_SYMBOL_GPL(wm8350_mask_irq);
846 int wm8350_unmask_irq(struct wm8350 *wm8350, int irq)
849 case WM8350_IRQ_CHG_BAT_HOT:
850 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
851 WM8350_IM_CHG_BAT_HOT_EINT);
852 case WM8350_IRQ_CHG_BAT_COLD:
853 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
854 WM8350_IM_CHG_BAT_COLD_EINT);
855 case WM8350_IRQ_CHG_BAT_FAIL:
856 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
857 WM8350_IM_CHG_BAT_FAIL_EINT);
858 case WM8350_IRQ_CHG_TO:
859 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
860 WM8350_IM_CHG_TO_EINT);
861 case WM8350_IRQ_CHG_END:
862 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
863 WM8350_IM_CHG_END_EINT);
864 case WM8350_IRQ_CHG_START:
865 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
866 WM8350_IM_CHG_START_EINT);
867 case WM8350_IRQ_CHG_FAST_RDY:
868 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
869 WM8350_IM_CHG_FAST_RDY_EINT);
870 case WM8350_IRQ_RTC_PER:
871 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
872 WM8350_IM_RTC_PER_EINT);
873 case WM8350_IRQ_RTC_SEC:
874 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
875 WM8350_IM_RTC_SEC_EINT);
876 case WM8350_IRQ_RTC_ALM:
877 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
878 WM8350_IM_RTC_ALM_EINT);
879 case WM8350_IRQ_CHG_VBATT_LT_3P9:
880 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
881 WM8350_IM_CHG_VBATT_LT_3P9_EINT);
882 case WM8350_IRQ_CHG_VBATT_LT_3P1:
883 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
884 WM8350_IM_CHG_VBATT_LT_3P1_EINT);
885 case WM8350_IRQ_CHG_VBATT_LT_2P85:
886 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
887 WM8350_IM_CHG_VBATT_LT_2P85_EINT);
889 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
892 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
894 case WM8350_IRQ_USB_LIMIT:
895 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
896 WM8350_IM_USB_LIMIT_EINT);
897 case WM8350_IRQ_AUXADC_DATARDY:
898 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
899 WM8350_IM_AUXADC_DATARDY_EINT);
900 case WM8350_IRQ_AUXADC_DCOMP4:
901 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
902 WM8350_IM_AUXADC_DCOMP4_EINT);
903 case WM8350_IRQ_AUXADC_DCOMP3:
904 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
905 WM8350_IM_AUXADC_DCOMP3_EINT);
906 case WM8350_IRQ_AUXADC_DCOMP2:
907 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
908 WM8350_IM_AUXADC_DCOMP2_EINT);
909 case WM8350_IRQ_AUXADC_DCOMP1:
910 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
911 WM8350_IM_AUXADC_DCOMP1_EINT);
912 case WM8350_IRQ_SYS_HYST_COMP_FAIL:
913 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
914 WM8350_IM_SYS_HYST_COMP_FAIL_EINT);
915 case WM8350_IRQ_SYS_CHIP_GT115:
916 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
917 WM8350_IM_SYS_CHIP_GT115_EINT);
918 case WM8350_IRQ_SYS_CHIP_GT140:
919 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
920 WM8350_IM_SYS_CHIP_GT140_EINT);
921 case WM8350_IRQ_SYS_WDOG_TO:
922 return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
923 WM8350_IM_SYS_WDOG_TO_EINT);
924 case WM8350_IRQ_UV_LDO4:
925 return wm8350_clear_bits(wm8350,
926 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
927 WM8350_IM_UV_LDO4_EINT);
928 case WM8350_IRQ_UV_LDO3:
929 return wm8350_clear_bits(wm8350,
930 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
931 WM8350_IM_UV_LDO3_EINT);
932 case WM8350_IRQ_UV_LDO2:
933 return wm8350_clear_bits(wm8350,
934 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
935 WM8350_IM_UV_LDO2_EINT);
936 case WM8350_IRQ_UV_LDO1:
937 return wm8350_clear_bits(wm8350,
938 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
939 WM8350_IM_UV_LDO1_EINT);
940 case WM8350_IRQ_UV_DC6:
941 return wm8350_clear_bits(wm8350,
942 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
943 WM8350_IM_UV_DC6_EINT);
944 case WM8350_IRQ_UV_DC5:
945 return wm8350_clear_bits(wm8350,
946 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
947 WM8350_IM_UV_DC5_EINT);
948 case WM8350_IRQ_UV_DC4:
949 return wm8350_clear_bits(wm8350,
950 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
951 WM8350_IM_UV_DC4_EINT);
952 case WM8350_IRQ_UV_DC3:
953 return wm8350_clear_bits(wm8350,
954 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
955 WM8350_IM_UV_DC3_EINT);
956 case WM8350_IRQ_UV_DC2:
957 return wm8350_clear_bits(wm8350,
958 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
959 WM8350_IM_UV_DC2_EINT);
960 case WM8350_IRQ_UV_DC1:
961 return wm8350_clear_bits(wm8350,
962 WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
963 WM8350_IM_UV_DC1_EINT);
964 case WM8350_IRQ_OC_LS:
965 return wm8350_clear_bits(wm8350,
966 WM8350_OVER_CURRENT_INT_STATUS_MASK,
967 WM8350_IM_OC_LS_EINT);
968 case WM8350_IRQ_EXT_USB_FB:
969 return wm8350_clear_bits(wm8350,
970 WM8350_COMPARATOR_INT_STATUS_MASK,
971 WM8350_IM_EXT_USB_FB_EINT);
972 case WM8350_IRQ_EXT_WALL_FB:
973 return wm8350_clear_bits(wm8350,
974 WM8350_COMPARATOR_INT_STATUS_MASK,
975 WM8350_IM_EXT_WALL_FB_EINT);
976 case WM8350_IRQ_EXT_BAT_FB:
977 return wm8350_clear_bits(wm8350,
978 WM8350_COMPARATOR_INT_STATUS_MASK,
979 WM8350_IM_EXT_BAT_FB_EINT);
980 case WM8350_IRQ_CODEC_JCK_DET_L:
981 return wm8350_clear_bits(wm8350,
982 WM8350_COMPARATOR_INT_STATUS_MASK,
983 WM8350_IM_CODEC_JCK_DET_L_EINT);
984 case WM8350_IRQ_CODEC_JCK_DET_R:
985 return wm8350_clear_bits(wm8350,
986 WM8350_COMPARATOR_INT_STATUS_MASK,
987 WM8350_IM_CODEC_JCK_DET_R_EINT);
988 case WM8350_IRQ_CODEC_MICSCD:
989 return wm8350_clear_bits(wm8350,
990 WM8350_COMPARATOR_INT_STATUS_MASK,
991 WM8350_IM_CODEC_MICSCD_EINT);
992 case WM8350_IRQ_CODEC_MICD:
993 return wm8350_clear_bits(wm8350,
994 WM8350_COMPARATOR_INT_STATUS_MASK,
995 WM8350_IM_CODEC_MICD_EINT);
996 case WM8350_IRQ_WKUP_OFF_STATE:
997 return wm8350_clear_bits(wm8350,
998 WM8350_COMPARATOR_INT_STATUS_MASK,
999 WM8350_IM_WKUP_OFF_STATE_EINT);
1000 case WM8350_IRQ_WKUP_HIB_STATE:
1001 return wm8350_clear_bits(wm8350,
1002 WM8350_COMPARATOR_INT_STATUS_MASK,
1003 WM8350_IM_WKUP_HIB_STATE_EINT);
1004 case WM8350_IRQ_WKUP_CONV_FAULT:
1005 return wm8350_clear_bits(wm8350,
1006 WM8350_COMPARATOR_INT_STATUS_MASK,
1007 WM8350_IM_WKUP_CONV_FAULT_EINT);
1008 case WM8350_IRQ_WKUP_WDOG_RST:
1009 return wm8350_clear_bits(wm8350,
1010 WM8350_COMPARATOR_INT_STATUS_MASK,
1011 WM8350_IM_WKUP_OFF_STATE_EINT);
1012 case WM8350_IRQ_WKUP_GP_PWR_ON:
1013 return wm8350_clear_bits(wm8350,
1014 WM8350_COMPARATOR_INT_STATUS_MASK,
1015 WM8350_IM_WKUP_GP_PWR_ON_EINT);
1016 case WM8350_IRQ_WKUP_ONKEY:
1017 return wm8350_clear_bits(wm8350,
1018 WM8350_COMPARATOR_INT_STATUS_MASK,
1019 WM8350_IM_WKUP_ONKEY_EINT);
1020 case WM8350_IRQ_WKUP_GP_WAKEUP:
1021 return wm8350_clear_bits(wm8350,
1022 WM8350_COMPARATOR_INT_STATUS_MASK,
1023 WM8350_IM_WKUP_GP_WAKEUP_EINT);
1024 case WM8350_IRQ_GPIO(0):
1025 return wm8350_clear_bits(wm8350,
1026 WM8350_GPIO_INT_STATUS_MASK,
1027 WM8350_IM_GP0_EINT);
1028 case WM8350_IRQ_GPIO(1):
1029 return wm8350_clear_bits(wm8350,
1030 WM8350_GPIO_INT_STATUS_MASK,
1031 WM8350_IM_GP1_EINT);
1032 case WM8350_IRQ_GPIO(2):
1033 return wm8350_clear_bits(wm8350,
1034 WM8350_GPIO_INT_STATUS_MASK,
1035 WM8350_IM_GP2_EINT);
1036 case WM8350_IRQ_GPIO(3):
1037 return wm8350_clear_bits(wm8350,
1038 WM8350_GPIO_INT_STATUS_MASK,
1039 WM8350_IM_GP3_EINT);
1040 case WM8350_IRQ_GPIO(4):
1041 return wm8350_clear_bits(wm8350,
1042 WM8350_GPIO_INT_STATUS_MASK,
1043 WM8350_IM_GP4_EINT);
1044 case WM8350_IRQ_GPIO(5):
1045 return wm8350_clear_bits(wm8350,
1046 WM8350_GPIO_INT_STATUS_MASK,
1047 WM8350_IM_GP5_EINT);
1048 case WM8350_IRQ_GPIO(6):
1049 return wm8350_clear_bits(wm8350,
1050 WM8350_GPIO_INT_STATUS_MASK,
1051 WM8350_IM_GP6_EINT);
1052 case WM8350_IRQ_GPIO(7):
1053 return wm8350_clear_bits(wm8350,
1054 WM8350_GPIO_INT_STATUS_MASK,
1055 WM8350_IM_GP7_EINT);
1056 case WM8350_IRQ_GPIO(8):
1057 return wm8350_clear_bits(wm8350,
1058 WM8350_GPIO_INT_STATUS_MASK,
1059 WM8350_IM_GP8_EINT);
1060 case WM8350_IRQ_GPIO(9):
1061 return wm8350_clear_bits(wm8350,
1062 WM8350_GPIO_INT_STATUS_MASK,
1063 WM8350_IM_GP9_EINT);
1064 case WM8350_IRQ_GPIO(10):
1065 return wm8350_clear_bits(wm8350,
1066 WM8350_GPIO_INT_STATUS_MASK,
1067 WM8350_IM_GP10_EINT);
1068 case WM8350_IRQ_GPIO(11):
1069 return wm8350_clear_bits(wm8350,
1070 WM8350_GPIO_INT_STATUS_MASK,
1071 WM8350_IM_GP11_EINT);
1072 case WM8350_IRQ_GPIO(12):
1073 return wm8350_clear_bits(wm8350,
1074 WM8350_GPIO_INT_STATUS_MASK,
1075 WM8350_IM_GP12_EINT);
1077 dev_warn(wm8350->dev, "Attempting to unmask unknown IRQ %d\n",
1083 EXPORT_SYMBOL_GPL(wm8350_unmask_irq);
1086 * Cache is always host endian.
1088 static int wm8350_create_cache(struct wm8350 *wm8350, int mode)
1095 #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0
1097 reg_map = wm8350_mode0_defaults;
1100 #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1
1102 reg_map = wm8350_mode1_defaults;
1105 #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2
1107 reg_map = wm8350_mode2_defaults;
1110 #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3
1112 reg_map = wm8350_mode3_defaults;
1116 dev_err(wm8350->dev, "Configuration mode %d not supported\n",
1122 kzalloc(sizeof(u16) * (WM8350_MAX_REGISTER + 1), GFP_KERNEL);
1123 if (wm8350->reg_cache == NULL)
1126 /* Read the initial cache state back from the device - this is
1127 * a PMIC so the device many not be in a virgin state and we
1128 * can't rely on the silicon values.
1130 for (i = 0; i < WM8350_MAX_REGISTER; i++) {
1131 /* audio register range */
1132 if (wm8350_reg_io_map[i].readable &&
1133 (i < WM8350_CLOCK_CONTROL_1 || i > WM8350_AIF_TEST)) {
1134 ret = wm8350->read_dev(wm8350, i, 2, (char *)&value);
1136 dev_err(wm8350->dev,
1137 "failed to read initial cache value\n");
1140 value = be16_to_cpu(value);
1141 value &= wm8350_reg_io_map[i].readable;
1142 value &= ~wm8350_reg_io_map[i].vol;
1143 wm8350->reg_cache[i] = value;
1145 wm8350->reg_cache[i] = reg_map[i];
1153 * Register a client device. This is non-fatal since there is no need to
1154 * fail the entire device init due to a single platform device failing.
1156 static void wm8350_client_dev_register(struct wm8350 *wm8350,
1158 struct platform_device **pdev)
1162 *pdev = platform_device_alloc(name, -1);
1164 dev_err(wm8350->dev, "Failed to allocate %s\n", name);
1168 (*pdev)->dev.parent = wm8350->dev;
1169 platform_set_drvdata(*pdev, wm8350);
1170 ret = platform_device_add(*pdev);
1172 dev_err(wm8350->dev, "Failed to register %s: %d\n", name, ret);
1173 platform_device_put(*pdev);
1178 int wm8350_device_init(struct wm8350 *wm8350, int irq,
1179 struct wm8350_platform_data *pdata)
1182 u16 id1, id2, mask, mode;
1184 /* get WM8350 revision and config mode */
1185 wm8350->read_dev(wm8350, WM8350_RESET_ID, sizeof(id1), &id1);
1186 wm8350->read_dev(wm8350, WM8350_ID, sizeof(id2), &id2);
1188 id1 = be16_to_cpu(id1);
1189 id2 = be16_to_cpu(id2);
1191 if (id1 == 0x6143) {
1192 switch ((id2 & WM8350_CHIP_REV_MASK) >> 12) {
1194 dev_info(wm8350->dev, "Found Rev E device\n");
1195 wm8350->rev = WM8350_REV_E;
1198 dev_info(wm8350->dev, "Found Rev F device\n");
1199 wm8350->rev = WM8350_REV_F;
1202 dev_info(wm8350->dev, "Found Rev G device\n");
1203 wm8350->rev = WM8350_REV_G;
1206 dev_info(wm8350->dev, "Found Rev H device\n");
1207 wm8350->rev = WM8350_REV_H;
1210 /* For safety we refuse to run on unknown hardware */
1211 dev_info(wm8350->dev, "Found unknown rev %x\n",
1212 (id2 & WM8350_CHIP_REV_MASK) >> 12);
1217 dev_info(wm8350->dev, "Device with ID %x is not a WM8350\n",
1223 mode = id2 & WM8350_CONF_STS_MASK >> 10;
1224 mask = id2 & WM8350_CUST_ID_MASK;
1225 dev_info(wm8350->dev, "Config mode %d, ROM mask %d\n", mode, mask);
1227 ret = wm8350_create_cache(wm8350, mode);
1229 printk(KERN_ERR "wm8350: failed to create register cache\n");
1234 ret = pdata->init(wm8350);
1236 dev_err(wm8350->dev, "Platform init() failed: %d\n",
1242 mutex_init(&wm8350->irq_mutex);
1243 INIT_WORK(&wm8350->irq_work, wm8350_irq_worker);
1245 ret = request_irq(irq, wm8350_irq, 0,
1248 dev_err(wm8350->dev, "Failed to request IRQ: %d\n",
1253 dev_err(wm8350->dev, "No IRQ configured\n");
1256 wm8350->chip_irq = irq;
1258 wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x0);
1260 wm8350_client_dev_register(wm8350, "wm8350-codec",
1261 &(wm8350->codec.pdev));
1262 wm8350_client_dev_register(wm8350, "wm8350-gpio",
1263 &(wm8350->gpio.pdev));
1264 wm8350_client_dev_register(wm8350, "wm8350-power",
1265 &(wm8350->power.pdev));
1266 wm8350_client_dev_register(wm8350, "wm8350-rtc", &(wm8350->rtc.pdev));
1267 wm8350_client_dev_register(wm8350, "wm8350-wdt", &(wm8350->wdt.pdev));
1272 kfree(wm8350->reg_cache);
1275 EXPORT_SYMBOL_GPL(wm8350_device_init);
1277 void wm8350_device_exit(struct wm8350 *wm8350)
1281 for (i = 0; i < ARRAY_SIZE(wm8350->pmic.pdev); i++)
1282 platform_device_unregister(wm8350->pmic.pdev[i]);
1284 platform_device_unregister(wm8350->wdt.pdev);
1285 platform_device_unregister(wm8350->rtc.pdev);
1286 platform_device_unregister(wm8350->power.pdev);
1287 platform_device_unregister(wm8350->gpio.pdev);
1288 platform_device_unregister(wm8350->codec.pdev);
1290 free_irq(wm8350->chip_irq, wm8350);
1291 flush_work(&wm8350->irq_work);
1292 kfree(wm8350->reg_cache);
1294 EXPORT_SYMBOL_GPL(wm8350_device_exit);
1296 MODULE_DESCRIPTION("WM8350 AudioPlus PMIC core driver");
1297 MODULE_LICENSE("GPL");