2 * Driver for Motorola PCAP2 as present in EZX phones
4 * Copyright (C) 2006 Harald Welte <laforge@openezx.org>
5 * Copyright (C) 2009 Daniel Ribeiro <drwyrm@gmail.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/mfd/ezx-pcap.h>
19 #include <linux/spi/spi.h>
21 #define PCAP_ADC_MAXQ 8
22 struct pcap_adc_request {
26 void (*callback)(void *, u16[]);
30 struct pcap_adc_sync_request {
32 struct completion completion;
36 struct spi_device *spi;
40 struct mutex io_mutex;
43 unsigned int irq_base;
45 struct work_struct isr_work;
46 struct work_struct msr_work;
47 struct workqueue_struct *workqueue;
50 struct pcap_adc_request *adc_queue[PCAP_ADC_MAXQ];
53 struct mutex adc_mutex;
57 static int ezx_pcap_putget(struct pcap_chip *pcap, u32 *data)
59 struct spi_transfer t;
63 memset(&t, 0, sizeof t);
66 spi_message_add_tail(&t, &m);
69 t.tx_buf = (u8 *) &pcap->buf;
70 t.rx_buf = (u8 *) &pcap->buf;
71 status = spi_sync(pcap->spi, &m);
79 int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value)
83 mutex_lock(&pcap->io_mutex);
84 value &= PCAP_REGISTER_VALUE_MASK;
85 value |= PCAP_REGISTER_WRITE_OP_BIT
86 | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
87 ret = ezx_pcap_putget(pcap, &value);
88 mutex_unlock(&pcap->io_mutex);
92 EXPORT_SYMBOL_GPL(ezx_pcap_write);
94 int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value)
98 mutex_lock(&pcap->io_mutex);
99 *value = PCAP_REGISTER_READ_OP_BIT
100 | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
102 ret = ezx_pcap_putget(pcap, value);
103 mutex_unlock(&pcap->io_mutex);
107 EXPORT_SYMBOL_GPL(ezx_pcap_read);
110 int irq_to_pcap(struct pcap_chip *pcap, int irq)
112 return irq - pcap->irq_base;
114 EXPORT_SYMBOL_GPL(irq_to_pcap);
116 int pcap_to_irq(struct pcap_chip *pcap, int irq)
118 return pcap->irq_base + irq;
120 EXPORT_SYMBOL_GPL(pcap_to_irq);
122 static void pcap_mask_irq(unsigned int irq)
124 struct pcap_chip *pcap = get_irq_chip_data(irq);
126 pcap->msr |= 1 << irq_to_pcap(pcap, irq);
127 queue_work(pcap->workqueue, &pcap->msr_work);
130 static void pcap_unmask_irq(unsigned int irq)
132 struct pcap_chip *pcap = get_irq_chip_data(irq);
134 pcap->msr &= ~(1 << irq_to_pcap(pcap, irq));
135 queue_work(pcap->workqueue, &pcap->msr_work);
138 static struct irq_chip pcap_irq_chip = {
140 .mask = pcap_mask_irq,
141 .unmask = pcap_unmask_irq,
144 static void pcap_msr_work(struct work_struct *work)
146 struct pcap_chip *pcap = container_of(work, struct pcap_chip, msr_work);
148 ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
151 static void pcap_isr_work(struct work_struct *work)
153 struct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work);
154 struct pcap_platform_data *pdata = pcap->spi->dev.platform_data;
155 u32 msr, isr, int_sel, service;
158 ezx_pcap_read(pcap, PCAP_REG_MSR, &msr);
159 ezx_pcap_read(pcap, PCAP_REG_ISR, &isr);
161 /* We cant service/ack irqs that are assigned to port 2 */
162 if (!(pdata->config & PCAP_SECOND_PORT)) {
163 ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel);
166 ezx_pcap_write(pcap, PCAP_REG_ISR, isr);
169 service = isr & ~msr;
171 for (irq = pcap->irq_base; service; service >>= 1, irq++) {
173 struct irq_desc *desc = irq_to_desc(irq);
175 if (WARN(!desc, KERN_WARNING
176 "Invalid PCAP IRQ %d\n", irq))
179 if (desc->status & IRQ_DISABLED)
180 note_interrupt(irq, desc, IRQ_NONE);
182 desc->handle_irq(irq, desc);
188 static void pcap_irq_handler(unsigned int irq, struct irq_desc *desc)
190 struct pcap_chip *pcap = get_irq_data(irq);
192 desc->chip->ack(irq);
193 queue_work(pcap->workqueue, &pcap->isr_work);
198 void pcap_set_ts_bits(struct pcap_chip *pcap, u32 bits)
202 mutex_lock(&pcap->adc_mutex);
203 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
204 tmp &= ~(PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
205 tmp |= bits & (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
206 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
207 mutex_unlock(&pcap->adc_mutex);
209 EXPORT_SYMBOL_GPL(pcap_set_ts_bits);
211 static void pcap_disable_adc(struct pcap_chip *pcap)
215 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
216 tmp &= ~(PCAP_ADC_ADEN|PCAP_ADC_BATT_I_ADC|PCAP_ADC_BATT_I_POLARITY);
217 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
220 static void pcap_adc_trigger(struct pcap_chip *pcap)
225 mutex_lock(&pcap->adc_mutex);
226 head = pcap->adc_head;
227 if (!pcap->adc_queue[head]) {
228 /* queue is empty, save power */
229 pcap_disable_adc(pcap);
230 mutex_unlock(&pcap->adc_mutex);
233 /* start conversion on requested bank, save TS_M bits */
234 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
235 tmp &= (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
236 tmp |= pcap->adc_queue[head]->flags | PCAP_ADC_ADEN;
238 if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1)
239 tmp |= PCAP_ADC_AD_SEL1;
241 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
242 mutex_unlock(&pcap->adc_mutex);
243 ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC);
246 static irqreturn_t pcap_adc_irq(int irq, void *_pcap)
248 struct pcap_chip *pcap = _pcap;
249 struct pcap_adc_request *req;
253 mutex_lock(&pcap->adc_mutex);
254 req = pcap->adc_queue[pcap->adc_head];
256 if (WARN(!req, KERN_WARNING "adc irq without pending request\n")) {
257 mutex_unlock(&pcap->adc_mutex);
261 /* read requested channels results */
262 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
263 tmp &= ~(PCAP_ADC_ADA1_MASK | PCAP_ADC_ADA2_MASK);
264 tmp |= (req->ch[0] << PCAP_ADC_ADA1_SHIFT);
265 tmp |= (req->ch[1] << PCAP_ADC_ADA2_SHIFT);
266 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
267 ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp);
268 res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT;
269 res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT;
271 pcap->adc_queue[pcap->adc_head] = NULL;
272 pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1);
273 mutex_unlock(&pcap->adc_mutex);
275 /* pass the results and release memory */
276 req->callback(req->data, res);
279 /* trigger next conversion (if any) on queue */
280 pcap_adc_trigger(pcap);
285 int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
286 void *callback, void *data)
288 struct pcap_adc_request *req;
290 /* This will be freed after we have a result */
291 req = kmalloc(sizeof(struct pcap_adc_request), GFP_KERNEL);
299 req->callback = callback;
302 mutex_lock(&pcap->adc_mutex);
303 if (pcap->adc_queue[pcap->adc_tail]) {
304 mutex_unlock(&pcap->adc_mutex);
308 pcap->adc_queue[pcap->adc_tail] = req;
309 pcap->adc_tail = (pcap->adc_tail + 1) & (PCAP_ADC_MAXQ - 1);
310 mutex_unlock(&pcap->adc_mutex);
312 /* start conversion */
313 pcap_adc_trigger(pcap);
317 EXPORT_SYMBOL_GPL(pcap_adc_async);
319 static void pcap_adc_sync_cb(void *param, u16 res[])
321 struct pcap_adc_sync_request *req = param;
323 req->res[0] = res[0];
324 req->res[1] = res[1];
325 complete(&req->completion);
328 int pcap_adc_sync(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
331 struct pcap_adc_sync_request sync_data;
334 init_completion(&sync_data.completion);
335 ret = pcap_adc_async(pcap, bank, flags, ch, pcap_adc_sync_cb,
339 wait_for_completion(&sync_data.completion);
340 res[0] = sync_data.res[0];
341 res[1] = sync_data.res[1];
345 EXPORT_SYMBOL_GPL(pcap_adc_sync);
348 static int pcap_remove_subdev(struct device *dev, void *unused)
350 platform_device_unregister(to_platform_device(dev));
354 static int __devinit pcap_add_subdev(struct pcap_chip *pcap,
355 struct pcap_subdev *subdev)
357 struct platform_device *pdev;
359 pdev = platform_device_alloc(subdev->name, subdev->id);
360 pdev->dev.parent = &pcap->spi->dev;
361 pdev->dev.platform_data = subdev->platform_data;
362 platform_set_drvdata(pdev, pcap);
364 return platform_device_add(pdev);
367 static int __devexit ezx_pcap_remove(struct spi_device *spi)
369 struct pcap_chip *pcap = dev_get_drvdata(&spi->dev);
370 struct pcap_platform_data *pdata = spi->dev.platform_data;
373 /* remove all registered subdevs */
374 device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
377 adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
378 PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);
379 free_irq(adc_irq, pcap);
380 mutex_lock(&pcap->adc_mutex);
381 for (i = 0; i < PCAP_ADC_MAXQ; i++)
382 kfree(pcap->adc_queue[i]);
383 mutex_unlock(&pcap->adc_mutex);
385 /* cleanup irqchip */
386 for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
387 set_irq_chip_and_handler(i, NULL, NULL);
389 destroy_workqueue(pcap->workqueue);
396 static int __devinit ezx_pcap_probe(struct spi_device *spi)
398 struct pcap_platform_data *pdata = spi->dev.platform_data;
399 struct pcap_chip *pcap;
403 /* platform data is required */
407 pcap = kzalloc(sizeof(*pcap), GFP_KERNEL);
413 mutex_init(&pcap->io_mutex);
414 mutex_init(&pcap->adc_mutex);
415 INIT_WORK(&pcap->isr_work, pcap_isr_work);
416 INIT_WORK(&pcap->msr_work, pcap_msr_work);
417 dev_set_drvdata(&spi->dev, pcap);
420 spi->bits_per_word = 32;
421 spi->mode = SPI_MODE_0 | (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0);
422 ret = spi_setup(spi);
429 pcap->irq_base = pdata->irq_base;
430 pcap->workqueue = create_singlethread_workqueue("pcapd");
431 if (!pcap->workqueue) {
432 dev_err(&spi->dev, "cant create pcap thread\n");
436 /* redirect interrupts to AP, except adcdone2 */
437 if (!(pdata->config & PCAP_SECOND_PORT))
438 ezx_pcap_write(pcap, PCAP_REG_INT_SEL,
439 (1 << PCAP_IRQ_ADCDONE2));
442 for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) {
443 set_irq_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq);
444 set_irq_chip_data(i, pcap);
446 set_irq_flags(i, IRQF_VALID);
452 /* mask/ack all PCAP interrupts */
453 ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT);
454 ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER);
455 pcap->msr = PCAP_MASK_ALL_INTERRUPT;
457 set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING);
458 set_irq_data(spi->irq, pcap);
459 set_irq_chained_handler(spi->irq, pcap_irq_handler);
460 set_irq_wake(spi->irq, 1);
463 adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
464 PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);
466 ret = request_irq(adc_irq, pcap_adc_irq, 0, "ADC", pcap);
471 for (i = 0; i < pdata->num_subdevs; i++) {
472 ret = pcap_add_subdev(pcap, &pdata->subdevs[i]);
477 /* board specific quirks */
484 device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
486 free_irq(adc_irq, pcap);
488 for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
489 set_irq_chip_and_handler(i, NULL, NULL);
490 /* destroy_workqueue: */
491 destroy_workqueue(pcap->workqueue);
498 static struct spi_driver ezxpcap_driver = {
499 .probe = ezx_pcap_probe,
500 .remove = __devexit_p(ezx_pcap_remove),
503 .owner = THIS_MODULE,
507 static int __init ezx_pcap_init(void)
509 return spi_register_driver(&ezxpcap_driver);
512 static void __exit ezx_pcap_exit(void)
514 spi_unregister_driver(&ezxpcap_driver);
517 module_init(ezx_pcap_init);
518 module_exit(ezx_pcap_exit);
520 MODULE_LICENSE("GPL");
521 MODULE_AUTHOR("Daniel Ribeiro / Harald Welte");
522 MODULE_DESCRIPTION("Motorola PCAP2 ASIC Driver");