SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/mfd/asic3.c

   1 /*
   2  * driver/mfd/asic3.c
   3  *
   4  * Compaq ASIC3 support.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Copyright 2001 Compaq Computer Corporation.
  11  * Copyright 2004-2005 Phil Blundell
  12  * Copyright 2007-2008 OpenedHand Ltd.
  13  *
  14  * Authors: Phil Blundell <pb@handhelds.org>,
  15  *          Samuel Ortiz <sameo@openedhand.com>
  16  *
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/irq.h>
  21 #include <linux/gpio.h>
  22 #include <linux/io.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/platform_device.h>
  25
  26 #include <linux/mfd/asic3.h>
  27
  28 struct asic3 {
  29         void __iomem *mapping;
  30         unsigned int bus_shift;
  31         unsigned int irq_nr;
  32         unsigned int irq_base;
  33         spinlock_t lock;
  34         u16 irq_bothedge[4];
  35         struct gpio_chip gpio;
  36         struct device *dev;
  37 };
  38
  39 static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
  40
  41 static inline void asic3_write_register(struct asic3 *asic,
  42                                  unsigned int reg, u32 value)
  43 {
  44         iowrite16(value, asic->mapping +
  45                   (reg >> asic->bus_shift));
  46 }
  47
  48 static inline u32 asic3_read_register(struct asic3 *asic,
  49                                unsigned int reg)
  50 {
  51         return ioread16(asic->mapping +
  52                         (reg >> asic->bus_shift));
  53 }
  54
  55 void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
  56 {
  57         unsigned long flags;
  58         u32 val;
  59
  60         spin_lock_irqsave(&asic->lock, flags);
  61         val = asic3_read_register(asic, reg);
  62         if (set)
  63                 val |= bits;
  64         else
  65                 val &= ~bits;
  66         asic3_write_register(asic, reg, val);
  67         spin_unlock_irqrestore(&asic->lock, flags);
  68 }
  69
  70 /* IRQs */
  71 #define MAX_ASIC_ISR_LOOPS    20
  72 #define ASIC3_GPIO_BASE_INCR \
  73         (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
  74
  75 static void asic3_irq_flip_edge(struct asic3 *asic,
  76                                 u32 base, int bit)
  77 {
  78         u16 edge;
  79         unsigned long flags;
  80
  81         spin_lock_irqsave(&asic->lock, flags);
  82         edge = asic3_read_register(asic,
  83                                    base + ASIC3_GPIO_EDGE_TRIGGER);
  84         edge ^= bit;
  85         asic3_write_register(asic,
  86                              base + ASIC3_GPIO_EDGE_TRIGGER, edge);
  87         spin_unlock_irqrestore(&asic->lock, flags);
  88 }
  89
  90 static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
  91 {
  92         int iter, i;
  93         unsigned long flags;
  94         struct asic3 *asic;
  95
  96         desc->chip->ack(irq);
  97
  98         asic = desc->handler_data;
  99
 100         for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
 101                 u32 status;
 102                 int bank;
 103
 104                 spin_lock_irqsave(&asic->lock, flags);
 105                 status = asic3_read_register(asic,
 106                                              ASIC3_OFFSET(INTR, P_INT_STAT));
 107                 spin_unlock_irqrestore(&asic->lock, flags);
 108
 109                 /* Check all ten register bits */
 110                 if ((status & 0x3ff) == 0)
 111                         break;
 112
 113                 /* Handle GPIO IRQs */
 114                 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
 115                         if (status & (1 << bank)) {
 116                                 unsigned long base, istat;
 117
 118                                 base = ASIC3_GPIO_A_BASE
 119                                        + bank * ASIC3_GPIO_BASE_INCR;
 120
 121                                 spin_lock_irqsave(&asic->lock, flags);
 122                                 istat = asic3_read_register(asic,
 123                                                             base +
 124                                                             ASIC3_GPIO_INT_STATUS);
 125                                 /* Clearing IntStatus */
 126                                 asic3_write_register(asic,
 127                                                      base +
 128                                                      ASIC3_GPIO_INT_STATUS, 0);
 129                                 spin_unlock_irqrestore(&asic->lock, flags);
 130
 131                                 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
 132                                         int bit = (1 << i);
 133                                         unsigned int irqnr;
 134
 135                                         if (!(istat & bit))
 136                                                 continue;
 137
 138                                         irqnr = asic->irq_base +
 139                                                 (ASIC3_GPIOS_PER_BANK * bank)
 140                                                 + i;
 141                                         desc = irq_to_desc(irqnr);
 142                                         desc->handle_irq(irqnr, desc);
 143                                         if (asic->irq_bothedge[bank] & bit)
 144                                                 asic3_irq_flip_edge(asic, base,
 145                                                                     bit);
 146                                 }
 147                         }
 148                 }
 149
 150                 /* Handle remaining IRQs in the status register */
 151                 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
 152                         /* They start at bit 4 and go up */
 153                         if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
 154                                 desc = irq_to_desc(asic->irq_base + i);
 155                                 desc->handle_irq(asic->irq_base + i,
 156                                                  desc);
 157                         }
 158                 }
 159         }
 160
 161         if (iter >= MAX_ASIC_ISR_LOOPS)
 162                 dev_err(asic->dev, "interrupt processing overrun\n");
 163 }
 164
 165 static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
 166 {
 167         int n;
 168
 169         n = (irq - asic->irq_base) >> 4;
 170
 171         return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
 172 }
 173
 174 static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
 175 {
 176         return (irq - asic->irq_base) & 0xf;
 177 }
 178
 179 static void asic3_mask_gpio_irq(unsigned int irq)
 180 {
 181         struct asic3 *asic = get_irq_chip_data(irq);
 182         u32 val, bank, index;
 183         unsigned long flags;
 184
 185         bank = asic3_irq_to_bank(asic, irq);
 186         index = asic3_irq_to_index(asic, irq);
 187
 188         spin_lock_irqsave(&asic->lock, flags);
 189         val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
 190         val |= 1 << index;
 191         asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
 192         spin_unlock_irqrestore(&asic->lock, flags);
 193 }
 194
 195 static void asic3_mask_irq(unsigned int irq)
 196 {
 197         struct asic3 *asic = get_irq_chip_data(irq);
 198         int regval;
 199         unsigned long flags;
 200
 201         spin_lock_irqsave(&asic->lock, flags);
 202         regval = asic3_read_register(asic,
 203                                      ASIC3_INTR_BASE +
 204                                      ASIC3_INTR_INT_MASK);
 205
 206         regval &= ~(ASIC3_INTMASK_MASK0 <<
 207                     (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
 208
 209         asic3_write_register(asic,
 210                              ASIC3_INTR_BASE +
 211                              ASIC3_INTR_INT_MASK,
 212                              regval);
 213         spin_unlock_irqrestore(&asic->lock, flags);
 214 }
 215
 216 static void asic3_unmask_gpio_irq(unsigned int irq)
 217 {
 218         struct asic3 *asic = get_irq_chip_data(irq);
 219         u32 val, bank, index;
 220         unsigned long flags;
 221
 222         bank = asic3_irq_to_bank(asic, irq);
 223         index = asic3_irq_to_index(asic, irq);
 224
 225         spin_lock_irqsave(&asic->lock, flags);
 226         val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
 227         val &= ~(1 << index);
 228         asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
 229         spin_unlock_irqrestore(&asic->lock, flags);
 230 }
 231
 232 static void asic3_unmask_irq(unsigned int irq)
 233 {
 234         struct asic3 *asic = get_irq_chip_data(irq);
 235         int regval;
 236         unsigned long flags;
 237
 238         spin_lock_irqsave(&asic->lock, flags);
 239         regval = asic3_read_register(asic,
 240                                      ASIC3_INTR_BASE +
 241                                      ASIC3_INTR_INT_MASK);
 242
 243         regval |= (ASIC3_INTMASK_MASK0 <<
 244                    (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
 245
 246         asic3_write_register(asic,
 247                              ASIC3_INTR_BASE +
 248                              ASIC3_INTR_INT_MASK,
 249                              regval);
 250         spin_unlock_irqrestore(&asic->lock, flags);
 251 }
 252
 253 static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
 254 {
 255         struct asic3 *asic = get_irq_chip_data(irq);
 256         u32 bank, index;
 257         u16 trigger, level, edge, bit;
 258         unsigned long flags;
 259
 260         bank = asic3_irq_to_bank(asic, irq);
 261         index = asic3_irq_to_index(asic, irq);
 262         bit = 1<<index;
 263
 264         spin_lock_irqsave(&asic->lock, flags);
 265         level = asic3_read_register(asic,
 266                                     bank + ASIC3_GPIO_LEVEL_TRIGGER);
 267         edge = asic3_read_register(asic,
 268                                    bank + ASIC3_GPIO_EDGE_TRIGGER);
 269         trigger = asic3_read_register(asic,
 270                                       bank + ASIC3_GPIO_TRIGGER_TYPE);
 271         asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;
 272
 273         if (type == IRQ_TYPE_EDGE_RISING) {
 274                 trigger |= bit;
 275                 edge |= bit;
 276         } else if (type == IRQ_TYPE_EDGE_FALLING) {
 277                 trigger |= bit;
 278                 edge &= ~bit;
 279         } else if (type == IRQ_TYPE_EDGE_BOTH) {
 280                 trigger |= bit;
 281                 if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
 282                         edge &= ~bit;
 283                 else
 284                         edge |= bit;
 285                 asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit;
 286         } else if (type == IRQ_TYPE_LEVEL_LOW) {
 287                 trigger &= ~bit;
 288                 level &= ~bit;
 289         } else if (type == IRQ_TYPE_LEVEL_HIGH) {
 290                 trigger &= ~bit;
 291                 level |= bit;
 292         } else {
 293                 /*
 294                  * if type == IRQ_TYPE_NONE, we should mask interrupts, but
 295                  * be careful to not unmask them if mask was also called.
 296                  * Probably need internal state for mask.
 297                  */
 298                 dev_notice(asic->dev, "irq type not changed\n");
 299         }
 300         asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
 301                              level);
 302         asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
 303                              edge);
 304         asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
 305                              trigger);
 306         spin_unlock_irqrestore(&asic->lock, flags);
 307         return 0;
 308 }
 309
 310 static struct irq_chip asic3_gpio_irq_chip = {
 311         .name           = "ASIC3-GPIO",
 312         .ack            = asic3_mask_gpio_irq,
 313         .mask           = asic3_mask_gpio_irq,
 314         .unmask         = asic3_unmask_gpio_irq,
 315         .set_type       = asic3_gpio_irq_type,
 316 };
 317
 318 static struct irq_chip asic3_irq_chip = {
 319         .name           = "ASIC3",
 320         .ack            = asic3_mask_irq,
 321         .mask           = asic3_mask_irq,
 322         .unmask         = asic3_unmask_irq,
 323 };
 324
 325 static int __init asic3_irq_probe(struct platform_device *pdev)
 326 {
 327         struct asic3 *asic = platform_get_drvdata(pdev);
 328         unsigned long clksel = 0;
 329         unsigned int irq, irq_base;
 330         int ret;
 331
 332         ret = platform_get_irq(pdev, 0);
 333         if (ret < 0)
 334                 return ret;
 335         asic->irq_nr = ret;
 336
 337         /* turn on clock to IRQ controller */
 338         clksel |= CLOCK_SEL_CX;
 339         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
 340                              clksel);
 341
 342         irq_base = asic->irq_base;
 343
 344         for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
 345                 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
 346                         set_irq_chip(irq, &asic3_gpio_irq_chip);
 347                 else
 348                         set_irq_chip(irq, &asic3_irq_chip);
 349
 350                 set_irq_chip_data(irq, asic);
 351                 set_irq_handler(irq, handle_level_irq);
 352                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 353         }
 354
 355         asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
 356                              ASIC3_INTMASK_GINTMASK);
 357
 358         set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
 359         set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
 360         set_irq_data(asic->irq_nr, asic);
 361
 362         return 0;
 363 }
 364
 365 static void asic3_irq_remove(struct platform_device *pdev)
 366 {
 367         struct asic3 *asic = platform_get_drvdata(pdev);
 368         unsigned int irq, irq_base;
 369
 370         irq_base = asic->irq_base;
 371
 372         for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
 373                 set_irq_flags(irq, 0);
 374                 set_irq_handler(irq, NULL);
 375                 set_irq_chip(irq, NULL);
 376                 set_irq_chip_data(irq, NULL);
 377         }
 378         set_irq_chained_handler(asic->irq_nr, NULL);
 379 }
 380
 381 /* GPIOs */
 382 static int asic3_gpio_direction(struct gpio_chip *chip,
 383                                 unsigned offset, int out)
 384 {
 385         u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
 386         unsigned int gpio_base;
 387         unsigned long flags;
 388         struct asic3 *asic;
 389
 390         asic = container_of(chip, struct asic3, gpio);
 391         gpio_base = ASIC3_GPIO_TO_BASE(offset);
 392
 393         if (gpio_base > ASIC3_GPIO_D_BASE) {
 394                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
 395                         gpio_base, offset);
 396                 return -EINVAL;
 397         }
 398
 399         spin_lock_irqsave(&asic->lock, flags);
 400
 401         out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
 402
 403         /* Input is 0, Output is 1 */
 404         if (out)
 405                 out_reg |= mask;
 406         else
 407                 out_reg &= ~mask;
 408
 409         asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
 410
 411         spin_unlock_irqrestore(&asic->lock, flags);
 412
 413         return 0;
 414
 415 }
 416
 417 static int asic3_gpio_direction_input(struct gpio_chip *chip,
 418                                       unsigned offset)
 419 {
 420         return asic3_gpio_direction(chip, offset, 0);
 421 }
 422
 423 static int asic3_gpio_direction_output(struct gpio_chip *chip,
 424                                        unsigned offset, int value)
 425 {
 426         return asic3_gpio_direction(chip, offset, 1);
 427 }
 428
 429 static int asic3_gpio_get(struct gpio_chip *chip,
 430                           unsigned offset)
 431 {
 432         unsigned int gpio_base;
 433         u32 mask = ASIC3_GPIO_TO_MASK(offset);
 434         struct asic3 *asic;
 435
 436         asic = container_of(chip, struct asic3, gpio);
 437         gpio_base = ASIC3_GPIO_TO_BASE(offset);
 438
 439         if (gpio_base > ASIC3_GPIO_D_BASE) {
 440                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
 441                         gpio_base, offset);
 442                 return -EINVAL;
 443         }
 444
 445         return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
 446 }
 447
 448 static void asic3_gpio_set(struct gpio_chip *chip,
 449                            unsigned offset, int value)
 450 {
 451         u32 mask, out_reg;
 452         unsigned int gpio_base;
 453         unsigned long flags;
 454         struct asic3 *asic;
 455
 456         asic = container_of(chip, struct asic3, gpio);
 457         gpio_base = ASIC3_GPIO_TO_BASE(offset);
 458
 459         if (gpio_base > ASIC3_GPIO_D_BASE) {
 460                 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
 461                         gpio_base, offset);
 462                 return;
 463         }
 464
 465         mask = ASIC3_GPIO_TO_MASK(offset);
 466
 467         spin_lock_irqsave(&asic->lock, flags);
 468
 469         out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
 470
 471         if (value)
 472                 out_reg |= mask;
 473         else
 474                 out_reg &= ~mask;
 475
 476         asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
 477
 478         spin_unlock_irqrestore(&asic->lock, flags);
 479
 480         return;
 481 }
 482
 483 static __init int asic3_gpio_probe(struct platform_device *pdev,
 484                                    u16 *gpio_config, int num)
 485 {
 486         struct asic3 *asic = platform_get_drvdata(pdev);
 487         u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
 488         u16 out_reg[ASIC3_NUM_GPIO_BANKS];
 489         u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
 490         int i;
 491
 492         memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
 493         memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
 494         memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
 495
 496         /* Enable all GPIOs */
 497         asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
 498         asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
 499         asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
 500         asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
 501
 502         for (i = 0; i < num; i++) {
 503                 u8 alt, pin, dir, init, bank_num, bit_num;
 504                 u16 config = gpio_config[i];
 505
 506                 pin = ASIC3_CONFIG_GPIO_PIN(config);
 507                 alt = ASIC3_CONFIG_GPIO_ALT(config);
 508                 dir = ASIC3_CONFIG_GPIO_DIR(config);
 509                 init = ASIC3_CONFIG_GPIO_INIT(config);
 510
 511                 bank_num = ASIC3_GPIO_TO_BANK(pin);
 512                 bit_num = ASIC3_GPIO_TO_BIT(pin);
 513
 514                 alt_reg[bank_num] |= (alt << bit_num);
 515                 out_reg[bank_num] |= (init << bit_num);
 516                 dir_reg[bank_num] |= (dir << bit_num);
 517         }
 518
 519         for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
 520                 asic3_write_register(asic,
 521                                      ASIC3_BANK_TO_BASE(i) +
 522                                      ASIC3_GPIO_DIRECTION,
 523                                      dir_reg[i]);
 524                 asic3_write_register(asic,
 525                                      ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
 526                                      out_reg[i]);
 527                 asic3_write_register(asic,
 528                                      ASIC3_BANK_TO_BASE(i) +
 529                                      ASIC3_GPIO_ALT_FUNCTION,
 530                                      alt_reg[i]);
 531         }
 532
 533         return gpiochip_add(&asic->gpio);
 534 }
 535
 536 static int asic3_gpio_remove(struct platform_device *pdev)
 537 {
 538         struct asic3 *asic = platform_get_drvdata(pdev);
 539
 540         return gpiochip_remove(&asic->gpio);
 541 }
 542
 543
 544 /* Core */
 545 static int __init asic3_probe(struct platform_device *pdev)
 546 {
 547         struct asic3_platform_data *pdata = pdev->dev.platform_data;
 548         struct asic3 *asic;
 549         struct resource *mem;
 550         unsigned long clksel;
 551         int map_size;
 552         int ret = 0;
 553
 554         asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
 555         if (asic == NULL) {
 556                 printk(KERN_ERR "kzalloc failed\n");
 557                 return -ENOMEM;
 558         }
 559
 560         spin_lock_init(&asic->lock);
 561         platform_set_drvdata(pdev, asic);
 562         asic->dev = &pdev->dev;
 563
 564         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 565         if (!mem) {
 566                 ret = -ENOMEM;
 567                 dev_err(asic->dev, "no MEM resource\n");
 568                 goto out_free;
 569         }
 570
 571         map_size = mem->end - mem->start + 1;
 572         asic->mapping = ioremap(mem->start, map_size);
 573         if (!asic->mapping) {
 574                 ret = -ENOMEM;
 575                 dev_err(asic->dev, "Couldn't ioremap\n");
 576                 goto out_free;
 577         }
 578
 579         asic->irq_base = pdata->irq_base;
 580
 581         /* calculate bus shift from mem resource */
 582         asic->bus_shift = 2 - (map_size >> 12);
 583
 584         clksel = 0;
 585         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
 586
 587         ret = asic3_irq_probe(pdev);
 588         if (ret < 0) {
 589                 dev_err(asic->dev, "Couldn't probe IRQs\n");
 590                 goto out_unmap;
 591         }
 592
 593         asic->gpio.base = pdata->gpio_base;
 594         asic->gpio.ngpio = ASIC3_NUM_GPIOS;
 595         asic->gpio.get = asic3_gpio_get;
 596         asic->gpio.set = asic3_gpio_set;
 597         asic->gpio.direction_input = asic3_gpio_direction_input;
 598         asic->gpio.direction_output = asic3_gpio_direction_output;
 599
 600         ret = asic3_gpio_probe(pdev,
 601                                pdata->gpio_config,
 602                                pdata->gpio_config_num);
 603         if (ret < 0) {
 604                 dev_err(asic->dev, "GPIO probe failed\n");
 605                 goto out_irq;
 606         }
 607
 608         dev_info(asic->dev, "ASIC3 Core driver\n");
 609
 610         return 0;
 611
 612  out_irq:
 613         asic3_irq_remove(pdev);
 614
 615  out_unmap:
 616         iounmap(asic->mapping);
 617
 618  out_free:
 619         kfree(asic);
 620
 621         return ret;
 622 }
 623
 624 static int asic3_remove(struct platform_device *pdev)
 625 {
 626         int ret;
 627         struct asic3 *asic = platform_get_drvdata(pdev);
 628
 629         ret = asic3_gpio_remove(pdev);
 630         if (ret < 0)
 631                 return ret;
 632         asic3_irq_remove(pdev);
 633
 634         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
 635
 636         iounmap(asic->mapping);
 637
 638         kfree(asic);
 639
 640         return 0;
 641 }
 642
 643 static void asic3_shutdown(struct platform_device *pdev)
 644 {
 645 }
 646
 647 static struct platform_driver asic3_device_driver = {
 648         .driver         = {
 649                 .name   = "asic3",
 650         },
 651         .remove         = __devexit_p(asic3_remove),
 652         .shutdown       = asic3_shutdown,
 653 };
 654
 655 static int __init asic3_init(void)
 656 {
 657         int retval = 0;
 658         retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
 659         return retval;
 660 }
 661
 662 subsys_initcall(asic3_init);