1 /***************************************************************************
2 * Plug-in for PAS202BCB image sensor connected to the SN9C1xx PC Camera *
5 * Copyright (C) 2004 by Carlos Eduardo Medaglia Dyonisio *
6 * <medaglia@undl.org.br> *
7 * http://cadu.homelinux.com:8080/ *
9 * Support for SN9C103, DAC Magnitude, exposure and green gain controls *
10 * added by Luca Risolia <luca.risolia@studio.unibo.it> *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
22 * You should have received a copy of the GNU General Public License *
23 * along with this program; if not, write to the Free Software *
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
25 ***************************************************************************/
27 #include <linux/delay.h>
28 #include "sn9c102_sensor.h"
31 static int pas202bcb_init(struct sn9c102_device* cam)
35 switch (sn9c102_get_bridge(cam)) {
38 err += sn9c102_write_reg(cam, 0x00, 0x10);
39 err += sn9c102_write_reg(cam, 0x00, 0x11);
40 err += sn9c102_write_reg(cam, 0x00, 0x14);
41 err += sn9c102_write_reg(cam, 0x20, 0x17);
42 err += sn9c102_write_reg(cam, 0x30, 0x19);
43 err += sn9c102_write_reg(cam, 0x09, 0x18);
46 err += sn9c102_write_reg(cam, 0x00, 0x02);
47 err += sn9c102_write_reg(cam, 0x00, 0x03);
48 err += sn9c102_write_reg(cam, 0x1a, 0x04);
49 err += sn9c102_write_reg(cam, 0x20, 0x05);
50 err += sn9c102_write_reg(cam, 0x20, 0x06);
51 err += sn9c102_write_reg(cam, 0x20, 0x07);
52 err += sn9c102_write_reg(cam, 0x00, 0x10);
53 err += sn9c102_write_reg(cam, 0x00, 0x11);
54 err += sn9c102_write_reg(cam, 0x00, 0x14);
55 err += sn9c102_write_reg(cam, 0x20, 0x17);
56 err += sn9c102_write_reg(cam, 0x30, 0x19);
57 err += sn9c102_write_reg(cam, 0x09, 0x18);
58 err += sn9c102_write_reg(cam, 0x02, 0x1c);
59 err += sn9c102_write_reg(cam, 0x03, 0x1d);
60 err += sn9c102_write_reg(cam, 0x0f, 0x1e);
61 err += sn9c102_write_reg(cam, 0x0c, 0x1f);
62 err += sn9c102_write_reg(cam, 0x00, 0x20);
63 err += sn9c102_write_reg(cam, 0x10, 0x21);
64 err += sn9c102_write_reg(cam, 0x20, 0x22);
65 err += sn9c102_write_reg(cam, 0x30, 0x23);
66 err += sn9c102_write_reg(cam, 0x40, 0x24);
67 err += sn9c102_write_reg(cam, 0x50, 0x25);
68 err += sn9c102_write_reg(cam, 0x60, 0x26);
69 err += sn9c102_write_reg(cam, 0x70, 0x27);
70 err += sn9c102_write_reg(cam, 0x80, 0x28);
71 err += sn9c102_write_reg(cam, 0x90, 0x29);
72 err += sn9c102_write_reg(cam, 0xa0, 0x2a);
73 err += sn9c102_write_reg(cam, 0xb0, 0x2b);
74 err += sn9c102_write_reg(cam, 0xc0, 0x2c);
75 err += sn9c102_write_reg(cam, 0xd0, 0x2d);
76 err += sn9c102_write_reg(cam, 0xe0, 0x2e);
77 err += sn9c102_write_reg(cam, 0xf0, 0x2f);
78 err += sn9c102_write_reg(cam, 0xff, 0x30);
84 err += sn9c102_i2c_write(cam, 0x02, 0x14);
85 err += sn9c102_i2c_write(cam, 0x03, 0x40);
86 err += sn9c102_i2c_write(cam, 0x0d, 0x2c);
87 err += sn9c102_i2c_write(cam, 0x0e, 0x01);
88 err += sn9c102_i2c_write(cam, 0x0f, 0xa9);
89 err += sn9c102_i2c_write(cam, 0x10, 0x08);
90 err += sn9c102_i2c_write(cam, 0x13, 0x63);
91 err += sn9c102_i2c_write(cam, 0x15, 0x70);
92 err += sn9c102_i2c_write(cam, 0x11, 0x01);
100 static int pas202bcb_get_ctrl(struct sn9c102_device* cam,
101 struct v4l2_control* ctrl)
104 case V4L2_CID_EXPOSURE:
106 int r1 = sn9c102_i2c_read(cam, 0x04),
107 r2 = sn9c102_i2c_read(cam, 0x05);
108 if (r1 < 0 || r2 < 0)
110 ctrl->value = (r1 << 6) | (r2 & 0x3f);
113 case V4L2_CID_RED_BALANCE:
114 if ((ctrl->value = sn9c102_i2c_read(cam, 0x09)) < 0)
118 case V4L2_CID_BLUE_BALANCE:
119 if ((ctrl->value = sn9c102_i2c_read(cam, 0x07)) < 0)
124 if ((ctrl->value = sn9c102_i2c_read(cam, 0x10)) < 0)
128 case SN9C102_V4L2_CID_GREEN_BALANCE:
129 if ((ctrl->value = sn9c102_i2c_read(cam, 0x08)) < 0)
133 case SN9C102_V4L2_CID_DAC_MAGNITUDE:
134 if ((ctrl->value = sn9c102_i2c_read(cam, 0x0c)) < 0)
143 static int pas202bcb_set_pix_format(struct sn9c102_device* cam,
144 const struct v4l2_pix_format* pix)
148 if (pix->pixelformat == V4L2_PIX_FMT_SN9C10X)
149 err += sn9c102_write_reg(cam, 0x28, 0x17);
151 err += sn9c102_write_reg(cam, 0x20, 0x17);
157 static int pas202bcb_set_ctrl(struct sn9c102_device* cam,
158 const struct v4l2_control* ctrl)
163 case V4L2_CID_EXPOSURE:
164 err += sn9c102_i2c_write(cam, 0x04, ctrl->value >> 6);
165 err += sn9c102_i2c_write(cam, 0x05, ctrl->value & 0x3f);
167 case V4L2_CID_RED_BALANCE:
168 err += sn9c102_i2c_write(cam, 0x09, ctrl->value);
170 case V4L2_CID_BLUE_BALANCE:
171 err += sn9c102_i2c_write(cam, 0x07, ctrl->value);
174 err += sn9c102_i2c_write(cam, 0x10, ctrl->value);
176 case SN9C102_V4L2_CID_GREEN_BALANCE:
177 err += sn9c102_i2c_write(cam, 0x08, ctrl->value);
179 case SN9C102_V4L2_CID_DAC_MAGNITUDE:
180 err += sn9c102_i2c_write(cam, 0x0c, ctrl->value);
185 err += sn9c102_i2c_write(cam, 0x11, 0x01);
187 return err ? -EIO : 0;
191 static int pas202bcb_set_crop(struct sn9c102_device* cam,
192 const struct v4l2_rect* rect)
194 struct sn9c102_sensor* s = sn9c102_get_sensor(cam);
197 v_start = (u8)(rect->top - s->cropcap.bounds.top) + 3;
199 switch (sn9c102_get_bridge(cam)) {
202 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 4;
205 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 3;
211 err += sn9c102_write_reg(cam, h_start, 0x12);
212 err += sn9c102_write_reg(cam, v_start, 0x13);
218 static struct sn9c102_sensor pas202bcb = {
220 .maintainer = "Luca Risolia <luca.risolia@studio.unibo.it>",
221 .supported_bridge = BRIDGE_SN9C101 | BRIDGE_SN9C102 | BRIDGE_SN9C103,
222 .sysfs_ops = SN9C102_I2C_READ | SN9C102_I2C_WRITE,
223 .frequency = SN9C102_I2C_400KHZ | SN9C102_I2C_100KHZ,
224 .interface = SN9C102_I2C_2WIRES,
225 .i2c_slave_id = 0x40,
226 .init = &pas202bcb_init,
229 .id = V4L2_CID_EXPOSURE,
230 .type = V4L2_CTRL_TYPE_INTEGER,
235 .default_value = 0x01e5,
240 .type = V4L2_CTRL_TYPE_INTEGER,
241 .name = "global gain",
245 .default_value = 0x0b,
249 .id = V4L2_CID_RED_BALANCE,
250 .type = V4L2_CTRL_TYPE_INTEGER,
251 .name = "red balance",
255 .default_value = 0x00,
259 .id = V4L2_CID_BLUE_BALANCE,
260 .type = V4L2_CTRL_TYPE_INTEGER,
261 .name = "blue balance",
265 .default_value = 0x05,
269 .id = SN9C102_V4L2_CID_GREEN_BALANCE,
270 .type = V4L2_CTRL_TYPE_INTEGER,
271 .name = "green balance",
275 .default_value = 0x00,
279 .id = SN9C102_V4L2_CID_DAC_MAGNITUDE,
280 .type = V4L2_CTRL_TYPE_INTEGER,
281 .name = "DAC magnitude",
285 .default_value = 0x04,
289 .get_ctrl = &pas202bcb_get_ctrl,
290 .set_ctrl = &pas202bcb_set_ctrl,
305 .set_crop = &pas202bcb_set_crop,
309 .pixelformat = V4L2_PIX_FMT_SBGGR8,
312 .set_pix_format = &pas202bcb_set_pix_format
316 int sn9c102_probe_pas202bcb(struct sn9c102_device* cam)
318 int r0 = 0, r1 = 0, err = 0;
319 unsigned int pid = 0;
322 * Minimal initialization to enable the I2C communication
323 * NOTE: do NOT change the values!
325 switch (sn9c102_get_bridge(cam)) {
328 err += sn9c102_write_reg(cam, 0x01, 0x01); /* power down */
329 err += sn9c102_write_reg(cam, 0x40, 0x01); /* power on */
330 err += sn9c102_write_reg(cam, 0x28, 0x17); /* clock 24 MHz */
332 case BRIDGE_SN9C103: /* do _not_ change anything! */
333 err += sn9c102_write_reg(cam, 0x09, 0x01);
334 err += sn9c102_write_reg(cam, 0x44, 0x01);
335 err += sn9c102_write_reg(cam, 0x44, 0x02);
336 err += sn9c102_write_reg(cam, 0x29, 0x17);
342 r0 = sn9c102_i2c_try_read(cam, &pas202bcb, 0x00);
343 r1 = sn9c102_i2c_try_read(cam, &pas202bcb, 0x01);
345 if (err || r0 < 0 || r1 < 0)
348 pid = (r0 << 4) | ((r1 & 0xf0) >> 4);
352 sn9c102_attach_sensor(cam, &pas202bcb);