SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/media/video/saa7115.c

   1 /* saa711x - Philips SAA711x video decoder driver
   2  * This driver can work with saa7111, saa7111a, saa7113, saa7114,
   3  *                           saa7115 and saa7118.
   4  *
   5  * Based on saa7114 driver by Maxim Yevtyushkin, which is based on
   6  * the saa7111 driver by Dave Perks.
   7  *
   8  * Copyright (C) 1998 Dave Perks <dperks@ibm.net>
   9  * Copyright (C) 2002 Maxim Yevtyushkin <max@linuxmedialabs.com>
  10  *
  11  * Slight changes for video timing and attachment output by
  12  * Wolfgang Scherr <scherr@net4you.net>
  13  *
  14  * Moved over to the linux >= 2.4.x i2c protocol (1/1/2003)
  15  * by Ronald Bultje <rbultje@ronald.bitfreak.net>
  16  *
  17  * Added saa7115 support by Kevin Thayer <nufan_wfk at yahoo.com>
  18  * (2/17/2003)
  19  *
  20  * VBI support (2004) and cleanups (2005) by Hans Verkuil <hverkuil@xs4all.nl>
  21  *
  22  * Copyright (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org>
  23  *      SAA7111, SAA7113 and SAA7118 support
  24  *
  25  * This program is free software; you can redistribute it and/or
  26  * modify it under the terms of the GNU General Public License
  27  * as published by the Free Software Foundation; either version 2
  28  * of the License, or (at your option) any later version.
  29  *
  30  * This program is distributed in the hope that it will be useful,
  31  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  32  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  33  * GNU General Public License for more details.
  34  *
  35  * You should have received a copy of the GNU General Public License
  36  * along with this program; if not, write to the Free Software
  37  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  38  */
  39
  40 #include "saa711x_regs.h"
  41
  42 #include <linux/kernel.h>
  43 #include <linux/module.h>
  44 #include <linux/slab.h>
  45 #include <linux/i2c.h>
  46 #include <linux/videodev2.h>
  47 #include <media/v4l2-common.h>
  48 #include <media/saa7115.h>
  49 #include <asm/div64.h>
  50
  51 MODULE_DESCRIPTION("Philips SAA7111/SAA7113/SAA7114/SAA7115/SAA7118 video decoder driver");
  52 MODULE_AUTHOR(  "Maxim Yevtyushkin, Kevin Thayer, Chris Kennedy, "
  53                 "Hans Verkuil, Mauro Carvalho Chehab");
  54 MODULE_LICENSE("GPL");
  55
  56 static int debug = 0;
  57 module_param(debug, bool, 0644);
  58
  59 MODULE_PARM_DESC(debug, "Debug level (0-1)");
  60
  61 static unsigned short normal_i2c[] = {
  62                 0x4a >> 1, 0x48 >> 1,   /* SAA7111, SAA7111A and SAA7113 */
  63                 0x42 >> 1, 0x40 >> 1,   /* SAA7114, SAA7115 and SAA7118 */
  64                 I2C_CLIENT_END };
  65
  66
  67 I2C_CLIENT_INSMOD;
  68
  69 struct saa7115_state {
  70         v4l2_std_id std;
  71         int input;
  72         int enable;
  73         int radio;
  74         int bright;
  75         int contrast;
  76         int hue;
  77         int sat;
  78         enum v4l2_chip_ident ident;
  79         u32 audclk_freq;
  80         u32 crystal_freq;
  81         u8 ucgc;
  82         u8 cgcdiv;
  83         u8 apll;
  84 };
  85
  86 /* ----------------------------------------------------------------------- */
  87
  88 static inline int saa7115_write(struct i2c_client *client, u8 reg, u8 value)
  89 {
  90         return i2c_smbus_write_byte_data(client, reg, value);
  91 }
  92
  93 /* Sanity routine to check if a register is present */
  94 static int saa711x_has_reg(const int id, const u8 reg)
  95 {
  96         switch (id) {
  97         case V4L2_IDENT_SAA7111:
  98                 if (reg>0x1f || reg==1 || reg==0x0f || reg==0x14 || reg==0x18
  99                                        || reg==0x19 || reg==0x1d || reg==0x1e)
 100                         return 0;
 101         case V4L2_IDENT_SAA7113:
 102                 if (reg>0x62 || reg==0x14 || (reg>=0x18 && reg<=0x1e) ||
 103                                     (reg>=0x20 && reg<=0x3f) ||reg==0x5f )
 104                         return 0;
 105         case V4L2_IDENT_SAA7114:
 106                 if (reg>=0xf0 || (reg>=0x1a && reg<=0x1e) ||
 107                                   (reg>=0x20 && reg<=0x2f) ||
 108                                   (reg>=0x63 && reg<=0x7f) )
 109                         return 0;
 110         case V4L2_IDENT_SAA7115:
 111                 if ((reg>=0x20 && reg<=0x2f) || (reg==0x5c) ||
 112                                 (reg>=0xfc && reg<=0xfe) )
 113                         return 0;
 114         case V4L2_IDENT_SAA7118:
 115                 if (reg>=0xf0 || (reg>=0x1a && reg<=0x1d) ||
 116                                         (reg>=0x63 && reg<=0x6f) )
 117                         return 0;
 118         }
 119
 120         /* Those registers are reserved for all family */
 121         if (unlikely((reg>=0x20 && reg<=0x22) ||
 122                         (reg>=0x26 && reg<=0x28) ||
 123                         (reg>=0x3b && reg<=0x3f) || (reg==0x5f) ||
 124                         (reg>=0x63 && reg<=0x6f) ) )
 125                 return 0;
 126
 127         return 1;
 128 }
 129
 130 static int saa7115_writeregs(struct i2c_client *client, const unsigned char *regs)
 131 {
 132         struct saa7115_state *state = i2c_get_clientdata(client);
 133         unsigned char reg, data;
 134
 135         while (*regs != 0x00) {
 136                 reg = *(regs++);
 137                 data = *(regs++);
 138
 139                 /* According with datasheets, reserved regs should be
 140                    filled with 0 - seems better not to touch on they */
 141                 if (saa711x_has_reg(state->ident,reg)) {
 142                         if (saa7115_write(client, reg, data) < 0)
 143                                 return -1;
 144                 }
 145         }
 146         return 0;
 147 }
 148
 149 static inline int saa7115_read(struct i2c_client *client, u8 reg)
 150 {
 151         return i2c_smbus_read_byte_data(client, reg);
 152 }
 153
 154 /* ----------------------------------------------------------------------- */
 155
 156 /* SAA7111 initialization table */
 157 static const unsigned char saa7111_init_auto_input[] = {
 158         R_01_INC_DELAY, 0x00,           /* reserved */
 159
 160         /*front end */
 161         R_02_INPUT_CNTL_1, 0xd0,        /* FUSE=3, GUDL=2, MODE=0 */
 162         R_03_INPUT_CNTL_2, 0x23,        /* HLNRS=0, VBSL=1, WPOFF=0, HOLDG=0,
 163                                          * GAFIX=0, GAI1=256, GAI2=256 */
 164         R_04_INPUT_CNTL_3, 0x00,        /* GAI1=256 */
 165         R_05_INPUT_CNTL_4, 0x00,        /* GAI2=256 */
 166
 167         /* decoder */
 168         R_06_H_SYNC_START, 0xf3,        /* HSB at  13(50Hz) /  17(60Hz)
 169                                          * pixels after end of last line */
 170         R_07_H_SYNC_STOP, 0xe8,         /* HSS seems to be needed to
 171                                          * work with NTSC, too */
 172         R_08_SYNC_CNTL, 0xc8,           /* AUFD=1, FSEL=1, EXFIL=0,
 173                                          * VTRC=1, HPLL=0, VNOI=0 */
 174         R_09_LUMA_CNTL, 0x01,           /* BYPS=0, PREF=0, BPSS=0,
 175                                          * VBLB=0, UPTCV=0, APER=1 */
 176         R_0A_LUMA_BRIGHT_CNTL, 0x80,
 177         R_0B_LUMA_CONTRAST_CNTL, 0x47,  /* 0b - CONT=1.109 */
 178         R_0C_CHROMA_SAT_CNTL, 0x40,
 179         R_0D_CHROMA_HUE_CNTL, 0x00,
 180         R_0E_CHROMA_CNTL_1, 0x01,       /* 0e - CDTO=0, CSTD=0, DCCF=0,
 181                                          * FCTC=0, CHBW=1 */
 182         R_0F_CHROMA_GAIN_CNTL, 0x00,    /* reserved */
 183         R_10_CHROMA_CNTL_2, 0x48,       /* 10 - OFTS=1, HDEL=0, VRLN=1, YDEL=0 */
 184         R_11_MODE_DELAY_CNTL, 0x1c,     /* 11 - GPSW=0, CM99=0, FECO=0, COMPO=1,
 185                                          * OEYC=1, OEHV=1, VIPB=0, COLO=0 */
 186         R_12_RT_SIGNAL_CNTL, 0x00,      /* 12 - output control 2 */
 187         R_13_RT_X_PORT_OUT_CNTL, 0x00,  /* 13 - output control 3 */
 188         R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
 189         R_15_VGATE_START_FID_CHG, 0x00,
 190         R_16_VGATE_STOP, 0x00,
 191         R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
 192
 193         0x00, 0x00
 194 };
 195
 196 /* SAA7113 init codes */
 197 static const unsigned char saa7113_init_auto_input[] = {
 198         R_01_INC_DELAY, 0x08,
 199         R_02_INPUT_CNTL_1, 0xc2,
 200         R_03_INPUT_CNTL_2, 0x30,
 201         R_04_INPUT_CNTL_3, 0x00,
 202         R_05_INPUT_CNTL_4, 0x00,
 203         R_06_H_SYNC_START, 0x89,
 204         R_07_H_SYNC_STOP, 0x0d,
 205         R_08_SYNC_CNTL, 0x88,
 206         R_09_LUMA_CNTL, 0x01,
 207         R_0A_LUMA_BRIGHT_CNTL, 0x80,
 208         R_0B_LUMA_CONTRAST_CNTL, 0x47,
 209         R_0C_CHROMA_SAT_CNTL, 0x40,
 210         R_0D_CHROMA_HUE_CNTL, 0x00,
 211         R_0E_CHROMA_CNTL_1, 0x01,
 212         R_0F_CHROMA_GAIN_CNTL, 0x2a,
 213         R_10_CHROMA_CNTL_2, 0x08,
 214         R_11_MODE_DELAY_CNTL, 0x0c,
 215         R_12_RT_SIGNAL_CNTL, 0x07,
 216         R_13_RT_X_PORT_OUT_CNTL, 0x00,
 217         R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
 218         R_15_VGATE_START_FID_CHG, 0x00,
 219         R_16_VGATE_STOP, 0x00,
 220         R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
 221
 222         0x00, 0x00
 223 };
 224
 225 /* If a value differs from the Hauppauge driver values, then the comment starts with
 226    'was 0xXX' to denote the Hauppauge value. Otherwise the value is identical to what the
 227    Hauppauge driver sets. */
 228
 229 /* SAA7114 and SAA7115 initialization table */
 230 static const unsigned char saa7115_init_auto_input[] = {
 231                 /* Front-End Part */
 232         R_01_INC_DELAY, 0x48,                   /* white peak control disabled */
 233         R_03_INPUT_CNTL_2, 0x20,                /* was 0x30. 0x20: long vertical blanking */
 234         R_04_INPUT_CNTL_3, 0x90,                /* analog gain set to 0 */
 235         R_05_INPUT_CNTL_4, 0x90,                /* analog gain set to 0 */
 236                 /* Decoder Part */
 237         R_06_H_SYNC_START, 0xeb,                /* horiz sync begin = -21 */
 238         R_07_H_SYNC_STOP, 0xe0,                 /* horiz sync stop = -17 */
 239         R_0A_LUMA_BRIGHT_CNTL, 0x80,            /* was 0x88. decoder brightness, 0x80 is itu standard */
 240         R_0B_LUMA_CONTRAST_CNTL, 0x44,          /* was 0x48. decoder contrast, 0x44 is itu standard */
 241         R_0C_CHROMA_SAT_CNTL, 0x40,             /* was 0x47. decoder saturation, 0x40 is itu standard */
 242         R_0D_CHROMA_HUE_CNTL, 0x00,
 243         R_0F_CHROMA_GAIN_CNTL, 0x00,            /* use automatic gain  */
 244         R_10_CHROMA_CNTL_2, 0x06,               /* chroma: active adaptive combfilter */
 245         R_11_MODE_DELAY_CNTL, 0x00,
 246         R_12_RT_SIGNAL_CNTL, 0x9d,              /* RTS0 output control: VGATE */
 247         R_13_RT_X_PORT_OUT_CNTL, 0x80,          /* ITU656 standard mode, RTCO output enable RTCE */
 248         R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
 249         R_18_RAW_DATA_GAIN_CNTL, 0x40,          /* gain 0x00 = nominal */
 250         R_19_RAW_DATA_OFF_CNTL, 0x80,
 251         R_1A_COLOR_KILL_LVL_CNTL, 0x77,         /* recommended value */
 252         R_1B_MISC_TVVCRDET, 0x42,               /* recommended value */
 253         R_1C_ENHAN_COMB_CTRL1, 0xa9,            /* recommended value */
 254         R_1D_ENHAN_COMB_CTRL2, 0x01,            /* recommended value */
 255
 256                 /* Power Device Control */
 257         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,    /* reset device */
 258         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,    /* set device programmed, all in operational mode */
 259         0x00, 0x00
 260 };
 261
 262 /* Used to reset saa7113, saa7114 and saa7115 */
 263 static const unsigned char saa7115_cfg_reset_scaler[] = {
 264         R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00,    /* disable I-port output */
 265         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,            /* reset scaler */
 266         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,            /* activate scaler */
 267         R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,    /* enable I-port output */
 268         0x00, 0x00
 269 };
 270
 271 /* ============== SAA7715 VIDEO templates =============  */
 272
 273 /* Used on saa7114 and saa7115 */
 274 static const unsigned char saa7115_cfg_60hz_fullres_x[] = {
 275         /* hsize = 0x2d0 = 720 */
 276         R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
 277         R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
 278
 279         /* Why not in 60hz-Land, too? */
 280         R_D0_B_HORIZ_PRESCALING, 0x01,          /* downscale = 1 */
 281         /* hor lum scaling 0x0400 = 1 */
 282         R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00,
 283         R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
 284
 285         /* must be hor lum scaling / 2 */
 286         R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
 287         R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,
 288
 289         0x00, 0x00
 290 };
 291
 292 /* Used on saa7114 and saa7115 */
 293 static const unsigned char saa7115_cfg_60hz_fullres_y[] = {
 294         /* output window size = 248 (but 60hz is 240?) */
 295         R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, 0xf8,
 296         R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,
 297
 298         /* Why not in 60hz-Land, too? */
 299         R_D5_B_LUMA_CONTRAST_CNTL, 0x40,                /* Lum contrast, nominal value = 0x40 */
 300         R_D6_B_CHROMA_SATURATION_CNTL, 0x40,            /* Chroma satur. nominal value = 0x80 */
 301
 302         R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
 303         R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,
 304
 305         R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
 306         R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
 307
 308         0x00, 0x00
 309 };
 310
 311 static const unsigned char saa7115_cfg_60hz_video[] = {
 312         R_80_GLOBAL_CNTL_1, 0x00,                       /* reset tasks */
 313         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,            /* reset scaler */
 314
 315         R_15_VGATE_START_FID_CHG, 0x03,
 316         R_16_VGATE_STOP, 0x11,
 317         R_17_MISC_VGATE_CONF_AND_MSB, 0x9c,
 318
 319         R_08_SYNC_CNTL, 0x68,                   /* 0xBO: auto detection, 0x68 = NTSC */
 320         R_0E_CHROMA_CNTL_1, 0x07,               /* video autodetection is on */
 321
 322         R_5A_V_OFF_FOR_SLICER, 0x06,            /* standard 60hz value for ITU656 line counting */
 323
 324         /* Task A */
 325         R_90_A_TASK_HANDLING_CNTL, 0x80,
 326         R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
 327         R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
 328         R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
 329
 330         /* hoffset low (input), 0x0002 is minimum */
 331         R_94_A_HORIZ_INPUT_WINDOW_START, 0x01,
 332         R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
 333
 334         /* hsize low (input), 0x02d0 = 720 */
 335         R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
 336         R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
 337
 338         R_98_A_VERT_INPUT_WINDOW_START, 0x05,
 339         R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
 340
 341         R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x0c,
 342         R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
 343
 344         R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
 345         R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,
 346
 347         R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x0c,
 348         R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,
 349
 350         /* Task B */
 351         R_C0_B_TASK_HANDLING_CNTL, 0x00,
 352         R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
 353         R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
 354         R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
 355
 356         /* 0x0002 is minimum */
 357         R_C4_B_HORIZ_INPUT_WINDOW_START, 0x02,
 358         R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
 359
 360         /* 0x02d0 = 720 */
 361         R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
 362         R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
 363
 364         /* vwindow start 0x12 = 18 */
 365         R_C8_B_VERT_INPUT_WINDOW_START, 0x12,
 366         R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
 367
 368         /* vwindow length 0xf8 = 248 */
 369         R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0xf8,
 370         R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
 371
 372         /* hwindow 0x02d0 = 720 */
 373         R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
 374         R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
 375
 376         R_F0_LFCO_PER_LINE, 0xad,               /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */
 377         R_F1_P_I_PARAM_SELECT, 0x05,            /* low bit with 0xF0 */
 378         R_F5_PULSGEN_LINE_LENGTH, 0xad,
 379         R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
 380
 381         R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00,    /* Disable I-port output */
 382         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,            /* reset scaler */
 383         R_80_GLOBAL_CNTL_1, 0x20,                       /* Activate only task "B", continuous mode (was 0xA0) */
 384         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,            /* activate scaler */
 385         R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,    /* Enable I-port output */
 386         0x00, 0x00
 387 };
 388
 389 static const unsigned char saa7115_cfg_50hz_fullres_x[] = {
 390         /* hsize low (output), 720 same as 60hz */
 391         R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
 392         R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
 393
 394         R_D0_B_HORIZ_PRESCALING, 0x01,          /* down scale = 1 */
 395         R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00,    /* hor lum scaling 0x0400 = 1 */
 396         R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
 397
 398         /* must be hor lum scaling / 2 */
 399         R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
 400         R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,
 401
 402         0x00, 0x00
 403 };
 404 static const unsigned char saa7115_cfg_50hz_fullres_y[] = {
 405         /* vsize low (output), 0x0120 = 288 */
 406         R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, 0x20,
 407         R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x01,
 408
 409         R_D5_B_LUMA_CONTRAST_CNTL, 0x40,        /* Lum contrast, nominal value = 0x40 */
 410         R_D6_B_CHROMA_SATURATION_CNTL, 0x40,    /* Chroma satur. nominal value = 0x80 */
 411
 412         R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
 413         R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,
 414
 415         R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
 416         R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
 417
 418         0x00, 0x00
 419 };
 420
 421 static const unsigned char saa7115_cfg_50hz_video[] = {
 422         R_80_GLOBAL_CNTL_1, 0x00,
 423         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,    /* reset scaler */
 424
 425         R_15_VGATE_START_FID_CHG, 0x37,         /* VGATE start */
 426         R_16_VGATE_STOP, 0x16,
 427         R_17_MISC_VGATE_CONF_AND_MSB, 0x99,
 428
 429         R_08_SYNC_CNTL, 0x28,                   /* 0x28 = PAL */
 430         R_0E_CHROMA_CNTL_1, 0x07,
 431
 432         R_5A_V_OFF_FOR_SLICER, 0x03,            /* standard 50hz value */
 433
 434         /* Task A */
 435         R_90_A_TASK_HANDLING_CNTL, 0x81,
 436         R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
 437         R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
 438         R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
 439
 440         /* This is weird: the datasheet says that you should use 2 as the minimum value, */
 441         /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
 442         /* hoffset low (input), 0x0002 is minimum */
 443         R_94_A_HORIZ_INPUT_WINDOW_START, 0x00,
 444         R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
 445
 446         /* hsize low (input), 0x02d0 = 720 */
 447         R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
 448         R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
 449
 450         R_98_A_VERT_INPUT_WINDOW_START, 0x03,
 451         R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
 452
 453         /* vsize 0x12 = 18 */
 454         R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x12,
 455         R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
 456
 457         /* hsize 0x05a0 = 1440 */
 458         R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
 459         R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,    /* hsize hi (output) */
 460         R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x12,         /* vsize low (output), 0x12 = 18 */
 461         R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,     /* vsize hi (output) */
 462
 463         /* Task B */
 464         R_C0_B_TASK_HANDLING_CNTL, 0x00,
 465         R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
 466         R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
 467         R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
 468
 469         /* This is weird: the datasheet says that you should use 2 as the minimum value, */
 470         /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
 471         /* hoffset low (input), 0x0002 is minimum. See comment above. */
 472         R_C4_B_HORIZ_INPUT_WINDOW_START, 0x00,
 473         R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
 474
 475         /* hsize 0x02d0 = 720 */
 476         R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
 477         R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
 478
 479         /* voffset 0x16 = 22 */
 480         R_C8_B_VERT_INPUT_WINDOW_START, 0x16,
 481         R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
 482
 483         /* vsize 0x0120 = 288 */
 484         R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0x20,
 485         R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x01,
 486
 487         /* hsize 0x02d0 = 720 */
 488         R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
 489         R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
 490
 491         /* vsize 0x0120 = 288 */
 492         R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, 0x20,
 493         R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x01,
 494
 495         R_F0_LFCO_PER_LINE, 0xb0,               /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */
 496         R_F1_P_I_PARAM_SELECT, 0x05,            /* low bit with 0xF0, (was 0x05) */
 497         R_F5_PULSGEN_LINE_LENGTH, 0xb0,
 498         R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
 499
 500         R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00,    /* Disable I-port output */
 501         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,            /* reset scaler (was 0xD0) */
 502         R_80_GLOBAL_CNTL_1, 0x20,                       /* Activate only task "B" */
 503         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,            /* activate scaler */
 504         R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,    /* Enable I-port output */
 505
 506         0x00, 0x00
 507 };
 508
 509 /* ============== SAA7715 VIDEO templates (end) =======  */
 510
 511 static const unsigned char saa7115_cfg_vbi_on[] = {
 512         R_80_GLOBAL_CNTL_1, 0x00,                       /* reset tasks */
 513         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,            /* reset scaler */
 514         R_80_GLOBAL_CNTL_1, 0x30,                       /* Activate both tasks */
 515         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,            /* activate scaler */
 516         R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,    /* Enable I-port output */
 517
 518         0x00, 0x00
 519 };
 520
 521 static const unsigned char saa7115_cfg_vbi_off[] = {
 522         R_80_GLOBAL_CNTL_1, 0x00,                       /* reset tasks */
 523         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,            /* reset scaler */
 524         R_80_GLOBAL_CNTL_1, 0x20,                       /* Activate only task "B" */
 525         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,            /* activate scaler */
 526         R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,    /* Enable I-port output */
 527
 528         0x00, 0x00
 529 };
 530
 531
 532 static const unsigned char saa7115_init_misc[] = {
 533         R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F, 0x01,
 534         0x82, 0x00,             /* Reserved register - value should be zero*/
 535         R_83_X_PORT_I_O_ENA_AND_OUT_CLK, 0x01,
 536         R_84_I_PORT_SIGNAL_DEF, 0x20,
 537         R_85_I_PORT_SIGNAL_POLAR, 0x21,
 538         R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT, 0xc5,
 539         R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,
 540
 541         /* Task A */
 542         R_A0_A_HORIZ_PRESCALING, 0x01,
 543         R_A1_A_ACCUMULATION_LENGTH, 0x00,
 544         R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
 545
 546         /* Configure controls at nominal value*/
 547         R_A4_A_LUMA_BRIGHTNESS_CNTL, 0x80,
 548         R_A5_A_LUMA_CONTRAST_CNTL, 0x40,
 549         R_A6_A_CHROMA_SATURATION_CNTL, 0x40,
 550
 551         /* note: 2 x zoom ensures that VBI lines have same length as video lines. */
 552         R_A8_A_HORIZ_LUMA_SCALING_INC, 0x00,
 553         R_A9_A_HORIZ_LUMA_SCALING_INC_MSB, 0x02,
 554
 555         R_AA_A_HORIZ_LUMA_PHASE_OFF, 0x00,
 556
 557         /* must be horiz lum scaling / 2 */
 558         R_AC_A_HORIZ_CHROMA_SCALING_INC, 0x00,
 559         R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB, 0x01,
 560
 561         /* must be offset luma / 2 */
 562         R_AE_A_HORIZ_CHROMA_PHASE_OFF, 0x00,
 563
 564         R_B0_A_VERT_LUMA_SCALING_INC, 0x00,
 565         R_B1_A_VERT_LUMA_SCALING_INC_MSB, 0x04,
 566
 567         R_B2_A_VERT_CHROMA_SCALING_INC, 0x00,
 568         R_B3_A_VERT_CHROMA_SCALING_INC_MSB, 0x04,
 569
 570         R_B4_A_VERT_SCALING_MODE_CNTL, 0x01,
 571
 572         R_B8_A_VERT_CHROMA_PHASE_OFF_00, 0x00,
 573         R_B9_A_VERT_CHROMA_PHASE_OFF_01, 0x00,
 574         R_BA_A_VERT_CHROMA_PHASE_OFF_10, 0x00,
 575         R_BB_A_VERT_CHROMA_PHASE_OFF_11, 0x00,
 576
 577         R_BC_A_VERT_LUMA_PHASE_OFF_00, 0x00,
 578         R_BD_A_VERT_LUMA_PHASE_OFF_01, 0x00,
 579         R_BE_A_VERT_LUMA_PHASE_OFF_10, 0x00,
 580         R_BF_A_VERT_LUMA_PHASE_OFF_11, 0x00,
 581
 582         /* Task B */
 583         R_D0_B_HORIZ_PRESCALING, 0x01,
 584         R_D1_B_ACCUMULATION_LENGTH, 0x00,
 585         R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
 586
 587         /* Configure controls at nominal value*/
 588         R_D4_B_LUMA_BRIGHTNESS_CNTL, 0x80,
 589         R_D5_B_LUMA_CONTRAST_CNTL, 0x40,
 590         R_D6_B_CHROMA_SATURATION_CNTL, 0x40,
 591
 592         /* hor lum scaling 0x0400 = 1 */
 593         R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00,
 594         R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
 595
 596         R_DA_B_HORIZ_LUMA_PHASE_OFF, 0x00,
 597
 598         /* must be hor lum scaling / 2 */
 599         R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
 600         R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,
 601
 602         /* must be offset luma / 2 */
 603         R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA, 0x00,
 604
 605         R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
 606         R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,
 607
 608         R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
 609         R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
 610
 611         R_E4_B_VERT_SCALING_MODE_CNTL, 0x01,
 612
 613         R_E8_B_VERT_CHROMA_PHASE_OFF_00, 0x00,
 614         R_E9_B_VERT_CHROMA_PHASE_OFF_01, 0x00,
 615         R_EA_B_VERT_CHROMA_PHASE_OFF_10, 0x00,
 616         R_EB_B_VERT_CHROMA_PHASE_OFF_11, 0x00,
 617
 618         R_EC_B_VERT_LUMA_PHASE_OFF_00, 0x00,
 619         R_ED_B_VERT_LUMA_PHASE_OFF_01, 0x00,
 620         R_EE_B_VERT_LUMA_PHASE_OFF_10, 0x00,
 621         R_EF_B_VERT_LUMA_PHASE_OFF_11, 0x00,
 622
 623         R_F2_NOMINAL_PLL2_DTO, 0x50,            /* crystal clock = 24.576 MHz, target = 27MHz */
 624         R_F3_PLL_INCREMENT, 0x46,
 625         R_F4_PLL2_STATUS, 0x00,
 626         R_F7_PULSE_A_POS_MSB, 0x4b,             /* not the recommended settings! */
 627         R_F8_PULSE_B_POS, 0x00,
 628         R_F9_PULSE_B_POS_MSB, 0x4b,
 629         R_FA_PULSE_C_POS, 0x00,
 630         R_FB_PULSE_C_POS_MSB, 0x4b,
 631
 632         /* PLL2 lock detection settings: 71 lines 50% phase error */
 633         R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES, 0x88,
 634
 635         /* Turn off VBI */
 636         R_40_SLICER_CNTL_1, 0x20,             /* No framing code errors allowed. */
 637         R_41_LCR_BASE, 0xff,
 638         R_41_LCR_BASE+1, 0xff,
 639         R_41_LCR_BASE+2, 0xff,
 640         R_41_LCR_BASE+3, 0xff,
 641         R_41_LCR_BASE+4, 0xff,
 642         R_41_LCR_BASE+5, 0xff,
 643         R_41_LCR_BASE+6, 0xff,
 644         R_41_LCR_BASE+7, 0xff,
 645         R_41_LCR_BASE+8, 0xff,
 646         R_41_LCR_BASE+9, 0xff,
 647         R_41_LCR_BASE+10, 0xff,
 648         R_41_LCR_BASE+11, 0xff,
 649         R_41_LCR_BASE+12, 0xff,
 650         R_41_LCR_BASE+13, 0xff,
 651         R_41_LCR_BASE+14, 0xff,
 652         R_41_LCR_BASE+15, 0xff,
 653         R_41_LCR_BASE+16, 0xff,
 654         R_41_LCR_BASE+17, 0xff,
 655         R_41_LCR_BASE+18, 0xff,
 656         R_41_LCR_BASE+19, 0xff,
 657         R_41_LCR_BASE+20, 0xff,
 658         R_41_LCR_BASE+21, 0xff,
 659         R_41_LCR_BASE+22, 0xff,
 660         R_58_PROGRAM_FRAMING_CODE, 0x40,
 661         R_59_H_OFF_FOR_SLICER, 0x47,
 662         R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF, 0x83,
 663         R_5D_DID, 0xbd,
 664         R_5E_SDID, 0x35,
 665
 666         R_02_INPUT_CNTL_1, 0x84,                /* input tuner -> input 4, amplifier active */
 667         R_09_LUMA_CNTL, 0x53,                   /* 0x53, was 0x56 for 60hz. luminance control */
 668
 669         R_80_GLOBAL_CNTL_1, 0x20,               /* enable task B */
 670         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,
 671         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,
 672         0x00, 0x00
 673 };
 674
 675 static int saa7115_odd_parity(u8 c)
 676 {
 677         c ^= (c >> 4);
 678         c ^= (c >> 2);
 679         c ^= (c >> 1);
 680
 681         return c & 1;
 682 }
 683
 684 static int saa7115_decode_vps(u8 * dst, u8 * p)
 685 {
 686         static const u8 biphase_tbl[] = {
 687                 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
 688                 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
 689                 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
 690                 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
 691                 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
 692                 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
 693                 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
 694                 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
 695                 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
 696                 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
 697                 0xc3, 0x4b, 0x43, 0xc3, 0x87, 0x0f, 0x07, 0x87,
 698                 0x83, 0x0b, 0x03, 0x83, 0xc3, 0x4b, 0x43, 0xc3,
 699                 0xc1, 0x49, 0x41, 0xc1, 0x85, 0x0d, 0x05, 0x85,
 700                 0x81, 0x09, 0x01, 0x81, 0xc1, 0x49, 0x41, 0xc1,
 701                 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
 702                 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
 703                 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
 704                 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
 705                 0xc2, 0x4a, 0x42, 0xc2, 0x86, 0x0e, 0x06, 0x86,
 706                 0x82, 0x0a, 0x02, 0x82, 0xc2, 0x4a, 0x42, 0xc2,
 707                 0xc0, 0x48, 0x40, 0xc0, 0x84, 0x0c, 0x04, 0x84,
 708                 0x80, 0x08, 0x00, 0x80, 0xc0, 0x48, 0x40, 0xc0,
 709                 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
 710                 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
 711                 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
 712                 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
 713                 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
 714                 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
 715                 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
 716                 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
 717                 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
 718                 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
 719         };
 720         int i;
 721         u8 c, err = 0;
 722
 723         for (i = 0; i < 2 * 13; i += 2) {
 724                 err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]];
 725                 c = (biphase_tbl[p[i + 1]] & 0xf) | ((biphase_tbl[p[i]] & 0xf) << 4);
 726                 dst[i / 2] = c;
 727         }
 728         return err & 0xf0;
 729 }
 730
 731 static int saa7115_decode_wss(u8 * p)
 732 {
 733         static const int wss_bits[8] = {
 734                 0, 0, 0, 1, 0, 1, 1, 1
 735         };
 736         unsigned char parity;
 737         int wss = 0;
 738         int i;
 739
 740         for (i = 0; i < 16; i++) {
 741                 int b1 = wss_bits[p[i] & 7];
 742                 int b2 = wss_bits[(p[i] >> 3) & 7];
 743
 744                 if (b1 == b2)
 745                         return -1;
 746                 wss |= b2 << i;
 747         }
 748         parity = wss & 15;
 749         parity ^= parity >> 2;
 750         parity ^= parity >> 1;
 751
 752         if (!(parity & 1))
 753                 return -1;
 754
 755         return wss;
 756 }
 757
 758 static int saa7115_set_audio_clock_freq(struct i2c_client *client, u32 freq)
 759 {
 760         struct saa7115_state *state = i2c_get_clientdata(client);
 761         u32 acpf;
 762         u32 acni;
 763         u32 hz;
 764         u64 f;
 765         u8 acc = 0;     /* reg 0x3a, audio clock control */
 766
 767         /* Checks for chips that don't have audio clock (saa7111, saa7113) */
 768         if (!saa711x_has_reg(state->ident,R_30_AUD_MAST_CLK_CYCLES_PER_FIELD))
 769                 return 0;
 770
 771         v4l_dbg(1, debug, client, "set audio clock freq: %d\n", freq);
 772
 773         /* sanity check */
 774         if (freq < 32000 || freq > 48000)
 775                 return -EINVAL;
 776
 777         /* hz is the refresh rate times 100 */
 778         hz = (state->std & V4L2_STD_525_60) ? 5994 : 5000;
 779         /* acpf = (256 * freq) / field_frequency == (256 * 100 * freq) / hz */
 780         acpf = (25600 * freq) / hz;
 781         /* acni = (256 * freq * 2^23) / crystal_frequency =
 782                   (freq * 2^(8+23)) / crystal_frequency =
 783                   (freq << 31) / crystal_frequency */
 784         f = freq;
 785         f = f << 31;
 786         do_div(f, state->crystal_freq);
 787         acni = f;
 788         if (state->ucgc) {
 789                 acpf = acpf * state->cgcdiv / 16;
 790                 acni = acni * state->cgcdiv / 16;
 791                 acc = 0x80;
 792                 if (state->cgcdiv == 3)
 793                         acc |= 0x40;
 794         }
 795         if (state->apll)
 796                 acc |= 0x08;
 797
 798         saa7115_write(client, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03);
 799         saa7115_write(client, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10);
 800         saa7115_write(client, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc);
 801
 802         saa7115_write(client, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff);
 803         saa7115_write(client, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+1,
 804                                                         (acpf >> 8) & 0xff);
 805         saa7115_write(client, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+2,
 806                                                         (acpf >> 16) & 0x03);
 807
 808         saa7115_write(client, R_34_AUD_MAST_CLK_NOMINAL_INC, acni & 0xff);
 809         saa7115_write(client, R_34_AUD_MAST_CLK_NOMINAL_INC+1, (acni >> 8) & 0xff);
 810         saa7115_write(client, R_34_AUD_MAST_CLK_NOMINAL_INC+2, (acni >> 16) & 0x3f);
 811         state->audclk_freq = freq;
 812         return 0;
 813 }
 814
 815 static int saa7115_set_v4lctrl(struct i2c_client *client, struct v4l2_control *ctrl)
 816 {
 817         struct saa7115_state *state = i2c_get_clientdata(client);
 818
 819         switch (ctrl->id) {
 820         case V4L2_CID_BRIGHTNESS:
 821                 if (ctrl->value < 0 || ctrl->value > 255) {
 822                         v4l_err(client, "invalid brightness setting %d\n", ctrl->value);
 823                         return -ERANGE;
 824                 }
 825
 826                 state->bright = ctrl->value;
 827                 saa7115_write(client, R_0A_LUMA_BRIGHT_CNTL, state->bright);
 828                 break;
 829
 830         case V4L2_CID_CONTRAST:
 831                 if (ctrl->value < 0 || ctrl->value > 127) {
 832                         v4l_err(client, "invalid contrast setting %d\n", ctrl->value);
 833                         return -ERANGE;
 834                 }
 835
 836                 state->contrast = ctrl->value;
 837                 saa7115_write(client, R_0B_LUMA_CONTRAST_CNTL, state->contrast);
 838                 break;
 839
 840         case V4L2_CID_SATURATION:
 841                 if (ctrl->value < 0 || ctrl->value > 127) {
 842                         v4l_err(client, "invalid saturation setting %d\n", ctrl->value);
 843                         return -ERANGE;
 844                 }
 845
 846                 state->sat = ctrl->value;
 847                 saa7115_write(client, R_0C_CHROMA_SAT_CNTL, state->sat);
 848                 break;
 849
 850         case V4L2_CID_HUE:
 851                 if (ctrl->value < -127 || ctrl->value > 127) {
 852                         v4l_err(client, "invalid hue setting %d\n", ctrl->value);
 853                         return -ERANGE;
 854                 }
 855
 856                 state->hue = ctrl->value;
 857                 saa7115_write(client, R_0D_CHROMA_HUE_CNTL, state->hue);
 858                 break;
 859
 860         default:
 861                 return -EINVAL;
 862         }
 863
 864         return 0;
 865 }
 866
 867 static int saa7115_get_v4lctrl(struct i2c_client *client, struct v4l2_control *ctrl)
 868 {
 869         struct saa7115_state *state = i2c_get_clientdata(client);
 870
 871         switch (ctrl->id) {
 872         case V4L2_CID_BRIGHTNESS:
 873                 ctrl->value = state->bright;
 874                 break;
 875         case V4L2_CID_CONTRAST:
 876                 ctrl->value = state->contrast;
 877                 break;
 878         case V4L2_CID_SATURATION:
 879                 ctrl->value = state->sat;
 880                 break;
 881         case V4L2_CID_HUE:
 882                 ctrl->value = state->hue;
 883                 break;
 884         default:
 885                 return -EINVAL;
 886         }
 887
 888         return 0;
 889 }
 890
 891 static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std)
 892 {
 893         struct saa7115_state *state = i2c_get_clientdata(client);
 894
 895         /* Prevent unnecessary standard changes. During a standard
 896            change the I-Port is temporarily disabled. Any devices
 897            reading from that port can get confused.
 898            Note that VIDIOC_S_STD is also used to switch from
 899            radio to TV mode, so if a VIDIOC_S_STD is broadcast to
 900            all I2C devices then you do not want to have an unwanted
 901            side-effect here. */
 902         if (std == state->std)
 903                 return;
 904
 905         // This works for NTSC-M, SECAM-L and the 50Hz PAL variants.
 906         if (std & V4L2_STD_525_60) {
 907                 v4l_dbg(1, debug, client, "decoder set standard 60 Hz\n");
 908                 saa7115_writeregs(client, saa7115_cfg_60hz_video);
 909         } else {
 910                 v4l_dbg(1, debug, client, "decoder set standard 50 Hz\n");
 911                 saa7115_writeregs(client, saa7115_cfg_50hz_video);
 912         }
 913
 914         /* Register 0E - Bits D6-D4 on NO-AUTO mode
 915                 (SAA7111 and SAA7113 doesn't have auto mode)
 916             50 Hz / 625 lines           60 Hz / 525 lines
 917         000 PAL BGDHI (4.43Mhz)         NTSC M (3.58MHz)
 918         001 NTSC 4.43 (50 Hz)           PAL 4.43 (60 Hz)
 919         010 Combination-PAL N (3.58MHz) NTSC 4.43 (60 Hz)
 920         011 NTSC N (3.58MHz)            PAL M (3.58MHz)
 921         100 reserved                    NTSC-Japan (3.58MHz)
 922         */
 923         if (state->ident == V4L2_IDENT_SAA7111 ||
 924             state->ident == V4L2_IDENT_SAA7113) {
 925                 u8 reg = saa7115_read(client, R_0E_CHROMA_CNTL_1) & 0x8f;
 926
 927                 if (std == V4L2_STD_PAL_M) {
 928                         reg |= 0x30;
 929                 } else if (std == V4L2_STD_PAL_N) {
 930                         reg |= 0x20;
 931                 } else if (std == V4L2_STD_PAL_60) {
 932                         reg |= 0x10;
 933                 } else if (std == V4L2_STD_NTSC_M_JP) {
 934                         reg |= 0x40;
 935                 }
 936                 saa7115_write(client, R_0E_CHROMA_CNTL_1, reg);
 937         } else {
 938                 /* restart task B if needed */
 939                 int taskb = saa7115_read(client, R_80_GLOBAL_CNTL_1) & 0x10;
 940
 941                 if (taskb && state->ident == V4L2_IDENT_SAA7114) {
 942                         saa7115_writeregs(client, saa7115_cfg_vbi_on);
 943                 }
 944
 945                 /* switch audio mode too! */
 946                 saa7115_set_audio_clock_freq(client, state->audclk_freq);
 947         }
 948
 949         state->std = std;
 950 }
 951
 952 static v4l2_std_id saa7115_get_v4lstd(struct i2c_client *client)
 953 {
 954         struct saa7115_state *state = i2c_get_clientdata(client);
 955
 956         return state->std;
 957 }
 958
 959 static void saa7115_log_status(struct i2c_client *client)
 960 {
 961         struct saa7115_state *state = i2c_get_clientdata(client);
 962         int reg1e, reg1f;
 963         int signalOk;
 964         int vcr;
 965
 966         v4l_info(client, "Audio frequency: %d Hz\n", state->audclk_freq);
 967         if (state->ident != V4L2_IDENT_SAA7115) {
 968                 /* status for the saa7114 */
 969                 reg1f = saa7115_read(client, R_1F_STATUS_BYTE_2_VD_DEC);
 970                 signalOk = (reg1f & 0xc1) == 0x81;
 971                 v4l_info(client, "Video signal:    %s\n", signalOk ? "ok" : "bad");
 972                 v4l_info(client, "Frequency:       %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
 973                 return;
 974         }
 975
 976         /* status for the saa7115 */
 977         reg1e = saa7115_read(client, R_1E_STATUS_BYTE_1_VD_DEC);
 978         reg1f = saa7115_read(client, R_1F_STATUS_BYTE_2_VD_DEC);
 979
 980         signalOk = (reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80;
 981         vcr = !(reg1f & 0x10);
 982
 983         if (state->input >= 6) {
 984                 v4l_info(client, "Input:           S-Video %d\n", state->input - 6);
 985         } else {
 986                 v4l_info(client, "Input:           Composite %d\n", state->input);
 987         }
 988         v4l_info(client, "Video signal:    %s\n", signalOk ? (vcr ? "VCR" : "broadcast/DVD") : "bad");
 989         v4l_info(client, "Frequency:       %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
 990
 991         switch (reg1e & 0x03) {
 992                 case 1:
 993                         v4l_info(client, "Detected format: NTSC\n");
 994                         break;
 995                 case 2:
 996                         v4l_info(client, "Detected format: PAL\n");
 997                         break;
 998                 case 3:
 999                         v4l_info(client, "Detected format: SECAM\n");
1000                         break;
1001                 default:
1002                         v4l_info(client, "Detected format: BW/No color\n");
1003                         break;
1004         }
1005 }
1006
1007 /* setup the sliced VBI lcr registers according to the sliced VBI format */
1008 static void saa7115_set_lcr(struct i2c_client *client, struct v4l2_sliced_vbi_format *fmt)
1009 {
1010         struct saa7115_state *state = i2c_get_clientdata(client);
1011         int is_50hz = (state->std & V4L2_STD_625_50);
1012         u8 lcr[24];
1013         int i, x;
1014
1015 #if 1
1016         /* saa7113/7114/7118 VBI support are experimental */
1017         if (!saa711x_has_reg(state->ident,R_41_LCR_BASE))
1018                 return;
1019
1020 #else
1021         /* SAA7113 and SAA7118 also should support VBI - Need testing */
1022         if (state->ident != V4L2_IDENT_SAA7115)
1023                 return;
1024 #endif
1025
1026         for (i = 0; i <= 23; i++)
1027                 lcr[i] = 0xff;
1028
1029         if (fmt->service_set == 0) {
1030                 /* raw VBI */
1031                 if (is_50hz)
1032                         for (i = 6; i <= 23; i++)
1033                                 lcr[i] = 0xdd;
1034                 else
1035                         for (i = 10; i <= 21; i++)
1036                                 lcr[i] = 0xdd;
1037         } else {
1038                 /* sliced VBI */
1039                 /* first clear lines that cannot be captured */
1040                 if (is_50hz) {
1041                         for (i = 0; i <= 5; i++)
1042                                 fmt->service_lines[0][i] =
1043                                         fmt->service_lines[1][i] = 0;
1044                 }
1045                 else {
1046                         for (i = 0; i <= 9; i++)
1047                                 fmt->service_lines[0][i] =
1048                                         fmt->service_lines[1][i] = 0;
1049                         for (i = 22; i <= 23; i++)
1050                                 fmt->service_lines[0][i] =
1051                                         fmt->service_lines[1][i] = 0;
1052                 }
1053
1054                 /* Now set the lcr values according to the specified service */
1055                 for (i = 6; i <= 23; i++) {
1056                         lcr[i] = 0;
1057                         for (x = 0; x <= 1; x++) {
1058                                 switch (fmt->service_lines[1-x][i]) {
1059                                         case 0:
1060                                                 lcr[i] |= 0xf << (4 * x);
1061                                                 break;
1062                                         case V4L2_SLICED_TELETEXT_B:
1063                                                 lcr[i] |= 1 << (4 * x);
1064                                                 break;
1065                                         case V4L2_SLICED_CAPTION_525:
1066                                                 lcr[i] |= 4 << (4 * x);
1067                                                 break;
1068                                         case V4L2_SLICED_WSS_625:
1069                                                 lcr[i] |= 5 << (4 * x);
1070                                                 break;
1071                                         case V4L2_SLICED_VPS:
1072                                                 lcr[i] |= 7 << (4 * x);
1073                                                 break;
1074                                 }
1075                         }
1076                 }
1077         }
1078
1079         /* write the lcr registers */
1080         for (i = 2; i <= 23; i++) {
1081                 saa7115_write(client, i - 2 + R_41_LCR_BASE, lcr[i]);
1082         }
1083
1084         /* enable/disable raw VBI capturing */
1085         saa7115_writeregs(client, fmt->service_set == 0 ?
1086                                 saa7115_cfg_vbi_on :
1087                                 saa7115_cfg_vbi_off);
1088 }
1089
1090 static int saa7115_get_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt)
1091 {
1092         static u16 lcr2vbi[] = {
1093                 0, V4L2_SLICED_TELETEXT_B, 0,   /* 1 */
1094                 0, V4L2_SLICED_CAPTION_525,     /* 4 */
1095                 V4L2_SLICED_WSS_625, 0,         /* 5 */
1096                 V4L2_SLICED_VPS, 0, 0, 0, 0,    /* 7 */
1097                 0, 0, 0, 0
1098         };
1099         struct v4l2_sliced_vbi_format *sliced = &fmt->fmt.sliced;
1100         int i;
1101
1102         if (fmt->type != V4L2_BUF_TYPE_SLICED_VBI_CAPTURE)
1103                 return -EINVAL;
1104         memset(sliced, 0, sizeof(*sliced));
1105         /* done if using raw VBI */
1106         if (saa7115_read(client, R_80_GLOBAL_CNTL_1) & 0x10)
1107                 return 0;
1108         for (i = 2; i <= 23; i++) {
1109                 u8 v = saa7115_read(client, i - 2 + R_41_LCR_BASE);
1110
1111                 sliced->service_lines[0][i] = lcr2vbi[v >> 4];
1112                 sliced->service_lines[1][i] = lcr2vbi[v & 0xf];
1113                 sliced->service_set |=
1114                         sliced->service_lines[0][i] | sliced->service_lines[1][i];
1115         }
1116         return 0;
1117 }
1118
1119 static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt)
1120 {
1121         struct saa7115_state *state = i2c_get_clientdata(client);
1122         struct v4l2_pix_format *pix;
1123         int HPSC, HFSC;
1124         int VSCY;
1125         int is_50hz = state->std & V4L2_STD_625_50;
1126         int Vsrc = is_50hz ? 576 : 480;
1127
1128         if (fmt->type == V4L2_BUF_TYPE_SLICED_VBI_CAPTURE) {
1129                 saa7115_set_lcr(client, &fmt->fmt.sliced);
1130                 return 0;
1131         }
1132         if (fmt->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1133                 return -EINVAL;
1134
1135         pix = &(fmt->fmt.pix);
1136
1137         v4l_dbg(1, debug, client, "decoder set size\n");
1138
1139         /* FIXME need better bounds checking here */
1140         if ((pix->width < 1) || (pix->width > 1440))
1141                 return -EINVAL;
1142         if ((pix->height < 1) || (pix->height > 960))
1143                 return -EINVAL;
1144
1145         if (!saa711x_has_reg(state->ident,R_D0_B_HORIZ_PRESCALING)) {
1146                 /* Decoder only supports 720 columns and 480 or 576 lines */
1147                 if (pix->width != 720)
1148                         return -EINVAL;
1149                 if (pix->height != Vsrc)
1150                         return -EINVAL;
1151         }
1152
1153         /* probably have a valid size, let's set it */
1154         /* Set output width/height */
1155         /* width */
1156
1157         if (!saa711x_has_reg(state->ident,R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH)) {
1158                 saa7115_write(client, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,
1159                                         (u8) (pix->width & 0xff));
1160                 saa7115_write(client, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB,
1161                                         (u8) ((pix->width >> 8) & 0xff));
1162                 /* height */
1163                 saa7115_write(client, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,
1164                                         (u8) (pix->height & 0xff));
1165                 saa7115_write(client, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB,
1166                                         (u8) ((pix->height >> 8) & 0xff));
1167         }
1168
1169         /* Scaling settings */
1170         /* Hprescaler is floor(inres/outres) */
1171         /* FIXME hardcoding input res */
1172         if (pix->width != 720) {
1173                 HPSC = (int)(720 / pix->width);
1174                 /* 0 is not allowed (div. by zero) */
1175                 HPSC = HPSC ? HPSC : 1;
1176                 HFSC = (int)((1024 * 720) / (HPSC * pix->width));
1177
1178                 v4l_dbg(1, debug, client, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC);
1179                 /* FIXME hardcodes to "Task B"
1180                  * write H prescaler integer */
1181                 saa7115_write(client, R_D0_B_HORIZ_PRESCALING,
1182                                         (u8) (HPSC & 0x3f));
1183
1184                 /* write H fine-scaling (luminance) */
1185                 saa7115_write(client, R_D8_B_HORIZ_LUMA_SCALING_INC,
1186                                         (u8) (HFSC & 0xff));
1187                 saa7115_write(client, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB,
1188                                         (u8) ((HFSC >> 8) & 0xff));
1189                 /* write H fine-scaling (chrominance)
1190                  * must be lum/2, so i'll just bitshift :) */
1191                 saa7115_write(client, R_DC_B_HORIZ_CHROMA_SCALING,
1192                                         (u8) ((HFSC >> 1) & 0xff));
1193                 saa7115_write(client, R_DD_B_HORIZ_CHROMA_SCALING_MSB,
1194                                         (u8) ((HFSC >> 9) & 0xff));
1195         } else {
1196                 if (is_50hz) {
1197                         v4l_dbg(1, debug, client, "Setting full 50hz width\n");
1198                         saa7115_writeregs(client, saa7115_cfg_50hz_fullres_x);
1199                 } else {
1200                         v4l_dbg(1, debug, client, "Setting full 60hz width\n");
1201                         saa7115_writeregs(client, saa7115_cfg_60hz_fullres_x);
1202                 }
1203         }
1204
1205         if (pix->height != Vsrc) {
1206                 VSCY = (int)((1024 * Vsrc) / pix->height);
1207                 v4l_dbg(1, debug, client, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY);
1208
1209                 /* Correct Contrast and Luminance */
1210                 saa7115_write(client, R_D5_B_LUMA_CONTRAST_CNTL,
1211                                         (u8) (64 * 1024 / VSCY));
1212                 saa7115_write(client, R_D6_B_CHROMA_SATURATION_CNTL,
1213                                         (u8) (64 * 1024 / VSCY));
1214
1215                 /* write V fine-scaling (luminance) */
1216                 saa7115_write(client, R_E0_B_VERT_LUMA_SCALING_INC,
1217                                         (u8) (VSCY & 0xff));
1218                 saa7115_write(client, R_E1_B_VERT_LUMA_SCALING_INC_MSB,
1219                                         (u8) ((VSCY >> 8) & 0xff));
1220                 /* write V fine-scaling (chrominance) */
1221                 saa7115_write(client, R_E2_B_VERT_CHROMA_SCALING_INC,
1222                                         (u8) (VSCY & 0xff));
1223                 saa7115_write(client, R_E3_B_VERT_CHROMA_SCALING_INC_MSB,
1224                                         (u8) ((VSCY >> 8) & 0xff));
1225         } else {
1226                 if (is_50hz) {
1227                         v4l_dbg(1, debug, client, "Setting full 50Hz height\n");
1228                         saa7115_writeregs(client, saa7115_cfg_50hz_fullres_y);
1229                 } else {
1230                         v4l_dbg(1, debug, client, "Setting full 60hz height\n");
1231                         saa7115_writeregs(client, saa7115_cfg_60hz_fullres_y);
1232                 }
1233         }
1234
1235         saa7115_writeregs(client, saa7115_cfg_reset_scaler);
1236
1237         return 0;
1238 }
1239
1240 /* Decode the sliced VBI data stream as created by the saa7115.
1241    The format is described in the saa7115 datasheet in Tables 25 and 26
1242    and in Figure 33.
1243    The current implementation uses SAV/EAV codes and not the ancillary data
1244    headers. The vbi->p pointer points to the R_5E_SDID byte right after the SAV
1245    code. */
1246 static void saa7115_decode_vbi_line(struct i2c_client *client,
1247                                     struct v4l2_decode_vbi_line *vbi)
1248 {
1249         static const char vbi_no_data_pattern[] = {
1250                 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0
1251         };
1252         struct saa7115_state *state = i2c_get_clientdata(client);
1253         u8 *p = vbi->p;
1254         u32 wss;
1255         int id1, id2;   /* the ID1 and ID2 bytes from the internal header */
1256
1257         vbi->type = 0;  /* mark result as a failure */
1258         id1 = p[2];
1259         id2 = p[3];
1260         /* Note: the field bit is inverted for 60 Hz video */
1261         if (state->std & V4L2_STD_525_60)
1262                 id1 ^= 0x40;
1263
1264         /* Skip internal header, p now points to the start of the payload */
1265         p += 4;
1266         vbi->p = p;
1267
1268         /* calculate field and line number of the VBI packet (1-23) */
1269         vbi->is_second_field = ((id1 & 0x40) != 0);
1270         vbi->line = (id1 & 0x3f) << 3;
1271         vbi->line |= (id2 & 0x70) >> 4;
1272
1273         /* Obtain data type */
1274         id2 &= 0xf;
1275
1276         /* If the VBI slicer does not detect any signal it will fill up
1277            the payload buffer with 0xa0 bytes. */
1278         if (!memcmp(p, vbi_no_data_pattern, sizeof(vbi_no_data_pattern)))
1279                 return;
1280
1281         /* decode payloads */
1282         switch (id2) {
1283         case 1:
1284                 vbi->type = V4L2_SLICED_TELETEXT_B;
1285                 break;
1286         case 4:
1287                 if (!saa7115_odd_parity(p[0]) || !saa7115_odd_parity(p[1]))
1288                         return;
1289                 vbi->type = V4L2_SLICED_CAPTION_525;
1290                 break;
1291         case 5:
1292                 wss = saa7115_decode_wss(p);
1293                 if (wss == -1)
1294                         return;
1295                 p[0] = wss & 0xff;
1296                 p[1] = wss >> 8;
1297                 vbi->type = V4L2_SLICED_WSS_625;
1298                 break;
1299         case 7:
1300                 if (saa7115_decode_vps(p, p) != 0)
1301                         return;
1302                 vbi->type = V4L2_SLICED_VPS;
1303                 break;
1304         default:
1305                 return;
1306         }
1307 }
1308
1309 /* ============ SAA7115 AUDIO settings (end) ============= */
1310
1311 static int saa7115_command(struct i2c_client *client, unsigned int cmd, void *arg)
1312 {
1313         struct saa7115_state *state = i2c_get_clientdata(client);
1314         int *iarg = arg;
1315
1316         /* ioctls to allow direct access to the saa7115 registers for testing */
1317         switch (cmd) {
1318         case VIDIOC_S_FMT:
1319                 return saa7115_set_v4lfmt(client, (struct v4l2_format *)arg);
1320
1321         case VIDIOC_G_FMT:
1322                 return saa7115_get_v4lfmt(client, (struct v4l2_format *)arg);
1323
1324         case VIDIOC_INT_AUDIO_CLOCK_FREQ:
1325                 return saa7115_set_audio_clock_freq(client, *(u32 *)arg);
1326
1327         case VIDIOC_G_TUNER:
1328         {
1329                 struct v4l2_tuner *vt = arg;
1330                 int status;
1331
1332                 if (state->radio)
1333                         break;
1334                 status = saa7115_read(client, R_1F_STATUS_BYTE_2_VD_DEC);
1335
1336                 v4l_dbg(1, debug, client, "status: 0x%02x\n", status);
1337                 vt->signal = ((status & (1 << 6)) == 0) ? 0xffff : 0x0;
1338                 break;
1339         }
1340
1341         case VIDIOC_LOG_STATUS:
1342                 saa7115_log_status(client);
1343                 break;
1344
1345         case VIDIOC_G_CTRL:
1346                 return saa7115_get_v4lctrl(client, (struct v4l2_control *)arg);
1347
1348         case VIDIOC_S_CTRL:
1349                 return saa7115_set_v4lctrl(client, (struct v4l2_control *)arg);
1350
1351         case VIDIOC_QUERYCTRL:
1352         {
1353                 struct v4l2_queryctrl *qc = arg;
1354
1355                 switch (qc->id) {
1356                         case V4L2_CID_BRIGHTNESS:
1357                         case V4L2_CID_CONTRAST:
1358                         case V4L2_CID_SATURATION:
1359                         case V4L2_CID_HUE:
1360                                 return v4l2_ctrl_query_fill_std(qc);
1361                         default:
1362                                 return -EINVAL;
1363                 }
1364         }
1365
1366         case VIDIOC_G_STD:
1367                 *(v4l2_std_id *)arg = saa7115_get_v4lstd(client);
1368                 break;
1369
1370         case VIDIOC_S_STD:
1371                 state->radio = 0;
1372                 saa7115_set_v4lstd(client, *(v4l2_std_id *)arg);
1373                 break;
1374
1375         case AUDC_SET_RADIO:
1376                 state->radio = 1;
1377                 break;
1378
1379         case VIDIOC_INT_G_VIDEO_ROUTING:
1380         {
1381                 struct v4l2_routing *route = arg;
1382
1383                 route->input = state->input;
1384                 route->output = 0;
1385                 break;
1386         }
1387
1388         case VIDIOC_INT_S_VIDEO_ROUTING:
1389         {
1390                 struct v4l2_routing *route = arg;
1391
1392                 v4l_dbg(1, debug, client, "decoder set input %d\n", route->input);
1393                 /* saa7113 does not have these inputs */
1394                 if (state->ident == V4L2_IDENT_SAA7113 &&
1395                     (route->input == SAA7115_COMPOSITE4 ||
1396                      route->input == SAA7115_COMPOSITE5)) {
1397                         return -EINVAL;
1398                 }
1399                 if (route->input > SAA7115_SVIDEO3)
1400                         return -EINVAL;
1401                 if (state->input == route->input)
1402                         break;
1403                 v4l_dbg(1, debug, client, "now setting %s input\n",
1404                         (route->input >= SAA7115_SVIDEO0) ? "S-Video" : "Composite");
1405                 state->input = route->input;
1406
1407                 /* select mode */
1408                 saa7115_write(client, R_02_INPUT_CNTL_1,
1409                               (saa7115_read(client, R_02_INPUT_CNTL_1) & 0xf0) |
1410                                state->input);
1411
1412                 /* bypass chrominance trap for S-Video modes */
1413                 saa7115_write(client, R_09_LUMA_CNTL,
1414                               (saa7115_read(client, R_09_LUMA_CNTL) & 0x7f) |
1415                                (state->input >= SAA7115_SVIDEO0 ? 0x80 : 0x0));
1416                 break;
1417         }
1418
1419         case VIDIOC_STREAMON:
1420         case VIDIOC_STREAMOFF:
1421                 v4l_dbg(1, debug, client, "%s output\n",
1422                         (cmd == VIDIOC_STREAMON) ? "enable" : "disable");
1423
1424                 if (state->enable != (cmd == VIDIOC_STREAMON)) {
1425                         state->enable = (cmd == VIDIOC_STREAMON);
1426                         saa7115_write(client,
1427                                 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED,
1428                                 state->enable);
1429                 }
1430                 break;
1431
1432         case VIDIOC_INT_S_CRYSTAL_FREQ:
1433         {
1434                 struct v4l2_crystal_freq *freq = arg;
1435
1436                 if (freq->freq != SAA7115_FREQ_32_11_MHZ &&
1437                     freq->freq != SAA7115_FREQ_24_576_MHZ)
1438                         return -EINVAL;
1439                 state->crystal_freq = freq->freq;
1440                 state->cgcdiv = (freq->flags & SAA7115_FREQ_FL_CGCDIV) ? 3 : 4;
1441                 state->ucgc = (freq->flags & SAA7115_FREQ_FL_UCGC) ? 1 : 0;
1442                 state->apll = (freq->flags & SAA7115_FREQ_FL_APLL) ? 1 : 0;
1443                 saa7115_set_audio_clock_freq(client, state->audclk_freq);
1444                 break;
1445         }
1446
1447         case VIDIOC_INT_DECODE_VBI_LINE:
1448                 saa7115_decode_vbi_line(client, arg);
1449                 break;
1450
1451         case VIDIOC_INT_RESET:
1452                 v4l_dbg(1, debug, client, "decoder RESET\n");
1453                 saa7115_writeregs(client, saa7115_cfg_reset_scaler);
1454                 break;
1455
1456         case VIDIOC_INT_G_VBI_DATA:
1457         {
1458                 struct v4l2_sliced_vbi_data *data = arg;
1459
1460                 switch (data->id) {
1461                 case V4L2_SLICED_WSS_625:
1462                         if (saa7115_read(client, 0x6b) & 0xc0)
1463                                 return -EIO;
1464                         data->data[0] = saa7115_read(client, 0x6c);
1465                         data->data[1] = saa7115_read(client, 0x6d);
1466                         return 0;
1467                 case V4L2_SLICED_CAPTION_525:
1468                         if (data->field == 0) {
1469                                 /* CC */
1470                                 if (saa7115_read(client, 0x66) & 0xc0)
1471                                         return -EIO;
1472                                 data->data[0] = saa7115_read(client, 0x67);
1473                                 data->data[1] = saa7115_read(client, 0x68);
1474                                 return 0;
1475                         }
1476                         /* XDS */
1477                         if (saa7115_read(client, 0x66) & 0x30)
1478                                 return -EIO;
1479                         data->data[0] = saa7115_read(client, 0x69);
1480                         data->data[1] = saa7115_read(client, 0x6a);
1481                         return 0;
1482                 default:
1483                         return -EINVAL;
1484                 }
1485                 break;
1486         }
1487
1488 #ifdef CONFIG_VIDEO_ADV_DEBUG
1489         case VIDIOC_INT_G_REGISTER:
1490         {
1491                 struct v4l2_register *reg = arg;
1492
1493                 if (reg->i2c_id != I2C_DRIVERID_SAA711X)
1494                         return -EINVAL;
1495                 reg->val = saa7115_read(client, reg->reg & 0xff);
1496                 break;
1497         }
1498
1499         case VIDIOC_INT_S_REGISTER:
1500         {
1501                 struct v4l2_register *reg = arg;
1502
1503                 if (reg->i2c_id != I2C_DRIVERID_SAA711X)
1504                         return -EINVAL;
1505                 if (!capable(CAP_SYS_ADMIN))
1506                         return -EPERM;
1507                 saa7115_write(client, reg->reg & 0xff, reg->val & 0xff);
1508                 break;
1509         }
1510 #endif
1511
1512         case VIDIOC_INT_G_CHIP_IDENT:
1513                 *iarg = state->ident;
1514                 break;
1515
1516         default:
1517                 return -EINVAL;
1518         }
1519
1520         return 0;
1521 }
1522
1523 /* ----------------------------------------------------------------------- */
1524
1525 static struct i2c_driver i2c_driver_saa7115;
1526
1527 static int saa7115_attach(struct i2c_adapter *adapter, int address, int kind)
1528 {
1529         struct i2c_client *client;
1530         struct saa7115_state *state;
1531         int     i;
1532         char    name[17];
1533         u8 chip_id;
1534
1535         /* Check if the adapter supports the needed features */
1536         if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1537                 return 0;
1538
1539         client = kzalloc(sizeof(struct i2c_client), GFP_KERNEL);
1540         if (client == 0)
1541                 return -ENOMEM;
1542         client->addr = address;
1543         client->adapter = adapter;
1544         client->driver = &i2c_driver_saa7115;
1545         snprintf(client->name, sizeof(client->name) - 1, "saa7115");
1546
1547         v4l_dbg(1, debug, client, "detecting saa7115 client on address 0x%x\n", address << 1);
1548
1549         for (i=0;i<0x0f;i++) {
1550                 saa7115_write(client, 0, i);
1551                 name[i] = (saa7115_read(client, 0) &0x0f) +'0';
1552                 if (name[i]>'9')
1553                         name[i]+='a'-'9'-1;
1554         }
1555         name[i]='\0';
1556
1557         saa7115_write(client, 0, 5);
1558         chip_id = saa7115_read(client, 0) & 0x0f;
1559         if (chip_id < 3 && chip_id > 5) {
1560                 v4l_dbg(1, debug, client, "saa7115 not found\n");
1561                 kfree(client);
1562                 return 0;
1563         }
1564         snprintf(client->name, sizeof(client->name) - 1, "saa711%d",chip_id);
1565         v4l_info(client, "saa711%d found (%s) @ 0x%x (%s)\n", chip_id, name, address << 1, adapter->name);
1566
1567         state = kzalloc(sizeof(struct saa7115_state), GFP_KERNEL);
1568         i2c_set_clientdata(client, state);
1569         if (state == NULL) {
1570                 kfree(client);
1571                 return -ENOMEM;
1572         }
1573         state->std = V4L2_STD_NTSC;
1574         state->input = -1;
1575         state->enable = 1;
1576         state->radio = 0;
1577         state->bright = 128;
1578         state->contrast = 64;
1579         state->hue = 0;
1580         state->sat = 64;
1581         switch (chip_id) {
1582         case 1:
1583                 state->ident = V4L2_IDENT_SAA7111;
1584                 break;
1585         case 3:
1586                 state->ident = V4L2_IDENT_SAA7113;
1587                 break;
1588         case 4:
1589                 state->ident = V4L2_IDENT_SAA7114;
1590                 break;
1591         case 5:
1592                 state->ident = V4L2_IDENT_SAA7115;
1593                 break;
1594         case 8:
1595                 state->ident = V4L2_IDENT_SAA7118;
1596                 break;
1597         default:
1598                 state->ident = V4L2_IDENT_SAA7111;
1599                 v4l_info(client, "WARNING: Chip is not known - Falling back to saa7111\n");
1600
1601         }
1602
1603         state->audclk_freq = 48000;
1604
1605         v4l_dbg(1, debug, client, "writing init values\n");
1606
1607         /* init to 60hz/48khz */
1608         if (state->ident == V4L2_IDENT_SAA7111 ||
1609                         state->ident == V4L2_IDENT_SAA7113) {
1610                 state->crystal_freq = SAA7115_FREQ_24_576_MHZ;
1611                 saa7115_writeregs(client, saa7113_init_auto_input);
1612         } else {
1613                 state->crystal_freq = SAA7115_FREQ_32_11_MHZ;
1614                 saa7115_writeregs(client, saa7115_init_auto_input);
1615         }
1616         saa7115_writeregs(client, saa7115_init_misc);
1617         saa7115_writeregs(client, saa7115_cfg_60hz_fullres_x);
1618         saa7115_writeregs(client, saa7115_cfg_60hz_fullres_y);
1619         saa7115_writeregs(client, saa7115_cfg_60hz_video);
1620         saa7115_set_audio_clock_freq(client, state->audclk_freq);
1621         saa7115_writeregs(client, saa7115_cfg_reset_scaler);
1622
1623         i2c_attach_client(client);
1624
1625         v4l_dbg(1, debug, client, "status: (1E) 0x%02x, (1F) 0x%02x\n",
1626                 saa7115_read(client, R_1E_STATUS_BYTE_1_VD_DEC), saa7115_read(client, R_1F_STATUS_BYTE_2_VD_DEC));
1627
1628         return 0;
1629 }
1630
1631 static int saa7115_probe(struct i2c_adapter *adapter)
1632 {
1633         if (adapter->class & I2C_CLASS_TV_ANALOG)
1634                 return i2c_probe(adapter, &addr_data, &saa7115_attach);
1635         return 0;
1636 }
1637
1638 static int saa7115_detach(struct i2c_client *client)
1639 {
1640         struct saa7115_state *state = i2c_get_clientdata(client);
1641         int err;
1642
1643         err = i2c_detach_client(client);
1644         if (err) {
1645                 return err;
1646         }
1647
1648         kfree(state);
1649         kfree(client);
1650         return 0;
1651 }
1652
1653 /* ----------------------------------------------------------------------- */
1654
1655 /* i2c implementation */
1656 static struct i2c_driver i2c_driver_saa7115 = {
1657         .driver = {
1658                 .name = "saa7115",
1659         },
1660         .id = I2C_DRIVERID_SAA711X,
1661         .attach_adapter = saa7115_probe,
1662         .detach_client = saa7115_detach,
1663         .command = saa7115_command,
1664 };
1665
1666
1667 static int __init saa7115_init_module(void)
1668 {
1669         return i2c_add_driver(&i2c_driver_saa7115);
1670 }
1671
1672 static void __exit saa7115_cleanup_module(void)
1673 {
1674         i2c_del_driver(&i2c_driver_saa7115);
1675 }
1676
1677 module_init(saa7115_init_module);
1678 module_exit(saa7115_cleanup_module);