2 * V4L2 Driver for PXA camera host
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
30 #include <media/v4l2-common.h>
31 #include <media/v4l2-dev.h>
32 #include <media/videobuf-dma-sg.h>
33 #include <media/soc_camera.h>
35 #include <linux/videodev2.h>
38 #include <mach/camera.h>
40 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
41 #define PXA_CAM_DRV_NAME "pxa27x-camera"
43 /* Camera Interface */
56 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
57 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
58 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
59 #define CICR0_ENB (1 << 28) /* Camera interface enable */
60 #define CICR0_DIS (1 << 27) /* Camera interface disable */
61 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
62 #define CICR0_TOM (1 << 9) /* Time-out mask */
63 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
64 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
65 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
66 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
67 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
68 #define CICR0_CDM (1 << 3) /* Disable-done mask */
69 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
70 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
71 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
73 #define CICR1_TBIT (1 << 31) /* Transparency bit */
74 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
75 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
76 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
77 #define CICR1_RGB_F (1 << 11) /* RGB format */
78 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
79 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
80 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
81 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
82 #define CICR1_DW (0x7 << 0) /* Data width mask */
84 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
86 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
88 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
89 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
91 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
94 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
96 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
98 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
99 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
101 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
103 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
104 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
105 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
106 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
107 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
108 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
109 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
110 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
112 #define CISR_FTO (1 << 15) /* FIFO time-out */
113 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
114 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
115 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
116 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
117 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
118 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
119 #define CISR_EOL (1 << 8) /* End of line */
120 #define CISR_PAR_ERR (1 << 7) /* Parity error */
121 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
122 #define CISR_CDD (1 << 5) /* Camera interface disable done */
123 #define CISR_SOF (1 << 4) /* Start of frame */
124 #define CISR_EOF (1 << 3) /* End of frame */
125 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
126 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
127 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
129 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
130 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
131 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
132 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
133 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
134 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
135 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
136 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
138 #define CICR0_SIM_MP (0 << 24)
139 #define CICR0_SIM_SP (1 << 24)
140 #define CICR0_SIM_MS (2 << 24)
141 #define CICR0_SIM_EP (3 << 24)
142 #define CICR0_SIM_ES (4 << 24)
144 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
145 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
146 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
147 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
148 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
150 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
151 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
152 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
153 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
154 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
156 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
157 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
158 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
159 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
161 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
162 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
163 CICR0_EOFM | CICR0_FOM)
168 enum pxa_camera_active_dma {
174 /* descriptor needed for the PXA DMA engine */
177 struct pxa_dma_desc *sg_cpu;
182 /* buffer for one video frame */
184 /* common v4l buffer stuff -- must be first */
185 struct videobuf_buffer vb;
187 const struct soc_camera_data_format *fmt;
189 /* our descriptor lists for Y, U and V channels */
190 struct pxa_cam_dma dmas[3];
194 enum pxa_camera_active_dma active_dma;
197 struct pxa_camera_dev {
198 struct soc_camera_host soc_host;
199 /* PXA27x is only supposed to handle one camera on its Quick Capture
200 * interface. If anyone ever builds hardware to enable more than
201 * one camera, they will have to modify this driver too */
202 struct soc_camera_device *icd;
209 unsigned int dma_chans[3];
211 struct pxacamera_platform_data *pdata;
212 struct resource *res;
213 unsigned long platform_flags;
218 struct list_head capture;
222 struct pxa_buffer *active;
223 struct pxa_dma_desc *sg_tail[3];
228 static const char *pxa_cam_driver_description = "PXA_Camera";
230 static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
233 * Videobuf operations
235 static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
238 struct soc_camera_device *icd = vq->priv_data;
240 dev_dbg(icd->dev.parent, "count=%d, size=%d\n", *count, *size);
242 *size = roundup(icd->rect_current.width * icd->rect_current.height *
243 ((icd->current_fmt->depth + 7) >> 3), 8);
247 while (*size * *count > vid_limit * 1024 * 1024)
253 static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
255 struct soc_camera_device *icd = vq->priv_data;
256 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
257 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
260 BUG_ON(in_interrupt());
262 dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
263 &buf->vb, buf->vb.baddr, buf->vb.bsize);
265 /* This waits until this buffer is out of danger, i.e., until it is no
266 * longer in STATE_QUEUED or STATE_ACTIVE */
267 videobuf_waiton(&buf->vb, 0, 0);
268 videobuf_dma_unmap(vq, dma);
269 videobuf_dma_free(dma);
271 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
272 if (buf->dmas[i].sg_cpu)
273 dma_free_coherent(ici->v4l2_dev.dev, buf->dmas[i].sg_size,
275 buf->dmas[i].sg_dma);
276 buf->dmas[i].sg_cpu = NULL;
279 buf->vb.state = VIDEOBUF_NEEDS_INIT;
282 static int calculate_dma_sglen(struct scatterlist *sglist, int sglen,
283 int sg_first_ofs, int size)
285 int i, offset, dma_len, xfer_len;
286 struct scatterlist *sg;
288 offset = sg_first_ofs;
289 for_each_sg(sglist, sg, sglen, i) {
290 dma_len = sg_dma_len(sg);
292 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
293 xfer_len = roundup(min(dma_len - offset, size), 8);
295 size = max(0, size - xfer_len);
306 * pxa_init_dma_channel - init dma descriptors
307 * @pcdev: pxa camera device
308 * @buf: pxa buffer to find pxa dma channel
309 * @dma: dma video buffer
310 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
311 * @cibr: camera Receive Buffer Register
312 * @size: bytes to transfer
313 * @sg_first: first element of sg_list
314 * @sg_first_ofs: offset in first element of sg_list
316 * Prepares the pxa dma descriptors to transfer one camera channel.
317 * Beware sg_first and sg_first_ofs are both input and output parameters.
319 * Returns 0 or -ENOMEM if no coherent memory is available
321 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
322 struct pxa_buffer *buf,
323 struct videobuf_dmabuf *dma, int channel,
325 struct scatterlist **sg_first, int *sg_first_ofs)
327 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
328 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
329 struct scatterlist *sg;
330 int i, offset, sglen;
331 int dma_len = 0, xfer_len = 0;
334 dma_free_coherent(dev, pxa_dma->sg_size,
335 pxa_dma->sg_cpu, pxa_dma->sg_dma);
337 sglen = calculate_dma_sglen(*sg_first, dma->sglen,
338 *sg_first_ofs, size);
340 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
341 pxa_dma->sg_cpu = dma_alloc_coherent(dev, pxa_dma->sg_size,
342 &pxa_dma->sg_dma, GFP_KERNEL);
343 if (!pxa_dma->sg_cpu)
346 pxa_dma->sglen = sglen;
347 offset = *sg_first_ofs;
349 dev_dbg(dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
350 *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma);
353 for_each_sg(*sg_first, sg, sglen, i) {
354 dma_len = sg_dma_len(sg);
356 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
357 xfer_len = roundup(min(dma_len - offset, size), 8);
359 size = max(0, size - xfer_len);
361 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
362 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset;
363 pxa_dma->sg_cpu[i].dcmd =
364 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
367 pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN;
369 pxa_dma->sg_cpu[i].ddadr =
370 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
372 dev_vdbg(dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
373 pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc),
374 sg_dma_address(sg) + offset, xfer_len);
381 pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP;
382 pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN;
385 * Handle 1 special case :
386 * - in 3 planes (YUV422P format), we might finish with xfer_len equal
387 * to dma_len (end on PAGE boundary). In this case, the sg element
388 * for next plane should be the next after the last used to store the
389 * last scatter gather RAM page
391 if (xfer_len >= dma_len) {
392 *sg_first_ofs = xfer_len - dma_len;
393 *sg_first = sg_next(sg);
395 *sg_first_ofs = xfer_len;
402 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
403 struct pxa_buffer *buf)
405 buf->active_dma = DMA_Y;
406 if (pcdev->channels == 3)
407 buf->active_dma |= DMA_U | DMA_V;
411 * Please check the DMA prepared buffer structure in :
412 * Documentation/video4linux/pxa_camera.txt
413 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
414 * modification while DMA chain is running will work anyway.
416 static int pxa_videobuf_prepare(struct videobuf_queue *vq,
417 struct videobuf_buffer *vb, enum v4l2_field field)
419 struct soc_camera_device *icd = vq->priv_data;
420 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
421 struct pxa_camera_dev *pcdev = ici->priv;
422 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
423 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
425 int size_y, size_u = 0, size_v = 0;
427 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
428 vb, vb->baddr, vb->bsize);
430 /* Added list head initialization on alloc */
431 WARN_ON(!list_empty(&vb->queue));
434 /* This can be useful if you want to see if we actually fill
435 * the buffer with something */
436 memset((void *)vb->baddr, 0xaa, vb->bsize);
439 BUG_ON(NULL == icd->current_fmt);
441 /* I think, in buf_prepare you only have to protect global data,
442 * the actual buffer is yours */
445 if (buf->fmt != icd->current_fmt ||
446 vb->width != icd->rect_current.width ||
447 vb->height != icd->rect_current.height ||
448 vb->field != field) {
449 buf->fmt = icd->current_fmt;
450 vb->width = icd->rect_current.width;
451 vb->height = icd->rect_current.height;
453 vb->state = VIDEOBUF_NEEDS_INIT;
456 vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3);
457 if (0 != vb->baddr && vb->bsize < vb->size) {
462 if (vb->state == VIDEOBUF_NEEDS_INIT) {
465 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
466 struct scatterlist *sg;
468 ret = videobuf_iolock(vq, vb, NULL);
472 if (pcdev->channels == 3) {
474 size_u = size_v = size / 4;
481 /* init DMA for Y channel */
482 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y,
485 dev_err(dev, "DMA initialization for Y/RGB failed\n");
489 /* init DMA for U channel */
491 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1,
492 size_u, &sg, &next_ofs);
494 dev_err(dev, "DMA initialization for U failed\n");
498 /* init DMA for V channel */
500 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2,
501 size_v, &sg, &next_ofs);
503 dev_err(dev, "DMA initialization for V failed\n");
507 vb->state = VIDEOBUF_PREPARED;
511 pxa_videobuf_set_actdma(pcdev, buf);
516 dma_free_coherent(dev, buf->dmas[1].sg_size,
517 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
519 dma_free_coherent(dev, buf->dmas[0].sg_size,
520 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
522 free_buffer(vq, buf);
529 * pxa_dma_start_channels - start DMA channel for active buffer
530 * @pcdev: pxa camera device
532 * Initialize DMA channels to the beginning of the active video buffer, and
533 * start these channels.
535 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
538 struct pxa_buffer *active;
540 active = pcdev->active;
542 for (i = 0; i < pcdev->channels; i++) {
543 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
544 "%s (channel=%d) ddadr=%08x\n", __func__,
545 i, active->dmas[i].sg_dma);
546 DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma;
547 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
551 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
555 for (i = 0; i < pcdev->channels; i++) {
556 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
557 "%s (channel=%d)\n", __func__, i);
558 DCSR(pcdev->dma_chans[i]) = 0;
562 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
563 struct pxa_buffer *buf)
566 struct pxa_dma_desc *buf_last_desc;
568 for (i = 0; i < pcdev->channels; i++) {
569 buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen;
570 buf_last_desc->ddadr = DDADR_STOP;
572 if (pcdev->sg_tail[i])
573 /* Link the new buffer to the old tail */
574 pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma;
576 /* Update the channel tail */
577 pcdev->sg_tail[i] = buf_last_desc;
582 * pxa_camera_start_capture - start video capturing
583 * @pcdev: camera device
585 * Launch capturing. DMA channels should not be active yet. They should get
586 * activated at the end of frame interrupt, to capture only whole frames, and
587 * never begin the capture of a partial frame.
589 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
591 unsigned long cicr0, cifr;
593 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
594 /* Reset the FIFOs */
595 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
596 __raw_writel(cifr, pcdev->base + CIFR);
597 /* Enable End-Of-Frame Interrupt */
598 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
599 cicr0 &= ~CICR0_EOFM;
600 __raw_writel(cicr0, pcdev->base + CICR0);
603 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
607 pxa_dma_stop_channels(pcdev);
609 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
610 __raw_writel(cicr0, pcdev->base + CICR0);
612 pcdev->active = NULL;
613 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
616 /* Called under spinlock_irqsave(&pcdev->lock, ...) */
617 static void pxa_videobuf_queue(struct videobuf_queue *vq,
618 struct videobuf_buffer *vb)
620 struct soc_camera_device *icd = vq->priv_data;
621 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
622 struct pxa_camera_dev *pcdev = ici->priv;
623 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
625 dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d active=%p\n",
626 __func__, vb, vb->baddr, vb->bsize, pcdev->active);
628 list_add_tail(&vb->queue, &pcdev->capture);
630 vb->state = VIDEOBUF_ACTIVE;
631 pxa_dma_add_tail_buf(pcdev, buf);
634 pxa_camera_start_capture(pcdev);
637 static void pxa_videobuf_release(struct videobuf_queue *vq,
638 struct videobuf_buffer *vb)
640 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
642 struct soc_camera_device *icd = vq->priv_data;
643 struct device *dev = icd->dev.parent;
645 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
646 vb, vb->baddr, vb->bsize);
649 case VIDEOBUF_ACTIVE:
650 dev_dbg(dev, "%s (active)\n", __func__);
652 case VIDEOBUF_QUEUED:
653 dev_dbg(dev, "%s (queued)\n", __func__);
655 case VIDEOBUF_PREPARED:
656 dev_dbg(dev, "%s (prepared)\n", __func__);
659 dev_dbg(dev, "%s (unknown)\n", __func__);
664 free_buffer(vq, buf);
667 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
668 struct videobuf_buffer *vb,
669 struct pxa_buffer *buf)
673 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
674 list_del_init(&vb->queue);
675 vb->state = VIDEOBUF_DONE;
676 do_gettimeofday(&vb->ts);
679 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s dequeud buffer (vb=0x%p)\n",
682 if (list_empty(&pcdev->capture)) {
683 pxa_camera_stop_capture(pcdev);
684 for (i = 0; i < pcdev->channels; i++)
685 pcdev->sg_tail[i] = NULL;
689 pcdev->active = list_entry(pcdev->capture.next,
690 struct pxa_buffer, vb.queue);
694 * pxa_camera_check_link_miss - check missed DMA linking
695 * @pcdev: camera device
697 * The DMA chaining is done with DMA running. This means a tiny temporal window
698 * remains, where a buffer is queued on the chain, while the chain is already
699 * stopped. This means the tailed buffer would never be transfered by DMA.
700 * This function restarts the capture for this corner case, where :
701 * - DADR() == DADDR_STOP
702 * - a videobuffer is queued on the pcdev->capture list
704 * Please check the "DMA hot chaining timeslice issue" in
705 * Documentation/video4linux/pxa_camera.txt
707 * Context: should only be called within the dma irq handler
709 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev)
711 int i, is_dma_stopped = 1;
713 for (i = 0; i < pcdev->channels; i++)
714 if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP)
716 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
717 "%s : top queued buffer=%p, dma_stopped=%d\n",
718 __func__, pcdev->active, is_dma_stopped);
719 if (pcdev->active && is_dma_stopped)
720 pxa_camera_start_capture(pcdev);
723 static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
724 enum pxa_camera_active_dma act_dma)
726 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
727 struct pxa_buffer *buf;
729 u32 status, camera_status, overrun;
730 struct videobuf_buffer *vb;
732 spin_lock_irqsave(&pcdev->lock, flags);
734 status = DCSR(channel);
735 DCSR(channel) = status;
737 camera_status = __raw_readl(pcdev->base + CISR);
738 overrun = CISR_IFO_0;
739 if (pcdev->channels == 3)
740 overrun |= CISR_IFO_1 | CISR_IFO_2;
742 if (status & DCSR_BUSERR) {
743 dev_err(dev, "DMA Bus Error IRQ!\n");
747 if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) {
748 dev_err(dev, "Unknown DMA IRQ source, status: 0x%08x\n",
754 * pcdev->active should not be NULL in DMA irq handler.
756 * But there is one corner case : if capture was stopped due to an
757 * overrun of channel 1, and at that same channel 2 was completed.
759 * When handling the overrun in DMA irq for channel 1, we'll stop the
760 * capture and restart it (and thus set pcdev->active to NULL). But the
761 * DMA irq handler will already be pending for channel 2. So on entering
762 * the DMA irq handler for channel 2 there will be no active buffer, yet
768 vb = &pcdev->active->vb;
769 buf = container_of(vb, struct pxa_buffer, vb);
770 WARN_ON(buf->inwork || list_empty(&vb->queue));
772 dev_dbg(dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n",
773 __func__, channel, status & DCSR_STARTINTR ? "SOF " : "",
774 status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel));
776 if (status & DCSR_ENDINTR) {
778 * It's normal if the last frame creates an overrun, as there
779 * are no more DMA descriptors to fetch from QCI fifos
781 if (camera_status & overrun &&
782 !list_is_last(pcdev->capture.next, &pcdev->capture)) {
783 dev_dbg(dev, "FIFO overrun! CISR: %x\n",
785 pxa_camera_stop_capture(pcdev);
786 pxa_camera_start_capture(pcdev);
789 buf->active_dma &= ~act_dma;
790 if (!buf->active_dma) {
791 pxa_camera_wakeup(pcdev, vb, buf);
792 pxa_camera_check_link_miss(pcdev);
797 spin_unlock_irqrestore(&pcdev->lock, flags);
800 static void pxa_camera_dma_irq_y(int channel, void *data)
802 struct pxa_camera_dev *pcdev = data;
803 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
806 static void pxa_camera_dma_irq_u(int channel, void *data)
808 struct pxa_camera_dev *pcdev = data;
809 pxa_camera_dma_irq(channel, pcdev, DMA_U);
812 static void pxa_camera_dma_irq_v(int channel, void *data)
814 struct pxa_camera_dev *pcdev = data;
815 pxa_camera_dma_irq(channel, pcdev, DMA_V);
818 static struct videobuf_queue_ops pxa_videobuf_ops = {
819 .buf_setup = pxa_videobuf_setup,
820 .buf_prepare = pxa_videobuf_prepare,
821 .buf_queue = pxa_videobuf_queue,
822 .buf_release = pxa_videobuf_release,
825 static void pxa_camera_init_videobuf(struct videobuf_queue *q,
826 struct soc_camera_device *icd)
828 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
829 struct pxa_camera_dev *pcdev = ici->priv;
831 /* We must pass NULL as dev pointer, then all pci_* dma operations
832 * transform to normal dma_* ones. */
833 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
834 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
835 sizeof(struct pxa_buffer), icd);
838 static u32 mclk_get_divisor(struct platform_device *pdev,
839 struct pxa_camera_dev *pcdev)
841 unsigned long mclk = pcdev->mclk;
842 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
844 unsigned long lcdclk;
846 lcdclk = clk_get_rate(pcdev->clk);
847 pcdev->ciclk = lcdclk;
849 /* mclk <= ciclk / 4 (27.4.2) */
850 if (mclk > lcdclk / 4) {
852 dev_warn(dev, "Limiting master clock to %lu\n", mclk);
855 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
856 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
858 /* If we're not supplying MCLK, leave it at 0 */
859 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
860 pcdev->mclk = lcdclk / (2 * (div + 1));
862 dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
868 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
871 /* We want a timeout > 1 pixel time, not ">=" */
872 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
874 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
877 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
879 struct pxacamera_platform_data *pdata = pcdev->pdata;
880 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
883 dev_dbg(dev, "Registered platform device at %p data %p\n",
886 if (pdata && pdata->init) {
887 dev_dbg(dev, "%s: Init gpios\n", __func__);
891 /* disable all interrupts */
892 __raw_writel(0x3ff, pcdev->base + CICR0);
894 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
895 cicr4 |= CICR4_PCLK_EN;
896 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
897 cicr4 |= CICR4_MCLK_EN;
898 if (pcdev->platform_flags & PXA_CAMERA_PCP)
900 if (pcdev->platform_flags & PXA_CAMERA_HSP)
902 if (pcdev->platform_flags & PXA_CAMERA_VSP)
905 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
907 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
908 /* Initialise the timeout under the assumption pclk = mclk */
909 recalculate_fifo_timeout(pcdev, pcdev->mclk);
911 /* "Safe default" - 13MHz */
912 recalculate_fifo_timeout(pcdev, 13000000);
914 clk_enable(pcdev->clk);
917 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
919 clk_disable(pcdev->clk);
922 static irqreturn_t pxa_camera_irq(int irq, void *data)
924 struct pxa_camera_dev *pcdev = data;
925 unsigned long status, cicr0;
926 struct pxa_buffer *buf;
927 struct videobuf_buffer *vb;
929 status = __raw_readl(pcdev->base + CISR);
930 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
931 "Camera interrupt status 0x%lx\n", status);
936 __raw_writel(status, pcdev->base + CISR);
938 if (status & CISR_EOF) {
939 pcdev->active = list_first_entry(&pcdev->capture,
940 struct pxa_buffer, vb.queue);
941 vb = &pcdev->active->vb;
942 buf = container_of(vb, struct pxa_buffer, vb);
943 pxa_videobuf_set_actdma(pcdev, buf);
945 pxa_dma_start_channels(pcdev);
947 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
948 __raw_writel(cicr0, pcdev->base + CICR0);
955 * The following two functions absolutely depend on the fact, that
956 * there can be only one camera on PXA quick capture interface
957 * Called with .video_lock held
959 static int pxa_camera_add_device(struct soc_camera_device *icd)
961 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
962 struct pxa_camera_dev *pcdev = ici->priv;
967 pxa_camera_activate(pcdev);
971 dev_info(icd->dev.parent, "PXA Camera driver attached to camera %d\n",
977 /* Called with .video_lock held */
978 static void pxa_camera_remove_device(struct soc_camera_device *icd)
980 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
981 struct pxa_camera_dev *pcdev = ici->priv;
983 BUG_ON(icd != pcdev->icd);
985 dev_info(icd->dev.parent, "PXA Camera driver detached from camera %d\n",
988 /* disable capture, disable interrupts */
989 __raw_writel(0x3ff, pcdev->base + CICR0);
991 /* Stop DMA engine */
992 DCSR(pcdev->dma_chans[0]) = 0;
993 DCSR(pcdev->dma_chans[1]) = 0;
994 DCSR(pcdev->dma_chans[2]) = 0;
996 pxa_camera_deactivate(pcdev);
1001 static int test_platform_param(struct pxa_camera_dev *pcdev,
1002 unsigned char buswidth, unsigned long *flags)
1005 * Platform specified synchronization and pixel clock polarities are
1006 * only a recommendation and are only used during probing. The PXA270
1007 * quick capture interface supports both.
1009 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1010 SOCAM_MASTER : SOCAM_SLAVE) |
1011 SOCAM_HSYNC_ACTIVE_HIGH |
1012 SOCAM_HSYNC_ACTIVE_LOW |
1013 SOCAM_VSYNC_ACTIVE_HIGH |
1014 SOCAM_VSYNC_ACTIVE_LOW |
1015 SOCAM_DATA_ACTIVE_HIGH |
1016 SOCAM_PCLK_SAMPLE_RISING |
1017 SOCAM_PCLK_SAMPLE_FALLING;
1019 /* If requested data width is supported by the platform, use it */
1022 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
1024 *flags |= SOCAM_DATAWIDTH_10;
1027 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
1029 *flags |= SOCAM_DATAWIDTH_9;
1032 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
1034 *flags |= SOCAM_DATAWIDTH_8;
1043 static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
1045 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1046 struct pxa_camera_dev *pcdev = ici->priv;
1047 unsigned long dw, bpp, bus_flags, camera_flags, common_flags;
1048 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0;
1049 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
1054 camera_flags = icd->ops->query_bus_param(icd);
1056 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
1060 pcdev->channels = 1;
1062 /* Make choises, based on platform preferences */
1063 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
1064 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
1065 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1066 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
1068 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
1071 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
1072 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
1073 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1074 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
1076 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
1079 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
1080 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
1081 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1082 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
1084 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
1087 ret = icd->ops->set_bus_param(icd, common_flags);
1091 /* Datawidth is now guaranteed to be equal to one of the three values.
1092 * We fix bit-per-pixel equal to data-width... */
1093 switch (common_flags & SOCAM_DATAWIDTH_MASK) {
1094 case SOCAM_DATAWIDTH_10:
1098 case SOCAM_DATAWIDTH_9:
1103 /* Actually it can only be 8 now,
1104 * default is just to silence compiler warnings */
1105 case SOCAM_DATAWIDTH_8:
1110 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1111 cicr4 |= CICR4_PCLK_EN;
1112 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1113 cicr4 |= CICR4_MCLK_EN;
1114 if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
1116 if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
1118 if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
1121 cicr0 = __raw_readl(pcdev->base + CICR0);
1122 if (cicr0 & CICR0_ENB)
1123 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1125 cicr1 = CICR1_PPL_VAL(icd->rect_current.width - 1) | bpp | dw;
1128 case V4L2_PIX_FMT_YUV422P:
1129 pcdev->channels = 3;
1130 cicr1 |= CICR1_YCBCR_F;
1132 * Normally, pxa bus wants as input UYVY format. We allow all
1133 * reorderings of the YUV422 format, as no processing is done,
1134 * and the YUV stream is just passed through without any
1135 * transformation. Note that UYVY is the only format that
1136 * should be used if pxa framebuffer Overlay2 is used.
1138 case V4L2_PIX_FMT_UYVY:
1139 case V4L2_PIX_FMT_VYUY:
1140 case V4L2_PIX_FMT_YUYV:
1141 case V4L2_PIX_FMT_YVYU:
1142 cicr1 |= CICR1_COLOR_SP_VAL(2);
1144 case V4L2_PIX_FMT_RGB555:
1145 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1146 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1148 case V4L2_PIX_FMT_RGB565:
1149 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1154 cicr3 = CICR3_LPF_VAL(icd->rect_current.height - 1) |
1155 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
1156 cicr4 |= pcdev->mclk_divisor;
1158 __raw_writel(cicr1, pcdev->base + CICR1);
1159 __raw_writel(cicr2, pcdev->base + CICR2);
1160 __raw_writel(cicr3, pcdev->base + CICR3);
1161 __raw_writel(cicr4, pcdev->base + CICR4);
1163 /* CIF interrupts are not used, only DMA */
1164 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1165 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1166 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1167 __raw_writel(cicr0, pcdev->base + CICR0);
1172 static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1173 unsigned char buswidth)
1175 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1176 struct pxa_camera_dev *pcdev = ici->priv;
1177 unsigned long bus_flags, camera_flags;
1178 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1183 camera_flags = icd->ops->query_bus_param(icd);
1185 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
1188 static const struct soc_camera_data_format pxa_camera_formats[] = {
1190 .name = "Planar YUV422 16 bit",
1192 .fourcc = V4L2_PIX_FMT_YUV422P,
1193 .colorspace = V4L2_COLORSPACE_JPEG,
1197 static bool buswidth_supported(struct soc_camera_device *icd, int depth)
1199 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1200 struct pxa_camera_dev *pcdev = ici->priv;
1204 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8);
1206 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9);
1208 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10);
1213 static int required_buswidth(const struct soc_camera_data_format *fmt)
1215 switch (fmt->fourcc) {
1216 case V4L2_PIX_FMT_UYVY:
1217 case V4L2_PIX_FMT_VYUY:
1218 case V4L2_PIX_FMT_YUYV:
1219 case V4L2_PIX_FMT_YVYU:
1220 case V4L2_PIX_FMT_RGB565:
1221 case V4L2_PIX_FMT_RGB555:
1228 static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx,
1229 struct soc_camera_format_xlate *xlate)
1231 struct device *dev = icd->dev.parent;
1232 int formats = 0, buswidth, ret;
1234 buswidth = required_buswidth(icd->formats + idx);
1236 if (!buswidth_supported(icd, buswidth))
1239 ret = pxa_camera_try_bus_param(icd, buswidth);
1243 switch (icd->formats[idx].fourcc) {
1244 case V4L2_PIX_FMT_UYVY:
1247 xlate->host_fmt = &pxa_camera_formats[0];
1248 xlate->cam_fmt = icd->formats + idx;
1249 xlate->buswidth = buswidth;
1251 dev_dbg(dev, "Providing format %s using %s\n",
1252 pxa_camera_formats[0].name,
1253 icd->formats[idx].name);
1255 case V4L2_PIX_FMT_VYUY:
1256 case V4L2_PIX_FMT_YUYV:
1257 case V4L2_PIX_FMT_YVYU:
1258 case V4L2_PIX_FMT_RGB565:
1259 case V4L2_PIX_FMT_RGB555:
1262 xlate->host_fmt = icd->formats + idx;
1263 xlate->cam_fmt = icd->formats + idx;
1264 xlate->buswidth = buswidth;
1266 dev_dbg(dev, "Providing format %s packed\n",
1267 icd->formats[idx].name);
1271 /* Generic pass-through */
1274 xlate->host_fmt = icd->formats + idx;
1275 xlate->cam_fmt = icd->formats + idx;
1276 xlate->buswidth = icd->formats[idx].depth;
1279 "Providing format %s in pass-through mode\n",
1280 icd->formats[idx].name);
1287 static int pxa_camera_set_crop(struct soc_camera_device *icd,
1288 struct v4l2_crop *a)
1290 struct v4l2_rect *rect = &a->c;
1291 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1292 struct pxa_camera_dev *pcdev = ici->priv;
1293 struct device *dev = icd->dev.parent;
1294 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1295 struct soc_camera_sense sense = {
1296 .master_clock = pcdev->mclk,
1297 .pixel_clock_max = pcdev->ciclk / 4,
1301 /* If PCLK is used to latch data from the sensor, check sense */
1302 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1303 icd->sense = &sense;
1305 ret = v4l2_subdev_call(sd, video, s_crop, a);
1310 dev_warn(dev, "Failed to crop to %ux%u@%u:%u\n",
1311 rect->width, rect->height, rect->left, rect->top);
1312 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1313 if (sense.pixel_clock > sense.pixel_clock_max) {
1315 "pixel clock %lu set by the camera too high!",
1319 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1325 static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1326 struct v4l2_format *f)
1328 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1329 struct pxa_camera_dev *pcdev = ici->priv;
1330 struct device *dev = icd->dev.parent;
1331 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1332 const struct soc_camera_data_format *cam_fmt = NULL;
1333 const struct soc_camera_format_xlate *xlate = NULL;
1334 struct soc_camera_sense sense = {
1335 .master_clock = pcdev->mclk,
1336 .pixel_clock_max = pcdev->ciclk / 4,
1338 struct v4l2_pix_format *pix = &f->fmt.pix;
1339 struct v4l2_format cam_f = *f;
1342 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1344 dev_warn(dev, "Format %x not found\n", pix->pixelformat);
1348 cam_fmt = xlate->cam_fmt;
1350 /* If PCLK is used to latch data from the sensor, check sense */
1351 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1352 icd->sense = &sense;
1354 cam_f.fmt.pix.pixelformat = cam_fmt->fourcc;
1355 ret = v4l2_subdev_call(sd, video, s_fmt, f);
1360 dev_warn(dev, "Failed to configure for format %x\n",
1362 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1363 if (sense.pixel_clock > sense.pixel_clock_max) {
1365 "pixel clock %lu set by the camera too high!",
1369 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1373 icd->buswidth = xlate->buswidth;
1374 icd->current_fmt = xlate->host_fmt;
1380 static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1381 struct v4l2_format *f)
1383 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1384 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1385 const struct soc_camera_format_xlate *xlate;
1386 struct v4l2_pix_format *pix = &f->fmt.pix;
1387 __u32 pixfmt = pix->pixelformat;
1388 enum v4l2_field field;
1391 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1393 dev_warn(ici->v4l2_dev.dev, "Format %x not found\n", pixfmt);
1398 * Limit to pxa hardware capabilities. YUV422P planar format requires
1399 * images size to be a multiple of 16 bytes. If not, zeros will be
1400 * inserted between Y and U planes, and U and V planes, which violates
1401 * the YUV422P standard.
1403 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1404 &pix->height, 32, 2048, 0,
1405 xlate->host_fmt->fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1407 pix->bytesperline = pix->width *
1408 DIV_ROUND_UP(xlate->host_fmt->depth, 8);
1409 pix->sizeimage = pix->height * pix->bytesperline;
1411 /* camera has to see its format, but the user the original one */
1412 pix->pixelformat = xlate->cam_fmt->fourcc;
1413 /* limit to sensor capabilities */
1414 ret = v4l2_subdev_call(sd, video, try_fmt, f);
1415 pix->pixelformat = xlate->host_fmt->fourcc;
1419 if (field == V4L2_FIELD_ANY) {
1420 pix->field = V4L2_FIELD_NONE;
1421 } else if (field != V4L2_FIELD_NONE) {
1422 dev_err(icd->dev.parent, "Field type %d unsupported.\n", field);
1429 static int pxa_camera_reqbufs(struct soc_camera_file *icf,
1430 struct v4l2_requestbuffers *p)
1434 /* This is for locking debugging only. I removed spinlocks and now I
1435 * check whether .prepare is ever called on a linked buffer, or whether
1436 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1437 * it hadn't triggered */
1438 for (i = 0; i < p->count; i++) {
1439 struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
1440 struct pxa_buffer, vb);
1442 INIT_LIST_HEAD(&buf->vb.queue);
1448 static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
1450 struct soc_camera_file *icf = file->private_data;
1451 struct pxa_buffer *buf;
1453 buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
1456 poll_wait(file, &buf->vb.done, pt);
1458 if (buf->vb.state == VIDEOBUF_DONE ||
1459 buf->vb.state == VIDEOBUF_ERROR)
1460 return POLLIN|POLLRDNORM;
1465 static int pxa_camera_querycap(struct soc_camera_host *ici,
1466 struct v4l2_capability *cap)
1468 /* cap->name is set by the firendly caller:-> */
1469 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1470 cap->version = PXA_CAM_VERSION_CODE;
1471 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1476 static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state)
1478 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1479 struct pxa_camera_dev *pcdev = ici->priv;
1482 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1483 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1484 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1485 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1486 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
1488 if ((pcdev->icd) && (pcdev->icd->ops->suspend))
1489 ret = pcdev->icd->ops->suspend(pcdev->icd, state);
1494 static int pxa_camera_resume(struct soc_camera_device *icd)
1496 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1497 struct pxa_camera_dev *pcdev = ici->priv;
1500 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1501 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1502 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1504 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1505 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1506 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1507 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1508 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1510 if ((pcdev->icd) && (pcdev->icd->ops->resume))
1511 ret = pcdev->icd->ops->resume(pcdev->icd);
1513 /* Restart frame capture if active buffer exists */
1514 if (!ret && pcdev->active)
1515 pxa_camera_start_capture(pcdev);
1520 static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1521 .owner = THIS_MODULE,
1522 .add = pxa_camera_add_device,
1523 .remove = pxa_camera_remove_device,
1524 .suspend = pxa_camera_suspend,
1525 .resume = pxa_camera_resume,
1526 .set_crop = pxa_camera_set_crop,
1527 .get_formats = pxa_camera_get_formats,
1528 .set_fmt = pxa_camera_set_fmt,
1529 .try_fmt = pxa_camera_try_fmt,
1530 .init_videobuf = pxa_camera_init_videobuf,
1531 .reqbufs = pxa_camera_reqbufs,
1532 .poll = pxa_camera_poll,
1533 .querycap = pxa_camera_querycap,
1534 .set_bus_param = pxa_camera_set_bus_param,
1537 static int __devinit pxa_camera_probe(struct platform_device *pdev)
1539 struct pxa_camera_dev *pcdev;
1540 struct resource *res;
1545 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1546 irq = platform_get_irq(pdev, 0);
1547 if (!res || irq < 0) {
1552 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1554 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1559 pcdev->clk = clk_get(&pdev->dev, NULL);
1560 if (IS_ERR(pcdev->clk)) {
1561 err = PTR_ERR(pcdev->clk);
1567 pcdev->pdata = pdev->dev.platform_data;
1568 pcdev->platform_flags = pcdev->pdata->flags;
1569 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1570 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1571 /* Platform hasn't set available data widths. This is bad.
1572 * Warn and use a default. */
1573 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1574 "data widths, using default 10 bit\n");
1575 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1577 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1579 dev_warn(&pdev->dev,
1580 "mclk == 0! Please, fix your platform data. "
1581 "Using default 20MHz\n");
1582 pcdev->mclk = 20000000;
1585 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
1587 INIT_LIST_HEAD(&pcdev->capture);
1588 spin_lock_init(&pcdev->lock);
1591 * Request the regions.
1593 if (!request_mem_region(res->start, resource_size(res),
1594 PXA_CAM_DRV_NAME)) {
1599 base = ioremap(res->start, resource_size(res));
1608 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1609 pxa_camera_dma_irq_y, pcdev);
1611 dev_err(&pdev->dev, "Can't request DMA for Y\n");
1614 pcdev->dma_chans[0] = err;
1615 dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1617 err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1618 pxa_camera_dma_irq_u, pcdev);
1620 dev_err(&pdev->dev, "Can't request DMA for U\n");
1621 goto exit_free_dma_y;
1623 pcdev->dma_chans[1] = err;
1624 dev_dbg(&pdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1626 err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1627 pxa_camera_dma_irq_v, pcdev);
1629 dev_err(&pdev->dev, "Can't request DMA for V\n");
1630 goto exit_free_dma_u;
1632 pcdev->dma_chans[2] = err;
1633 dev_dbg(&pdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1635 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1636 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1637 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1640 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1643 dev_err(&pdev->dev, "Camera interrupt register failed \n");
1647 pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME;
1648 pcdev->soc_host.ops = &pxa_soc_camera_host_ops;
1649 pcdev->soc_host.priv = pcdev;
1650 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1651 pcdev->soc_host.nr = pdev->id;
1653 err = soc_camera_host_register(&pcdev->soc_host);
1660 free_irq(pcdev->irq, pcdev);
1662 pxa_free_dma(pcdev->dma_chans[2]);
1664 pxa_free_dma(pcdev->dma_chans[1]);
1666 pxa_free_dma(pcdev->dma_chans[0]);
1670 release_mem_region(res->start, resource_size(res));
1672 clk_put(pcdev->clk);
1679 static int __devexit pxa_camera_remove(struct platform_device *pdev)
1681 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1682 struct pxa_camera_dev *pcdev = container_of(soc_host,
1683 struct pxa_camera_dev, soc_host);
1684 struct resource *res;
1686 clk_put(pcdev->clk);
1688 pxa_free_dma(pcdev->dma_chans[0]);
1689 pxa_free_dma(pcdev->dma_chans[1]);
1690 pxa_free_dma(pcdev->dma_chans[2]);
1691 free_irq(pcdev->irq, pcdev);
1693 soc_camera_host_unregister(soc_host);
1695 iounmap(pcdev->base);
1698 release_mem_region(res->start, resource_size(res));
1702 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1707 static struct platform_driver pxa_camera_driver = {
1709 .name = PXA_CAM_DRV_NAME,
1711 .probe = pxa_camera_probe,
1712 .remove = __devexit_p(pxa_camera_remove),
1716 static int __init pxa_camera_init(void)
1718 return platform_driver_register(&pxa_camera_driver);
1721 static void __exit pxa_camera_exit(void)
1723 platform_driver_unregister(&pxa_camera_driver);
1726 module_init(pxa_camera_init);
1727 module_exit(pxa_camera_exit);
1729 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1730 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1731 MODULE_LICENSE("GPL");
1732 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);