SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *  $Id$
   4  *
   5  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  *
  20  */
  21
  22 #include <linux/errno.h>
  23 #include <linux/string.h>
  24 #include <linux/slab.h>
  25 #include <linux/firmware.h>
  26 #include <linux/videodev2.h>
  27 #include <media/v4l2-common.h>
  28 #include "pvrusb2.h"
  29 #include "pvrusb2-std.h"
  30 #include "pvrusb2-util.h"
  31 #include "pvrusb2-hdw.h"
  32 #include "pvrusb2-i2c-core.h"
  33 #include "pvrusb2-tuner.h"
  34 #include "pvrusb2-eeprom.h"
  35 #include "pvrusb2-hdw-internal.h"
  36 #include "pvrusb2-encoder.h"
  37 #include "pvrusb2-debug.h"
  38 #include "pvrusb2-fx2-cmd.h"
  39
  40 #define TV_MIN_FREQ     55250000L
  41 #define TV_MAX_FREQ    850000000L
  42
  43 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  44 static DEFINE_MUTEX(pvr2_unit_mtx);
  45
  46 static int ctlchg;
  47 static int initusbreset = 1;
  48 static int procreload;
  49 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  50 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  51 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  52 static int init_pause_msec;
  53
  54 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  55 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  56 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  57 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  58 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
  59 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
  60 module_param(procreload, int, S_IRUGO|S_IWUSR);
  61 MODULE_PARM_DESC(procreload,
  62                  "Attempt init failure recovery with firmware reload");
  63 module_param_array(tuner,    int, NULL, 0444);
  64 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  65 module_param_array(video_std,    int, NULL, 0444);
  66 MODULE_PARM_DESC(video_std,"specify initial video standard");
  67 module_param_array(tolerance,    int, NULL, 0444);
  68 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  69
  70 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  71 #define PVR2_CTL_READ_ENDPOINT   0x81
  72
  73 #define PVR2_GPIO_IN 0x9008
  74 #define PVR2_GPIO_OUT 0x900c
  75 #define PVR2_GPIO_DIR 0x9020
  76
  77 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
  78
  79 #define PVR2_FIRMWARE_ENDPOINT   0x02
  80
  81 /* size of a firmware chunk */
  82 #define FIRMWARE_CHUNK_SIZE 0x2000
  83
  84 /* Define the list of additional controls we'll dynamically construct based
  85    on query of the cx2341x module. */
  86 struct pvr2_mpeg_ids {
  87         const char *strid;
  88         int id;
  89 };
  90 static const struct pvr2_mpeg_ids mpeg_ids[] = {
  91         {
  92                 .strid = "audio_layer",
  93                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
  94         },{
  95                 .strid = "audio_bitrate",
  96                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
  97         },{
  98                 /* Already using audio_mode elsewhere :-( */
  99                 .strid = "mpeg_audio_mode",
 100                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 101         },{
 102                 .strid = "mpeg_audio_mode_extension",
 103                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 104         },{
 105                 .strid = "audio_emphasis",
 106                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 107         },{
 108                 .strid = "audio_crc",
 109                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 110         },{
 111                 .strid = "video_aspect",
 112                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 113         },{
 114                 .strid = "video_b_frames",
 115                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 116         },{
 117                 .strid = "video_gop_size",
 118                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 119         },{
 120                 .strid = "video_gop_closure",
 121                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 122         },{
 123                 .strid = "video_bitrate_mode",
 124                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 125         },{
 126                 .strid = "video_bitrate",
 127                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 128         },{
 129                 .strid = "video_bitrate_peak",
 130                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 131         },{
 132                 .strid = "video_temporal_decimation",
 133                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 134         },{
 135                 .strid = "stream_type",
 136                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 137         },{
 138                 .strid = "video_spatial_filter_mode",
 139                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 140         },{
 141                 .strid = "video_spatial_filter",
 142                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 143         },{
 144                 .strid = "video_luma_spatial_filter_type",
 145                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 146         },{
 147                 .strid = "video_chroma_spatial_filter_type",
 148                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 149         },{
 150                 .strid = "video_temporal_filter_mode",
 151                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 152         },{
 153                 .strid = "video_temporal_filter",
 154                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 155         },{
 156                 .strid = "video_median_filter_type",
 157                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 158         },{
 159                 .strid = "video_luma_median_filter_top",
 160                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 161         },{
 162                 .strid = "video_luma_median_filter_bottom",
 163                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 164         },{
 165                 .strid = "video_chroma_median_filter_top",
 166                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 167         },{
 168                 .strid = "video_chroma_median_filter_bottom",
 169                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 170         }
 171 };
 172 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 173
 174
 175 static const char *control_values_srate[] = {
 176         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 177         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 178         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 179 };
 180
 181
 182
 183 static const char *control_values_input[] = {
 184         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 185         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 186         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 187         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 188         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 189 };
 190
 191
 192 static const char *control_values_audiomode[] = {
 193         [V4L2_TUNER_MODE_MONO]   = "Mono",
 194         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 195         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 196         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 197         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 198 };
 199
 200
 201 static const char *control_values_hsm[] = {
 202         [PVR2_CVAL_HSM_FAIL] = "Fail",
 203         [PVR2_CVAL_HSM_HIGH] = "High",
 204         [PVR2_CVAL_HSM_FULL] = "Full",
 205 };
 206
 207
 208 static const char *pvr2_state_names[] = {
 209         [PVR2_STATE_NONE] =    "none",
 210         [PVR2_STATE_DEAD] =    "dead",
 211         [PVR2_STATE_COLD] =    "cold",
 212         [PVR2_STATE_WARM] =    "warm",
 213         [PVR2_STATE_ERROR] =   "error",
 214         [PVR2_STATE_READY] =   "ready",
 215         [PVR2_STATE_RUN] =     "run",
 216 };
 217
 218
 219 struct pvr2_fx2cmd_descdef {
 220         unsigned char id;
 221         unsigned char *desc;
 222 };
 223
 224 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 225         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 226         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 227         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 228         {FX2CMD_REG_WRITE, "write encoder register"},
 229         {FX2CMD_REG_READ, "read encoder register"},
 230         {FX2CMD_MEMSEL, "encoder memsel"},
 231         {FX2CMD_I2C_WRITE, "i2c write"},
 232         {FX2CMD_I2C_READ, "i2c read"},
 233         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 234         {FX2CMD_STREAMING_ON, "stream on"},
 235         {FX2CMD_STREAMING_OFF, "stream off"},
 236         {FX2CMD_FWPOST1, "fwpost1"},
 237         {FX2CMD_POWER_OFF, "power off"},
 238         {FX2CMD_POWER_ON, "power on"},
 239         {FX2CMD_DEEP_RESET, "deep reset"},
 240         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 241         {FX2CMD_GET_IR_CODE, "get IR code"},
 242         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 243         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 244         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 245         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 246         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 247         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 248         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 249 };
 250
 251
 252 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 253 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 254 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 255 static void pvr2_hdw_worker_i2c(struct work_struct *work);
 256 static void pvr2_hdw_worker_poll(struct work_struct *work);
 257 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 258 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 259 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 260 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 261 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 262 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 263 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 264 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 265 static void pvr2_hdw_quiescent_timeout(unsigned long);
 266 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 267 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 268 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 269 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 270                                 unsigned int timeout,int probe_fl,
 271                                 void *write_data,unsigned int write_len,
 272                                 void *read_data,unsigned int read_len);
 273
 274
 275 static void trace_stbit(const char *name,int val)
 276 {
 277         pvr2_trace(PVR2_TRACE_STBITS,
 278                    "State bit %s <-- %s",
 279                    name,(val ? "true" : "false"));
 280 }
 281
 282 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 283 {
 284         struct pvr2_hdw *hdw = cptr->hdw;
 285         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 286                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 287         } else {
 288                 *vp = 0;
 289         }
 290         return 0;
 291 }
 292
 293 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 294 {
 295         struct pvr2_hdw *hdw = cptr->hdw;
 296         unsigned int slotId = hdw->freqProgSlot;
 297         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 298                 hdw->freqTable[slotId-1] = v;
 299                 /* Handle side effects correctly - if we're tuned to this
 300                    slot, then forgot the slot id relation since the stored
 301                    frequency has been changed. */
 302                 if (hdw->freqSelector) {
 303                         if (hdw->freqSlotRadio == slotId) {
 304                                 hdw->freqSlotRadio = 0;
 305                         }
 306                 } else {
 307                         if (hdw->freqSlotTelevision == slotId) {
 308                                 hdw->freqSlotTelevision = 0;
 309                         }
 310                 }
 311         }
 312         return 0;
 313 }
 314
 315 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 316 {
 317         *vp = cptr->hdw->freqProgSlot;
 318         return 0;
 319 }
 320
 321 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 322 {
 323         struct pvr2_hdw *hdw = cptr->hdw;
 324         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 325                 hdw->freqProgSlot = v;
 326         }
 327         return 0;
 328 }
 329
 330 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 331 {
 332         struct pvr2_hdw *hdw = cptr->hdw;
 333         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 334         return 0;
 335 }
 336
 337 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 338 {
 339         unsigned freq = 0;
 340         struct pvr2_hdw *hdw = cptr->hdw;
 341         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 342         if (slotId > 0) {
 343                 freq = hdw->freqTable[slotId-1];
 344                 if (!freq) return 0;
 345                 pvr2_hdw_set_cur_freq(hdw,freq);
 346         }
 347         if (hdw->freqSelector) {
 348                 hdw->freqSlotRadio = slotId;
 349         } else {
 350                 hdw->freqSlotTelevision = slotId;
 351         }
 352         return 0;
 353 }
 354
 355 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 356 {
 357         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 358         return 0;
 359 }
 360
 361 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 362 {
 363         return cptr->hdw->freqDirty != 0;
 364 }
 365
 366 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 367 {
 368         cptr->hdw->freqDirty = 0;
 369 }
 370
 371 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 372 {
 373         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 374         return 0;
 375 }
 376
 377 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 378 {
 379         /* Actual maximum depends on the video standard in effect. */
 380         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 381                 *vp = 480;
 382         } else {
 383                 *vp = 576;
 384         }
 385         return 0;
 386 }
 387
 388 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 389 {
 390         /* Actual minimum depends on device digitizer type. */
 391         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 392                 *vp = 75;
 393         } else {
 394                 *vp = 17;
 395         }
 396         return 0;
 397 }
 398
 399 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 400 {
 401         *vp = cptr->hdw->input_val;
 402         return 0;
 403 }
 404
 405 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 406 {
 407         return ((1 << v) & cptr->hdw->input_avail_mask) != 0;
 408 }
 409
 410 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 411 {
 412         struct pvr2_hdw *hdw = cptr->hdw;
 413
 414         if (hdw->input_val != v) {
 415                 hdw->input_val = v;
 416                 hdw->input_dirty = !0;
 417         }
 418
 419         /* Handle side effects - if we switch to a mode that needs the RF
 420            tuner, then select the right frequency choice as well and mark
 421            it dirty. */
 422         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
 423                 hdw->freqSelector = 0;
 424                 hdw->freqDirty = !0;
 425         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
 426                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
 427                 hdw->freqSelector = 1;
 428                 hdw->freqDirty = !0;
 429         }
 430         return 0;
 431 }
 432
 433 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 434 {
 435         return cptr->hdw->input_dirty != 0;
 436 }
 437
 438 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 439 {
 440         cptr->hdw->input_dirty = 0;
 441 }
 442
 443
 444 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 445 {
 446         unsigned long fv;
 447         struct pvr2_hdw *hdw = cptr->hdw;
 448         if (hdw->tuner_signal_stale) {
 449                 pvr2_i2c_core_status_poll(hdw);
 450         }
 451         fv = hdw->tuner_signal_info.rangehigh;
 452         if (!fv) {
 453                 /* Safety fallback */
 454                 *vp = TV_MAX_FREQ;
 455                 return 0;
 456         }
 457         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 458                 fv = (fv * 125) / 2;
 459         } else {
 460                 fv = fv * 62500;
 461         }
 462         *vp = fv;
 463         return 0;
 464 }
 465
 466 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 467 {
 468         unsigned long fv;
 469         struct pvr2_hdw *hdw = cptr->hdw;
 470         if (hdw->tuner_signal_stale) {
 471                 pvr2_i2c_core_status_poll(hdw);
 472         }
 473         fv = hdw->tuner_signal_info.rangelow;
 474         if (!fv) {
 475                 /* Safety fallback */
 476                 *vp = TV_MIN_FREQ;
 477                 return 0;
 478         }
 479         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 480                 fv = (fv * 125) / 2;
 481         } else {
 482                 fv = fv * 62500;
 483         }
 484         *vp = fv;
 485         return 0;
 486 }
 487
 488 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 489 {
 490         return cptr->hdw->enc_stale != 0;
 491 }
 492
 493 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 494 {
 495         cptr->hdw->enc_stale = 0;
 496         cptr->hdw->enc_unsafe_stale = 0;
 497 }
 498
 499 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 500 {
 501         int ret;
 502         struct v4l2_ext_controls cs;
 503         struct v4l2_ext_control c1;
 504         memset(&cs,0,sizeof(cs));
 505         memset(&c1,0,sizeof(c1));
 506         cs.controls = &c1;
 507         cs.count = 1;
 508         c1.id = cptr->info->v4l_id;
 509         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 510                                 VIDIOC_G_EXT_CTRLS);
 511         if (ret) return ret;
 512         *vp = c1.value;
 513         return 0;
 514 }
 515
 516 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 517 {
 518         int ret;
 519         struct pvr2_hdw *hdw = cptr->hdw;
 520         struct v4l2_ext_controls cs;
 521         struct v4l2_ext_control c1;
 522         memset(&cs,0,sizeof(cs));
 523         memset(&c1,0,sizeof(c1));
 524         cs.controls = &c1;
 525         cs.count = 1;
 526         c1.id = cptr->info->v4l_id;
 527         c1.value = v;
 528         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 529                                 hdw->state_encoder_run, &cs,
 530                                 VIDIOC_S_EXT_CTRLS);
 531         if (ret == -EBUSY) {
 532                 /* Oops.  cx2341x is telling us it's not safe to change
 533                    this control while we're capturing.  Make a note of this
 534                    fact so that the pipeline will be stopped the next time
 535                    controls are committed.  Then go on ahead and store this
 536                    change anyway. */
 537                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 538                                         0, &cs,
 539                                         VIDIOC_S_EXT_CTRLS);
 540                 if (!ret) hdw->enc_unsafe_stale = !0;
 541         }
 542         if (ret) return ret;
 543         hdw->enc_stale = !0;
 544         return 0;
 545 }
 546
 547 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 548 {
 549         struct v4l2_queryctrl qctrl;
 550         struct pvr2_ctl_info *info;
 551         qctrl.id = cptr->info->v4l_id;
 552         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 553         /* Strip out the const so we can adjust a function pointer.  It's
 554            OK to do this here because we know this is a dynamically created
 555            control, so the underlying storage for the info pointer is (a)
 556            private to us, and (b) not in read-only storage.  Either we do
 557            this or we significantly complicate the underlying control
 558            implementation. */
 559         info = (struct pvr2_ctl_info *)(cptr->info);
 560         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 561                 if (info->set_value) {
 562                         info->set_value = NULL;
 563                 }
 564         } else {
 565                 if (!(info->set_value)) {
 566                         info->set_value = ctrl_cx2341x_set;
 567                 }
 568         }
 569         return qctrl.flags;
 570 }
 571
 572 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 573 {
 574         *vp = cptr->hdw->state_pipeline_req;
 575         return 0;
 576 }
 577
 578 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 579 {
 580         *vp = cptr->hdw->master_state;
 581         return 0;
 582 }
 583
 584 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 585 {
 586         int result = pvr2_hdw_is_hsm(cptr->hdw);
 587         *vp = PVR2_CVAL_HSM_FULL;
 588         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 589         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 590         return 0;
 591 }
 592
 593 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 594 {
 595         *vp = cptr->hdw->std_mask_avail;
 596         return 0;
 597 }
 598
 599 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 600 {
 601         struct pvr2_hdw *hdw = cptr->hdw;
 602         v4l2_std_id ns;
 603         ns = hdw->std_mask_avail;
 604         ns = (ns & ~m) | (v & m);
 605         if (ns == hdw->std_mask_avail) return 0;
 606         hdw->std_mask_avail = ns;
 607         pvr2_hdw_internal_set_std_avail(hdw);
 608         pvr2_hdw_internal_find_stdenum(hdw);
 609         return 0;
 610 }
 611
 612 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 613                                char *bufPtr,unsigned int bufSize,
 614                                unsigned int *len)
 615 {
 616         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 617         return 0;
 618 }
 619
 620 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 621                                const char *bufPtr,unsigned int bufSize,
 622                                int *mskp,int *valp)
 623 {
 624         int ret;
 625         v4l2_std_id id;
 626         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 627         if (ret < 0) return ret;
 628         if (mskp) *mskp = id;
 629         if (valp) *valp = id;
 630         return 0;
 631 }
 632
 633 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 634 {
 635         *vp = cptr->hdw->std_mask_cur;
 636         return 0;
 637 }
 638
 639 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 640 {
 641         struct pvr2_hdw *hdw = cptr->hdw;
 642         v4l2_std_id ns;
 643         ns = hdw->std_mask_cur;
 644         ns = (ns & ~m) | (v & m);
 645         if (ns == hdw->std_mask_cur) return 0;
 646         hdw->std_mask_cur = ns;
 647         hdw->std_dirty = !0;
 648         pvr2_hdw_internal_find_stdenum(hdw);
 649         return 0;
 650 }
 651
 652 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 653 {
 654         return cptr->hdw->std_dirty != 0;
 655 }
 656
 657 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 658 {
 659         cptr->hdw->std_dirty = 0;
 660 }
 661
 662 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 663 {
 664         struct pvr2_hdw *hdw = cptr->hdw;
 665         pvr2_i2c_core_status_poll(hdw);
 666         *vp = hdw->tuner_signal_info.signal;
 667         return 0;
 668 }
 669
 670 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 671 {
 672         int val = 0;
 673         unsigned int subchan;
 674         struct pvr2_hdw *hdw = cptr->hdw;
 675         pvr2_i2c_core_status_poll(hdw);
 676         subchan = hdw->tuner_signal_info.rxsubchans;
 677         if (subchan & V4L2_TUNER_SUB_MONO) {
 678                 val |= (1 << V4L2_TUNER_MODE_MONO);
 679         }
 680         if (subchan & V4L2_TUNER_SUB_STEREO) {
 681                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 682         }
 683         if (subchan & V4L2_TUNER_SUB_LANG1) {
 684                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 685         }
 686         if (subchan & V4L2_TUNER_SUB_LANG2) {
 687                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 688         }
 689         *vp = val;
 690         return 0;
 691 }
 692
 693
 694 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 695 {
 696         struct pvr2_hdw *hdw = cptr->hdw;
 697         if (v < 0) return -EINVAL;
 698         if (v > hdw->std_enum_cnt) return -EINVAL;
 699         hdw->std_enum_cur = v;
 700         if (!v) return 0;
 701         v--;
 702         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 703         hdw->std_mask_cur = hdw->std_defs[v].id;
 704         hdw->std_dirty = !0;
 705         return 0;
 706 }
 707
 708
 709 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 710 {
 711         *vp = cptr->hdw->std_enum_cur;
 712         return 0;
 713 }
 714
 715
 716 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 717 {
 718         return cptr->hdw->std_dirty != 0;
 719 }
 720
 721
 722 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 723 {
 724         cptr->hdw->std_dirty = 0;
 725 }
 726
 727
 728 #define DEFINT(vmin,vmax) \
 729         .type = pvr2_ctl_int, \
 730         .def.type_int.min_value = vmin, \
 731         .def.type_int.max_value = vmax
 732
 733 #define DEFENUM(tab) \
 734         .type = pvr2_ctl_enum, \
 735         .def.type_enum.count = ARRAY_SIZE(tab), \
 736         .def.type_enum.value_names = tab
 737
 738 #define DEFBOOL \
 739         .type = pvr2_ctl_bool
 740
 741 #define DEFMASK(msk,tab) \
 742         .type = pvr2_ctl_bitmask, \
 743         .def.type_bitmask.valid_bits = msk, \
 744         .def.type_bitmask.bit_names = tab
 745
 746 #define DEFREF(vname) \
 747         .set_value = ctrl_set_##vname, \
 748         .get_value = ctrl_get_##vname, \
 749         .is_dirty = ctrl_isdirty_##vname, \
 750         .clear_dirty = ctrl_cleardirty_##vname
 751
 752
 753 #define VCREATE_FUNCS(vname) \
 754 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 755 {*vp = cptr->hdw->vname##_val; return 0;} \
 756 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 757 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 758 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 759 {return cptr->hdw->vname##_dirty != 0;} \
 760 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 761 {cptr->hdw->vname##_dirty = 0;}
 762
 763 VCREATE_FUNCS(brightness)
 764 VCREATE_FUNCS(contrast)
 765 VCREATE_FUNCS(saturation)
 766 VCREATE_FUNCS(hue)
 767 VCREATE_FUNCS(volume)
 768 VCREATE_FUNCS(balance)
 769 VCREATE_FUNCS(bass)
 770 VCREATE_FUNCS(treble)
 771 VCREATE_FUNCS(mute)
 772 VCREATE_FUNCS(audiomode)
 773 VCREATE_FUNCS(res_hor)
 774 VCREATE_FUNCS(res_ver)
 775 VCREATE_FUNCS(srate)
 776
 777 /* Table definition of all controls which can be manipulated */
 778 static const struct pvr2_ctl_info control_defs[] = {
 779         {
 780                 .v4l_id = V4L2_CID_BRIGHTNESS,
 781                 .desc = "Brightness",
 782                 .name = "brightness",
 783                 .default_value = 128,
 784                 DEFREF(brightness),
 785                 DEFINT(0,255),
 786         },{
 787                 .v4l_id = V4L2_CID_CONTRAST,
 788                 .desc = "Contrast",
 789                 .name = "contrast",
 790                 .default_value = 68,
 791                 DEFREF(contrast),
 792                 DEFINT(0,127),
 793         },{
 794                 .v4l_id = V4L2_CID_SATURATION,
 795                 .desc = "Saturation",
 796                 .name = "saturation",
 797                 .default_value = 64,
 798                 DEFREF(saturation),
 799                 DEFINT(0,127),
 800         },{
 801                 .v4l_id = V4L2_CID_HUE,
 802                 .desc = "Hue",
 803                 .name = "hue",
 804                 .default_value = 0,
 805                 DEFREF(hue),
 806                 DEFINT(-128,127),
 807         },{
 808                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
 809                 .desc = "Volume",
 810                 .name = "volume",
 811                 .default_value = 62000,
 812                 DEFREF(volume),
 813                 DEFINT(0,65535),
 814         },{
 815                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
 816                 .desc = "Balance",
 817                 .name = "balance",
 818                 .default_value = 0,
 819                 DEFREF(balance),
 820                 DEFINT(-32768,32767),
 821         },{
 822                 .v4l_id = V4L2_CID_AUDIO_BASS,
 823                 .desc = "Bass",
 824                 .name = "bass",
 825                 .default_value = 0,
 826                 DEFREF(bass),
 827                 DEFINT(-32768,32767),
 828         },{
 829                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
 830                 .desc = "Treble",
 831                 .name = "treble",
 832                 .default_value = 0,
 833                 DEFREF(treble),
 834                 DEFINT(-32768,32767),
 835         },{
 836                 .v4l_id = V4L2_CID_AUDIO_MUTE,
 837                 .desc = "Mute",
 838                 .name = "mute",
 839                 .default_value = 0,
 840                 DEFREF(mute),
 841                 DEFBOOL,
 842         },{
 843                 .desc = "Video Source",
 844                 .name = "input",
 845                 .internal_id = PVR2_CID_INPUT,
 846                 .default_value = PVR2_CVAL_INPUT_TV,
 847                 .check_value = ctrl_check_input,
 848                 DEFREF(input),
 849                 DEFENUM(control_values_input),
 850         },{
 851                 .desc = "Audio Mode",
 852                 .name = "audio_mode",
 853                 .internal_id = PVR2_CID_AUDIOMODE,
 854                 .default_value = V4L2_TUNER_MODE_STEREO,
 855                 DEFREF(audiomode),
 856                 DEFENUM(control_values_audiomode),
 857         },{
 858                 .desc = "Horizontal capture resolution",
 859                 .name = "resolution_hor",
 860                 .internal_id = PVR2_CID_HRES,
 861                 .default_value = 720,
 862                 DEFREF(res_hor),
 863                 DEFINT(19,720),
 864         },{
 865                 .desc = "Vertical capture resolution",
 866                 .name = "resolution_ver",
 867                 .internal_id = PVR2_CID_VRES,
 868                 .default_value = 480,
 869                 DEFREF(res_ver),
 870                 DEFINT(17,576),
 871                 /* Hook in check for video standard and adjust maximum
 872                    depending on the standard. */
 873                 .get_max_value = ctrl_vres_max_get,
 874                 .get_min_value = ctrl_vres_min_get,
 875         },{
 876                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
 877                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
 878                 .desc = "Audio Sampling Frequency",
 879                 .name = "srate",
 880                 DEFREF(srate),
 881                 DEFENUM(control_values_srate),
 882         },{
 883                 .desc = "Tuner Frequency (Hz)",
 884                 .name = "frequency",
 885                 .internal_id = PVR2_CID_FREQUENCY,
 886                 .default_value = 0,
 887                 .set_value = ctrl_freq_set,
 888                 .get_value = ctrl_freq_get,
 889                 .is_dirty = ctrl_freq_is_dirty,
 890                 .clear_dirty = ctrl_freq_clear_dirty,
 891                 DEFINT(0,0),
 892                 /* Hook in check for input value (tv/radio) and adjust
 893                    max/min values accordingly */
 894                 .get_max_value = ctrl_freq_max_get,
 895                 .get_min_value = ctrl_freq_min_get,
 896         },{
 897                 .desc = "Channel",
 898                 .name = "channel",
 899                 .set_value = ctrl_channel_set,
 900                 .get_value = ctrl_channel_get,
 901                 DEFINT(0,FREQTABLE_SIZE),
 902         },{
 903                 .desc = "Channel Program Frequency",
 904                 .name = "freq_table_value",
 905                 .set_value = ctrl_channelfreq_set,
 906                 .get_value = ctrl_channelfreq_get,
 907                 DEFINT(0,0),
 908                 /* Hook in check for input value (tv/radio) and adjust
 909                    max/min values accordingly */
 910                 .get_max_value = ctrl_freq_max_get,
 911                 .get_min_value = ctrl_freq_min_get,
 912         },{
 913                 .desc = "Channel Program ID",
 914                 .name = "freq_table_channel",
 915                 .set_value = ctrl_channelprog_set,
 916                 .get_value = ctrl_channelprog_get,
 917                 DEFINT(0,FREQTABLE_SIZE),
 918         },{
 919                 .desc = "Streaming Enabled",
 920                 .name = "streaming_enabled",
 921                 .get_value = ctrl_streamingenabled_get,
 922                 DEFBOOL,
 923         },{
 924                 .desc = "USB Speed",
 925                 .name = "usb_speed",
 926                 .get_value = ctrl_hsm_get,
 927                 DEFENUM(control_values_hsm),
 928         },{
 929                 .desc = "Master State",
 930                 .name = "master_state",
 931                 .get_value = ctrl_masterstate_get,
 932                 DEFENUM(pvr2_state_names),
 933         },{
 934                 .desc = "Signal Present",
 935                 .name = "signal_present",
 936                 .get_value = ctrl_signal_get,
 937                 DEFINT(0,65535),
 938         },{
 939                 .desc = "Audio Modes Present",
 940                 .name = "audio_modes_present",
 941                 .get_value = ctrl_audio_modes_present_get,
 942                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
 943                    v4l.  Nothing outside of this module cares about this,
 944                    but I reuse it in order to also reuse the
 945                    control_values_audiomode string table. */
 946                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
 947                          (1 << V4L2_TUNER_MODE_STEREO)|
 948                          (1 << V4L2_TUNER_MODE_LANG1)|
 949                          (1 << V4L2_TUNER_MODE_LANG2)),
 950                         control_values_audiomode),
 951         },{
 952                 .desc = "Video Standards Available Mask",
 953                 .name = "video_standard_mask_available",
 954                 .internal_id = PVR2_CID_STDAVAIL,
 955                 .skip_init = !0,
 956                 .get_value = ctrl_stdavail_get,
 957                 .set_value = ctrl_stdavail_set,
 958                 .val_to_sym = ctrl_std_val_to_sym,
 959                 .sym_to_val = ctrl_std_sym_to_val,
 960                 .type = pvr2_ctl_bitmask,
 961         },{
 962                 .desc = "Video Standards In Use Mask",
 963                 .name = "video_standard_mask_active",
 964                 .internal_id = PVR2_CID_STDCUR,
 965                 .skip_init = !0,
 966                 .get_value = ctrl_stdcur_get,
 967                 .set_value = ctrl_stdcur_set,
 968                 .is_dirty = ctrl_stdcur_is_dirty,
 969                 .clear_dirty = ctrl_stdcur_clear_dirty,
 970                 .val_to_sym = ctrl_std_val_to_sym,
 971                 .sym_to_val = ctrl_std_sym_to_val,
 972                 .type = pvr2_ctl_bitmask,
 973         },{
 974                 .desc = "Video Standard Name",
 975                 .name = "video_standard",
 976                 .internal_id = PVR2_CID_STDENUM,
 977                 .skip_init = !0,
 978                 .get_value = ctrl_stdenumcur_get,
 979                 .set_value = ctrl_stdenumcur_set,
 980                 .is_dirty = ctrl_stdenumcur_is_dirty,
 981                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
 982                 .type = pvr2_ctl_enum,
 983         }
 984 };
 985
 986 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
 987
 988
 989 const char *pvr2_config_get_name(enum pvr2_config cfg)
 990 {
 991         switch (cfg) {
 992         case pvr2_config_empty: return "empty";
 993         case pvr2_config_mpeg: return "mpeg";
 994         case pvr2_config_vbi: return "vbi";
 995         case pvr2_config_pcm: return "pcm";
 996         case pvr2_config_rawvideo: return "raw video";
 997         }
 998         return "<unknown>";
 999 }
1000
1001
1002 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1003 {
1004         return hdw->usb_dev;
1005 }
1006
1007
1008 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1009 {
1010         return hdw->serial_number;
1011 }
1012
1013
1014 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1015 {
1016         return hdw->bus_info;
1017 }
1018
1019
1020 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1021 {
1022         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1023 }
1024
1025 /* Set the currently tuned frequency and account for all possible
1026    driver-core side effects of this action. */
1027 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1028 {
1029         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1030                 if (hdw->freqSelector) {
1031                         /* Swing over to radio frequency selection */
1032                         hdw->freqSelector = 0;
1033                         hdw->freqDirty = !0;
1034                 }
1035                 if (hdw->freqValRadio != val) {
1036                         hdw->freqValRadio = val;
1037                         hdw->freqSlotRadio = 0;
1038                         hdw->freqDirty = !0;
1039                 }
1040         } else {
1041                 if (!(hdw->freqSelector)) {
1042                         /* Swing over to television frequency selection */
1043                         hdw->freqSelector = 1;
1044                         hdw->freqDirty = !0;
1045                 }
1046                 if (hdw->freqValTelevision != val) {
1047                         hdw->freqValTelevision = val;
1048                         hdw->freqSlotTelevision = 0;
1049                         hdw->freqDirty = !0;
1050                 }
1051         }
1052 }
1053
1054 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1055 {
1056         return hdw->unit_number;
1057 }
1058
1059
1060 /* Attempt to locate one of the given set of files.  Messages are logged
1061    appropriate to what has been found.  The return value will be 0 or
1062    greater on success (it will be the index of the file name found) and
1063    fw_entry will be filled in.  Otherwise a negative error is returned on
1064    failure.  If the return value is -ENOENT then no viable firmware file
1065    could be located. */
1066 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1067                                 const struct firmware **fw_entry,
1068                                 const char *fwtypename,
1069                                 unsigned int fwcount,
1070                                 const char *fwnames[])
1071 {
1072         unsigned int idx;
1073         int ret = -EINVAL;
1074         for (idx = 0; idx < fwcount; idx++) {
1075                 ret = request_firmware(fw_entry,
1076                                        fwnames[idx],
1077                                        &hdw->usb_dev->dev);
1078                 if (!ret) {
1079                         trace_firmware("Located %s firmware: %s;"
1080                                        " uploading...",
1081                                        fwtypename,
1082                                        fwnames[idx]);
1083                         return idx;
1084                 }
1085                 if (ret == -ENOENT) continue;
1086                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1087                            "request_firmware fatal error with code=%d",ret);
1088                 return ret;
1089         }
1090         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1091                    "***WARNING***"
1092                    " Device %s firmware"
1093                    " seems to be missing.",
1094                    fwtypename);
1095         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1096                    "Did you install the pvrusb2 firmware files"
1097                    " in their proper location?");
1098         if (fwcount == 1) {
1099                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1100                            "request_firmware unable to locate %s file %s",
1101                            fwtypename,fwnames[0]);
1102         } else {
1103                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1104                            "request_firmware unable to locate"
1105                            " one of the following %s files:",
1106                            fwtypename);
1107                 for (idx = 0; idx < fwcount; idx++) {
1108                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1109                                    "request_firmware: Failed to find %s",
1110                                    fwnames[idx]);
1111                 }
1112         }
1113         return ret;
1114 }
1115
1116
1117 /*
1118  * pvr2_upload_firmware1().
1119  *
1120  * Send the 8051 firmware to the device.  After the upload, arrange for
1121  * device to re-enumerate.
1122  *
1123  * NOTE : the pointer to the firmware data given by request_firmware()
1124  * is not suitable for an usb transaction.
1125  *
1126  */
1127 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1128 {
1129         const struct firmware *fw_entry = NULL;
1130         void  *fw_ptr;
1131         unsigned int pipe;
1132         int ret;
1133         u16 address;
1134
1135         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1136                 hdw->fw1_state = FW1_STATE_OK;
1137                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1138                            "Connected device type defines"
1139                            " no firmware to upload; ignoring firmware");
1140                 return -ENOTTY;
1141         }
1142
1143         hdw->fw1_state = FW1_STATE_FAILED; // default result
1144
1145         trace_firmware("pvr2_upload_firmware1");
1146
1147         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1148                                    hdw->hdw_desc->fx2_firmware.cnt,
1149                                    hdw->hdw_desc->fx2_firmware.lst);
1150         if (ret < 0) {
1151                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1152                 return ret;
1153         }
1154
1155         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1156         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1157
1158         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1159
1160         if (fw_entry->size != 0x2000){
1161                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1162                 release_firmware(fw_entry);
1163                 return -ENOMEM;
1164         }
1165
1166         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1167         if (fw_ptr == NULL){
1168                 release_firmware(fw_entry);
1169                 return -ENOMEM;
1170         }
1171
1172         /* We have to hold the CPU during firmware upload. */
1173         pvr2_hdw_cpureset_assert(hdw,1);
1174
1175         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1176            chunk. */
1177
1178         ret = 0;
1179         for(address = 0; address < fw_entry->size; address += 0x800) {
1180                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1181                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1182                                        0, fw_ptr, 0x800, HZ);
1183         }
1184
1185         trace_firmware("Upload done, releasing device's CPU");
1186
1187         /* Now release the CPU.  It will disconnect and reconnect later. */
1188         pvr2_hdw_cpureset_assert(hdw,0);
1189
1190         kfree(fw_ptr);
1191         release_firmware(fw_entry);
1192
1193         trace_firmware("Upload done (%d bytes sent)",ret);
1194
1195         /* We should have written 8192 bytes */
1196         if (ret == 8192) {
1197                 hdw->fw1_state = FW1_STATE_RELOAD;
1198                 return 0;
1199         }
1200
1201         return -EIO;
1202 }
1203
1204
1205 /*
1206  * pvr2_upload_firmware2()
1207  *
1208  * This uploads encoder firmware on endpoint 2.
1209  *
1210  */
1211
1212 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1213 {
1214         const struct firmware *fw_entry = NULL;
1215         void  *fw_ptr;
1216         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1217         int actual_length;
1218         int ret = 0;
1219         int fwidx;
1220         static const char *fw_files[] = {
1221                 CX2341X_FIRM_ENC_FILENAME,
1222         };
1223
1224         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1225                 return 0;
1226         }
1227
1228         trace_firmware("pvr2_upload_firmware2");
1229
1230         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1231                                    ARRAY_SIZE(fw_files), fw_files);
1232         if (ret < 0) return ret;
1233         fwidx = ret;
1234         ret = 0;
1235         /* Since we're about to completely reinitialize the encoder,
1236            invalidate our cached copy of its configuration state.  Next
1237            time we configure the encoder, then we'll fully configure it. */
1238         hdw->enc_cur_valid = 0;
1239
1240         /* Encoder is about to be reset so note that as far as we're
1241            concerned now, the encoder has never been run. */
1242         del_timer_sync(&hdw->encoder_run_timer);
1243         if (hdw->state_encoder_runok) {
1244                 hdw->state_encoder_runok = 0;
1245                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1246         }
1247
1248         /* First prepare firmware loading */
1249         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1250         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1251         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1252         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1253         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1254         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1255         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1256         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1257         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1258         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1259         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1260         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1261         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1262         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1263         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1264         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1265         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1266         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1267
1268         if (ret) {
1269                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1270                            "firmware2 upload prep failed, ret=%d",ret);
1271                 release_firmware(fw_entry);
1272                 return ret;
1273         }
1274
1275         /* Now send firmware */
1276
1277         fw_len = fw_entry->size;
1278
1279         if (fw_len % sizeof(u32)) {
1280                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1281                            "size of %s firmware"
1282                            " must be a multiple of %zu bytes",
1283                            fw_files[fwidx],sizeof(u32));
1284                 release_firmware(fw_entry);
1285                 return -1;
1286         }
1287
1288         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1289         if (fw_ptr == NULL){
1290                 release_firmware(fw_entry);
1291                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1292                            "failed to allocate memory for firmware2 upload");
1293                 return -ENOMEM;
1294         }
1295
1296         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1297
1298         fw_done = 0;
1299         for (fw_done = 0; fw_done < fw_len;) {
1300                 bcnt = fw_len - fw_done;
1301                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1302                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1303                 /* Usbsnoop log shows that we must swap bytes... */
1304                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1305                         ((u32 *)fw_ptr)[icnt] =
1306                                 ___swab32(((u32 *)fw_ptr)[icnt]);
1307
1308                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1309                                     &actual_length, HZ);
1310                 ret |= (actual_length != bcnt);
1311                 if (ret) break;
1312                 fw_done += bcnt;
1313         }
1314
1315         trace_firmware("upload of %s : %i / %i ",
1316                        fw_files[fwidx],fw_done,fw_len);
1317
1318         kfree(fw_ptr);
1319         release_firmware(fw_entry);
1320
1321         if (ret) {
1322                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1323                            "firmware2 upload transfer failure");
1324                 return ret;
1325         }
1326
1327         /* Finish upload */
1328
1329         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1330         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1331         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1332
1333         if (ret) {
1334                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1335                            "firmware2 upload post-proc failure");
1336         }
1337         return ret;
1338 }
1339
1340
1341 static const char *pvr2_get_state_name(unsigned int st)
1342 {
1343         if (st < ARRAY_SIZE(pvr2_state_names)) {
1344                 return pvr2_state_names[st];
1345         }
1346         return "???";
1347 }
1348
1349 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1350 {
1351         if (!hdw->decoder_ctrl) {
1352                 if (!hdw->flag_decoder_missed) {
1353                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1354                                    "WARNING: No decoder present");
1355                         hdw->flag_decoder_missed = !0;
1356                         trace_stbit("flag_decoder_missed",
1357                                     hdw->flag_decoder_missed);
1358                 }
1359                 return -EIO;
1360         }
1361         hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1362         return 0;
1363 }
1364
1365
1366 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1367 {
1368         if (hdw->decoder_ctrl == ptr) return;
1369         hdw->decoder_ctrl = ptr;
1370         if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1371                 hdw->flag_decoder_missed = 0;
1372                 trace_stbit("flag_decoder_missed",
1373                             hdw->flag_decoder_missed);
1374                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1375                            "Decoder has appeared");
1376                 pvr2_hdw_state_sched(hdw);
1377         }
1378 }
1379
1380
1381 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1382 {
1383         return hdw->master_state;
1384 }
1385
1386
1387 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1388 {
1389         if (!hdw->flag_tripped) return 0;
1390         hdw->flag_tripped = 0;
1391         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1392                    "Clearing driver error statuss");
1393         return !0;
1394 }
1395
1396
1397 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1398 {
1399         int fl;
1400         LOCK_TAKE(hdw->big_lock); do {
1401                 fl = pvr2_hdw_untrip_unlocked(hdw);
1402         } while (0); LOCK_GIVE(hdw->big_lock);
1403         if (fl) pvr2_hdw_state_sched(hdw);
1404         return 0;
1405 }
1406
1407
1408
1409
1410 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1411 {
1412         return hdw->state_pipeline_req != 0;
1413 }
1414
1415
1416 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1417 {
1418         int ret,st;
1419         LOCK_TAKE(hdw->big_lock); do {
1420                 pvr2_hdw_untrip_unlocked(hdw);
1421                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1422                         hdw->state_pipeline_req = enable_flag != 0;
1423                         pvr2_trace(PVR2_TRACE_START_STOP,
1424                                    "/*--TRACE_STREAM--*/ %s",
1425                                    enable_flag ? "enable" : "disable");
1426                 }
1427                 pvr2_hdw_state_sched(hdw);
1428         } while (0); LOCK_GIVE(hdw->big_lock);
1429         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1430         if (enable_flag) {
1431                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1432                         if (st != PVR2_STATE_READY) return -EIO;
1433                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1434                 }
1435         }
1436         return 0;
1437 }
1438
1439
1440 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1441 {
1442         int fl;
1443         LOCK_TAKE(hdw->big_lock);
1444         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1445                 hdw->desired_stream_type = config;
1446                 hdw->state_pipeline_config = 0;
1447                 trace_stbit("state_pipeline_config",
1448                             hdw->state_pipeline_config);
1449                 pvr2_hdw_state_sched(hdw);
1450         }
1451         LOCK_GIVE(hdw->big_lock);
1452         if (fl) return 0;
1453         return pvr2_hdw_wait(hdw,0);
1454 }
1455
1456
1457 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1458 {
1459         int unit_number = hdw->unit_number;
1460         int tp = -1;
1461         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1462                 tp = tuner[unit_number];
1463         }
1464         if (tp < 0) return -EINVAL;
1465         hdw->tuner_type = tp;
1466         hdw->tuner_updated = !0;
1467         return 0;
1468 }
1469
1470
1471 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1472 {
1473         int unit_number = hdw->unit_number;
1474         int tp = 0;
1475         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1476                 tp = video_std[unit_number];
1477                 if (tp) return tp;
1478         }
1479         return 0;
1480 }
1481
1482
1483 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1484 {
1485         int unit_number = hdw->unit_number;
1486         int tp = 0;
1487         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1488                 tp = tolerance[unit_number];
1489         }
1490         return tp;
1491 }
1492
1493
1494 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1495 {
1496         /* Try a harmless request to fetch the eeprom's address over
1497            endpoint 1.  See what happens.  Only the full FX2 image can
1498            respond to this.  If this probe fails then likely the FX2
1499            firmware needs be loaded. */
1500         int result;
1501         LOCK_TAKE(hdw->ctl_lock); do {
1502                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1503                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1504                                            hdw->cmd_buffer,1,
1505                                            hdw->cmd_buffer,1);
1506                 if (result < 0) break;
1507         } while(0); LOCK_GIVE(hdw->ctl_lock);
1508         if (result) {
1509                 pvr2_trace(PVR2_TRACE_INIT,
1510                            "Probe of device endpoint 1 result status %d",
1511                            result);
1512         } else {
1513                 pvr2_trace(PVR2_TRACE_INIT,
1514                            "Probe of device endpoint 1 succeeded");
1515         }
1516         return result == 0;
1517 }
1518
1519 struct pvr2_std_hack {
1520         v4l2_std_id pat;  /* Pattern to match */
1521         v4l2_std_id msk;  /* Which bits we care about */
1522         v4l2_std_id std;  /* What additional standards or default to set */
1523 };
1524
1525 /* This data structure labels specific combinations of standards from
1526    tveeprom that we'll try to recognize.  If we recognize one, then assume
1527    a specified default standard to use.  This is here because tveeprom only
1528    tells us about available standards not the intended default standard (if
1529    any) for the device in question.  We guess the default based on what has
1530    been reported as available.  Note that this is only for guessing a
1531    default - which can always be overridden explicitly - and if the user
1532    has otherwise named a default then that default will always be used in
1533    place of this table. */
1534 static const struct pvr2_std_hack std_eeprom_maps[] = {
1535         {       /* PAL(B/G) */
1536                 .pat = V4L2_STD_B|V4L2_STD_GH,
1537                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1538         },
1539         {       /* NTSC(M) */
1540                 .pat = V4L2_STD_MN,
1541                 .std = V4L2_STD_NTSC_M,
1542         },
1543         {       /* PAL(I) */
1544                 .pat = V4L2_STD_PAL_I,
1545                 .std = V4L2_STD_PAL_I,
1546         },
1547         {       /* SECAM(L/L') */
1548                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1549                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1550         },
1551         {       /* PAL(D/D1/K) */
1552                 .pat = V4L2_STD_DK,
1553                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1554         },
1555 };
1556
1557 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1558 {
1559         char buf[40];
1560         unsigned int bcnt;
1561         v4l2_std_id std1,std2,std3;
1562
1563         std1 = get_default_standard(hdw);
1564         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1565
1566         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1567         pvr2_trace(PVR2_TRACE_STD,
1568                    "Supported video standard(s) reported available"
1569                    " in hardware: %.*s",
1570                    bcnt,buf);
1571
1572         hdw->std_mask_avail = hdw->std_mask_eeprom;
1573
1574         std2 = (std1|std3) & ~hdw->std_mask_avail;
1575         if (std2) {
1576                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1577                 pvr2_trace(PVR2_TRACE_STD,
1578                            "Expanding supported video standards"
1579                            " to include: %.*s",
1580                            bcnt,buf);
1581                 hdw->std_mask_avail |= std2;
1582         }
1583
1584         pvr2_hdw_internal_set_std_avail(hdw);
1585
1586         if (std1) {
1587                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1588                 pvr2_trace(PVR2_TRACE_STD,
1589                            "Initial video standard forced to %.*s",
1590                            bcnt,buf);
1591                 hdw->std_mask_cur = std1;
1592                 hdw->std_dirty = !0;
1593                 pvr2_hdw_internal_find_stdenum(hdw);
1594                 return;
1595         }
1596         if (std3) {
1597                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1598                 pvr2_trace(PVR2_TRACE_STD,
1599                            "Initial video standard"
1600                            " (determined by device type): %.*s",bcnt,buf);
1601                 hdw->std_mask_cur = std3;
1602                 hdw->std_dirty = !0;
1603                 pvr2_hdw_internal_find_stdenum(hdw);
1604                 return;
1605         }
1606
1607         {
1608                 unsigned int idx;
1609                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1610                         if (std_eeprom_maps[idx].msk ?
1611                             ((std_eeprom_maps[idx].pat ^
1612                              hdw->std_mask_eeprom) &
1613                              std_eeprom_maps[idx].msk) :
1614                             (std_eeprom_maps[idx].pat !=
1615                              hdw->std_mask_eeprom)) continue;
1616                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1617                                                   std_eeprom_maps[idx].std);
1618                         pvr2_trace(PVR2_TRACE_STD,
1619                                    "Initial video standard guessed as %.*s",
1620                                    bcnt,buf);
1621                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1622                         hdw->std_dirty = !0;
1623                         pvr2_hdw_internal_find_stdenum(hdw);
1624                         return;
1625                 }
1626         }
1627
1628         if (hdw->std_enum_cnt > 1) {
1629                 // Autoselect the first listed standard
1630                 hdw->std_enum_cur = 1;
1631                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1632                 hdw->std_dirty = !0;
1633                 pvr2_trace(PVR2_TRACE_STD,
1634                            "Initial video standard auto-selected to %s",
1635                            hdw->std_defs[hdw->std_enum_cur-1].name);
1636                 return;
1637         }
1638
1639         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1640                    "Unable to select a viable initial video standard");
1641 }
1642
1643
1644 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1645 {
1646         int ret;
1647         unsigned int idx;
1648         struct pvr2_ctrl *cptr;
1649         int reloadFl = 0;
1650         if (hdw->hdw_desc->fx2_firmware.cnt) {
1651                 if (!reloadFl) {
1652                         reloadFl =
1653                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1654                                  == 0);
1655                         if (reloadFl) {
1656                                 pvr2_trace(PVR2_TRACE_INIT,
1657                                            "USB endpoint config looks strange"
1658                                            "; possibly firmware needs to be"
1659                                            " loaded");
1660                         }
1661                 }
1662                 if (!reloadFl) {
1663                         reloadFl = !pvr2_hdw_check_firmware(hdw);
1664                         if (reloadFl) {
1665                                 pvr2_trace(PVR2_TRACE_INIT,
1666                                            "Check for FX2 firmware failed"
1667                                            "; possibly firmware needs to be"
1668                                            " loaded");
1669                         }
1670                 }
1671                 if (reloadFl) {
1672                         if (pvr2_upload_firmware1(hdw) != 0) {
1673                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1674                                            "Failure uploading firmware1");
1675                         }
1676                         return;
1677                 }
1678         }
1679         hdw->fw1_state = FW1_STATE_OK;
1680
1681         if (initusbreset) {
1682                 pvr2_hdw_device_reset(hdw);
1683         }
1684         if (!pvr2_hdw_dev_ok(hdw)) return;
1685
1686         for (idx = 0; idx < hdw->hdw_desc->client_modules.cnt; idx++) {
1687                 request_module(hdw->hdw_desc->client_modules.lst[idx]);
1688         }
1689
1690         if (!hdw->hdw_desc->flag_no_powerup) {
1691                 pvr2_hdw_cmd_powerup(hdw);
1692                 if (!pvr2_hdw_dev_ok(hdw)) return;
1693         }
1694
1695         // This step MUST happen after the earlier powerup step.
1696         pvr2_i2c_core_init(hdw);
1697         if (!pvr2_hdw_dev_ok(hdw)) return;
1698
1699         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1700                 cptr = hdw->controls + idx;
1701                 if (cptr->info->skip_init) continue;
1702                 if (!cptr->info->set_value) continue;
1703                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1704         }
1705
1706         /* Set up special default values for the television and radio
1707            frequencies here.  It's not really important what these defaults
1708            are, but I set them to something usable in the Chicago area just
1709            to make driver testing a little easier. */
1710
1711         /* US Broadcast channel 7 (175.25 MHz) */
1712         hdw->freqValTelevision = 175250000L;
1713         /* 104.3 MHz, a usable FM station for my area */
1714         hdw->freqValRadio = 104300000L;
1715
1716         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
1717         // thread-safe against the normal pvr2_send_request() mechanism.
1718         // (We should make it thread safe).
1719
1720         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
1721                 ret = pvr2_hdw_get_eeprom_addr(hdw);
1722                 if (!pvr2_hdw_dev_ok(hdw)) return;
1723                 if (ret < 0) {
1724                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1725                                    "Unable to determine location of eeprom,"
1726                                    " skipping");
1727                 } else {
1728                         hdw->eeprom_addr = ret;
1729                         pvr2_eeprom_analyze(hdw);
1730                         if (!pvr2_hdw_dev_ok(hdw)) return;
1731                 }
1732         } else {
1733                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
1734                 hdw->tuner_updated = !0;
1735                 hdw->std_mask_eeprom = V4L2_STD_ALL;
1736         }
1737
1738         pvr2_hdw_setup_std(hdw);
1739
1740         if (!get_default_tuner_type(hdw)) {
1741                 pvr2_trace(PVR2_TRACE_INIT,
1742                            "pvr2_hdw_setup: Tuner type overridden to %d",
1743                            hdw->tuner_type);
1744         }
1745
1746         pvr2_i2c_core_check_stale(hdw);
1747         hdw->tuner_updated = 0;
1748
1749         if (!pvr2_hdw_dev_ok(hdw)) return;
1750
1751         pvr2_hdw_commit_setup(hdw);
1752
1753         hdw->vid_stream = pvr2_stream_create();
1754         if (!pvr2_hdw_dev_ok(hdw)) return;
1755         pvr2_trace(PVR2_TRACE_INIT,
1756                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1757         if (hdw->vid_stream) {
1758                 idx = get_default_error_tolerance(hdw);
1759                 if (idx) {
1760                         pvr2_trace(PVR2_TRACE_INIT,
1761                                    "pvr2_hdw_setup: video stream %p"
1762                                    " setting tolerance %u",
1763                                    hdw->vid_stream,idx);
1764                 }
1765                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1766                                   PVR2_VID_ENDPOINT,idx);
1767         }
1768
1769         if (!pvr2_hdw_dev_ok(hdw)) return;
1770
1771         hdw->flag_init_ok = !0;
1772
1773         pvr2_hdw_state_sched(hdw);
1774 }
1775
1776
1777 /* Set up the structure and attempt to put the device into a usable state.
1778    This can be a time-consuming operation, which is why it is not done
1779    internally as part of the create() step. */
1780 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
1781 {
1782         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1783         do {
1784                 pvr2_hdw_setup_low(hdw);
1785                 pvr2_trace(PVR2_TRACE_INIT,
1786                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1787                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
1788                 if (pvr2_hdw_dev_ok(hdw)) {
1789                         if (hdw->flag_init_ok) {
1790                                 pvr2_trace(
1791                                         PVR2_TRACE_INFO,
1792                                         "Device initialization"
1793                                         " completed successfully.");
1794                                 break;
1795                         }
1796                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
1797                                 pvr2_trace(
1798                                         PVR2_TRACE_INFO,
1799                                         "Device microcontroller firmware"
1800                                         " (re)loaded; it should now reset"
1801                                         " and reconnect.");
1802                                 break;
1803                         }
1804                         pvr2_trace(
1805                                 PVR2_TRACE_ERROR_LEGS,
1806                                 "Device initialization was not successful.");
1807                         if (hdw->fw1_state == FW1_STATE_MISSING) {
1808                                 pvr2_trace(
1809                                         PVR2_TRACE_ERROR_LEGS,
1810                                         "Giving up since device"
1811                                         " microcontroller firmware"
1812                                         " appears to be missing.");
1813                                 break;
1814                         }
1815                 }
1816                 if (procreload) {
1817                         pvr2_trace(
1818                                 PVR2_TRACE_ERROR_LEGS,
1819                                 "Attempting pvrusb2 recovery by reloading"
1820                                 " primary firmware.");
1821                         pvr2_trace(
1822                                 PVR2_TRACE_ERROR_LEGS,
1823                                 "If this works, device should disconnect"
1824                                 " and reconnect in a sane state.");
1825                         hdw->fw1_state = FW1_STATE_UNKNOWN;
1826                         pvr2_upload_firmware1(hdw);
1827                 } else {
1828                         pvr2_trace(
1829                                 PVR2_TRACE_ERROR_LEGS,
1830                                 "***WARNING*** pvrusb2 device hardware"
1831                                 " appears to be jammed"
1832                                 " and I can't clear it.");
1833                         pvr2_trace(
1834                                 PVR2_TRACE_ERROR_LEGS,
1835                                 "You might need to power cycle"
1836                                 " the pvrusb2 device"
1837                                 " in order to recover.");
1838                 }
1839         } while (0);
1840         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1841 }
1842
1843
1844 /* Perform second stage initialization.  Set callback pointer first so that
1845    we can avoid a possible initialization race (if the kernel thread runs
1846    before the callback has been set). */
1847 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
1848                         void (*callback_func)(void *),
1849                         void *callback_data)
1850 {
1851         LOCK_TAKE(hdw->big_lock); do {
1852                 if (hdw->flag_disconnected) {
1853                         /* Handle a race here: If we're already
1854                            disconnected by this point, then give up.  If we
1855                            get past this then we'll remain connected for
1856                            the duration of initialization since the entire
1857                            initialization sequence is now protected by the
1858                            big_lock. */
1859                         break;
1860                 }
1861                 hdw->state_data = callback_data;
1862                 hdw->state_func = callback_func;
1863                 pvr2_hdw_setup(hdw);
1864         } while (0); LOCK_GIVE(hdw->big_lock);
1865         return hdw->flag_init_ok;
1866 }
1867
1868
1869 /* Create, set up, and return a structure for interacting with the
1870    underlying hardware.  */
1871 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1872                                  const struct usb_device_id *devid)
1873 {
1874         unsigned int idx,cnt1,cnt2,m;
1875         struct pvr2_hdw *hdw;
1876         int valid_std_mask;
1877         struct pvr2_ctrl *cptr;
1878         const struct pvr2_device_desc *hdw_desc;
1879         __u8 ifnum;
1880         struct v4l2_queryctrl qctrl;
1881         struct pvr2_ctl_info *ciptr;
1882
1883         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
1884
1885         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
1886         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1887                    hdw,hdw_desc->description);
1888         if (!hdw) goto fail;
1889
1890         init_timer(&hdw->quiescent_timer);
1891         hdw->quiescent_timer.data = (unsigned long)hdw;
1892         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
1893
1894         init_timer(&hdw->encoder_wait_timer);
1895         hdw->encoder_wait_timer.data = (unsigned long)hdw;
1896         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
1897
1898         init_timer(&hdw->encoder_run_timer);
1899         hdw->encoder_run_timer.data = (unsigned long)hdw;
1900         hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
1901
1902         hdw->master_state = PVR2_STATE_DEAD;
1903
1904         init_waitqueue_head(&hdw->state_wait_data);
1905
1906         hdw->tuner_signal_stale = !0;
1907         cx2341x_fill_defaults(&hdw->enc_ctl_state);
1908
1909         /* Calculate which inputs are OK */
1910         m = 0;
1911         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
1912         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
1913                 m |= 1 << PVR2_CVAL_INPUT_DTV;
1914         }
1915         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
1916         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
1917         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
1918         hdw->input_avail_mask = m;
1919
1920         /* If not a hybrid device, pathway_state never changes.  So
1921            initialize it here to what it should forever be. */
1922         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
1923                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
1924         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
1925                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
1926         }
1927
1928         hdw->control_cnt = CTRLDEF_COUNT;
1929         hdw->control_cnt += MPEGDEF_COUNT;
1930         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1931                                 GFP_KERNEL);
1932         if (!hdw->controls) goto fail;
1933         hdw->hdw_desc = hdw_desc;
1934         for (idx = 0; idx < hdw->control_cnt; idx++) {
1935                 cptr = hdw->controls + idx;
1936                 cptr->hdw = hdw;
1937         }
1938         for (idx = 0; idx < 32; idx++) {
1939                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1940         }
1941         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1942                 cptr = hdw->controls + idx;
1943                 cptr->info = control_defs+idx;
1944         }
1945
1946         /* Ensure that default input choice is a valid one. */
1947         m = hdw->input_avail_mask;
1948         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
1949                 if (!((1 << idx) & m)) continue;
1950                 hdw->input_val = idx;
1951                 break;
1952         }
1953
1954         /* Define and configure additional controls from cx2341x module. */
1955         hdw->mpeg_ctrl_info = kzalloc(
1956                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1957         if (!hdw->mpeg_ctrl_info) goto fail;
1958         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1959                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1960                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1961                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1962                 ciptr->name = mpeg_ids[idx].strid;
1963                 ciptr->v4l_id = mpeg_ids[idx].id;
1964                 ciptr->skip_init = !0;
1965                 ciptr->get_value = ctrl_cx2341x_get;
1966                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1967                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1968                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1969                 qctrl.id = ciptr->v4l_id;
1970                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1971                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1972                         ciptr->set_value = ctrl_cx2341x_set;
1973                 }
1974                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1975                         PVR2_CTLD_INFO_DESC_SIZE);
1976                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
1977                 ciptr->default_value = qctrl.default_value;
1978                 switch (qctrl.type) {
1979                 default:
1980                 case V4L2_CTRL_TYPE_INTEGER:
1981                         ciptr->type = pvr2_ctl_int;
1982                         ciptr->def.type_int.min_value = qctrl.minimum;
1983                         ciptr->def.type_int.max_value = qctrl.maximum;
1984                         break;
1985                 case V4L2_CTRL_TYPE_BOOLEAN:
1986                         ciptr->type = pvr2_ctl_bool;
1987                         break;
1988                 case V4L2_CTRL_TYPE_MENU:
1989                         ciptr->type = pvr2_ctl_enum;
1990                         ciptr->def.type_enum.value_names =
1991                                 cx2341x_ctrl_get_menu(ciptr->v4l_id);
1992                         for (cnt1 = 0;
1993                              ciptr->def.type_enum.value_names[cnt1] != NULL;
1994                              cnt1++) { }
1995                         ciptr->def.type_enum.count = cnt1;
1996                         break;
1997                 }
1998                 cptr->info = ciptr;
1999         }
2000
2001         // Initialize video standard enum dynamic control
2002         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2003         if (cptr) {
2004                 memcpy(&hdw->std_info_enum,cptr->info,
2005                        sizeof(hdw->std_info_enum));
2006                 cptr->info = &hdw->std_info_enum;
2007
2008         }
2009         // Initialize control data regarding video standard masks
2010         valid_std_mask = pvr2_std_get_usable();
2011         for (idx = 0; idx < 32; idx++) {
2012                 if (!(valid_std_mask & (1 << idx))) continue;
2013                 cnt1 = pvr2_std_id_to_str(
2014                         hdw->std_mask_names[idx],
2015                         sizeof(hdw->std_mask_names[idx])-1,
2016                         1 << idx);
2017                 hdw->std_mask_names[idx][cnt1] = 0;
2018         }
2019         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2020         if (cptr) {
2021                 memcpy(&hdw->std_info_avail,cptr->info,
2022                        sizeof(hdw->std_info_avail));
2023                 cptr->info = &hdw->std_info_avail;
2024                 hdw->std_info_avail.def.type_bitmask.bit_names =
2025                         hdw->std_mask_ptrs;
2026                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2027                         valid_std_mask;
2028         }
2029         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2030         if (cptr) {
2031                 memcpy(&hdw->std_info_cur,cptr->info,
2032                        sizeof(hdw->std_info_cur));
2033                 cptr->info = &hdw->std_info_cur;
2034                 hdw->std_info_cur.def.type_bitmask.bit_names =
2035                         hdw->std_mask_ptrs;
2036                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2037                         valid_std_mask;
2038         }
2039
2040         hdw->eeprom_addr = -1;
2041         hdw->unit_number = -1;
2042         hdw->v4l_minor_number_video = -1;
2043         hdw->v4l_minor_number_vbi = -1;
2044         hdw->v4l_minor_number_radio = -1;
2045         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2046         if (!hdw->ctl_write_buffer) goto fail;
2047         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2048         if (!hdw->ctl_read_buffer) goto fail;
2049         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2050         if (!hdw->ctl_write_urb) goto fail;
2051         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2052         if (!hdw->ctl_read_urb) goto fail;
2053
2054         mutex_lock(&pvr2_unit_mtx); do {
2055                 for (idx = 0; idx < PVR_NUM; idx++) {
2056                         if (unit_pointers[idx]) continue;
2057                         hdw->unit_number = idx;
2058                         unit_pointers[idx] = hdw;
2059                         break;
2060                 }
2061         } while (0); mutex_unlock(&pvr2_unit_mtx);
2062
2063         cnt1 = 0;
2064         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2065         cnt1 += cnt2;
2066         if (hdw->unit_number >= 0) {
2067                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2068                                  ('a' + hdw->unit_number));
2069                 cnt1 += cnt2;
2070         }
2071         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2072         hdw->name[cnt1] = 0;
2073
2074         hdw->workqueue = create_singlethread_workqueue(hdw->name);
2075         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2076         INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2077
2078         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2079                    hdw->unit_number,hdw->name);
2080
2081         hdw->tuner_type = -1;
2082         hdw->flag_ok = !0;
2083
2084         hdw->usb_intf = intf;
2085         hdw->usb_dev = interface_to_usbdev(intf);
2086
2087         scnprintf(hdw->bus_info,sizeof(hdw->bus_info),
2088                   "usb %s address %d",
2089                   hdw->usb_dev->dev.bus_id,
2090                   hdw->usb_dev->devnum);
2091
2092         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2093         usb_set_interface(hdw->usb_dev,ifnum,0);
2094
2095         mutex_init(&hdw->ctl_lock_mutex);
2096         mutex_init(&hdw->big_lock_mutex);
2097
2098         return hdw;
2099  fail:
2100         if (hdw) {
2101                 del_timer_sync(&hdw->quiescent_timer);
2102                 del_timer_sync(&hdw->encoder_run_timer);
2103                 del_timer_sync(&hdw->encoder_wait_timer);
2104                 if (hdw->workqueue) {
2105                         flush_workqueue(hdw->workqueue);
2106                         destroy_workqueue(hdw->workqueue);
2107                         hdw->workqueue = NULL;
2108                 }
2109                 usb_free_urb(hdw->ctl_read_urb);
2110                 usb_free_urb(hdw->ctl_write_urb);
2111                 kfree(hdw->ctl_read_buffer);
2112                 kfree(hdw->ctl_write_buffer);
2113                 kfree(hdw->controls);
2114                 kfree(hdw->mpeg_ctrl_info);
2115                 kfree(hdw->std_defs);
2116                 kfree(hdw->std_enum_names);
2117                 kfree(hdw);
2118         }
2119         return NULL;
2120 }
2121
2122
2123 /* Remove _all_ associations between this driver and the underlying USB
2124    layer. */
2125 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2126 {
2127         if (hdw->flag_disconnected) return;
2128         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2129         if (hdw->ctl_read_urb) {
2130                 usb_kill_urb(hdw->ctl_read_urb);
2131                 usb_free_urb(hdw->ctl_read_urb);
2132                 hdw->ctl_read_urb = NULL;
2133         }
2134         if (hdw->ctl_write_urb) {
2135                 usb_kill_urb(hdw->ctl_write_urb);
2136                 usb_free_urb(hdw->ctl_write_urb);
2137                 hdw->ctl_write_urb = NULL;
2138         }
2139         if (hdw->ctl_read_buffer) {
2140                 kfree(hdw->ctl_read_buffer);
2141                 hdw->ctl_read_buffer = NULL;
2142         }
2143         if (hdw->ctl_write_buffer) {
2144                 kfree(hdw->ctl_write_buffer);
2145                 hdw->ctl_write_buffer = NULL;
2146         }
2147         hdw->flag_disconnected = !0;
2148         hdw->usb_dev = NULL;
2149         hdw->usb_intf = NULL;
2150         pvr2_hdw_render_useless(hdw);
2151 }
2152
2153
2154 /* Destroy hardware interaction structure */
2155 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2156 {
2157         if (!hdw) return;
2158         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2159         if (hdw->workqueue) {
2160                 flush_workqueue(hdw->workqueue);
2161                 destroy_workqueue(hdw->workqueue);
2162                 hdw->workqueue = NULL;
2163         }
2164         del_timer_sync(&hdw->quiescent_timer);
2165         del_timer_sync(&hdw->encoder_run_timer);
2166         del_timer_sync(&hdw->encoder_wait_timer);
2167         if (hdw->fw_buffer) {
2168                 kfree(hdw->fw_buffer);
2169                 hdw->fw_buffer = NULL;
2170         }
2171         if (hdw->vid_stream) {
2172                 pvr2_stream_destroy(hdw->vid_stream);
2173                 hdw->vid_stream = NULL;
2174         }
2175         if (hdw->decoder_ctrl) {
2176                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2177         }
2178         pvr2_i2c_core_done(hdw);
2179         pvr2_hdw_remove_usb_stuff(hdw);
2180         mutex_lock(&pvr2_unit_mtx); do {
2181                 if ((hdw->unit_number >= 0) &&
2182                     (hdw->unit_number < PVR_NUM) &&
2183                     (unit_pointers[hdw->unit_number] == hdw)) {
2184                         unit_pointers[hdw->unit_number] = NULL;
2185                 }
2186         } while (0); mutex_unlock(&pvr2_unit_mtx);
2187         kfree(hdw->controls);
2188         kfree(hdw->mpeg_ctrl_info);
2189         kfree(hdw->std_defs);
2190         kfree(hdw->std_enum_names);
2191         kfree(hdw);
2192 }
2193
2194
2195 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2196 {
2197         return (hdw && hdw->flag_ok);
2198 }
2199
2200
2201 /* Called when hardware has been unplugged */
2202 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2203 {
2204         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2205         LOCK_TAKE(hdw->big_lock);
2206         LOCK_TAKE(hdw->ctl_lock);
2207         pvr2_hdw_remove_usb_stuff(hdw);
2208         LOCK_GIVE(hdw->ctl_lock);
2209         LOCK_GIVE(hdw->big_lock);
2210 }
2211
2212
2213 // Attempt to autoselect an appropriate value for std_enum_cur given
2214 // whatever is currently in std_mask_cur
2215 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2216 {
2217         unsigned int idx;
2218         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2219                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2220                         hdw->std_enum_cur = idx;
2221                         return;
2222                 }
2223         }
2224         hdw->std_enum_cur = 0;
2225 }
2226
2227
2228 // Calculate correct set of enumerated standards based on currently known
2229 // set of available standards bits.
2230 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2231 {
2232         struct v4l2_standard *newstd;
2233         unsigned int std_cnt;
2234         unsigned int idx;
2235
2236         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2237
2238         if (hdw->std_defs) {
2239                 kfree(hdw->std_defs);
2240                 hdw->std_defs = NULL;
2241         }
2242         hdw->std_enum_cnt = 0;
2243         if (hdw->std_enum_names) {
2244                 kfree(hdw->std_enum_names);
2245                 hdw->std_enum_names = NULL;
2246         }
2247
2248         if (!std_cnt) {
2249                 pvr2_trace(
2250                         PVR2_TRACE_ERROR_LEGS,
2251                         "WARNING: Failed to identify any viable standards");
2252         }
2253         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2254         hdw->std_enum_names[0] = "none";
2255         for (idx = 0; idx < std_cnt; idx++) {
2256                 hdw->std_enum_names[idx+1] =
2257                         newstd[idx].name;
2258         }
2259         // Set up the dynamic control for this standard
2260         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2261         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2262         hdw->std_defs = newstd;
2263         hdw->std_enum_cnt = std_cnt+1;
2264         hdw->std_enum_cur = 0;
2265         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2266 }
2267
2268
2269 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2270                                struct v4l2_standard *std,
2271                                unsigned int idx)
2272 {
2273         int ret = -EINVAL;
2274         if (!idx) return ret;
2275         LOCK_TAKE(hdw->big_lock); do {
2276                 if (idx >= hdw->std_enum_cnt) break;
2277                 idx--;
2278                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2279                 ret = 0;
2280         } while (0); LOCK_GIVE(hdw->big_lock);
2281         return ret;
2282 }
2283
2284
2285 /* Get the number of defined controls */
2286 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2287 {
2288         return hdw->control_cnt;
2289 }
2290
2291
2292 /* Retrieve a control handle given its index (0..count-1) */
2293 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2294                                              unsigned int idx)
2295 {
2296         if (idx >= hdw->control_cnt) return NULL;
2297         return hdw->controls + idx;
2298 }
2299
2300
2301 /* Retrieve a control handle given its index (0..count-1) */
2302 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2303                                           unsigned int ctl_id)
2304 {
2305         struct pvr2_ctrl *cptr;
2306         unsigned int idx;
2307         int i;
2308
2309         /* This could be made a lot more efficient, but for now... */
2310         for (idx = 0; idx < hdw->control_cnt; idx++) {
2311                 cptr = hdw->controls + idx;
2312                 i = cptr->info->internal_id;
2313                 if (i && (i == ctl_id)) return cptr;
2314         }
2315         return NULL;
2316 }
2317
2318
2319 /* Given a V4L ID, retrieve the control structure associated with it. */
2320 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2321 {
2322         struct pvr2_ctrl *cptr;
2323         unsigned int idx;
2324         int i;
2325
2326         /* This could be made a lot more efficient, but for now... */
2327         for (idx = 0; idx < hdw->control_cnt; idx++) {
2328                 cptr = hdw->controls + idx;
2329                 i = cptr->info->v4l_id;
2330                 if (i && (i == ctl_id)) return cptr;
2331         }
2332         return NULL;
2333 }
2334
2335
2336 /* Given a V4L ID for its immediate predecessor, retrieve the control
2337    structure associated with it. */
2338 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2339                                             unsigned int ctl_id)
2340 {
2341         struct pvr2_ctrl *cptr,*cp2;
2342         unsigned int idx;
2343         int i;
2344
2345         /* This could be made a lot more efficient, but for now... */
2346         cp2 = NULL;
2347         for (idx = 0; idx < hdw->control_cnt; idx++) {
2348                 cptr = hdw->controls + idx;
2349                 i = cptr->info->v4l_id;
2350                 if (!i) continue;
2351                 if (i <= ctl_id) continue;
2352                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2353                 cp2 = cptr;
2354         }
2355         return cp2;
2356         return NULL;
2357 }
2358
2359
2360 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2361 {
2362         switch (tp) {
2363         case pvr2_ctl_int: return "integer";
2364         case pvr2_ctl_enum: return "enum";
2365         case pvr2_ctl_bool: return "boolean";
2366         case pvr2_ctl_bitmask: return "bitmask";
2367         }
2368         return "";
2369 }
2370
2371
2372 /* Figure out if we need to commit control changes.  If so, mark internal
2373    state flags to indicate this fact and return true.  Otherwise do nothing
2374    else and return false. */
2375 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2376 {
2377         unsigned int idx;
2378         struct pvr2_ctrl *cptr;
2379         int value;
2380         int commit_flag = 0;
2381         char buf[100];
2382         unsigned int bcnt,ccnt;
2383
2384         for (idx = 0; idx < hdw->control_cnt; idx++) {
2385                 cptr = hdw->controls + idx;
2386                 if (!cptr->info->is_dirty) continue;
2387                 if (!cptr->info->is_dirty(cptr)) continue;
2388                 commit_flag = !0;
2389
2390                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2391                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2392                                  cptr->info->name);
2393                 value = 0;
2394                 cptr->info->get_value(cptr,&value);
2395                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2396                                                 buf+bcnt,
2397                                                 sizeof(buf)-bcnt,&ccnt);
2398                 bcnt += ccnt;
2399                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2400                                   get_ctrl_typename(cptr->info->type));
2401                 pvr2_trace(PVR2_TRACE_CTL,
2402                            "/*--TRACE_COMMIT--*/ %.*s",
2403                            bcnt,buf);
2404         }
2405
2406         if (!commit_flag) {
2407                 /* Nothing has changed */
2408                 return 0;
2409         }
2410
2411         hdw->state_pipeline_config = 0;
2412         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2413         pvr2_hdw_state_sched(hdw);
2414
2415         return !0;
2416 }
2417
2418
2419 /* Perform all operations needed to commit all control changes.  This must
2420    be performed in synchronization with the pipeline state and is thus
2421    expected to be called as part of the driver's worker thread.  Return
2422    true if commit successful, otherwise return false to indicate that
2423    commit isn't possible at this time. */
2424 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
2425 {
2426         unsigned int idx;
2427         struct pvr2_ctrl *cptr;
2428         int disruptive_change;
2429
2430         /* When video standard changes, reset the hres and vres values -
2431            but if the user has pending changes there, then let the changes
2432            take priority. */
2433         if (hdw->std_dirty) {
2434                 /* Rewrite the vertical resolution to be appropriate to the
2435                    video standard that has been selected. */
2436                 int nvres;
2437                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2438                         nvres = 480;
2439                 } else {
2440                         nvres = 576;
2441                 }
2442                 if (nvres != hdw->res_ver_val) {
2443                         hdw->res_ver_val = nvres;
2444                         hdw->res_ver_dirty = !0;
2445                 }
2446         }
2447
2448         if (hdw->input_dirty && hdw->state_pathway_ok &&
2449             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
2450               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
2451              hdw->pathway_state)) {
2452                 /* Change of mode being asked for... */
2453                 hdw->state_pathway_ok = 0;
2454                 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
2455         }
2456         if (!hdw->state_pathway_ok) {
2457                 /* Can't commit anything until pathway is ok. */
2458                 return 0;
2459         }
2460         /* If any of the below has changed, then we can't do the update
2461            while the pipeline is running.  Pipeline must be paused first
2462            and decoder -> encoder connection be made quiescent before we
2463            can proceed. */
2464         disruptive_change =
2465                 (hdw->std_dirty ||
2466                  hdw->enc_unsafe_stale ||
2467                  hdw->srate_dirty ||
2468                  hdw->res_ver_dirty ||
2469                  hdw->res_hor_dirty ||
2470                  hdw->input_dirty ||
2471                  (hdw->active_stream_type != hdw->desired_stream_type));
2472         if (disruptive_change && !hdw->state_pipeline_idle) {
2473                 /* Pipeline is not idle; we can't proceed.  Arrange to
2474                    cause pipeline to stop so that we can try this again
2475                    later.... */
2476                 hdw->state_pipeline_pause = !0;
2477                 return 0;
2478         }
2479
2480         if (hdw->srate_dirty) {
2481                 /* Write new sample rate into control structure since
2482                  * the master copy is stale.  We must track srate
2483                  * separate from the mpeg control structure because
2484                  * other logic also uses this value. */
2485                 struct v4l2_ext_controls cs;
2486                 struct v4l2_ext_control c1;
2487                 memset(&cs,0,sizeof(cs));
2488                 memset(&c1,0,sizeof(c1));
2489                 cs.controls = &c1;
2490                 cs.count = 1;
2491                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2492                 c1.value = hdw->srate_val;
2493                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
2494         }
2495
2496         /* Scan i2c core at this point - before we clear all the dirty
2497            bits.  Various parts of the i2c core will notice dirty bits as
2498            appropriate and arrange to broadcast or directly send updates to
2499            the client drivers in order to keep everything in sync */
2500         pvr2_i2c_core_check_stale(hdw);
2501
2502         for (idx = 0; idx < hdw->control_cnt; idx++) {
2503                 cptr = hdw->controls + idx;
2504                 if (!cptr->info->clear_dirty) continue;
2505                 cptr->info->clear_dirty(cptr);
2506         }
2507
2508         if (hdw->active_stream_type != hdw->desired_stream_type) {
2509                 /* Handle any side effects of stream config here */
2510                 hdw->active_stream_type = hdw->desired_stream_type;
2511         }
2512
2513         /* Now execute i2c core update */
2514         pvr2_i2c_core_sync(hdw);
2515
2516         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
2517             hdw->state_encoder_run) {
2518                 /* If encoder isn't running or it can't be touched, then
2519                    this will get worked out later when we start the
2520                    encoder. */
2521                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
2522         }
2523
2524         hdw->state_pipeline_config = !0;
2525         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2526         return !0;
2527 }
2528
2529
2530 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2531 {
2532         int fl;
2533         LOCK_TAKE(hdw->big_lock);
2534         fl = pvr2_hdw_commit_setup(hdw);
2535         LOCK_GIVE(hdw->big_lock);
2536         if (!fl) return 0;
2537         return pvr2_hdw_wait(hdw,0);
2538 }
2539
2540
2541 static void pvr2_hdw_worker_i2c(struct work_struct *work)
2542 {
2543         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
2544         LOCK_TAKE(hdw->big_lock); do {
2545                 pvr2_i2c_core_sync(hdw);
2546         } while (0); LOCK_GIVE(hdw->big_lock);
2547 }
2548
2549
2550 static void pvr2_hdw_worker_poll(struct work_struct *work)
2551 {
2552         int fl = 0;
2553         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
2554         LOCK_TAKE(hdw->big_lock); do {
2555                 fl = pvr2_hdw_state_eval(hdw);
2556         } while (0); LOCK_GIVE(hdw->big_lock);
2557         if (fl && hdw->state_func) {
2558                 hdw->state_func(hdw->state_data);
2559         }
2560 }
2561
2562
2563 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
2564 {
2565         return wait_event_interruptible(
2566                 hdw->state_wait_data,
2567                 (hdw->state_stale == 0) &&
2568                 (!state || (hdw->master_state != state)));
2569 }
2570
2571
2572 /* Return name for this driver instance */
2573 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2574 {
2575         return hdw->name;
2576 }
2577
2578
2579 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
2580 {
2581         return hdw->hdw_desc->description;
2582 }
2583
2584
2585 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
2586 {
2587         return hdw->hdw_desc->shortname;
2588 }
2589
2590
2591 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2592 {
2593         int result;
2594         LOCK_TAKE(hdw->ctl_lock); do {
2595                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
2596                 result = pvr2_send_request(hdw,
2597                                            hdw->cmd_buffer,1,
2598                                            hdw->cmd_buffer,1);
2599                 if (result < 0) break;
2600                 result = (hdw->cmd_buffer[0] != 0);
2601         } while(0); LOCK_GIVE(hdw->ctl_lock);
2602         return result;
2603 }
2604
2605
2606 /* Execute poll of tuner status */
2607 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
2608 {
2609         LOCK_TAKE(hdw->big_lock); do {
2610                 pvr2_i2c_core_status_poll(hdw);
2611         } while (0); LOCK_GIVE(hdw->big_lock);
2612 }
2613
2614
2615 /* Return information about the tuner */
2616 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
2617 {
2618         LOCK_TAKE(hdw->big_lock); do {
2619                 if (hdw->tuner_signal_stale) {
2620                         pvr2_i2c_core_status_poll(hdw);
2621                 }
2622                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
2623         } while (0); LOCK_GIVE(hdw->big_lock);
2624         return 0;
2625 }
2626
2627
2628 /* Get handle to video output stream */
2629 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2630 {
2631         return hp->vid_stream;
2632 }
2633
2634
2635 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2636 {
2637         int nr = pvr2_hdw_get_unit_number(hdw);
2638         LOCK_TAKE(hdw->big_lock); do {
2639                 hdw->log_requested = !0;
2640                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
2641                 pvr2_i2c_core_check_stale(hdw);
2642                 hdw->log_requested = 0;
2643                 pvr2_i2c_core_sync(hdw);
2644                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
2645                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
2646                 pvr2_hdw_state_log_state(hdw);
2647                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
2648         } while (0); LOCK_GIVE(hdw->big_lock);
2649 }
2650
2651
2652 /* Grab EEPROM contents, needed for direct method. */
2653 #define EEPROM_SIZE 8192
2654 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
2655 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
2656 {
2657         struct i2c_msg msg[2];
2658         u8 *eeprom;
2659         u8 iadd[2];
2660         u8 addr;
2661         u16 eepromSize;
2662         unsigned int offs;
2663         int ret;
2664         int mode16 = 0;
2665         unsigned pcnt,tcnt;
2666         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
2667         if (!eeprom) {
2668                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2669                            "Failed to allocate memory"
2670                            " required to read eeprom");
2671                 return NULL;
2672         }
2673
2674         trace_eeprom("Value for eeprom addr from controller was 0x%x",
2675                      hdw->eeprom_addr);
2676         addr = hdw->eeprom_addr;
2677         /* Seems that if the high bit is set, then the *real* eeprom
2678            address is shifted right now bit position (noticed this in
2679            newer PVR USB2 hardware) */
2680         if (addr & 0x80) addr >>= 1;
2681
2682         /* FX2 documentation states that a 16bit-addressed eeprom is
2683            expected if the I2C address is an odd number (yeah, this is
2684            strange but it's what they do) */
2685         mode16 = (addr & 1);
2686         eepromSize = (mode16 ? EEPROM_SIZE : 256);
2687         trace_eeprom("Examining %d byte eeprom at location 0x%x"
2688                      " using %d bit addressing",eepromSize,addr,
2689                      mode16 ? 16 : 8);
2690
2691         msg[0].addr = addr;
2692         msg[0].flags = 0;
2693         msg[0].len = mode16 ? 2 : 1;
2694         msg[0].buf = iadd;
2695         msg[1].addr = addr;
2696         msg[1].flags = I2C_M_RD;
2697
2698         /* We have to do the actual eeprom data fetch ourselves, because
2699            (1) we're only fetching part of the eeprom, and (2) if we were
2700            getting the whole thing our I2C driver can't grab it in one
2701            pass - which is what tveeprom is otherwise going to attempt */
2702         memset(eeprom,0,EEPROM_SIZE);
2703         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
2704                 pcnt = 16;
2705                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
2706                 offs = tcnt + (eepromSize - EEPROM_SIZE);
2707                 if (mode16) {
2708                         iadd[0] = offs >> 8;
2709                         iadd[1] = offs;
2710                 } else {
2711                         iadd[0] = offs;
2712                 }
2713                 msg[1].len = pcnt;
2714                 msg[1].buf = eeprom+tcnt;
2715                 if ((ret = i2c_transfer(&hdw->i2c_adap,
2716                                         msg,ARRAY_SIZE(msg))) != 2) {
2717                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2718                                    "eeprom fetch set offs err=%d",ret);
2719                         kfree(eeprom);
2720                         return NULL;
2721                 }
2722         }
2723         return eeprom;
2724 }
2725
2726
2727 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
2728                                 int prom_flag,
2729                                 int enable_flag)
2730 {
2731         int ret;
2732         u16 address;
2733         unsigned int pipe;
2734         LOCK_TAKE(hdw->big_lock); do {
2735                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
2736
2737                 if (!enable_flag) {
2738                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2739                                    "Cleaning up after CPU firmware fetch");
2740                         kfree(hdw->fw_buffer);
2741                         hdw->fw_buffer = NULL;
2742                         hdw->fw_size = 0;
2743                         if (hdw->fw_cpu_flag) {
2744                                 /* Now release the CPU.  It will disconnect
2745                                    and reconnect later. */
2746                                 pvr2_hdw_cpureset_assert(hdw,0);
2747                         }
2748                         break;
2749                 }
2750
2751                 hdw->fw_cpu_flag = (prom_flag == 0);
2752                 if (hdw->fw_cpu_flag) {
2753                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2754                                    "Preparing to suck out CPU firmware");
2755                         hdw->fw_size = 0x2000;
2756                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
2757                         if (!hdw->fw_buffer) {
2758                                 hdw->fw_size = 0;
2759                                 break;
2760                         }
2761
2762                         /* We have to hold the CPU during firmware upload. */
2763                         pvr2_hdw_cpureset_assert(hdw,1);
2764
2765                         /* download the firmware from address 0000-1fff in 2048
2766                            (=0x800) bytes chunk. */
2767
2768                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2769                                    "Grabbing CPU firmware");
2770                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2771                         for(address = 0; address < hdw->fw_size;
2772                             address += 0x800) {
2773                                 ret = usb_control_msg(hdw->usb_dev,pipe,
2774                                                       0xa0,0xc0,
2775                                                       address,0,
2776                                                       hdw->fw_buffer+address,
2777                                                       0x800,HZ);
2778                                 if (ret < 0) break;
2779                         }
2780
2781                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2782                                    "Done grabbing CPU firmware");
2783                 } else {
2784                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2785                                    "Sucking down EEPROM contents");
2786                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
2787                         if (!hdw->fw_buffer) {
2788                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2789                                            "EEPROM content suck failed.");
2790                                 break;
2791                         }
2792                         hdw->fw_size = EEPROM_SIZE;
2793                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2794                                    "Done sucking down EEPROM contents");
2795                 }
2796
2797         } while (0); LOCK_GIVE(hdw->big_lock);
2798 }
2799
2800
2801 /* Return true if we're in a mode for retrieval CPU firmware */
2802 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2803 {
2804         return hdw->fw_buffer != NULL;
2805 }
2806
2807
2808 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2809                        char *buf,unsigned int cnt)
2810 {
2811         int ret = -EINVAL;
2812         LOCK_TAKE(hdw->big_lock); do {
2813                 if (!buf) break;
2814                 if (!cnt) break;
2815
2816                 if (!hdw->fw_buffer) {
2817                         ret = -EIO;
2818                         break;
2819                 }
2820
2821                 if (offs >= hdw->fw_size) {
2822                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2823                                    "Read firmware data offs=%d EOF",
2824                                    offs);
2825                         ret = 0;
2826                         break;
2827                 }
2828
2829                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2830
2831                 memcpy(buf,hdw->fw_buffer+offs,cnt);
2832
2833                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2834                            "Read firmware data offs=%d cnt=%d",
2835                            offs,cnt);
2836                 ret = cnt;
2837         } while (0); LOCK_GIVE(hdw->big_lock);
2838
2839         return ret;
2840 }
2841
2842
2843 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
2844                                   enum pvr2_v4l_type index)
2845 {
2846         switch (index) {
2847         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
2848         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
2849         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
2850         default: return -1;
2851         }
2852 }
2853
2854
2855 /* Store a v4l minor device number */
2856 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
2857                                      enum pvr2_v4l_type index,int v)
2858 {
2859         switch (index) {
2860         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
2861         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
2862         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
2863         default: break;
2864         }
2865 }
2866
2867
2868 static void pvr2_ctl_write_complete(struct urb *urb)
2869 {
2870         struct pvr2_hdw *hdw = urb->context;
2871         hdw->ctl_write_pend_flag = 0;
2872         if (hdw->ctl_read_pend_flag) return;
2873         complete(&hdw->ctl_done);
2874 }
2875
2876
2877 static void pvr2_ctl_read_complete(struct urb *urb)
2878 {
2879         struct pvr2_hdw *hdw = urb->context;
2880         hdw->ctl_read_pend_flag = 0;
2881         if (hdw->ctl_write_pend_flag) return;
2882         complete(&hdw->ctl_done);
2883 }
2884
2885
2886 static void pvr2_ctl_timeout(unsigned long data)
2887 {
2888         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2889         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2890                 hdw->ctl_timeout_flag = !0;
2891                 if (hdw->ctl_write_pend_flag)
2892                         usb_unlink_urb(hdw->ctl_write_urb);
2893                 if (hdw->ctl_read_pend_flag)
2894                         usb_unlink_urb(hdw->ctl_read_urb);
2895         }
2896 }
2897
2898
2899 /* Issue a command and get a response from the device.  This extended
2900    version includes a probe flag (which if set means that device errors
2901    should not be logged or treated as fatal) and a timeout in jiffies.
2902    This can be used to non-lethally probe the health of endpoint 1. */
2903 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2904                                 unsigned int timeout,int probe_fl,
2905                                 void *write_data,unsigned int write_len,
2906                                 void *read_data,unsigned int read_len)
2907 {
2908         unsigned int idx;
2909         int status = 0;
2910         struct timer_list timer;
2911         if (!hdw->ctl_lock_held) {
2912                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2913                            "Attempted to execute control transfer"
2914                            " without lock!!");
2915                 return -EDEADLK;
2916         }
2917         if (!hdw->flag_ok && !probe_fl) {
2918                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2919                            "Attempted to execute control transfer"
2920                            " when device not ok");
2921                 return -EIO;
2922         }
2923         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2924                 if (!probe_fl) {
2925                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2926                                    "Attempted to execute control transfer"
2927                                    " when USB is disconnected");
2928                 }
2929                 return -ENOTTY;
2930         }
2931
2932         /* Ensure that we have sane parameters */
2933         if (!write_data) write_len = 0;
2934         if (!read_data) read_len = 0;
2935         if (write_len > PVR2_CTL_BUFFSIZE) {
2936                 pvr2_trace(
2937                         PVR2_TRACE_ERROR_LEGS,
2938                         "Attempted to execute %d byte"
2939                         " control-write transfer (limit=%d)",
2940                         write_len,PVR2_CTL_BUFFSIZE);
2941                 return -EINVAL;
2942         }
2943         if (read_len > PVR2_CTL_BUFFSIZE) {
2944                 pvr2_trace(
2945                         PVR2_TRACE_ERROR_LEGS,
2946                         "Attempted to execute %d byte"
2947                         " control-read transfer (limit=%d)",
2948                         write_len,PVR2_CTL_BUFFSIZE);
2949                 return -EINVAL;
2950         }
2951         if ((!write_len) && (!read_len)) {
2952                 pvr2_trace(
2953                         PVR2_TRACE_ERROR_LEGS,
2954                         "Attempted to execute null control transfer?");
2955                 return -EINVAL;
2956         }
2957
2958
2959         hdw->cmd_debug_state = 1;
2960         if (write_len) {
2961                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2962         } else {
2963                 hdw->cmd_debug_code = 0;
2964         }
2965         hdw->cmd_debug_write_len = write_len;
2966         hdw->cmd_debug_read_len = read_len;
2967
2968         /* Initialize common stuff */
2969         init_completion(&hdw->ctl_done);
2970         hdw->ctl_timeout_flag = 0;
2971         hdw->ctl_write_pend_flag = 0;
2972         hdw->ctl_read_pend_flag = 0;
2973         init_timer(&timer);
2974         timer.expires = jiffies + timeout;
2975         timer.data = (unsigned long)hdw;
2976         timer.function = pvr2_ctl_timeout;
2977
2978         if (write_len) {
2979                 hdw->cmd_debug_state = 2;
2980                 /* Transfer write data to internal buffer */
2981                 for (idx = 0; idx < write_len; idx++) {
2982                         hdw->ctl_write_buffer[idx] =
2983                                 ((unsigned char *)write_data)[idx];
2984                 }
2985                 /* Initiate a write request */
2986                 usb_fill_bulk_urb(hdw->ctl_write_urb,
2987                                   hdw->usb_dev,
2988                                   usb_sndbulkpipe(hdw->usb_dev,
2989                                                   PVR2_CTL_WRITE_ENDPOINT),
2990                                   hdw->ctl_write_buffer,
2991                                   write_len,
2992                                   pvr2_ctl_write_complete,
2993                                   hdw);
2994                 hdw->ctl_write_urb->actual_length = 0;
2995                 hdw->ctl_write_pend_flag = !0;
2996                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2997                 if (status < 0) {
2998                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2999                                    "Failed to submit write-control"
3000                                    " URB status=%d",status);
3001                         hdw->ctl_write_pend_flag = 0;
3002                         goto done;
3003                 }
3004         }
3005
3006         if (read_len) {
3007                 hdw->cmd_debug_state = 3;
3008                 memset(hdw->ctl_read_buffer,0x43,read_len);
3009                 /* Initiate a read request */
3010                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3011                                   hdw->usb_dev,
3012                                   usb_rcvbulkpipe(hdw->usb_dev,
3013                                                   PVR2_CTL_READ_ENDPOINT),
3014                                   hdw->ctl_read_buffer,
3015                                   read_len,
3016                                   pvr2_ctl_read_complete,
3017                                   hdw);
3018                 hdw->ctl_read_urb->actual_length = 0;
3019                 hdw->ctl_read_pend_flag = !0;
3020                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3021                 if (status < 0) {
3022                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3023                                    "Failed to submit read-control"
3024                                    " URB status=%d",status);
3025                         hdw->ctl_read_pend_flag = 0;
3026                         goto done;
3027                 }
3028         }
3029
3030         /* Start timer */
3031         add_timer(&timer);
3032
3033         /* Now wait for all I/O to complete */
3034         hdw->cmd_debug_state = 4;
3035         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3036                 wait_for_completion(&hdw->ctl_done);
3037         }
3038         hdw->cmd_debug_state = 5;
3039
3040         /* Stop timer */
3041         del_timer_sync(&timer);
3042
3043         hdw->cmd_debug_state = 6;
3044         status = 0;
3045
3046         if (hdw->ctl_timeout_flag) {
3047                 status = -ETIMEDOUT;
3048                 if (!probe_fl) {
3049                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3050                                    "Timed out control-write");
3051                 }
3052                 goto done;
3053         }
3054
3055         if (write_len) {
3056                 /* Validate results of write request */
3057                 if ((hdw->ctl_write_urb->status != 0) &&
3058                     (hdw->ctl_write_urb->status != -ENOENT) &&
3059                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3060                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3061                         /* USB subsystem is reporting some kind of failure
3062                            on the write */
3063                         status = hdw->ctl_write_urb->status;
3064                         if (!probe_fl) {
3065                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3066                                            "control-write URB failure,"
3067                                            " status=%d",
3068                                            status);
3069                         }
3070                         goto done;
3071                 }
3072                 if (hdw->ctl_write_urb->actual_length < write_len) {
3073                         /* Failed to write enough data */
3074                         status = -EIO;
3075                         if (!probe_fl) {
3076                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3077                                            "control-write URB short,"
3078                                            " expected=%d got=%d",
3079                                            write_len,
3080                                            hdw->ctl_write_urb->actual_length);
3081                         }
3082                         goto done;
3083                 }
3084         }
3085         if (read_len) {
3086                 /* Validate results of read request */
3087                 if ((hdw->ctl_read_urb->status != 0) &&
3088                     (hdw->ctl_read_urb->status != -ENOENT) &&
3089                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3090                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3091                         /* USB subsystem is reporting some kind of failure
3092                            on the read */
3093                         status = hdw->ctl_read_urb->status;
3094                         if (!probe_fl) {
3095                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3096                                            "control-read URB failure,"
3097                                            " status=%d",
3098                                            status);
3099                         }
3100                         goto done;
3101                 }
3102                 if (hdw->ctl_read_urb->actual_length < read_len) {
3103                         /* Failed to read enough data */
3104                         status = -EIO;
3105                         if (!probe_fl) {
3106                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3107                                            "control-read URB short,"
3108                                            " expected=%d got=%d",
3109                                            read_len,
3110                                            hdw->ctl_read_urb->actual_length);
3111                         }
3112                         goto done;
3113                 }
3114                 /* Transfer retrieved data out from internal buffer */
3115                 for (idx = 0; idx < read_len; idx++) {
3116                         ((unsigned char *)read_data)[idx] =
3117                                 hdw->ctl_read_buffer[idx];
3118                 }
3119         }
3120
3121  done:
3122
3123         hdw->cmd_debug_state = 0;
3124         if ((status < 0) && (!probe_fl)) {
3125                 pvr2_hdw_render_useless(hdw);
3126         }
3127         return status;
3128 }
3129
3130
3131 int pvr2_send_request(struct pvr2_hdw *hdw,
3132                       void *write_data,unsigned int write_len,
3133                       void *read_data,unsigned int read_len)
3134 {
3135         return pvr2_send_request_ex(hdw,HZ*4,0,
3136                                     write_data,write_len,
3137                                     read_data,read_len);
3138 }
3139
3140
3141 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3142 {
3143         int ret;
3144         unsigned int cnt = 1;
3145         unsigned int args = 0;
3146         LOCK_TAKE(hdw->ctl_lock);
3147         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3148         args = (cmdcode >> 8) & 0xffu;
3149         args = (args > 2) ? 2 : args;
3150         if (args) {
3151                 cnt += args;
3152                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3153                 if (args > 1) {
3154                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3155                 }
3156         }
3157         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3158                 unsigned int idx;
3159                 unsigned int ccnt,bcnt;
3160                 char tbuf[50];
3161                 cmdcode &= 0xffu;
3162                 bcnt = 0;
3163                 ccnt = scnprintf(tbuf+bcnt,
3164                                  sizeof(tbuf)-bcnt,
3165                                  "Sending FX2 command 0x%x",cmdcode);
3166                 bcnt += ccnt;
3167                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3168                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3169                                 ccnt = scnprintf(tbuf+bcnt,
3170                                                  sizeof(tbuf)-bcnt,
3171                                                  " \"%s\"",
3172                                                  pvr2_fx2cmd_desc[idx].desc);
3173                                 bcnt += ccnt;
3174                                 break;
3175                         }
3176                 }
3177                 if (args) {
3178                         ccnt = scnprintf(tbuf+bcnt,
3179                                          sizeof(tbuf)-bcnt,
3180                                          " (%u",hdw->cmd_buffer[1]);
3181                         bcnt += ccnt;
3182                         if (args > 1) {
3183                                 ccnt = scnprintf(tbuf+bcnt,
3184                                                  sizeof(tbuf)-bcnt,
3185                                                  ",%u",hdw->cmd_buffer[2]);
3186                                 bcnt += ccnt;
3187                         }
3188                         ccnt = scnprintf(tbuf+bcnt,
3189                                          sizeof(tbuf)-bcnt,
3190                                          ")");
3191                         bcnt += ccnt;
3192                 }
3193                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3194         }
3195         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3196         LOCK_GIVE(hdw->ctl_lock);
3197         return ret;
3198 }
3199
3200
3201 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3202 {
3203         int ret;
3204
3205         LOCK_TAKE(hdw->ctl_lock);
3206
3207         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3208         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3209         hdw->cmd_buffer[5] = 0;
3210         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3211         hdw->cmd_buffer[7] = reg & 0xff;
3212
3213
3214         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3215
3216         LOCK_GIVE(hdw->ctl_lock);
3217
3218         return ret;
3219 }
3220
3221
3222 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3223 {
3224         int ret = 0;
3225
3226         LOCK_TAKE(hdw->ctl_lock);
3227
3228         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3229         hdw->cmd_buffer[1] = 0;
3230         hdw->cmd_buffer[2] = 0;
3231         hdw->cmd_buffer[3] = 0;
3232         hdw->cmd_buffer[4] = 0;
3233         hdw->cmd_buffer[5] = 0;
3234         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3235         hdw->cmd_buffer[7] = reg & 0xff;
3236
3237         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3238         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3239
3240         LOCK_GIVE(hdw->ctl_lock);
3241
3242         return ret;
3243 }
3244
3245
3246 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3247 {
3248         if (!hdw->flag_ok) return;
3249         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3250                    "Device being rendered inoperable");
3251         if (hdw->vid_stream) {
3252                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3253         }
3254         hdw->flag_ok = 0;
3255         trace_stbit("flag_ok",hdw->flag_ok);
3256         pvr2_hdw_state_sched(hdw);
3257 }
3258
3259
3260 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3261 {
3262         int ret;
3263         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3264         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3265         if (ret == 1) {
3266                 ret = usb_reset_device(hdw->usb_dev);
3267                 usb_unlock_device(hdw->usb_dev);
3268         } else {
3269                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3270                            "Failed to lock USB device ret=%d",ret);
3271         }
3272         if (init_pause_msec) {
3273                 pvr2_trace(PVR2_TRACE_INFO,
3274                            "Waiting %u msec for hardware to settle",
3275                            init_pause_msec);
3276                 msleep(init_pause_msec);
3277         }
3278
3279 }
3280
3281
3282 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3283 {
3284         char da[1];
3285         unsigned int pipe;
3286         int ret;
3287
3288         if (!hdw->usb_dev) return;
3289
3290         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3291
3292         da[0] = val ? 0x01 : 0x00;
3293
3294         /* Write the CPUCS register on the 8051.  The lsb of the register
3295            is the reset bit; a 1 asserts reset while a 0 clears it. */
3296         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3297         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3298         if (ret < 0) {
3299                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3300                            "cpureset_assert(%d) error=%d",val,ret);
3301                 pvr2_hdw_render_useless(hdw);
3302         }
3303 }
3304
3305
3306 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3307 {
3308         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
3309 }
3310
3311
3312 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3313 {
3314         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
3315 }
3316
3317
3318 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
3319 {
3320         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
3321 }
3322
3323
3324 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3325 {
3326         if (!hdw->decoder_ctrl) {
3327                 pvr2_trace(PVR2_TRACE_INIT,
3328                            "Unable to reset decoder: nothing attached");
3329                 return -ENOTTY;
3330         }
3331
3332         if (!hdw->decoder_ctrl->force_reset) {
3333                 pvr2_trace(PVR2_TRACE_INIT,
3334                            "Unable to reset decoder: not implemented");
3335                 return -ENOTTY;
3336         }
3337
3338         pvr2_trace(PVR2_TRACE_INIT,
3339                    "Requesting decoder reset");
3340         hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3341         return 0;
3342 }
3343
3344
3345 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
3346 {
3347         hdw->flag_ok = !0;
3348         return pvr2_issue_simple_cmd(hdw,
3349                                      FX2CMD_HCW_DEMOD_RESETIN |
3350                                      (1 << 8) |
3351                                      ((onoff ? 1 : 0) << 16));
3352 }
3353
3354
3355 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
3356 {
3357         hdw->flag_ok = !0;
3358         return pvr2_issue_simple_cmd(hdw,(onoff ?
3359                                           FX2CMD_ONAIR_DTV_POWER_ON :
3360                                           FX2CMD_ONAIR_DTV_POWER_OFF));
3361 }
3362
3363
3364 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
3365                                                 int onoff)
3366 {
3367         return pvr2_issue_simple_cmd(hdw,(onoff ?
3368                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
3369                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
3370 }
3371
3372
3373 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
3374 {
3375         int cmode;
3376         /* Compare digital/analog desired setting with current setting.  If
3377            they don't match, fix it... */
3378         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
3379         if (cmode == hdw->pathway_state) {
3380                 /* They match; nothing to do */
3381                 return;
3382         }
3383
3384         switch (hdw->hdw_desc->digital_control_scheme) {
3385         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3386                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
3387                 if (cmode == PVR2_PATHWAY_ANALOG) {
3388                         /* If moving to analog mode, also force the decoder
3389                            to reset.  If no decoder is attached, then it's
3390                            ok to ignore this because if/when the decoder
3391                            attaches, it will reset itself at that time. */
3392                         pvr2_hdw_cmd_decoder_reset(hdw);
3393                 }
3394                 break;
3395         case PVR2_DIGITAL_SCHEME_ONAIR:
3396                 /* Supposedly we should always have the power on whether in
3397                    digital or analog mode.  But for now do what appears to
3398                    work... */
3399                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
3400                 break;
3401         default: break;
3402         }
3403
3404         pvr2_hdw_untrip_unlocked(hdw);
3405         hdw->pathway_state = cmode;
3406 }
3407
3408
3409 void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
3410 {
3411         /* change some GPIO data
3412          *
3413          * note: bit d7 of dir appears to control the LED,
3414          * so we shut it off here.
3415          *
3416          */
3417         if (onoff) {
3418                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
3419         } else {
3420                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
3421         }
3422         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
3423 }
3424
3425
3426 typedef void (*led_method_func)(struct pvr2_hdw *,int);
3427
3428 static led_method_func led_methods[] = {
3429         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
3430 };
3431
3432
3433 /* Toggle LED */
3434 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
3435 {
3436         unsigned int scheme_id;
3437         led_method_func fp;
3438
3439         if ((!onoff) == (!hdw->led_on)) return;
3440
3441         hdw->led_on = onoff != 0;
3442
3443         scheme_id = hdw->hdw_desc->led_scheme;
3444         if (scheme_id < ARRAY_SIZE(led_methods)) {
3445                 fp = led_methods[scheme_id];
3446         } else {
3447                 fp = NULL;
3448         }
3449
3450         if (fp) (*fp)(hdw,onoff);
3451 }
3452
3453
3454 /* Stop / start video stream transport */
3455 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
3456 {
3457         int ret;
3458
3459         /* If we're in analog mode, then just issue the usual analog
3460            command. */
3461         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3462                 return pvr2_issue_simple_cmd(hdw,
3463                                              (runFl ?
3464                                               FX2CMD_STREAMING_ON :
3465                                               FX2CMD_STREAMING_OFF));
3466                 /*Note: Not reached */
3467         }
3468
3469         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
3470                 /* Whoops, we don't know what mode we're in... */
3471                 return -EINVAL;
3472         }
3473
3474         /* To get here we have to be in digital mode.  The mechanism here
3475            is unfortunately different for different vendors.  So we switch
3476            on the device's digital scheme attribute in order to figure out
3477            what to do. */
3478         switch (hdw->hdw_desc->digital_control_scheme) {
3479         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3480                 return pvr2_issue_simple_cmd(hdw,
3481                                              (runFl ?
3482                                               FX2CMD_HCW_DTV_STREAMING_ON :
3483                                               FX2CMD_HCW_DTV_STREAMING_OFF));
3484         case PVR2_DIGITAL_SCHEME_ONAIR:
3485                 ret = pvr2_issue_simple_cmd(hdw,
3486                                             (runFl ?
3487                                              FX2CMD_STREAMING_ON :
3488                                              FX2CMD_STREAMING_OFF));
3489                 if (ret) return ret;
3490                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
3491         default:
3492                 return -EINVAL;
3493         }
3494 }
3495
3496
3497 /* Evaluate whether or not state_pathway_ok can change */
3498 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
3499 {
3500         if (hdw->state_pathway_ok) {
3501                 /* Nothing to do if pathway is already ok */
3502                 return 0;
3503         }
3504         if (!hdw->state_pipeline_idle) {
3505                 /* Not allowed to change anything if pipeline is not idle */
3506                 return 0;
3507         }
3508         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
3509         hdw->state_pathway_ok = !0;
3510         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3511         return !0;
3512 }
3513
3514
3515 /* Evaluate whether or not state_encoder_ok can change */
3516 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
3517 {
3518         if (hdw->state_encoder_ok) return 0;
3519         if (hdw->flag_tripped) return 0;
3520         if (hdw->state_encoder_run) return 0;
3521         if (hdw->state_encoder_config) return 0;
3522         if (hdw->state_decoder_run) return 0;
3523         if (hdw->state_usbstream_run) return 0;
3524         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
3525                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
3526         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
3527                 return 0;
3528         }
3529
3530         if (pvr2_upload_firmware2(hdw) < 0) {
3531                 hdw->flag_tripped = !0;
3532                 trace_stbit("flag_tripped",hdw->flag_tripped);
3533                 return !0;
3534         }
3535         hdw->state_encoder_ok = !0;
3536         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
3537         return !0;
3538 }
3539
3540
3541 /* Evaluate whether or not state_encoder_config can change */
3542 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
3543 {
3544         if (hdw->state_encoder_config) {
3545                 if (hdw->state_encoder_ok) {
3546                         if (hdw->state_pipeline_req &&
3547                             !hdw->state_pipeline_pause) return 0;
3548                 }
3549                 hdw->state_encoder_config = 0;
3550                 hdw->state_encoder_waitok = 0;
3551                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3552                 /* paranoia - solve race if timer just completed */
3553                 del_timer_sync(&hdw->encoder_wait_timer);
3554         } else {
3555                 if (!hdw->state_pathway_ok ||
3556                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3557                     !hdw->state_encoder_ok ||
3558                     !hdw->state_pipeline_idle ||
3559                     hdw->state_pipeline_pause ||
3560                     !hdw->state_pipeline_req ||
3561                     !hdw->state_pipeline_config) {
3562                         /* We must reset the enforced wait interval if
3563                            anything has happened that might have disturbed
3564                            the encoder.  This should be a rare case. */
3565                         if (timer_pending(&hdw->encoder_wait_timer)) {
3566                                 del_timer_sync(&hdw->encoder_wait_timer);
3567                         }
3568                         if (hdw->state_encoder_waitok) {
3569                                 /* Must clear the state - therefore we did
3570                                    something to a state bit and must also
3571                                    return true. */
3572                                 hdw->state_encoder_waitok = 0;
3573                                 trace_stbit("state_encoder_waitok",
3574                                             hdw->state_encoder_waitok);
3575                                 return !0;
3576                         }
3577                         return 0;
3578                 }
3579                 if (!hdw->state_encoder_waitok) {
3580                         if (!timer_pending(&hdw->encoder_wait_timer)) {
3581                                 /* waitok flag wasn't set and timer isn't
3582                                    running.  Check flag once more to avoid
3583                                    a race then start the timer.  This is
3584                                    the point when we measure out a minimal
3585                                    quiet interval before doing something to
3586                                    the encoder. */
3587                                 if (!hdw->state_encoder_waitok) {
3588                                         hdw->encoder_wait_timer.expires =
3589                                                 jiffies + (HZ*50/1000);
3590                                         add_timer(&hdw->encoder_wait_timer);
3591                                 }
3592                         }
3593                         /* We can't continue until we know we have been
3594                            quiet for the interval measured by this
3595                            timer. */
3596                         return 0;
3597                 }
3598                 pvr2_encoder_configure(hdw);
3599                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
3600         }
3601         trace_stbit("state_encoder_config",hdw->state_encoder_config);
3602         return !0;
3603 }
3604
3605
3606 /* Return true if the encoder should not be running. */
3607 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
3608 {
3609         if (!hdw->state_encoder_ok) {
3610                 /* Encoder isn't healthy at the moment, so stop it. */
3611                 return !0;
3612         }
3613         if (!hdw->state_pathway_ok) {
3614                 /* Mode is not understood at the moment (i.e. it wants to
3615                    change), so encoder must be stopped. */
3616                 return !0;
3617         }
3618
3619         switch (hdw->pathway_state) {
3620         case PVR2_PATHWAY_ANALOG:
3621                 if (!hdw->state_decoder_run) {
3622                         /* We're in analog mode and the decoder is not
3623                            running; thus the encoder should be stopped as
3624                            well. */
3625                         return !0;
3626                 }
3627                 break;
3628         case PVR2_PATHWAY_DIGITAL:
3629                 if (hdw->state_encoder_runok) {
3630                         /* This is a funny case.  We're in digital mode so
3631                            really the encoder should be stopped.  However
3632                            if it really is running, only kill it after
3633                            runok has been set.  This gives a chance for the
3634                            onair quirk to function (encoder must run
3635                            briefly first, at least once, before onair
3636                            digital streaming can work). */
3637                         return !0;
3638                 }
3639                 break;
3640         default:
3641                 /* Unknown mode; so encoder should be stopped. */
3642                 return !0;
3643         }
3644
3645         /* If we get here, we haven't found a reason to stop the
3646            encoder. */
3647         return 0;
3648 }
3649
3650
3651 /* Return true if the encoder should be running. */
3652 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
3653 {
3654         if (!hdw->state_encoder_ok) {
3655                 /* Don't run the encoder if it isn't healthy... */
3656                 return 0;
3657         }
3658         if (!hdw->state_pathway_ok) {
3659                 /* Don't run the encoder if we don't (yet) know what mode
3660                    we need to be in... */
3661                 return 0;
3662         }
3663
3664         switch (hdw->pathway_state) {
3665         case PVR2_PATHWAY_ANALOG:
3666                 if (hdw->state_decoder_run) {
3667                         /* In analog mode, if the decoder is running, then
3668                            run the encoder. */
3669                         return !0;
3670                 }
3671                 break;
3672         case PVR2_PATHWAY_DIGITAL:
3673                 if ((hdw->hdw_desc->digital_control_scheme ==
3674                      PVR2_DIGITAL_SCHEME_ONAIR) &&
3675                     !hdw->state_encoder_runok) {
3676                         /* This is a quirk.  OnAir hardware won't stream
3677                            digital until the encoder has been run at least
3678                            once, for a minimal period of time (empiricially
3679                            measured to be 1/4 second).  So if we're on
3680                            OnAir hardware and the encoder has never been
3681                            run at all, then start the encoder.  Normal
3682                            state machine logic in the driver will
3683                            automatically handle the remaining bits. */
3684                         return !0;
3685                 }
3686                 break;
3687         default:
3688                 /* For completeness (unknown mode; encoder won't run ever) */
3689                 break;
3690         }
3691         /* If we get here, then we haven't found any reason to run the
3692            encoder, so don't run it. */
3693         return 0;
3694 }
3695
3696
3697 /* Evaluate whether or not state_encoder_run can change */
3698 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
3699 {
3700         if (hdw->state_encoder_run) {
3701                 if (!state_check_disable_encoder_run(hdw)) return 0;
3702                 if (hdw->state_encoder_ok) {
3703                         del_timer_sync(&hdw->encoder_run_timer);
3704                         if (pvr2_encoder_stop(hdw) < 0) return !0;
3705                 }
3706                 hdw->state_encoder_run = 0;
3707         } else {
3708                 if (!state_check_enable_encoder_run(hdw)) return 0;
3709                 if (pvr2_encoder_start(hdw) < 0) return !0;
3710                 hdw->state_encoder_run = !0;
3711                 if (!hdw->state_encoder_runok) {
3712                         hdw->encoder_run_timer.expires =
3713                                 jiffies + (HZ*250/1000);
3714                         add_timer(&hdw->encoder_run_timer);
3715                 }
3716         }
3717         trace_stbit("state_encoder_run",hdw->state_encoder_run);
3718         return !0;
3719 }
3720
3721
3722 /* Timeout function for quiescent timer. */
3723 static void pvr2_hdw_quiescent_timeout(unsigned long data)
3724 {
3725         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3726         hdw->state_decoder_quiescent = !0;
3727         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3728         hdw->state_stale = !0;
3729         queue_work(hdw->workqueue,&hdw->workpoll);
3730 }
3731
3732
3733 /* Timeout function for encoder wait timer. */
3734 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
3735 {
3736         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3737         hdw->state_encoder_waitok = !0;
3738         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3739         hdw->state_stale = !0;
3740         queue_work(hdw->workqueue,&hdw->workpoll);
3741 }
3742
3743
3744 /* Timeout function for encoder run timer. */
3745 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
3746 {
3747         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3748         if (!hdw->state_encoder_runok) {
3749                 hdw->state_encoder_runok = !0;
3750                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
3751                 hdw->state_stale = !0;
3752                 queue_work(hdw->workqueue,&hdw->workpoll);
3753         }
3754 }
3755
3756
3757 /* Evaluate whether or not state_decoder_run can change */
3758 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
3759 {
3760         if (hdw->state_decoder_run) {
3761                 if (hdw->state_encoder_ok) {
3762                         if (hdw->state_pipeline_req &&
3763                             !hdw->state_pipeline_pause &&
3764                             hdw->state_pathway_ok) return 0;
3765                 }
3766                 if (!hdw->flag_decoder_missed) {
3767                         pvr2_decoder_enable(hdw,0);
3768                 }
3769                 hdw->state_decoder_quiescent = 0;
3770                 hdw->state_decoder_run = 0;
3771                 /* paranoia - solve race if timer just completed */
3772                 del_timer_sync(&hdw->quiescent_timer);
3773         } else {
3774                 if (!hdw->state_decoder_quiescent) {
3775                         if (!timer_pending(&hdw->quiescent_timer)) {
3776                                 /* We don't do something about the
3777                                    quiescent timer until right here because
3778                                    we also want to catch cases where the
3779                                    decoder was already not running (like
3780                                    after initialization) as opposed to
3781                                    knowing that we had just stopped it.
3782                                    The second flag check is here to cover a
3783                                    race - the timer could have run and set
3784                                    this flag just after the previous check
3785                                    but before we did the pending check. */
3786                                 if (!hdw->state_decoder_quiescent) {
3787                                         hdw->quiescent_timer.expires =
3788                                                 jiffies + (HZ*50/1000);
3789                                         add_timer(&hdw->quiescent_timer);
3790                                 }
3791                         }
3792                         /* Don't allow decoder to start again until it has
3793                            been quiesced first.  This little detail should
3794                            hopefully further stabilize the encoder. */
3795                         return 0;
3796                 }
3797                 if (!hdw->state_pathway_ok ||
3798                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3799                     !hdw->state_pipeline_req ||
3800                     hdw->state_pipeline_pause ||
3801                     !hdw->state_pipeline_config ||
3802                     !hdw->state_encoder_config ||
3803                     !hdw->state_encoder_ok) return 0;
3804                 del_timer_sync(&hdw->quiescent_timer);
3805                 if (hdw->flag_decoder_missed) return 0;
3806                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
3807                 hdw->state_decoder_quiescent = 0;
3808                 hdw->state_decoder_run = !0;
3809         }
3810         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3811         trace_stbit("state_decoder_run",hdw->state_decoder_run);
3812         return !0;
3813 }
3814
3815
3816 /* Evaluate whether or not state_usbstream_run can change */
3817 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
3818 {
3819         if (hdw->state_usbstream_run) {
3820                 int fl = !0;
3821                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3822                         fl = (hdw->state_encoder_ok &&
3823                               hdw->state_encoder_run);
3824                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
3825                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
3826                         fl = hdw->state_encoder_ok;
3827                 }
3828                 if (fl &&
3829                     hdw->state_pipeline_req &&
3830                     !hdw->state_pipeline_pause &&
3831                     hdw->state_pathway_ok) {
3832                         return 0;
3833                 }
3834                 pvr2_hdw_cmd_usbstream(hdw,0);
3835                 hdw->state_usbstream_run = 0;
3836         } else {
3837                 if (!hdw->state_pipeline_req ||
3838                     hdw->state_pipeline_pause ||
3839                     !hdw->state_pathway_ok) return 0;
3840                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3841                         if (!hdw->state_encoder_ok ||
3842                             !hdw->state_encoder_run) return 0;
3843                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
3844                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
3845                         if (!hdw->state_encoder_ok) return 0;
3846                         if (hdw->state_encoder_run) return 0;
3847                         if (hdw->hdw_desc->digital_control_scheme ==
3848                             PVR2_DIGITAL_SCHEME_ONAIR) {
3849                                 /* OnAir digital receivers won't stream
3850                                    unless the analog encoder has run first.
3851                                    Why?  I have no idea.  But don't even
3852                                    try until we know the analog side is
3853                                    known to have run. */
3854                                 if (!hdw->state_encoder_runok) return 0;
3855                         }
3856                 }
3857                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
3858                 hdw->state_usbstream_run = !0;
3859         }
3860         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
3861         return !0;
3862 }
3863
3864
3865 /* Attempt to configure pipeline, if needed */
3866 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
3867 {
3868         if (hdw->state_pipeline_config ||
3869             hdw->state_pipeline_pause) return 0;
3870         pvr2_hdw_commit_execute(hdw);
3871         return !0;
3872 }
3873
3874
3875 /* Update pipeline idle and pipeline pause tracking states based on other
3876    inputs.  This must be called whenever the other relevant inputs have
3877    changed. */
3878 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
3879 {
3880         unsigned int st;
3881         int updatedFl = 0;
3882         /* Update pipeline state */
3883         st = !(hdw->state_encoder_run ||
3884                hdw->state_decoder_run ||
3885                hdw->state_usbstream_run ||
3886                (!hdw->state_decoder_quiescent));
3887         if (!st != !hdw->state_pipeline_idle) {
3888                 hdw->state_pipeline_idle = st;
3889                 updatedFl = !0;
3890         }
3891         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
3892                 hdw->state_pipeline_pause = 0;
3893                 updatedFl = !0;
3894         }
3895         return updatedFl;
3896 }
3897
3898
3899 typedef int (*state_eval_func)(struct pvr2_hdw *);
3900
3901 /* Set of functions to be run to evaluate various states in the driver. */
3902 static const state_eval_func eval_funcs[] = {
3903         state_eval_pathway_ok,
3904         state_eval_pipeline_config,
3905         state_eval_encoder_ok,
3906         state_eval_encoder_config,
3907         state_eval_decoder_run,
3908         state_eval_encoder_run,
3909         state_eval_usbstream_run,
3910 };
3911
3912
3913 /* Process various states and return true if we did anything interesting. */
3914 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
3915 {
3916         unsigned int i;
3917         int state_updated = 0;
3918         int check_flag;
3919
3920         if (!hdw->state_stale) return 0;
3921         if ((hdw->fw1_state != FW1_STATE_OK) ||
3922             !hdw->flag_ok) {
3923                 hdw->state_stale = 0;
3924                 return !0;
3925         }
3926         /* This loop is the heart of the entire driver.  It keeps trying to
3927            evaluate various bits of driver state until nothing changes for
3928            one full iteration.  Each "bit of state" tracks some global
3929            aspect of the driver, e.g. whether decoder should run, if
3930            pipeline is configured, usb streaming is on, etc.  We separately
3931            evaluate each of those questions based on other driver state to
3932            arrive at the correct running configuration. */
3933         do {
3934                 check_flag = 0;
3935                 state_update_pipeline_state(hdw);
3936                 /* Iterate over each bit of state */
3937                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
3938                         if ((*eval_funcs[i])(hdw)) {
3939                                 check_flag = !0;
3940                                 state_updated = !0;
3941                                 state_update_pipeline_state(hdw);
3942                         }
3943                 }
3944         } while (check_flag && hdw->flag_ok);
3945         hdw->state_stale = 0;
3946         trace_stbit("state_stale",hdw->state_stale);
3947         return state_updated;
3948 }
3949
3950
3951 static const char *pvr2_pathway_state_name(int id)
3952 {
3953         switch (id) {
3954         case PVR2_PATHWAY_ANALOG: return "analog";
3955         case PVR2_PATHWAY_DIGITAL: return "digital";
3956         default: return "unknown";
3957         }
3958 }
3959
3960
3961 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
3962                                              char *buf,unsigned int acnt)
3963 {
3964         switch (which) {
3965         case 0:
3966                 return scnprintf(
3967                         buf,acnt,
3968                         "driver:%s%s%s%s%s <mode=%s>",
3969                         (hdw->flag_ok ? " <ok>" : " <fail>"),
3970                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
3971                         (hdw->flag_disconnected ? " <disconnected>" :
3972                          " <connected>"),
3973                         (hdw->flag_tripped ? " <tripped>" : ""),
3974                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
3975                         pvr2_pathway_state_name(hdw->pathway_state));
3976
3977         case 1:
3978                 return scnprintf(
3979                         buf,acnt,
3980                         "pipeline:%s%s%s%s",
3981                         (hdw->state_pipeline_idle ? " <idle>" : ""),
3982                         (hdw->state_pipeline_config ?
3983                          " <configok>" : " <stale>"),
3984                         (hdw->state_pipeline_req ? " <req>" : ""),
3985                         (hdw->state_pipeline_pause ? " <pause>" : ""));
3986         case 2:
3987                 return scnprintf(
3988                         buf,acnt,
3989                         "worker:%s%s%s%s%s%s%s",
3990                         (hdw->state_decoder_run ?
3991                          " <decode:run>" :
3992                          (hdw->state_decoder_quiescent ?
3993                           "" : " <decode:stop>")),
3994                         (hdw->state_decoder_quiescent ?
3995                          " <decode:quiescent>" : ""),
3996                         (hdw->state_encoder_ok ?
3997                          "" : " <encode:init>"),
3998                         (hdw->state_encoder_run ?
3999                          (hdw->state_encoder_runok ?
4000                           " <encode:run>" :
4001                           " <encode:firstrun>") :
4002                          (hdw->state_encoder_runok ?
4003                           " <encode:stop>" :
4004                           " <encode:virgin>")),
4005                         (hdw->state_encoder_config ?
4006                          " <encode:configok>" :
4007                          (hdw->state_encoder_waitok ?
4008                           "" : " <encode:waitok>")),
4009                         (hdw->state_usbstream_run ?
4010                          " <usb:run>" : " <usb:stop>"),
4011                         (hdw->state_pathway_ok ?
4012                          " <pathway:ok>" : ""));
4013         case 3:
4014                 return scnprintf(
4015                         buf,acnt,
4016                         "state: %s",
4017                         pvr2_get_state_name(hdw->master_state));
4018         case 4: {
4019                 struct pvr2_stream_stats stats;
4020                 if (!hdw->vid_stream) break;
4021                 pvr2_stream_get_stats(hdw->vid_stream,
4022                                       &stats,
4023                                       0);
4024                 return scnprintf(
4025                         buf,acnt,
4026                         "Bytes streamed=%u"
4027                         " URBs: queued=%u idle=%u ready=%u"
4028                         " processed=%u failed=%u",
4029                         stats.bytes_processed,
4030                         stats.buffers_in_queue,
4031                         stats.buffers_in_idle,
4032                         stats.buffers_in_ready,
4033                         stats.buffers_processed,
4034                         stats.buffers_failed);
4035         }
4036         default: break;
4037         }
4038         return 0;
4039 }
4040
4041
4042 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4043                                    char *buf,unsigned int acnt)
4044 {
4045         unsigned int bcnt,ccnt,idx;
4046         bcnt = 0;
4047         LOCK_TAKE(hdw->big_lock);
4048         for (idx = 0; ; idx++) {
4049                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4050                 if (!ccnt) break;
4051                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4052                 if (!acnt) break;
4053                 buf[0] = '\n'; ccnt = 1;
4054                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4055         }
4056         LOCK_GIVE(hdw->big_lock);
4057         return bcnt;
4058 }
4059
4060
4061 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4062 {
4063         char buf[128];
4064         unsigned int idx,ccnt;
4065
4066         for (idx = 0; ; idx++) {
4067                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4068                 if (!ccnt) break;
4069                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4070         }
4071 }
4072
4073
4074 /* Evaluate and update the driver's current state, taking various actions
4075    as appropriate for the update. */
4076 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4077 {
4078         unsigned int st;
4079         int state_updated = 0;
4080         int callback_flag = 0;
4081         int analog_mode;
4082
4083         pvr2_trace(PVR2_TRACE_STBITS,
4084                    "Drive state check START");
4085         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4086                 pvr2_hdw_state_log_state(hdw);
4087         }
4088
4089         /* Process all state and get back over disposition */
4090         state_updated = pvr2_hdw_state_update(hdw);
4091
4092         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4093
4094         /* Update master state based upon all other states. */
4095         if (!hdw->flag_ok) {
4096                 st = PVR2_STATE_DEAD;
4097         } else if (hdw->fw1_state != FW1_STATE_OK) {
4098                 st = PVR2_STATE_COLD;
4099         } else if ((analog_mode ||
4100                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4101                    !hdw->state_encoder_ok) {
4102                 st = PVR2_STATE_WARM;
4103         } else if (hdw->flag_tripped ||
4104                    (analog_mode && hdw->flag_decoder_missed)) {
4105                 st = PVR2_STATE_ERROR;
4106         } else if (hdw->state_usbstream_run &&
4107                    (!analog_mode ||
4108                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4109                 st = PVR2_STATE_RUN;
4110         } else {
4111                 st = PVR2_STATE_READY;
4112         }
4113         if (hdw->master_state != st) {
4114                 pvr2_trace(PVR2_TRACE_STATE,
4115                            "Device state change from %s to %s",
4116                            pvr2_get_state_name(hdw->master_state),
4117                            pvr2_get_state_name(st));
4118                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4119                 hdw->master_state = st;
4120                 state_updated = !0;
4121                 callback_flag = !0;
4122         }
4123         if (state_updated) {
4124                 /* Trigger anyone waiting on any state changes here. */
4125                 wake_up(&hdw->state_wait_data);
4126         }
4127
4128         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4129                 pvr2_hdw_state_log_state(hdw);
4130         }
4131         pvr2_trace(PVR2_TRACE_STBITS,
4132                    "Drive state check DONE callback=%d",callback_flag);
4133
4134         return callback_flag;
4135 }
4136
4137
4138 /* Cause kernel thread to check / update driver state */
4139 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4140 {
4141         if (hdw->state_stale) return;
4142         hdw->state_stale = !0;
4143         trace_stbit("state_stale",hdw->state_stale);
4144         queue_work(hdw->workqueue,&hdw->workpoll);
4145 }
4146
4147
4148 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4149 {
4150         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4151 }
4152
4153
4154 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4155 {
4156         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4157 }
4158
4159
4160 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4161 {
4162         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4163 }
4164
4165
4166 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4167 {
4168         u32 cval,nval;
4169         int ret;
4170         if (~msk) {
4171                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4172                 if (ret) return ret;
4173                 nval = (cval & ~msk) | (val & msk);
4174                 pvr2_trace(PVR2_TRACE_GPIO,
4175                            "GPIO direction changing 0x%x:0x%x"
4176                            " from 0x%x to 0x%x",
4177                            msk,val,cval,nval);
4178         } else {
4179                 nval = val;
4180                 pvr2_trace(PVR2_TRACE_GPIO,
4181                            "GPIO direction changing to 0x%x",nval);
4182         }
4183         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4184 }
4185
4186
4187 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4188 {
4189         u32 cval,nval;
4190         int ret;
4191         if (~msk) {
4192                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
4193                 if (ret) return ret;
4194                 nval = (cval & ~msk) | (val & msk);
4195                 pvr2_trace(PVR2_TRACE_GPIO,
4196                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
4197                            msk,val,cval,nval);
4198         } else {
4199                 nval = val;
4200                 pvr2_trace(PVR2_TRACE_GPIO,
4201                            "GPIO output changing to 0x%x",nval);
4202         }
4203         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
4204 }
4205
4206
4207 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
4208 {
4209         return hdw->input_avail_mask;
4210 }
4211
4212
4213 /* Find I2C address of eeprom */
4214 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
4215 {
4216         int result;
4217         LOCK_TAKE(hdw->ctl_lock); do {
4218                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
4219                 result = pvr2_send_request(hdw,
4220                                            hdw->cmd_buffer,1,
4221                                            hdw->cmd_buffer,1);
4222                 if (result < 0) break;
4223                 result = hdw->cmd_buffer[0];
4224         } while(0); LOCK_GIVE(hdw->ctl_lock);
4225         return result;
4226 }
4227
4228
4229 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
4230                              u32 match_type, u32 match_chip, u64 reg_id,
4231                              int setFl,u64 *val_ptr)
4232 {
4233 #ifdef CONFIG_VIDEO_ADV_DEBUG
4234         struct pvr2_i2c_client *cp;
4235         struct v4l2_register req;
4236         int stat = 0;
4237         int okFl = 0;
4238
4239         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
4240
4241         req.match_type = match_type;
4242         req.match_chip = match_chip;
4243         req.reg = reg_id;
4244         if (setFl) req.val = *val_ptr;
4245         mutex_lock(&hdw->i2c_list_lock); do {
4246                 list_for_each_entry(cp, &hdw->i2c_clients, list) {
4247                         if (!v4l2_chip_match_i2c_client(
4248                                     cp->client,
4249                                     req.match_type, req.match_chip)) {
4250                                 continue;
4251                         }
4252                         stat = pvr2_i2c_client_cmd(
4253                                 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
4254                                     VIDIOC_DBG_G_REGISTER),&req);
4255                         if (!setFl) *val_ptr = req.val;
4256                         okFl = !0;
4257                         break;
4258                 }
4259         } while (0); mutex_unlock(&hdw->i2c_list_lock);
4260         if (okFl) {
4261                 return stat;
4262         }
4263         return -EINVAL;
4264 #else
4265         return -ENOSYS;
4266 #endif
4267 }
4268
4269
4270 /*
4271   Stuff for Emacs to see, in order to encourage consistent editing style:
4272   *** Local Variables: ***
4273   *** mode: c ***
4274   *** fill-column: 75 ***
4275   *** tab-width: 8 ***
4276   *** c-basic-offset: 8 ***
4277   *** End: ***
4278   */