SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *  $Id$
   4  *
   5  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  *
  20  */
  21
  22 #include <linux/errno.h>
  23 #include <linux/string.h>
  24 #include <linux/slab.h>
  25 #include <linux/firmware.h>
  26 #include <linux/videodev2.h>
  27 #include <media/v4l2-common.h>
  28 #include <asm/semaphore.h>
  29 #include "pvrusb2.h"
  30 #include "pvrusb2-std.h"
  31 #include "pvrusb2-util.h"
  32 #include "pvrusb2-hdw.h"
  33 #include "pvrusb2-i2c-core.h"
  34 #include "pvrusb2-tuner.h"
  35 #include "pvrusb2-eeprom.h"
  36 #include "pvrusb2-hdw-internal.h"
  37 #include "pvrusb2-encoder.h"
  38 #include "pvrusb2-debug.h"
  39 #include "pvrusb2-fx2-cmd.h"
  40
  41 #define TV_MIN_FREQ     55250000L
  42 #define TV_MAX_FREQ    850000000L
  43
  44 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  45 static DEFINE_MUTEX(pvr2_unit_mtx);
  46
  47 static int ctlchg = 0;
  48 static int initusbreset = 1;
  49 static int procreload = 0;
  50 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  51 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  52 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  53 static int init_pause_msec = 0;
  54
  55 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  56 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  57 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  58 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  59 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
  60 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
  61 module_param(procreload, int, S_IRUGO|S_IWUSR);
  62 MODULE_PARM_DESC(procreload,
  63                  "Attempt init failure recovery with firmware reload");
  64 module_param_array(tuner,    int, NULL, 0444);
  65 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  66 module_param_array(video_std,    int, NULL, 0444);
  67 MODULE_PARM_DESC(video_std,"specify initial video standard");
  68 module_param_array(tolerance,    int, NULL, 0444);
  69 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  70
  71 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  72 #define PVR2_CTL_READ_ENDPOINT   0x81
  73
  74 #define PVR2_GPIO_IN 0x9008
  75 #define PVR2_GPIO_OUT 0x900c
  76 #define PVR2_GPIO_DIR 0x9020
  77
  78 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
  79
  80 #define PVR2_FIRMWARE_ENDPOINT   0x02
  81
  82 /* size of a firmware chunk */
  83 #define FIRMWARE_CHUNK_SIZE 0x2000
  84
  85 /* Define the list of additional controls we'll dynamically construct based
  86    on query of the cx2341x module. */
  87 struct pvr2_mpeg_ids {
  88         const char *strid;
  89         int id;
  90 };
  91 static const struct pvr2_mpeg_ids mpeg_ids[] = {
  92         {
  93                 .strid = "audio_layer",
  94                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
  95         },{
  96                 .strid = "audio_bitrate",
  97                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
  98         },{
  99                 /* Already using audio_mode elsewhere :-( */
 100                 .strid = "mpeg_audio_mode",
 101                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 102         },{
 103                 .strid = "mpeg_audio_mode_extension",
 104                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 105         },{
 106                 .strid = "audio_emphasis",
 107                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 108         },{
 109                 .strid = "audio_crc",
 110                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 111         },{
 112                 .strid = "video_aspect",
 113                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 114         },{
 115                 .strid = "video_b_frames",
 116                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 117         },{
 118                 .strid = "video_gop_size",
 119                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 120         },{
 121                 .strid = "video_gop_closure",
 122                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 123         },{
 124                 .strid = "video_bitrate_mode",
 125                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 126         },{
 127                 .strid = "video_bitrate",
 128                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 129         },{
 130                 .strid = "video_bitrate_peak",
 131                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 132         },{
 133                 .strid = "video_temporal_decimation",
 134                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 135         },{
 136                 .strid = "stream_type",
 137                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 138         },{
 139                 .strid = "video_spatial_filter_mode",
 140                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 141         },{
 142                 .strid = "video_spatial_filter",
 143                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 144         },{
 145                 .strid = "video_luma_spatial_filter_type",
 146                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 147         },{
 148                 .strid = "video_chroma_spatial_filter_type",
 149                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 150         },{
 151                 .strid = "video_temporal_filter_mode",
 152                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 153         },{
 154                 .strid = "video_temporal_filter",
 155                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 156         },{
 157                 .strid = "video_median_filter_type",
 158                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 159         },{
 160                 .strid = "video_luma_median_filter_top",
 161                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 162         },{
 163                 .strid = "video_luma_median_filter_bottom",
 164                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 165         },{
 166                 .strid = "video_chroma_median_filter_top",
 167                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 168         },{
 169                 .strid = "video_chroma_median_filter_bottom",
 170                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 171         }
 172 };
 173 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 174
 175
 176 static const char *control_values_srate[] = {
 177         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 178         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 179         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 180 };
 181
 182
 183
 184 static const char *control_values_input[] = {
 185         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 186         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 187         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 188         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 189 };
 190
 191
 192 static const char *control_values_audiomode[] = {
 193         [V4L2_TUNER_MODE_MONO]   = "Mono",
 194         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 195         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 196         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 197         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 198 };
 199
 200
 201 static const char *control_values_hsm[] = {
 202         [PVR2_CVAL_HSM_FAIL] = "Fail",
 203         [PVR2_CVAL_HSM_HIGH] = "High",
 204         [PVR2_CVAL_HSM_FULL] = "Full",
 205 };
 206
 207
 208 static const char *pvr2_state_names[] = {
 209         [PVR2_STATE_NONE] =    "none",
 210         [PVR2_STATE_DEAD] =    "dead",
 211         [PVR2_STATE_COLD] =    "cold",
 212         [PVR2_STATE_WARM] =    "warm",
 213         [PVR2_STATE_ERROR] =   "error",
 214         [PVR2_STATE_READY] =   "ready",
 215         [PVR2_STATE_RUN] =     "run",
 216 };
 217
 218
 219 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 220 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 221 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 222 static void pvr2_hdw_worker_i2c(struct work_struct *work);
 223 static void pvr2_hdw_worker_poll(struct work_struct *work);
 224 static void pvr2_hdw_worker_init(struct work_struct *work);
 225 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 226 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 227 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 228 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 229 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 230 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 231 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 232 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 233 static void pvr2_hdw_quiescent_timeout(unsigned long);
 234 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 235 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 236                                 unsigned int timeout,int probe_fl,
 237                                 void *write_data,unsigned int write_len,
 238                                 void *read_data,unsigned int read_len);
 239
 240
 241 static void trace_stbit(const char *name,int val)
 242 {
 243         pvr2_trace(PVR2_TRACE_STBITS,
 244                    "State bit %s <-- %s",
 245                    name,(val ? "true" : "false"));
 246 }
 247
 248 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 249 {
 250         struct pvr2_hdw *hdw = cptr->hdw;
 251         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 252                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 253         } else {
 254                 *vp = 0;
 255         }
 256         return 0;
 257 }
 258
 259 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 260 {
 261         struct pvr2_hdw *hdw = cptr->hdw;
 262         unsigned int slotId = hdw->freqProgSlot;
 263         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 264                 hdw->freqTable[slotId-1] = v;
 265                 /* Handle side effects correctly - if we're tuned to this
 266                    slot, then forgot the slot id relation since the stored
 267                    frequency has been changed. */
 268                 if (hdw->freqSelector) {
 269                         if (hdw->freqSlotRadio == slotId) {
 270                                 hdw->freqSlotRadio = 0;
 271                         }
 272                 } else {
 273                         if (hdw->freqSlotTelevision == slotId) {
 274                                 hdw->freqSlotTelevision = 0;
 275                         }
 276                 }
 277         }
 278         return 0;
 279 }
 280
 281 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 282 {
 283         *vp = cptr->hdw->freqProgSlot;
 284         return 0;
 285 }
 286
 287 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 288 {
 289         struct pvr2_hdw *hdw = cptr->hdw;
 290         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 291                 hdw->freqProgSlot = v;
 292         }
 293         return 0;
 294 }
 295
 296 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 297 {
 298         struct pvr2_hdw *hdw = cptr->hdw;
 299         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 300         return 0;
 301 }
 302
 303 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 304 {
 305         unsigned freq = 0;
 306         struct pvr2_hdw *hdw = cptr->hdw;
 307         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 308         if (slotId > 0) {
 309                 freq = hdw->freqTable[slotId-1];
 310                 if (!freq) return 0;
 311                 pvr2_hdw_set_cur_freq(hdw,freq);
 312         }
 313         if (hdw->freqSelector) {
 314                 hdw->freqSlotRadio = slotId;
 315         } else {
 316                 hdw->freqSlotTelevision = slotId;
 317         }
 318         return 0;
 319 }
 320
 321 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 322 {
 323         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 324         return 0;
 325 }
 326
 327 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 328 {
 329         return cptr->hdw->freqDirty != 0;
 330 }
 331
 332 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 333 {
 334         cptr->hdw->freqDirty = 0;
 335 }
 336
 337 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 338 {
 339         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 340         return 0;
 341 }
 342
 343 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 344 {
 345         /* Actual maximum depends on the video standard in effect. */
 346         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 347                 *vp = 480;
 348         } else {
 349                 *vp = 576;
 350         }
 351         return 0;
 352 }
 353
 354 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 355 {
 356         /* Actual minimum depends on device digitizer type. */
 357         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 358                 *vp = 75;
 359         } else {
 360                 *vp = 17;
 361         }
 362         return 0;
 363 }
 364
 365 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 366 {
 367         *vp = cptr->hdw->input_val;
 368         return 0;
 369 }
 370
 371 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 372 {
 373         struct pvr2_hdw *hdw = cptr->hdw;
 374
 375         if (hdw->input_val != v) {
 376                 hdw->input_val = v;
 377                 hdw->input_dirty = !0;
 378         }
 379
 380         /* Handle side effects - if we switch to a mode that needs the RF
 381            tuner, then select the right frequency choice as well and mark
 382            it dirty. */
 383         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
 384                 hdw->freqSelector = 0;
 385                 hdw->freqDirty = !0;
 386         } else if (hdw->input_val == PVR2_CVAL_INPUT_TV) {
 387                 hdw->freqSelector = 1;
 388                 hdw->freqDirty = !0;
 389         }
 390         return 0;
 391 }
 392
 393 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 394 {
 395         return cptr->hdw->input_dirty != 0;
 396 }
 397
 398 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 399 {
 400         cptr->hdw->input_dirty = 0;
 401 }
 402
 403
 404 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 405 {
 406         unsigned long fv;
 407         struct pvr2_hdw *hdw = cptr->hdw;
 408         if (hdw->tuner_signal_stale) {
 409                 pvr2_i2c_core_status_poll(hdw);
 410         }
 411         fv = hdw->tuner_signal_info.rangehigh;
 412         if (!fv) {
 413                 /* Safety fallback */
 414                 *vp = TV_MAX_FREQ;
 415                 return 0;
 416         }
 417         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 418                 fv = (fv * 125) / 2;
 419         } else {
 420                 fv = fv * 62500;
 421         }
 422         *vp = fv;
 423         return 0;
 424 }
 425
 426 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 427 {
 428         unsigned long fv;
 429         struct pvr2_hdw *hdw = cptr->hdw;
 430         if (hdw->tuner_signal_stale) {
 431                 pvr2_i2c_core_status_poll(hdw);
 432         }
 433         fv = hdw->tuner_signal_info.rangelow;
 434         if (!fv) {
 435                 /* Safety fallback */
 436                 *vp = TV_MIN_FREQ;
 437                 return 0;
 438         }
 439         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 440                 fv = (fv * 125) / 2;
 441         } else {
 442                 fv = fv * 62500;
 443         }
 444         *vp = fv;
 445         return 0;
 446 }
 447
 448 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 449 {
 450         return cptr->hdw->enc_stale != 0;
 451 }
 452
 453 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 454 {
 455         cptr->hdw->enc_stale = 0;
 456         cptr->hdw->enc_unsafe_stale = 0;
 457 }
 458
 459 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 460 {
 461         int ret;
 462         struct v4l2_ext_controls cs;
 463         struct v4l2_ext_control c1;
 464         memset(&cs,0,sizeof(cs));
 465         memset(&c1,0,sizeof(c1));
 466         cs.controls = &c1;
 467         cs.count = 1;
 468         c1.id = cptr->info->v4l_id;
 469         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 470                                 VIDIOC_G_EXT_CTRLS);
 471         if (ret) return ret;
 472         *vp = c1.value;
 473         return 0;
 474 }
 475
 476 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 477 {
 478         int ret;
 479         struct pvr2_hdw *hdw = cptr->hdw;
 480         struct v4l2_ext_controls cs;
 481         struct v4l2_ext_control c1;
 482         memset(&cs,0,sizeof(cs));
 483         memset(&c1,0,sizeof(c1));
 484         cs.controls = &c1;
 485         cs.count = 1;
 486         c1.id = cptr->info->v4l_id;
 487         c1.value = v;
 488         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 489                                 hdw->state_encoder_run, &cs,
 490                                 VIDIOC_S_EXT_CTRLS);
 491         if (ret == -EBUSY) {
 492                 /* Oops.  cx2341x is telling us it's not safe to change
 493                    this control while we're capturing.  Make a note of this
 494                    fact so that the pipeline will be stopped the next time
 495                    controls are committed.  Then go on ahead and store this
 496                    change anyway. */
 497                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 498                                         0, &cs,
 499                                         VIDIOC_S_EXT_CTRLS);
 500                 if (!ret) hdw->enc_unsafe_stale = !0;
 501         }
 502         if (ret) return ret;
 503         hdw->enc_stale = !0;
 504         return 0;
 505 }
 506
 507 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 508 {
 509         struct v4l2_queryctrl qctrl;
 510         struct pvr2_ctl_info *info;
 511         qctrl.id = cptr->info->v4l_id;
 512         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 513         /* Strip out the const so we can adjust a function pointer.  It's
 514            OK to do this here because we know this is a dynamically created
 515            control, so the underlying storage for the info pointer is (a)
 516            private to us, and (b) not in read-only storage.  Either we do
 517            this or we significantly complicate the underlying control
 518            implementation. */
 519         info = (struct pvr2_ctl_info *)(cptr->info);
 520         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 521                 if (info->set_value) {
 522                         info->set_value = NULL;
 523                 }
 524         } else {
 525                 if (!(info->set_value)) {
 526                         info->set_value = ctrl_cx2341x_set;
 527                 }
 528         }
 529         return qctrl.flags;
 530 }
 531
 532 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 533 {
 534         *vp = cptr->hdw->state_pipeline_req;
 535         return 0;
 536 }
 537
 538 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 539 {
 540         *vp = cptr->hdw->master_state;
 541         return 0;
 542 }
 543
 544 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 545 {
 546         int result = pvr2_hdw_is_hsm(cptr->hdw);
 547         *vp = PVR2_CVAL_HSM_FULL;
 548         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 549         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 550         return 0;
 551 }
 552
 553 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 554 {
 555         *vp = cptr->hdw->std_mask_avail;
 556         return 0;
 557 }
 558
 559 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 560 {
 561         struct pvr2_hdw *hdw = cptr->hdw;
 562         v4l2_std_id ns;
 563         ns = hdw->std_mask_avail;
 564         ns = (ns & ~m) | (v & m);
 565         if (ns == hdw->std_mask_avail) return 0;
 566         hdw->std_mask_avail = ns;
 567         pvr2_hdw_internal_set_std_avail(hdw);
 568         pvr2_hdw_internal_find_stdenum(hdw);
 569         return 0;
 570 }
 571
 572 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 573                                char *bufPtr,unsigned int bufSize,
 574                                unsigned int *len)
 575 {
 576         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 577         return 0;
 578 }
 579
 580 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 581                                const char *bufPtr,unsigned int bufSize,
 582                                int *mskp,int *valp)
 583 {
 584         int ret;
 585         v4l2_std_id id;
 586         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 587         if (ret < 0) return ret;
 588         if (mskp) *mskp = id;
 589         if (valp) *valp = id;
 590         return 0;
 591 }
 592
 593 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 594 {
 595         *vp = cptr->hdw->std_mask_cur;
 596         return 0;
 597 }
 598
 599 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 600 {
 601         struct pvr2_hdw *hdw = cptr->hdw;
 602         v4l2_std_id ns;
 603         ns = hdw->std_mask_cur;
 604         ns = (ns & ~m) | (v & m);
 605         if (ns == hdw->std_mask_cur) return 0;
 606         hdw->std_mask_cur = ns;
 607         hdw->std_dirty = !0;
 608         pvr2_hdw_internal_find_stdenum(hdw);
 609         return 0;
 610 }
 611
 612 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 613 {
 614         return cptr->hdw->std_dirty != 0;
 615 }
 616
 617 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 618 {
 619         cptr->hdw->std_dirty = 0;
 620 }
 621
 622 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 623 {
 624         struct pvr2_hdw *hdw = cptr->hdw;
 625         pvr2_i2c_core_status_poll(hdw);
 626         *vp = hdw->tuner_signal_info.signal;
 627         return 0;
 628 }
 629
 630 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 631 {
 632         int val = 0;
 633         unsigned int subchan;
 634         struct pvr2_hdw *hdw = cptr->hdw;
 635         pvr2_i2c_core_status_poll(hdw);
 636         subchan = hdw->tuner_signal_info.rxsubchans;
 637         if (subchan & V4L2_TUNER_SUB_MONO) {
 638                 val |= (1 << V4L2_TUNER_MODE_MONO);
 639         }
 640         if (subchan & V4L2_TUNER_SUB_STEREO) {
 641                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 642         }
 643         if (subchan & V4L2_TUNER_SUB_LANG1) {
 644                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 645         }
 646         if (subchan & V4L2_TUNER_SUB_LANG2) {
 647                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 648         }
 649         *vp = val;
 650         return 0;
 651 }
 652
 653
 654 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 655 {
 656         struct pvr2_hdw *hdw = cptr->hdw;
 657         if (v < 0) return -EINVAL;
 658         if (v > hdw->std_enum_cnt) return -EINVAL;
 659         hdw->std_enum_cur = v;
 660         if (!v) return 0;
 661         v--;
 662         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 663         hdw->std_mask_cur = hdw->std_defs[v].id;
 664         hdw->std_dirty = !0;
 665         return 0;
 666 }
 667
 668
 669 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 670 {
 671         *vp = cptr->hdw->std_enum_cur;
 672         return 0;
 673 }
 674
 675
 676 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 677 {
 678         return cptr->hdw->std_dirty != 0;
 679 }
 680
 681
 682 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 683 {
 684         cptr->hdw->std_dirty = 0;
 685 }
 686
 687
 688 #define DEFINT(vmin,vmax) \
 689         .type = pvr2_ctl_int, \
 690         .def.type_int.min_value = vmin, \
 691         .def.type_int.max_value = vmax
 692
 693 #define DEFENUM(tab) \
 694         .type = pvr2_ctl_enum, \
 695         .def.type_enum.count = ARRAY_SIZE(tab), \
 696         .def.type_enum.value_names = tab
 697
 698 #define DEFBOOL \
 699         .type = pvr2_ctl_bool
 700
 701 #define DEFMASK(msk,tab) \
 702         .type = pvr2_ctl_bitmask, \
 703         .def.type_bitmask.valid_bits = msk, \
 704         .def.type_bitmask.bit_names = tab
 705
 706 #define DEFREF(vname) \
 707         .set_value = ctrl_set_##vname, \
 708         .get_value = ctrl_get_##vname, \
 709         .is_dirty = ctrl_isdirty_##vname, \
 710         .clear_dirty = ctrl_cleardirty_##vname
 711
 712
 713 #define VCREATE_FUNCS(vname) \
 714 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 715 {*vp = cptr->hdw->vname##_val; return 0;} \
 716 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 717 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 718 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 719 {return cptr->hdw->vname##_dirty != 0;} \
 720 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 721 {cptr->hdw->vname##_dirty = 0;}
 722
 723 VCREATE_FUNCS(brightness)
 724 VCREATE_FUNCS(contrast)
 725 VCREATE_FUNCS(saturation)
 726 VCREATE_FUNCS(hue)
 727 VCREATE_FUNCS(volume)
 728 VCREATE_FUNCS(balance)
 729 VCREATE_FUNCS(bass)
 730 VCREATE_FUNCS(treble)
 731 VCREATE_FUNCS(mute)
 732 VCREATE_FUNCS(audiomode)
 733 VCREATE_FUNCS(res_hor)
 734 VCREATE_FUNCS(res_ver)
 735 VCREATE_FUNCS(srate)
 736
 737 /* Table definition of all controls which can be manipulated */
 738 static const struct pvr2_ctl_info control_defs[] = {
 739         {
 740                 .v4l_id = V4L2_CID_BRIGHTNESS,
 741                 .desc = "Brightness",
 742                 .name = "brightness",
 743                 .default_value = 128,
 744                 DEFREF(brightness),
 745                 DEFINT(0,255),
 746         },{
 747                 .v4l_id = V4L2_CID_CONTRAST,
 748                 .desc = "Contrast",
 749                 .name = "contrast",
 750                 .default_value = 68,
 751                 DEFREF(contrast),
 752                 DEFINT(0,127),
 753         },{
 754                 .v4l_id = V4L2_CID_SATURATION,
 755                 .desc = "Saturation",
 756                 .name = "saturation",
 757                 .default_value = 64,
 758                 DEFREF(saturation),
 759                 DEFINT(0,127),
 760         },{
 761                 .v4l_id = V4L2_CID_HUE,
 762                 .desc = "Hue",
 763                 .name = "hue",
 764                 .default_value = 0,
 765                 DEFREF(hue),
 766                 DEFINT(-128,127),
 767         },{
 768                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
 769                 .desc = "Volume",
 770                 .name = "volume",
 771                 .default_value = 62000,
 772                 DEFREF(volume),
 773                 DEFINT(0,65535),
 774         },{
 775                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
 776                 .desc = "Balance",
 777                 .name = "balance",
 778                 .default_value = 0,
 779                 DEFREF(balance),
 780                 DEFINT(-32768,32767),
 781         },{
 782                 .v4l_id = V4L2_CID_AUDIO_BASS,
 783                 .desc = "Bass",
 784                 .name = "bass",
 785                 .default_value = 0,
 786                 DEFREF(bass),
 787                 DEFINT(-32768,32767),
 788         },{
 789                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
 790                 .desc = "Treble",
 791                 .name = "treble",
 792                 .default_value = 0,
 793                 DEFREF(treble),
 794                 DEFINT(-32768,32767),
 795         },{
 796                 .v4l_id = V4L2_CID_AUDIO_MUTE,
 797                 .desc = "Mute",
 798                 .name = "mute",
 799                 .default_value = 0,
 800                 DEFREF(mute),
 801                 DEFBOOL,
 802         },{
 803                 .desc = "Video Source",
 804                 .name = "input",
 805                 .internal_id = PVR2_CID_INPUT,
 806                 .default_value = PVR2_CVAL_INPUT_TV,
 807                 DEFREF(input),
 808                 DEFENUM(control_values_input),
 809         },{
 810                 .desc = "Audio Mode",
 811                 .name = "audio_mode",
 812                 .internal_id = PVR2_CID_AUDIOMODE,
 813                 .default_value = V4L2_TUNER_MODE_STEREO,
 814                 DEFREF(audiomode),
 815                 DEFENUM(control_values_audiomode),
 816         },{
 817                 .desc = "Horizontal capture resolution",
 818                 .name = "resolution_hor",
 819                 .internal_id = PVR2_CID_HRES,
 820                 .default_value = 720,
 821                 DEFREF(res_hor),
 822                 DEFINT(19,720),
 823         },{
 824                 .desc = "Vertical capture resolution",
 825                 .name = "resolution_ver",
 826                 .internal_id = PVR2_CID_VRES,
 827                 .default_value = 480,
 828                 DEFREF(res_ver),
 829                 DEFINT(17,576),
 830                 /* Hook in check for video standard and adjust maximum
 831                    depending on the standard. */
 832                 .get_max_value = ctrl_vres_max_get,
 833                 .get_min_value = ctrl_vres_min_get,
 834         },{
 835                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
 836                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
 837                 .desc = "Audio Sampling Frequency",
 838                 .name = "srate",
 839                 DEFREF(srate),
 840                 DEFENUM(control_values_srate),
 841         },{
 842                 .desc = "Tuner Frequency (Hz)",
 843                 .name = "frequency",
 844                 .internal_id = PVR2_CID_FREQUENCY,
 845                 .default_value = 0,
 846                 .set_value = ctrl_freq_set,
 847                 .get_value = ctrl_freq_get,
 848                 .is_dirty = ctrl_freq_is_dirty,
 849                 .clear_dirty = ctrl_freq_clear_dirty,
 850                 DEFINT(0,0),
 851                 /* Hook in check for input value (tv/radio) and adjust
 852                    max/min values accordingly */
 853                 .get_max_value = ctrl_freq_max_get,
 854                 .get_min_value = ctrl_freq_min_get,
 855         },{
 856                 .desc = "Channel",
 857                 .name = "channel",
 858                 .set_value = ctrl_channel_set,
 859                 .get_value = ctrl_channel_get,
 860                 DEFINT(0,FREQTABLE_SIZE),
 861         },{
 862                 .desc = "Channel Program Frequency",
 863                 .name = "freq_table_value",
 864                 .set_value = ctrl_channelfreq_set,
 865                 .get_value = ctrl_channelfreq_get,
 866                 DEFINT(0,0),
 867                 /* Hook in check for input value (tv/radio) and adjust
 868                    max/min values accordingly */
 869                 .get_max_value = ctrl_freq_max_get,
 870                 .get_min_value = ctrl_freq_min_get,
 871         },{
 872                 .desc = "Channel Program ID",
 873                 .name = "freq_table_channel",
 874                 .set_value = ctrl_channelprog_set,
 875                 .get_value = ctrl_channelprog_get,
 876                 DEFINT(0,FREQTABLE_SIZE),
 877         },{
 878                 .desc = "Streaming Enabled",
 879                 .name = "streaming_enabled",
 880                 .get_value = ctrl_streamingenabled_get,
 881                 DEFBOOL,
 882         },{
 883                 .desc = "USB Speed",
 884                 .name = "usb_speed",
 885                 .get_value = ctrl_hsm_get,
 886                 DEFENUM(control_values_hsm),
 887         },{
 888                 .desc = "Master State",
 889                 .name = "master_state",
 890                 .get_value = ctrl_masterstate_get,
 891                 DEFENUM(pvr2_state_names),
 892         },{
 893                 .desc = "Signal Present",
 894                 .name = "signal_present",
 895                 .get_value = ctrl_signal_get,
 896                 DEFINT(0,65535),
 897         },{
 898                 .desc = "Audio Modes Present",
 899                 .name = "audio_modes_present",
 900                 .get_value = ctrl_audio_modes_present_get,
 901                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
 902                    v4l.  Nothing outside of this module cares about this,
 903                    but I reuse it in order to also reuse the
 904                    control_values_audiomode string table. */
 905                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
 906                          (1 << V4L2_TUNER_MODE_STEREO)|
 907                          (1 << V4L2_TUNER_MODE_LANG1)|
 908                          (1 << V4L2_TUNER_MODE_LANG2)),
 909                         control_values_audiomode),
 910         },{
 911                 .desc = "Video Standards Available Mask",
 912                 .name = "video_standard_mask_available",
 913                 .internal_id = PVR2_CID_STDAVAIL,
 914                 .skip_init = !0,
 915                 .get_value = ctrl_stdavail_get,
 916                 .set_value = ctrl_stdavail_set,
 917                 .val_to_sym = ctrl_std_val_to_sym,
 918                 .sym_to_val = ctrl_std_sym_to_val,
 919                 .type = pvr2_ctl_bitmask,
 920         },{
 921                 .desc = "Video Standards In Use Mask",
 922                 .name = "video_standard_mask_active",
 923                 .internal_id = PVR2_CID_STDCUR,
 924                 .skip_init = !0,
 925                 .get_value = ctrl_stdcur_get,
 926                 .set_value = ctrl_stdcur_set,
 927                 .is_dirty = ctrl_stdcur_is_dirty,
 928                 .clear_dirty = ctrl_stdcur_clear_dirty,
 929                 .val_to_sym = ctrl_std_val_to_sym,
 930                 .sym_to_val = ctrl_std_sym_to_val,
 931                 .type = pvr2_ctl_bitmask,
 932         },{
 933                 .desc = "Video Standard Name",
 934                 .name = "video_standard",
 935                 .internal_id = PVR2_CID_STDENUM,
 936                 .skip_init = !0,
 937                 .get_value = ctrl_stdenumcur_get,
 938                 .set_value = ctrl_stdenumcur_set,
 939                 .is_dirty = ctrl_stdenumcur_is_dirty,
 940                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
 941                 .type = pvr2_ctl_enum,
 942         }
 943 };
 944
 945 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
 946
 947
 948 const char *pvr2_config_get_name(enum pvr2_config cfg)
 949 {
 950         switch (cfg) {
 951         case pvr2_config_empty: return "empty";
 952         case pvr2_config_mpeg: return "mpeg";
 953         case pvr2_config_vbi: return "vbi";
 954         case pvr2_config_pcm: return "pcm";
 955         case pvr2_config_rawvideo: return "raw video";
 956         }
 957         return "<unknown>";
 958 }
 959
 960
 961 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
 962 {
 963         return hdw->usb_dev;
 964 }
 965
 966
 967 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
 968 {
 969         return hdw->serial_number;
 970 }
 971
 972
 973 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
 974 {
 975         return hdw->bus_info;
 976 }
 977
 978
 979 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
 980 {
 981         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
 982 }
 983
 984 /* Set the currently tuned frequency and account for all possible
 985    driver-core side effects of this action. */
 986 void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
 987 {
 988         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
 989                 if (hdw->freqSelector) {
 990                         /* Swing over to radio frequency selection */
 991                         hdw->freqSelector = 0;
 992                         hdw->freqDirty = !0;
 993                 }
 994                 if (hdw->freqValRadio != val) {
 995                         hdw->freqValRadio = val;
 996                         hdw->freqSlotRadio = 0;
 997                         hdw->freqDirty = !0;
 998                 }
 999         } else {
1000                 if (!(hdw->freqSelector)) {
1001                         /* Swing over to television frequency selection */
1002                         hdw->freqSelector = 1;
1003                         hdw->freqDirty = !0;
1004                 }
1005                 if (hdw->freqValTelevision != val) {
1006                         hdw->freqValTelevision = val;
1007                         hdw->freqSlotTelevision = 0;
1008                         hdw->freqDirty = !0;
1009                 }
1010         }
1011 }
1012
1013 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1014 {
1015         return hdw->unit_number;
1016 }
1017
1018
1019 /* Attempt to locate one of the given set of files.  Messages are logged
1020    appropriate to what has been found.  The return value will be 0 or
1021    greater on success (it will be the index of the file name found) and
1022    fw_entry will be filled in.  Otherwise a negative error is returned on
1023    failure.  If the return value is -ENOENT then no viable firmware file
1024    could be located. */
1025 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1026                                 const struct firmware **fw_entry,
1027                                 const char *fwtypename,
1028                                 unsigned int fwcount,
1029                                 const char *fwnames[])
1030 {
1031         unsigned int idx;
1032         int ret = -EINVAL;
1033         for (idx = 0; idx < fwcount; idx++) {
1034                 ret = request_firmware(fw_entry,
1035                                        fwnames[idx],
1036                                        &hdw->usb_dev->dev);
1037                 if (!ret) {
1038                         trace_firmware("Located %s firmware: %s;"
1039                                        " uploading...",
1040                                        fwtypename,
1041                                        fwnames[idx]);
1042                         return idx;
1043                 }
1044                 if (ret == -ENOENT) continue;
1045                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1046                            "request_firmware fatal error with code=%d",ret);
1047                 return ret;
1048         }
1049         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1050                    "***WARNING***"
1051                    " Device %s firmware"
1052                    " seems to be missing.",
1053                    fwtypename);
1054         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1055                    "Did you install the pvrusb2 firmware files"
1056                    " in their proper location?");
1057         if (fwcount == 1) {
1058                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1059                            "request_firmware unable to locate %s file %s",
1060                            fwtypename,fwnames[0]);
1061         } else {
1062                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1063                            "request_firmware unable to locate"
1064                            " one of the following %s files:",
1065                            fwtypename);
1066                 for (idx = 0; idx < fwcount; idx++) {
1067                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1068                                    "request_firmware: Failed to find %s",
1069                                    fwnames[idx]);
1070                 }
1071         }
1072         return ret;
1073 }
1074
1075
1076 /*
1077  * pvr2_upload_firmware1().
1078  *
1079  * Send the 8051 firmware to the device.  After the upload, arrange for
1080  * device to re-enumerate.
1081  *
1082  * NOTE : the pointer to the firmware data given by request_firmware()
1083  * is not suitable for an usb transaction.
1084  *
1085  */
1086 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1087 {
1088         const struct firmware *fw_entry = NULL;
1089         void  *fw_ptr;
1090         unsigned int pipe;
1091         int ret;
1092         u16 address;
1093
1094         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1095                 hdw->fw1_state = FW1_STATE_OK;
1096                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1097                            "Connected device type defines"
1098                            " no firmware to upload; ignoring firmware");
1099                 return -ENOTTY;
1100         }
1101
1102         hdw->fw1_state = FW1_STATE_FAILED; // default result
1103
1104         trace_firmware("pvr2_upload_firmware1");
1105
1106         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1107                                    hdw->hdw_desc->fx2_firmware.cnt,
1108                                    hdw->hdw_desc->fx2_firmware.lst);
1109         if (ret < 0) {
1110                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1111                 return ret;
1112         }
1113
1114         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1115         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1116
1117         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1118
1119         if (fw_entry->size != 0x2000){
1120                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1121                 release_firmware(fw_entry);
1122                 return -ENOMEM;
1123         }
1124
1125         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1126         if (fw_ptr == NULL){
1127                 release_firmware(fw_entry);
1128                 return -ENOMEM;
1129         }
1130
1131         /* We have to hold the CPU during firmware upload. */
1132         pvr2_hdw_cpureset_assert(hdw,1);
1133
1134         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1135            chunk. */
1136
1137         ret = 0;
1138         for(address = 0; address < fw_entry->size; address += 0x800) {
1139                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1140                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1141                                        0, fw_ptr, 0x800, HZ);
1142         }
1143
1144         trace_firmware("Upload done, releasing device's CPU");
1145
1146         /* Now release the CPU.  It will disconnect and reconnect later. */
1147         pvr2_hdw_cpureset_assert(hdw,0);
1148
1149         kfree(fw_ptr);
1150         release_firmware(fw_entry);
1151
1152         trace_firmware("Upload done (%d bytes sent)",ret);
1153
1154         /* We should have written 8192 bytes */
1155         if (ret == 8192) {
1156                 hdw->fw1_state = FW1_STATE_RELOAD;
1157                 return 0;
1158         }
1159
1160         return -EIO;
1161 }
1162
1163
1164 /*
1165  * pvr2_upload_firmware2()
1166  *
1167  * This uploads encoder firmware on endpoint 2.
1168  *
1169  */
1170
1171 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1172 {
1173         const struct firmware *fw_entry = NULL;
1174         void  *fw_ptr;
1175         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1176         int actual_length;
1177         int ret = 0;
1178         int fwidx;
1179         static const char *fw_files[] = {
1180                 CX2341X_FIRM_ENC_FILENAME,
1181         };
1182
1183         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1184                 return 0;
1185         }
1186
1187         trace_firmware("pvr2_upload_firmware2");
1188
1189         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1190                                    ARRAY_SIZE(fw_files), fw_files);
1191         if (ret < 0) return ret;
1192         fwidx = ret;
1193         ret = 0;
1194         /* Since we're about to completely reinitialize the encoder,
1195            invalidate our cached copy of its configuration state.  Next
1196            time we configure the encoder, then we'll fully configure it. */
1197         hdw->enc_cur_valid = 0;
1198
1199         /* First prepare firmware loading */
1200         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1201         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1202         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1203         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1204         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1205         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1206         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1207         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1208         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1209         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1210         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1211         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1212         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1213         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1214         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1215         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1216         LOCK_TAKE(hdw->ctl_lock); do {
1217                 hdw->cmd_buffer[0] = FX2CMD_FWPOST1;
1218                 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
1219                 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1220                 hdw->cmd_buffer[1] = 0;
1221                 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
1222         } while (0); LOCK_GIVE(hdw->ctl_lock);
1223
1224         if (ret) {
1225                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1226                            "firmware2 upload prep failed, ret=%d",ret);
1227                 release_firmware(fw_entry);
1228                 return ret;
1229         }
1230
1231         /* Now send firmware */
1232
1233         fw_len = fw_entry->size;
1234
1235         if (fw_len % sizeof(u32)) {
1236                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1237                            "size of %s firmware"
1238                            " must be a multiple of %zu bytes",
1239                            fw_files[fwidx],sizeof(u32));
1240                 release_firmware(fw_entry);
1241                 return -1;
1242         }
1243
1244         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1245         if (fw_ptr == NULL){
1246                 release_firmware(fw_entry);
1247                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1248                            "failed to allocate memory for firmware2 upload");
1249                 return -ENOMEM;
1250         }
1251
1252         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1253
1254         fw_done = 0;
1255         for (fw_done = 0; fw_done < fw_len;) {
1256                 bcnt = fw_len - fw_done;
1257                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1258                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1259                 /* Usbsnoop log shows that we must swap bytes... */
1260                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1261                         ((u32 *)fw_ptr)[icnt] =
1262                                 ___swab32(((u32 *)fw_ptr)[icnt]);
1263
1264                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1265                                     &actual_length, HZ);
1266                 ret |= (actual_length != bcnt);
1267                 if (ret) break;
1268                 fw_done += bcnt;
1269         }
1270
1271         trace_firmware("upload of %s : %i / %i ",
1272                        fw_files[fwidx],fw_done,fw_len);
1273
1274         kfree(fw_ptr);
1275         release_firmware(fw_entry);
1276
1277         if (ret) {
1278                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1279                            "firmware2 upload transfer failure");
1280                 return ret;
1281         }
1282
1283         /* Finish upload */
1284
1285         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1286         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1287         LOCK_TAKE(hdw->ctl_lock); do {
1288                 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1289                 hdw->cmd_buffer[1] = 0;
1290                 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
1291         } while (0); LOCK_GIVE(hdw->ctl_lock);
1292
1293         if (ret) {
1294                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1295                            "firmware2 upload post-proc failure");
1296         }
1297         return ret;
1298 }
1299
1300
1301 static const char *pvr2_get_state_name(unsigned int st)
1302 {
1303         if (st < ARRAY_SIZE(pvr2_state_names)) {
1304                 return pvr2_state_names[st];
1305         }
1306         return "???";
1307 }
1308
1309 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1310 {
1311         if (!hdw->decoder_ctrl) {
1312                 if (!hdw->flag_decoder_missed) {
1313                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1314                                    "WARNING: No decoder present");
1315                         hdw->flag_decoder_missed = !0;
1316                         trace_stbit("flag_decoder_missed",
1317                                     hdw->flag_decoder_missed);
1318                 }
1319                 return -EIO;
1320         }
1321         hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1322         return 0;
1323 }
1324
1325
1326 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1327 {
1328         if (hdw->decoder_ctrl == ptr) return;
1329         hdw->decoder_ctrl = ptr;
1330         if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1331                 hdw->flag_decoder_missed = 0;
1332                 trace_stbit("flag_decoder_missed",
1333                             hdw->flag_decoder_missed);
1334                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1335                            "Decoder has appeared");
1336                 pvr2_hdw_state_sched(hdw);
1337         }
1338 }
1339
1340
1341 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1342 {
1343         return hdw->master_state;
1344 }
1345
1346
1347 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1348 {
1349         if (!hdw->flag_tripped) return 0;
1350         hdw->flag_tripped = 0;
1351         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1352                    "Clearing driver error statuss");
1353         return !0;
1354 }
1355
1356
1357 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1358 {
1359         int fl;
1360         LOCK_TAKE(hdw->big_lock); do {
1361                 fl = pvr2_hdw_untrip_unlocked(hdw);
1362         } while (0); LOCK_GIVE(hdw->big_lock);
1363         if (fl) pvr2_hdw_state_sched(hdw);
1364         return 0;
1365 }
1366
1367
1368 const char *pvr2_hdw_get_state_name(unsigned int id)
1369 {
1370         if (id >= ARRAY_SIZE(pvr2_state_names)) return NULL;
1371         return pvr2_state_names[id];
1372 }
1373
1374
1375 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1376 {
1377         return hdw->state_pipeline_req != 0;
1378 }
1379
1380
1381 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1382 {
1383         int ret,st;
1384         LOCK_TAKE(hdw->big_lock); do {
1385                 pvr2_hdw_untrip_unlocked(hdw);
1386                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1387                         hdw->state_pipeline_req = enable_flag != 0;
1388                         pvr2_trace(PVR2_TRACE_START_STOP,
1389                                    "/*--TRACE_STREAM--*/ %s",
1390                                    enable_flag ? "enable" : "disable");
1391                 }
1392                 pvr2_hdw_state_sched(hdw);
1393         } while (0); LOCK_GIVE(hdw->big_lock);
1394         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1395         if (enable_flag) {
1396                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1397                         if (st != PVR2_STATE_READY) return -EIO;
1398                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1399                 }
1400         }
1401         return 0;
1402 }
1403
1404
1405 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1406 {
1407         int fl;
1408         LOCK_TAKE(hdw->big_lock);
1409         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1410                 hdw->desired_stream_type = config;
1411                 hdw->state_pipeline_config = 0;
1412                 trace_stbit("state_pipeline_config",
1413                             hdw->state_pipeline_config);
1414                 pvr2_hdw_state_sched(hdw);
1415         }
1416         LOCK_GIVE(hdw->big_lock);
1417         if (fl) return 0;
1418         return pvr2_hdw_wait(hdw,0);
1419 }
1420
1421
1422 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1423 {
1424         int unit_number = hdw->unit_number;
1425         int tp = -1;
1426         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1427                 tp = tuner[unit_number];
1428         }
1429         if (tp < 0) return -EINVAL;
1430         hdw->tuner_type = tp;
1431         hdw->tuner_updated = !0;
1432         return 0;
1433 }
1434
1435
1436 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1437 {
1438         int unit_number = hdw->unit_number;
1439         int tp = 0;
1440         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1441                 tp = video_std[unit_number];
1442         }
1443         return tp;
1444 }
1445
1446
1447 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1448 {
1449         int unit_number = hdw->unit_number;
1450         int tp = 0;
1451         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1452                 tp = tolerance[unit_number];
1453         }
1454         return tp;
1455 }
1456
1457
1458 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1459 {
1460         /* Try a harmless request to fetch the eeprom's address over
1461            endpoint 1.  See what happens.  Only the full FX2 image can
1462            respond to this.  If this probe fails then likely the FX2
1463            firmware needs be loaded. */
1464         int result;
1465         LOCK_TAKE(hdw->ctl_lock); do {
1466                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1467                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1468                                            hdw->cmd_buffer,1,
1469                                            hdw->cmd_buffer,1);
1470                 if (result < 0) break;
1471         } while(0); LOCK_GIVE(hdw->ctl_lock);
1472         if (result) {
1473                 pvr2_trace(PVR2_TRACE_INIT,
1474                            "Probe of device endpoint 1 result status %d",
1475                            result);
1476         } else {
1477                 pvr2_trace(PVR2_TRACE_INIT,
1478                            "Probe of device endpoint 1 succeeded");
1479         }
1480         return result == 0;
1481 }
1482
1483 struct pvr2_std_hack {
1484         v4l2_std_id pat;  /* Pattern to match */
1485         v4l2_std_id msk;  /* Which bits we care about */
1486         v4l2_std_id std;  /* What additional standards or default to set */
1487 };
1488
1489 /* This data structure labels specific combinations of standards from
1490    tveeprom that we'll try to recognize.  If we recognize one, then assume
1491    a specified default standard to use.  This is here because tveeprom only
1492    tells us about available standards not the intended default standard (if
1493    any) for the device in question.  We guess the default based on what has
1494    been reported as available.  Note that this is only for guessing a
1495    default - which can always be overridden explicitly - and if the user
1496    has otherwise named a default then that default will always be used in
1497    place of this table. */
1498 const static struct pvr2_std_hack std_eeprom_maps[] = {
1499         {       /* PAL(B/G) */
1500                 .pat = V4L2_STD_B|V4L2_STD_GH,
1501                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1502         },
1503         {       /* NTSC(M) */
1504                 .pat = V4L2_STD_MN,
1505                 .std = V4L2_STD_NTSC_M,
1506         },
1507         {       /* PAL(I) */
1508                 .pat = V4L2_STD_PAL_I,
1509                 .std = V4L2_STD_PAL_I,
1510         },
1511         {       /* SECAM(L/L') */
1512                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1513                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1514         },
1515         {       /* PAL(D/D1/K) */
1516                 .pat = V4L2_STD_DK,
1517                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1518         },
1519 };
1520
1521 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1522 {
1523         char buf[40];
1524         unsigned int bcnt;
1525         v4l2_std_id std1,std2;
1526
1527         std1 = get_default_standard(hdw);
1528
1529         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1530         pvr2_trace(PVR2_TRACE_STD,
1531                    "Supported video standard(s) reported available"
1532                    " in hardware: %.*s",
1533                    bcnt,buf);
1534
1535         hdw->std_mask_avail = hdw->std_mask_eeprom;
1536
1537         std2 = std1 & ~hdw->std_mask_avail;
1538         if (std2) {
1539                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1540                 pvr2_trace(PVR2_TRACE_STD,
1541                            "Expanding supported video standards"
1542                            " to include: %.*s",
1543                            bcnt,buf);
1544                 hdw->std_mask_avail |= std2;
1545         }
1546
1547         pvr2_hdw_internal_set_std_avail(hdw);
1548
1549         if (std1) {
1550                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1551                 pvr2_trace(PVR2_TRACE_STD,
1552                            "Initial video standard forced to %.*s",
1553                            bcnt,buf);
1554                 hdw->std_mask_cur = std1;
1555                 hdw->std_dirty = !0;
1556                 pvr2_hdw_internal_find_stdenum(hdw);
1557                 return;
1558         }
1559
1560         {
1561                 unsigned int idx;
1562                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1563                         if (std_eeprom_maps[idx].msk ?
1564                             ((std_eeprom_maps[idx].pat ^
1565                              hdw->std_mask_eeprom) &
1566                              std_eeprom_maps[idx].msk) :
1567                             (std_eeprom_maps[idx].pat !=
1568                              hdw->std_mask_eeprom)) continue;
1569                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1570                                                   std_eeprom_maps[idx].std);
1571                         pvr2_trace(PVR2_TRACE_STD,
1572                                    "Initial video standard guessed as %.*s",
1573                                    bcnt,buf);
1574                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1575                         hdw->std_dirty = !0;
1576                         pvr2_hdw_internal_find_stdenum(hdw);
1577                         return;
1578                 }
1579         }
1580
1581         if (hdw->std_enum_cnt > 1) {
1582                 // Autoselect the first listed standard
1583                 hdw->std_enum_cur = 1;
1584                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1585                 hdw->std_dirty = !0;
1586                 pvr2_trace(PVR2_TRACE_STD,
1587                            "Initial video standard auto-selected to %s",
1588                            hdw->std_defs[hdw->std_enum_cur-1].name);
1589                 return;
1590         }
1591
1592         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1593                    "Unable to select a viable initial video standard");
1594 }
1595
1596
1597 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1598 {
1599         int ret;
1600         unsigned int idx;
1601         struct pvr2_ctrl *cptr;
1602         int reloadFl = 0;
1603         if (hdw->hdw_desc->fx2_firmware.cnt) {
1604                 if (!reloadFl) {
1605                         reloadFl =
1606                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1607                                  == 0);
1608                         if (reloadFl) {
1609                                 pvr2_trace(PVR2_TRACE_INIT,
1610                                            "USB endpoint config looks strange"
1611                                            "; possibly firmware needs to be"
1612                                            " loaded");
1613                         }
1614                 }
1615                 if (!reloadFl) {
1616                         reloadFl = !pvr2_hdw_check_firmware(hdw);
1617                         if (reloadFl) {
1618                                 pvr2_trace(PVR2_TRACE_INIT,
1619                                            "Check for FX2 firmware failed"
1620                                            "; possibly firmware needs to be"
1621                                            " loaded");
1622                         }
1623                 }
1624                 if (reloadFl) {
1625                         if (pvr2_upload_firmware1(hdw) != 0) {
1626                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1627                                            "Failure uploading firmware1");
1628                         }
1629                         return;
1630                 }
1631         }
1632         hdw->fw1_state = FW1_STATE_OK;
1633
1634         if (initusbreset) {
1635                 pvr2_hdw_device_reset(hdw);
1636         }
1637         if (!pvr2_hdw_dev_ok(hdw)) return;
1638
1639         for (idx = 0; idx < hdw->hdw_desc->client_modules.cnt; idx++) {
1640                 request_module(hdw->hdw_desc->client_modules.lst[idx]);
1641         }
1642
1643         if (!hdw->hdw_desc->flag_no_powerup) {
1644                 pvr2_hdw_cmd_powerup(hdw);
1645                 if (!pvr2_hdw_dev_ok(hdw)) return;
1646         }
1647
1648         // This step MUST happen after the earlier powerup step.
1649         pvr2_i2c_core_init(hdw);
1650         if (!pvr2_hdw_dev_ok(hdw)) return;
1651
1652         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1653                 cptr = hdw->controls + idx;
1654                 if (cptr->info->skip_init) continue;
1655                 if (!cptr->info->set_value) continue;
1656                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1657         }
1658
1659         /* Set up special default values for the television and radio
1660            frequencies here.  It's not really important what these defaults
1661            are, but I set them to something usable in the Chicago area just
1662            to make driver testing a little easier. */
1663
1664         /* US Broadcast channel 7 (175.25 MHz) */
1665         hdw->freqValTelevision = 175250000L;
1666         /* 104.3 MHz, a usable FM station for my area */
1667         hdw->freqValRadio = 104300000L;
1668
1669         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
1670         // thread-safe against the normal pvr2_send_request() mechanism.
1671         // (We should make it thread safe).
1672
1673         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
1674                 ret = pvr2_hdw_get_eeprom_addr(hdw);
1675                 if (!pvr2_hdw_dev_ok(hdw)) return;
1676                 if (ret < 0) {
1677                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1678                                    "Unable to determine location of eeprom,"
1679                                    " skipping");
1680                 } else {
1681                         hdw->eeprom_addr = ret;
1682                         pvr2_eeprom_analyze(hdw);
1683                         if (!pvr2_hdw_dev_ok(hdw)) return;
1684                 }
1685         } else {
1686                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
1687                 hdw->tuner_updated = !0;
1688                 hdw->std_mask_eeprom = V4L2_STD_ALL;
1689         }
1690
1691         pvr2_hdw_setup_std(hdw);
1692
1693         if (!get_default_tuner_type(hdw)) {
1694                 pvr2_trace(PVR2_TRACE_INIT,
1695                            "pvr2_hdw_setup: Tuner type overridden to %d",
1696                            hdw->tuner_type);
1697         }
1698
1699         pvr2_i2c_core_check_stale(hdw);
1700         hdw->tuner_updated = 0;
1701
1702         if (!pvr2_hdw_dev_ok(hdw)) return;
1703
1704         pvr2_hdw_commit_setup(hdw);
1705
1706         hdw->vid_stream = pvr2_stream_create();
1707         if (!pvr2_hdw_dev_ok(hdw)) return;
1708         pvr2_trace(PVR2_TRACE_INIT,
1709                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1710         if (hdw->vid_stream) {
1711                 idx = get_default_error_tolerance(hdw);
1712                 if (idx) {
1713                         pvr2_trace(PVR2_TRACE_INIT,
1714                                    "pvr2_hdw_setup: video stream %p"
1715                                    " setting tolerance %u",
1716                                    hdw->vid_stream,idx);
1717                 }
1718                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1719                                   PVR2_VID_ENDPOINT,idx);
1720         }
1721
1722         if (!pvr2_hdw_dev_ok(hdw)) return;
1723
1724         hdw->flag_init_ok = !0;
1725
1726         pvr2_hdw_state_sched(hdw);
1727 }
1728
1729
1730 /* Set up the structure and attempt to put the device into a usable state.
1731    This can be a time-consuming operation, which is why it is not done
1732    internally as part of the create() step. */
1733 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
1734 {
1735         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1736         do {
1737                 pvr2_hdw_setup_low(hdw);
1738                 pvr2_trace(PVR2_TRACE_INIT,
1739                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1740                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
1741                 if (pvr2_hdw_dev_ok(hdw)) {
1742                         if (hdw->flag_init_ok) {
1743                                 pvr2_trace(
1744                                         PVR2_TRACE_INFO,
1745                                         "Device initialization"
1746                                         " completed successfully.");
1747                                 break;
1748                         }
1749                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
1750                                 pvr2_trace(
1751                                         PVR2_TRACE_INFO,
1752                                         "Device microcontroller firmware"
1753                                         " (re)loaded; it should now reset"
1754                                         " and reconnect.");
1755                                 break;
1756                         }
1757                         pvr2_trace(
1758                                 PVR2_TRACE_ERROR_LEGS,
1759                                 "Device initialization was not successful.");
1760                         if (hdw->fw1_state == FW1_STATE_MISSING) {
1761                                 pvr2_trace(
1762                                         PVR2_TRACE_ERROR_LEGS,
1763                                         "Giving up since device"
1764                                         " microcontroller firmware"
1765                                         " appears to be missing.");
1766                                 break;
1767                         }
1768                 }
1769                 if (procreload) {
1770                         pvr2_trace(
1771                                 PVR2_TRACE_ERROR_LEGS,
1772                                 "Attempting pvrusb2 recovery by reloading"
1773                                 " primary firmware.");
1774                         pvr2_trace(
1775                                 PVR2_TRACE_ERROR_LEGS,
1776                                 "If this works, device should disconnect"
1777                                 " and reconnect in a sane state.");
1778                         hdw->fw1_state = FW1_STATE_UNKNOWN;
1779                         pvr2_upload_firmware1(hdw);
1780                 } else {
1781                         pvr2_trace(
1782                                 PVR2_TRACE_ERROR_LEGS,
1783                                 "***WARNING*** pvrusb2 device hardware"
1784                                 " appears to be jammed"
1785                                 " and I can't clear it.");
1786                         pvr2_trace(
1787                                 PVR2_TRACE_ERROR_LEGS,
1788                                 "You might need to power cycle"
1789                                 " the pvrusb2 device"
1790                                 " in order to recover.");
1791                 }
1792         } while (0);
1793         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1794 }
1795
1796
1797 /* Create and return a structure for interacting with the underlying
1798    hardware */
1799 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1800                                  const struct usb_device_id *devid)
1801 {
1802         unsigned int idx,cnt1,cnt2;
1803         struct pvr2_hdw *hdw;
1804         unsigned int hdw_type;
1805         int valid_std_mask;
1806         struct pvr2_ctrl *cptr;
1807         const struct pvr2_device_desc *hdw_desc;
1808         __u8 ifnum;
1809         struct v4l2_queryctrl qctrl;
1810         struct pvr2_ctl_info *ciptr;
1811
1812         hdw_type = devid - pvr2_device_table;
1813         if (hdw_type >= pvr2_device_count) {
1814                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1815                            "Bogus device type of %u reported",hdw_type);
1816                 return NULL;
1817         }
1818         hdw_desc = pvr2_device_descriptions + hdw_type;
1819
1820         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
1821         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1822                    hdw,hdw_desc->description);
1823         if (!hdw) goto fail;
1824
1825         init_timer(&hdw->quiescent_timer);
1826         hdw->quiescent_timer.data = (unsigned long)hdw;
1827         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
1828
1829         init_timer(&hdw->encoder_wait_timer);
1830         hdw->encoder_wait_timer.data = (unsigned long)hdw;
1831         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
1832
1833         hdw->master_state = PVR2_STATE_DEAD;
1834
1835         init_waitqueue_head(&hdw->state_wait_data);
1836
1837         hdw->tuner_signal_stale = !0;
1838         cx2341x_fill_defaults(&hdw->enc_ctl_state);
1839
1840         hdw->control_cnt = CTRLDEF_COUNT;
1841         hdw->control_cnt += MPEGDEF_COUNT;
1842         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1843                                 GFP_KERNEL);
1844         if (!hdw->controls) goto fail;
1845         hdw->hdw_desc = hdw_desc;
1846         for (idx = 0; idx < hdw->control_cnt; idx++) {
1847                 cptr = hdw->controls + idx;
1848                 cptr->hdw = hdw;
1849         }
1850         for (idx = 0; idx < 32; idx++) {
1851                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1852         }
1853         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1854                 cptr = hdw->controls + idx;
1855                 cptr->info = control_defs+idx;
1856         }
1857         /* Define and configure additional controls from cx2341x module. */
1858         hdw->mpeg_ctrl_info = kzalloc(
1859                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1860         if (!hdw->mpeg_ctrl_info) goto fail;
1861         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1862                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1863                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1864                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1865                 ciptr->name = mpeg_ids[idx].strid;
1866                 ciptr->v4l_id = mpeg_ids[idx].id;
1867                 ciptr->skip_init = !0;
1868                 ciptr->get_value = ctrl_cx2341x_get;
1869                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1870                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1871                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1872                 qctrl.id = ciptr->v4l_id;
1873                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1874                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1875                         ciptr->set_value = ctrl_cx2341x_set;
1876                 }
1877                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1878                         PVR2_CTLD_INFO_DESC_SIZE);
1879                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
1880                 ciptr->default_value = qctrl.default_value;
1881                 switch (qctrl.type) {
1882                 default:
1883                 case V4L2_CTRL_TYPE_INTEGER:
1884                         ciptr->type = pvr2_ctl_int;
1885                         ciptr->def.type_int.min_value = qctrl.minimum;
1886                         ciptr->def.type_int.max_value = qctrl.maximum;
1887                         break;
1888                 case V4L2_CTRL_TYPE_BOOLEAN:
1889                         ciptr->type = pvr2_ctl_bool;
1890                         break;
1891                 case V4L2_CTRL_TYPE_MENU:
1892                         ciptr->type = pvr2_ctl_enum;
1893                         ciptr->def.type_enum.value_names =
1894                                 cx2341x_ctrl_get_menu(ciptr->v4l_id);
1895                         for (cnt1 = 0;
1896                              ciptr->def.type_enum.value_names[cnt1] != NULL;
1897                              cnt1++) { }
1898                         ciptr->def.type_enum.count = cnt1;
1899                         break;
1900                 }
1901                 cptr->info = ciptr;
1902         }
1903
1904         // Initialize video standard enum dynamic control
1905         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1906         if (cptr) {
1907                 memcpy(&hdw->std_info_enum,cptr->info,
1908                        sizeof(hdw->std_info_enum));
1909                 cptr->info = &hdw->std_info_enum;
1910
1911         }
1912         // Initialize control data regarding video standard masks
1913         valid_std_mask = pvr2_std_get_usable();
1914         for (idx = 0; idx < 32; idx++) {
1915                 if (!(valid_std_mask & (1 << idx))) continue;
1916                 cnt1 = pvr2_std_id_to_str(
1917                         hdw->std_mask_names[idx],
1918                         sizeof(hdw->std_mask_names[idx])-1,
1919                         1 << idx);
1920                 hdw->std_mask_names[idx][cnt1] = 0;
1921         }
1922         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1923         if (cptr) {
1924                 memcpy(&hdw->std_info_avail,cptr->info,
1925                        sizeof(hdw->std_info_avail));
1926                 cptr->info = &hdw->std_info_avail;
1927                 hdw->std_info_avail.def.type_bitmask.bit_names =
1928                         hdw->std_mask_ptrs;
1929                 hdw->std_info_avail.def.type_bitmask.valid_bits =
1930                         valid_std_mask;
1931         }
1932         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1933         if (cptr) {
1934                 memcpy(&hdw->std_info_cur,cptr->info,
1935                        sizeof(hdw->std_info_cur));
1936                 cptr->info = &hdw->std_info_cur;
1937                 hdw->std_info_cur.def.type_bitmask.bit_names =
1938                         hdw->std_mask_ptrs;
1939                 hdw->std_info_avail.def.type_bitmask.valid_bits =
1940                         valid_std_mask;
1941         }
1942
1943         hdw->eeprom_addr = -1;
1944         hdw->unit_number = -1;
1945         hdw->v4l_minor_number_video = -1;
1946         hdw->v4l_minor_number_vbi = -1;
1947         hdw->v4l_minor_number_radio = -1;
1948         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1949         if (!hdw->ctl_write_buffer) goto fail;
1950         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1951         if (!hdw->ctl_read_buffer) goto fail;
1952         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
1953         if (!hdw->ctl_write_urb) goto fail;
1954         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
1955         if (!hdw->ctl_read_urb) goto fail;
1956
1957         mutex_lock(&pvr2_unit_mtx); do {
1958                 for (idx = 0; idx < PVR_NUM; idx++) {
1959                         if (unit_pointers[idx]) continue;
1960                         hdw->unit_number = idx;
1961                         unit_pointers[idx] = hdw;
1962                         break;
1963                 }
1964         } while (0); mutex_unlock(&pvr2_unit_mtx);
1965
1966         cnt1 = 0;
1967         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
1968         cnt1 += cnt2;
1969         if (hdw->unit_number >= 0) {
1970                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
1971                                  ('a' + hdw->unit_number));
1972                 cnt1 += cnt2;
1973         }
1974         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
1975         hdw->name[cnt1] = 0;
1976
1977         hdw->workqueue = create_singlethread_workqueue(hdw->name);
1978         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
1979         INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
1980         INIT_WORK(&hdw->workinit,pvr2_hdw_worker_init);
1981
1982         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
1983                    hdw->unit_number,hdw->name);
1984
1985         hdw->tuner_type = -1;
1986         hdw->flag_ok = !0;
1987
1988         hdw->usb_intf = intf;
1989         hdw->usb_dev = interface_to_usbdev(intf);
1990
1991         scnprintf(hdw->bus_info,sizeof(hdw->bus_info),
1992                   "usb %s address %d",
1993                   hdw->usb_dev->dev.bus_id,
1994                   hdw->usb_dev->devnum);
1995
1996         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
1997         usb_set_interface(hdw->usb_dev,ifnum,0);
1998
1999         mutex_init(&hdw->ctl_lock_mutex);
2000         mutex_init(&hdw->big_lock_mutex);
2001
2002         queue_work(hdw->workqueue,&hdw->workinit);
2003         return hdw;
2004  fail:
2005         if (hdw) {
2006                 del_timer_sync(&hdw->quiescent_timer);
2007                 del_timer_sync(&hdw->encoder_wait_timer);
2008                 if (hdw->workqueue) {
2009                         flush_workqueue(hdw->workqueue);
2010                         destroy_workqueue(hdw->workqueue);
2011                         hdw->workqueue = NULL;
2012                 }
2013                 usb_free_urb(hdw->ctl_read_urb);
2014                 usb_free_urb(hdw->ctl_write_urb);
2015                 kfree(hdw->ctl_read_buffer);
2016                 kfree(hdw->ctl_write_buffer);
2017                 kfree(hdw->controls);
2018                 kfree(hdw->mpeg_ctrl_info);
2019                 kfree(hdw->std_defs);
2020                 kfree(hdw->std_enum_names);
2021                 kfree(hdw);
2022         }
2023         return NULL;
2024 }
2025
2026
2027 /* Remove _all_ associations between this driver and the underlying USB
2028    layer. */
2029 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2030 {
2031         if (hdw->flag_disconnected) return;
2032         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2033         if (hdw->ctl_read_urb) {
2034                 usb_kill_urb(hdw->ctl_read_urb);
2035                 usb_free_urb(hdw->ctl_read_urb);
2036                 hdw->ctl_read_urb = NULL;
2037         }
2038         if (hdw->ctl_write_urb) {
2039                 usb_kill_urb(hdw->ctl_write_urb);
2040                 usb_free_urb(hdw->ctl_write_urb);
2041                 hdw->ctl_write_urb = NULL;
2042         }
2043         if (hdw->ctl_read_buffer) {
2044                 kfree(hdw->ctl_read_buffer);
2045                 hdw->ctl_read_buffer = NULL;
2046         }
2047         if (hdw->ctl_write_buffer) {
2048                 kfree(hdw->ctl_write_buffer);
2049                 hdw->ctl_write_buffer = NULL;
2050         }
2051         hdw->flag_disconnected = !0;
2052         hdw->usb_dev = NULL;
2053         hdw->usb_intf = NULL;
2054         pvr2_hdw_render_useless(hdw);
2055 }
2056
2057
2058 /* Destroy hardware interaction structure */
2059 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2060 {
2061         if (!hdw) return;
2062         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2063         del_timer_sync(&hdw->quiescent_timer);
2064         del_timer_sync(&hdw->encoder_wait_timer);
2065         if (hdw->workqueue) {
2066                 flush_workqueue(hdw->workqueue);
2067                 destroy_workqueue(hdw->workqueue);
2068                 hdw->workqueue = NULL;
2069         }
2070         if (hdw->fw_buffer) {
2071                 kfree(hdw->fw_buffer);
2072                 hdw->fw_buffer = NULL;
2073         }
2074         if (hdw->vid_stream) {
2075                 pvr2_stream_destroy(hdw->vid_stream);
2076                 hdw->vid_stream = NULL;
2077         }
2078         if (hdw->decoder_ctrl) {
2079                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2080         }
2081         pvr2_i2c_core_done(hdw);
2082         pvr2_hdw_remove_usb_stuff(hdw);
2083         mutex_lock(&pvr2_unit_mtx); do {
2084                 if ((hdw->unit_number >= 0) &&
2085                     (hdw->unit_number < PVR_NUM) &&
2086                     (unit_pointers[hdw->unit_number] == hdw)) {
2087                         unit_pointers[hdw->unit_number] = NULL;
2088                 }
2089         } while (0); mutex_unlock(&pvr2_unit_mtx);
2090         kfree(hdw->controls);
2091         kfree(hdw->mpeg_ctrl_info);
2092         kfree(hdw->std_defs);
2093         kfree(hdw->std_enum_names);
2094         kfree(hdw);
2095 }
2096
2097
2098 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2099 {
2100         return (hdw && hdw->flag_ok);
2101 }
2102
2103
2104 /* Called when hardware has been unplugged */
2105 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2106 {
2107         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2108         LOCK_TAKE(hdw->big_lock);
2109         LOCK_TAKE(hdw->ctl_lock);
2110         pvr2_hdw_remove_usb_stuff(hdw);
2111         LOCK_GIVE(hdw->ctl_lock);
2112         LOCK_GIVE(hdw->big_lock);
2113 }
2114
2115
2116 // Attempt to autoselect an appropriate value for std_enum_cur given
2117 // whatever is currently in std_mask_cur
2118 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2119 {
2120         unsigned int idx;
2121         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2122                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2123                         hdw->std_enum_cur = idx;
2124                         return;
2125                 }
2126         }
2127         hdw->std_enum_cur = 0;
2128 }
2129
2130
2131 // Calculate correct set of enumerated standards based on currently known
2132 // set of available standards bits.
2133 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2134 {
2135         struct v4l2_standard *newstd;
2136         unsigned int std_cnt;
2137         unsigned int idx;
2138
2139         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2140
2141         if (hdw->std_defs) {
2142                 kfree(hdw->std_defs);
2143                 hdw->std_defs = NULL;
2144         }
2145         hdw->std_enum_cnt = 0;
2146         if (hdw->std_enum_names) {
2147                 kfree(hdw->std_enum_names);
2148                 hdw->std_enum_names = NULL;
2149         }
2150
2151         if (!std_cnt) {
2152                 pvr2_trace(
2153                         PVR2_TRACE_ERROR_LEGS,
2154                         "WARNING: Failed to identify any viable standards");
2155         }
2156         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2157         hdw->std_enum_names[0] = "none";
2158         for (idx = 0; idx < std_cnt; idx++) {
2159                 hdw->std_enum_names[idx+1] =
2160                         newstd[idx].name;
2161         }
2162         // Set up the dynamic control for this standard
2163         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2164         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2165         hdw->std_defs = newstd;
2166         hdw->std_enum_cnt = std_cnt+1;
2167         hdw->std_enum_cur = 0;
2168         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2169 }
2170
2171
2172 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2173                                struct v4l2_standard *std,
2174                                unsigned int idx)
2175 {
2176         int ret = -EINVAL;
2177         if (!idx) return ret;
2178         LOCK_TAKE(hdw->big_lock); do {
2179                 if (idx >= hdw->std_enum_cnt) break;
2180                 idx--;
2181                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2182                 ret = 0;
2183         } while (0); LOCK_GIVE(hdw->big_lock);
2184         return ret;
2185 }
2186
2187
2188 /* Get the number of defined controls */
2189 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2190 {
2191         return hdw->control_cnt;
2192 }
2193
2194
2195 /* Retrieve a control handle given its index (0..count-1) */
2196 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2197                                              unsigned int idx)
2198 {
2199         if (idx >= hdw->control_cnt) return NULL;
2200         return hdw->controls + idx;
2201 }
2202
2203
2204 /* Retrieve a control handle given its index (0..count-1) */
2205 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2206                                           unsigned int ctl_id)
2207 {
2208         struct pvr2_ctrl *cptr;
2209         unsigned int idx;
2210         int i;
2211
2212         /* This could be made a lot more efficient, but for now... */
2213         for (idx = 0; idx < hdw->control_cnt; idx++) {
2214                 cptr = hdw->controls + idx;
2215                 i = cptr->info->internal_id;
2216                 if (i && (i == ctl_id)) return cptr;
2217         }
2218         return NULL;
2219 }
2220
2221
2222 /* Given a V4L ID, retrieve the control structure associated with it. */
2223 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2224 {
2225         struct pvr2_ctrl *cptr;
2226         unsigned int idx;
2227         int i;
2228
2229         /* This could be made a lot more efficient, but for now... */
2230         for (idx = 0; idx < hdw->control_cnt; idx++) {
2231                 cptr = hdw->controls + idx;
2232                 i = cptr->info->v4l_id;
2233                 if (i && (i == ctl_id)) return cptr;
2234         }
2235         return NULL;
2236 }
2237
2238
2239 /* Given a V4L ID for its immediate predecessor, retrieve the control
2240    structure associated with it. */
2241 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2242                                             unsigned int ctl_id)
2243 {
2244         struct pvr2_ctrl *cptr,*cp2;
2245         unsigned int idx;
2246         int i;
2247
2248         /* This could be made a lot more efficient, but for now... */
2249         cp2 = NULL;
2250         for (idx = 0; idx < hdw->control_cnt; idx++) {
2251                 cptr = hdw->controls + idx;
2252                 i = cptr->info->v4l_id;
2253                 if (!i) continue;
2254                 if (i <= ctl_id) continue;
2255                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2256                 cp2 = cptr;
2257         }
2258         return cp2;
2259         return NULL;
2260 }
2261
2262
2263 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2264 {
2265         switch (tp) {
2266         case pvr2_ctl_int: return "integer";
2267         case pvr2_ctl_enum: return "enum";
2268         case pvr2_ctl_bool: return "boolean";
2269         case pvr2_ctl_bitmask: return "bitmask";
2270         }
2271         return "";
2272 }
2273
2274
2275 /* Figure out if we need to commit control changes.  If so, mark internal
2276    state flags to indicate this fact and return true.  Otherwise do nothing
2277    else and return false. */
2278 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2279 {
2280         unsigned int idx;
2281         struct pvr2_ctrl *cptr;
2282         int value;
2283         int commit_flag = 0;
2284         char buf[100];
2285         unsigned int bcnt,ccnt;
2286
2287         for (idx = 0; idx < hdw->control_cnt; idx++) {
2288                 cptr = hdw->controls + idx;
2289                 if (cptr->info->is_dirty == 0) continue;
2290                 if (!cptr->info->is_dirty(cptr)) continue;
2291                 commit_flag = !0;
2292
2293                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2294                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2295                                  cptr->info->name);
2296                 value = 0;
2297                 cptr->info->get_value(cptr,&value);
2298                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2299                                                 buf+bcnt,
2300                                                 sizeof(buf)-bcnt,&ccnt);
2301                 bcnt += ccnt;
2302                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2303                                   get_ctrl_typename(cptr->info->type));
2304                 pvr2_trace(PVR2_TRACE_CTL,
2305                            "/*--TRACE_COMMIT--*/ %.*s",
2306                            bcnt,buf);
2307         }
2308
2309         if (!commit_flag) {
2310                 /* Nothing has changed */
2311                 return 0;
2312         }
2313
2314         hdw->state_pipeline_config = 0;
2315         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2316         pvr2_hdw_state_sched(hdw);
2317
2318         return !0;
2319 }
2320
2321
2322 /* Perform all operations needed to commit all control changes.  This must
2323    be performed in synchronization with the pipeline state and is thus
2324    expected to be called as part of the driver's worker thread.  Return
2325    true if commit successful, otherwise return false to indicate that
2326    commit isn't possible at this time. */
2327 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
2328 {
2329         unsigned int idx;
2330         struct pvr2_ctrl *cptr;
2331         int disruptive_change;
2332
2333         /* When video standard changes, reset the hres and vres values -
2334            but if the user has pending changes there, then let the changes
2335            take priority. */
2336         if (hdw->std_dirty) {
2337                 /* Rewrite the vertical resolution to be appropriate to the
2338                    video standard that has been selected. */
2339                 int nvres;
2340                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2341                         nvres = 480;
2342                 } else {
2343                         nvres = 576;
2344                 }
2345                 if (nvres != hdw->res_ver_val) {
2346                         hdw->res_ver_val = nvres;
2347                         hdw->res_ver_dirty = !0;
2348                 }
2349         }
2350
2351         /* If any of the below has changed, then we can't do the update
2352            while the pipeline is running.  Pipeline must be paused first
2353            and decoder -> encoder connection be made quiescent before we
2354            can proceed. */
2355         disruptive_change =
2356                 (hdw->std_dirty ||
2357                  hdw->enc_unsafe_stale ||
2358                  hdw->srate_dirty ||
2359                  hdw->res_ver_dirty ||
2360                  hdw->res_hor_dirty ||
2361                  hdw->input_dirty ||
2362                  (hdw->active_stream_type != hdw->desired_stream_type));
2363         if (disruptive_change && !hdw->state_pipeline_idle) {
2364                 /* Pipeline is not idle; we can't proceed.  Arrange to
2365                    cause pipeline to stop so that we can try this again
2366                    later.... */
2367                 hdw->state_pipeline_pause = !0;
2368                 return 0;
2369         }
2370
2371         if (hdw->srate_dirty) {
2372                 /* Write new sample rate into control structure since
2373                  * the master copy is stale.  We must track srate
2374                  * separate from the mpeg control structure because
2375                  * other logic also uses this value. */
2376                 struct v4l2_ext_controls cs;
2377                 struct v4l2_ext_control c1;
2378                 memset(&cs,0,sizeof(cs));
2379                 memset(&c1,0,sizeof(c1));
2380                 cs.controls = &c1;
2381                 cs.count = 1;
2382                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2383                 c1.value = hdw->srate_val;
2384                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
2385         }
2386
2387         /* Scan i2c core at this point - before we clear all the dirty
2388            bits.  Various parts of the i2c core will notice dirty bits as
2389            appropriate and arrange to broadcast or directly send updates to
2390            the client drivers in order to keep everything in sync */
2391         pvr2_i2c_core_check_stale(hdw);
2392
2393         for (idx = 0; idx < hdw->control_cnt; idx++) {
2394                 cptr = hdw->controls + idx;
2395                 if (!cptr->info->clear_dirty) continue;
2396                 cptr->info->clear_dirty(cptr);
2397         }
2398
2399         if (hdw->active_stream_type != hdw->desired_stream_type) {
2400                 /* Handle any side effects of stream config here */
2401                 hdw->active_stream_type = hdw->desired_stream_type;
2402         }
2403
2404         /* Now execute i2c core update */
2405         pvr2_i2c_core_sync(hdw);
2406
2407         if (hdw->state_encoder_run) {
2408                 /* If encoder isn't running, then this will get worked out
2409                    later when we start the encoder. */
2410                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
2411         }
2412
2413         hdw->state_pipeline_config = !0;
2414         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2415         return !0;
2416 }
2417
2418
2419 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2420 {
2421         int fl;
2422         LOCK_TAKE(hdw->big_lock);
2423         fl = pvr2_hdw_commit_setup(hdw);
2424         LOCK_GIVE(hdw->big_lock);
2425         if (!fl) return 0;
2426         return pvr2_hdw_wait(hdw,0);
2427 }
2428
2429
2430 static void pvr2_hdw_worker_i2c(struct work_struct *work)
2431 {
2432         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
2433         LOCK_TAKE(hdw->big_lock); do {
2434                 pvr2_i2c_core_sync(hdw);
2435         } while (0); LOCK_GIVE(hdw->big_lock);
2436 }
2437
2438
2439 static void pvr2_hdw_worker_poll(struct work_struct *work)
2440 {
2441         int fl = 0;
2442         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
2443         LOCK_TAKE(hdw->big_lock); do {
2444                 fl = pvr2_hdw_state_eval(hdw);
2445         } while (0); LOCK_GIVE(hdw->big_lock);
2446         if (fl && hdw->state_func) {
2447                 hdw->state_func(hdw->state_data);
2448         }
2449 }
2450
2451
2452 static void pvr2_hdw_worker_init(struct work_struct *work)
2453 {
2454         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workinit);
2455         LOCK_TAKE(hdw->big_lock); do {
2456                 pvr2_hdw_setup(hdw);
2457         } while (0); LOCK_GIVE(hdw->big_lock);
2458 }
2459
2460
2461 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
2462 {
2463         return wait_event_interruptible(
2464                 hdw->state_wait_data,
2465                 (hdw->state_stale == 0) &&
2466                 (!state || (hdw->master_state != state)));
2467 }
2468
2469
2470 void pvr2_hdw_set_state_callback(struct pvr2_hdw *hdw,
2471                                  void (*callback_func)(void *),
2472                                  void *callback_data)
2473 {
2474         LOCK_TAKE(hdw->big_lock); do {
2475                 hdw->state_data = callback_data;
2476                 hdw->state_func = callback_func;
2477         } while (0); LOCK_GIVE(hdw->big_lock);
2478 }
2479
2480
2481 /* Return name for this driver instance */
2482 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2483 {
2484         return hdw->name;
2485 }
2486
2487
2488 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
2489 {
2490         return hdw->hdw_desc->description;
2491 }
2492
2493
2494 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
2495 {
2496         return hdw->hdw_desc->shortname;
2497 }
2498
2499
2500 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2501 {
2502         int result;
2503         LOCK_TAKE(hdw->ctl_lock); do {
2504                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
2505                 result = pvr2_send_request(hdw,
2506                                            hdw->cmd_buffer,1,
2507                                            hdw->cmd_buffer,1);
2508                 if (result < 0) break;
2509                 result = (hdw->cmd_buffer[0] != 0);
2510         } while(0); LOCK_GIVE(hdw->ctl_lock);
2511         return result;
2512 }
2513
2514
2515 /* Execute poll of tuner status */
2516 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
2517 {
2518         LOCK_TAKE(hdw->big_lock); do {
2519                 pvr2_i2c_core_status_poll(hdw);
2520         } while (0); LOCK_GIVE(hdw->big_lock);
2521 }
2522
2523
2524 /* Return information about the tuner */
2525 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
2526 {
2527         LOCK_TAKE(hdw->big_lock); do {
2528                 if (hdw->tuner_signal_stale) {
2529                         pvr2_i2c_core_status_poll(hdw);
2530                 }
2531                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
2532         } while (0); LOCK_GIVE(hdw->big_lock);
2533         return 0;
2534 }
2535
2536
2537 /* Get handle to video output stream */
2538 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2539 {
2540         return hp->vid_stream;
2541 }
2542
2543
2544 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2545 {
2546         int nr = pvr2_hdw_get_unit_number(hdw);
2547         LOCK_TAKE(hdw->big_lock); do {
2548                 hdw->log_requested = !0;
2549                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
2550                 pvr2_i2c_core_check_stale(hdw);
2551                 hdw->log_requested = 0;
2552                 pvr2_i2c_core_sync(hdw);
2553                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
2554                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
2555                 pvr2_hdw_state_log_state(hdw);
2556                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
2557         } while (0); LOCK_GIVE(hdw->big_lock);
2558 }
2559
2560
2561 /* Grab EEPROM contents, needed for direct method. */
2562 #define EEPROM_SIZE 8192
2563 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
2564 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
2565 {
2566         struct i2c_msg msg[2];
2567         u8 *eeprom;
2568         u8 iadd[2];
2569         u8 addr;
2570         u16 eepromSize;
2571         unsigned int offs;
2572         int ret;
2573         int mode16 = 0;
2574         unsigned pcnt,tcnt;
2575         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
2576         if (!eeprom) {
2577                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2578                            "Failed to allocate memory"
2579                            " required to read eeprom");
2580                 return NULL;
2581         }
2582
2583         trace_eeprom("Value for eeprom addr from controller was 0x%x",
2584                      hdw->eeprom_addr);
2585         addr = hdw->eeprom_addr;
2586         /* Seems that if the high bit is set, then the *real* eeprom
2587            address is shifted right now bit position (noticed this in
2588            newer PVR USB2 hardware) */
2589         if (addr & 0x80) addr >>= 1;
2590
2591         /* FX2 documentation states that a 16bit-addressed eeprom is
2592            expected if the I2C address is an odd number (yeah, this is
2593            strange but it's what they do) */
2594         mode16 = (addr & 1);
2595         eepromSize = (mode16 ? EEPROM_SIZE : 256);
2596         trace_eeprom("Examining %d byte eeprom at location 0x%x"
2597                      " using %d bit addressing",eepromSize,addr,
2598                      mode16 ? 16 : 8);
2599
2600         msg[0].addr = addr;
2601         msg[0].flags = 0;
2602         msg[0].len = mode16 ? 2 : 1;
2603         msg[0].buf = iadd;
2604         msg[1].addr = addr;
2605         msg[1].flags = I2C_M_RD;
2606
2607         /* We have to do the actual eeprom data fetch ourselves, because
2608            (1) we're only fetching part of the eeprom, and (2) if we were
2609            getting the whole thing our I2C driver can't grab it in one
2610            pass - which is what tveeprom is otherwise going to attempt */
2611         memset(eeprom,0,EEPROM_SIZE);
2612         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
2613                 pcnt = 16;
2614                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
2615                 offs = tcnt + (eepromSize - EEPROM_SIZE);
2616                 if (mode16) {
2617                         iadd[0] = offs >> 8;
2618                         iadd[1] = offs;
2619                 } else {
2620                         iadd[0] = offs;
2621                 }
2622                 msg[1].len = pcnt;
2623                 msg[1].buf = eeprom+tcnt;
2624                 if ((ret = i2c_transfer(&hdw->i2c_adap,
2625                                         msg,ARRAY_SIZE(msg))) != 2) {
2626                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2627                                    "eeprom fetch set offs err=%d",ret);
2628                         kfree(eeprom);
2629                         return NULL;
2630                 }
2631         }
2632         return eeprom;
2633 }
2634
2635
2636 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
2637                                 int prom_flag,
2638                                 int enable_flag)
2639 {
2640         int ret;
2641         u16 address;
2642         unsigned int pipe;
2643         LOCK_TAKE(hdw->big_lock); do {
2644                 if ((hdw->fw_buffer == 0) == !enable_flag) break;
2645
2646                 if (!enable_flag) {
2647                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2648                                    "Cleaning up after CPU firmware fetch");
2649                         kfree(hdw->fw_buffer);
2650                         hdw->fw_buffer = NULL;
2651                         hdw->fw_size = 0;
2652                         if (hdw->fw_cpu_flag) {
2653                                 /* Now release the CPU.  It will disconnect
2654                                    and reconnect later. */
2655                                 pvr2_hdw_cpureset_assert(hdw,0);
2656                         }
2657                         break;
2658                 }
2659
2660                 hdw->fw_cpu_flag = (prom_flag == 0);
2661                 if (hdw->fw_cpu_flag) {
2662                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2663                                    "Preparing to suck out CPU firmware");
2664                         hdw->fw_size = 0x2000;
2665                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
2666                         if (!hdw->fw_buffer) {
2667                                 hdw->fw_size = 0;
2668                                 break;
2669                         }
2670
2671                         /* We have to hold the CPU during firmware upload. */
2672                         pvr2_hdw_cpureset_assert(hdw,1);
2673
2674                         /* download the firmware from address 0000-1fff in 2048
2675                            (=0x800) bytes chunk. */
2676
2677                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2678                                    "Grabbing CPU firmware");
2679                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2680                         for(address = 0; address < hdw->fw_size;
2681                             address += 0x800) {
2682                                 ret = usb_control_msg(hdw->usb_dev,pipe,
2683                                                       0xa0,0xc0,
2684                                                       address,0,
2685                                                       hdw->fw_buffer+address,
2686                                                       0x800,HZ);
2687                                 if (ret < 0) break;
2688                         }
2689
2690                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2691                                    "Done grabbing CPU firmware");
2692                 } else {
2693                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2694                                    "Sucking down EEPROM contents");
2695                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
2696                         if (!hdw->fw_buffer) {
2697                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2698                                            "EEPROM content suck failed.");
2699                                 break;
2700                         }
2701                         hdw->fw_size = EEPROM_SIZE;
2702                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2703                                    "Done sucking down EEPROM contents");
2704                 }
2705
2706         } while (0); LOCK_GIVE(hdw->big_lock);
2707 }
2708
2709
2710 /* Return true if we're in a mode for retrieval CPU firmware */
2711 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2712 {
2713         return hdw->fw_buffer != 0;
2714 }
2715
2716
2717 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2718                        char *buf,unsigned int cnt)
2719 {
2720         int ret = -EINVAL;
2721         LOCK_TAKE(hdw->big_lock); do {
2722                 if (!buf) break;
2723                 if (!cnt) break;
2724
2725                 if (!hdw->fw_buffer) {
2726                         ret = -EIO;
2727                         break;
2728                 }
2729
2730                 if (offs >= hdw->fw_size) {
2731                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2732                                    "Read firmware data offs=%d EOF",
2733                                    offs);
2734                         ret = 0;
2735                         break;
2736                 }
2737
2738                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2739
2740                 memcpy(buf,hdw->fw_buffer+offs,cnt);
2741
2742                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2743                            "Read firmware data offs=%d cnt=%d",
2744                            offs,cnt);
2745                 ret = cnt;
2746         } while (0); LOCK_GIVE(hdw->big_lock);
2747
2748         return ret;
2749 }
2750
2751
2752 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
2753                                   enum pvr2_v4l_type index)
2754 {
2755         switch (index) {
2756         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
2757         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
2758         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
2759         default: return -1;
2760         }
2761 }
2762
2763
2764 /* Store a v4l minor device number */
2765 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
2766                                      enum pvr2_v4l_type index,int v)
2767 {
2768         switch (index) {
2769         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
2770         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
2771         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
2772         default: break;
2773         }
2774 }
2775
2776
2777 static void pvr2_ctl_write_complete(struct urb *urb)
2778 {
2779         struct pvr2_hdw *hdw = urb->context;
2780         hdw->ctl_write_pend_flag = 0;
2781         if (hdw->ctl_read_pend_flag) return;
2782         complete(&hdw->ctl_done);
2783 }
2784
2785
2786 static void pvr2_ctl_read_complete(struct urb *urb)
2787 {
2788         struct pvr2_hdw *hdw = urb->context;
2789         hdw->ctl_read_pend_flag = 0;
2790         if (hdw->ctl_write_pend_flag) return;
2791         complete(&hdw->ctl_done);
2792 }
2793
2794
2795 static void pvr2_ctl_timeout(unsigned long data)
2796 {
2797         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2798         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2799                 hdw->ctl_timeout_flag = !0;
2800                 if (hdw->ctl_write_pend_flag)
2801                         usb_unlink_urb(hdw->ctl_write_urb);
2802                 if (hdw->ctl_read_pend_flag)
2803                         usb_unlink_urb(hdw->ctl_read_urb);
2804         }
2805 }
2806
2807
2808 /* Issue a command and get a response from the device.  This extended
2809    version includes a probe flag (which if set means that device errors
2810    should not be logged or treated as fatal) and a timeout in jiffies.
2811    This can be used to non-lethally probe the health of endpoint 1. */
2812 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2813                                 unsigned int timeout,int probe_fl,
2814                                 void *write_data,unsigned int write_len,
2815                                 void *read_data,unsigned int read_len)
2816 {
2817         unsigned int idx;
2818         int status = 0;
2819         struct timer_list timer;
2820         if (!hdw->ctl_lock_held) {
2821                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2822                            "Attempted to execute control transfer"
2823                            " without lock!!");
2824                 return -EDEADLK;
2825         }
2826         if (!hdw->flag_ok && !probe_fl) {
2827                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2828                            "Attempted to execute control transfer"
2829                            " when device not ok");
2830                 return -EIO;
2831         }
2832         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2833                 if (!probe_fl) {
2834                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2835                                    "Attempted to execute control transfer"
2836                                    " when USB is disconnected");
2837                 }
2838                 return -ENOTTY;
2839         }
2840
2841         /* Ensure that we have sane parameters */
2842         if (!write_data) write_len = 0;
2843         if (!read_data) read_len = 0;
2844         if (write_len > PVR2_CTL_BUFFSIZE) {
2845                 pvr2_trace(
2846                         PVR2_TRACE_ERROR_LEGS,
2847                         "Attempted to execute %d byte"
2848                         " control-write transfer (limit=%d)",
2849                         write_len,PVR2_CTL_BUFFSIZE);
2850                 return -EINVAL;
2851         }
2852         if (read_len > PVR2_CTL_BUFFSIZE) {
2853                 pvr2_trace(
2854                         PVR2_TRACE_ERROR_LEGS,
2855                         "Attempted to execute %d byte"
2856                         " control-read transfer (limit=%d)",
2857                         write_len,PVR2_CTL_BUFFSIZE);
2858                 return -EINVAL;
2859         }
2860         if ((!write_len) && (!read_len)) {
2861                 pvr2_trace(
2862                         PVR2_TRACE_ERROR_LEGS,
2863                         "Attempted to execute null control transfer?");
2864                 return -EINVAL;
2865         }
2866
2867
2868         hdw->cmd_debug_state = 1;
2869         if (write_len) {
2870                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2871         } else {
2872                 hdw->cmd_debug_code = 0;
2873         }
2874         hdw->cmd_debug_write_len = write_len;
2875         hdw->cmd_debug_read_len = read_len;
2876
2877         /* Initialize common stuff */
2878         init_completion(&hdw->ctl_done);
2879         hdw->ctl_timeout_flag = 0;
2880         hdw->ctl_write_pend_flag = 0;
2881         hdw->ctl_read_pend_flag = 0;
2882         init_timer(&timer);
2883         timer.expires = jiffies + timeout;
2884         timer.data = (unsigned long)hdw;
2885         timer.function = pvr2_ctl_timeout;
2886
2887         if (write_len) {
2888                 hdw->cmd_debug_state = 2;
2889                 /* Transfer write data to internal buffer */
2890                 for (idx = 0; idx < write_len; idx++) {
2891                         hdw->ctl_write_buffer[idx] =
2892                                 ((unsigned char *)write_data)[idx];
2893                 }
2894                 /* Initiate a write request */
2895                 usb_fill_bulk_urb(hdw->ctl_write_urb,
2896                                   hdw->usb_dev,
2897                                   usb_sndbulkpipe(hdw->usb_dev,
2898                                                   PVR2_CTL_WRITE_ENDPOINT),
2899                                   hdw->ctl_write_buffer,
2900                                   write_len,
2901                                   pvr2_ctl_write_complete,
2902                                   hdw);
2903                 hdw->ctl_write_urb->actual_length = 0;
2904                 hdw->ctl_write_pend_flag = !0;
2905                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2906                 if (status < 0) {
2907                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2908                                    "Failed to submit write-control"
2909                                    " URB status=%d",status);
2910                         hdw->ctl_write_pend_flag = 0;
2911                         goto done;
2912                 }
2913         }
2914
2915         if (read_len) {
2916                 hdw->cmd_debug_state = 3;
2917                 memset(hdw->ctl_read_buffer,0x43,read_len);
2918                 /* Initiate a read request */
2919                 usb_fill_bulk_urb(hdw->ctl_read_urb,
2920                                   hdw->usb_dev,
2921                                   usb_rcvbulkpipe(hdw->usb_dev,
2922                                                   PVR2_CTL_READ_ENDPOINT),
2923                                   hdw->ctl_read_buffer,
2924                                   read_len,
2925                                   pvr2_ctl_read_complete,
2926                                   hdw);
2927                 hdw->ctl_read_urb->actual_length = 0;
2928                 hdw->ctl_read_pend_flag = !0;
2929                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2930                 if (status < 0) {
2931                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2932                                    "Failed to submit read-control"
2933                                    " URB status=%d",status);
2934                         hdw->ctl_read_pend_flag = 0;
2935                         goto done;
2936                 }
2937         }
2938
2939         /* Start timer */
2940         add_timer(&timer);
2941
2942         /* Now wait for all I/O to complete */
2943         hdw->cmd_debug_state = 4;
2944         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2945                 wait_for_completion(&hdw->ctl_done);
2946         }
2947         hdw->cmd_debug_state = 5;
2948
2949         /* Stop timer */
2950         del_timer_sync(&timer);
2951
2952         hdw->cmd_debug_state = 6;
2953         status = 0;
2954
2955         if (hdw->ctl_timeout_flag) {
2956                 status = -ETIMEDOUT;
2957                 if (!probe_fl) {
2958                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2959                                    "Timed out control-write");
2960                 }
2961                 goto done;
2962         }
2963
2964         if (write_len) {
2965                 /* Validate results of write request */
2966                 if ((hdw->ctl_write_urb->status != 0) &&
2967                     (hdw->ctl_write_urb->status != -ENOENT) &&
2968                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2969                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
2970                         /* USB subsystem is reporting some kind of failure
2971                            on the write */
2972                         status = hdw->ctl_write_urb->status;
2973                         if (!probe_fl) {
2974                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2975                                            "control-write URB failure,"
2976                                            " status=%d",
2977                                            status);
2978                         }
2979                         goto done;
2980                 }
2981                 if (hdw->ctl_write_urb->actual_length < write_len) {
2982                         /* Failed to write enough data */
2983                         status = -EIO;
2984                         if (!probe_fl) {
2985                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2986                                            "control-write URB short,"
2987                                            " expected=%d got=%d",
2988                                            write_len,
2989                                            hdw->ctl_write_urb->actual_length);
2990                         }
2991                         goto done;
2992                 }
2993         }
2994         if (read_len) {
2995                 /* Validate results of read request */
2996                 if ((hdw->ctl_read_urb->status != 0) &&
2997                     (hdw->ctl_read_urb->status != -ENOENT) &&
2998                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
2999                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3000                         /* USB subsystem is reporting some kind of failure
3001                            on the read */
3002                         status = hdw->ctl_read_urb->status;
3003                         if (!probe_fl) {
3004                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3005                                            "control-read URB failure,"
3006                                            " status=%d",
3007                                            status);
3008                         }
3009                         goto done;
3010                 }
3011                 if (hdw->ctl_read_urb->actual_length < read_len) {
3012                         /* Failed to read enough data */
3013                         status = -EIO;
3014                         if (!probe_fl) {
3015                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3016                                            "control-read URB short,"
3017                                            " expected=%d got=%d",
3018                                            read_len,
3019                                            hdw->ctl_read_urb->actual_length);
3020                         }
3021                         goto done;
3022                 }
3023                 /* Transfer retrieved data out from internal buffer */
3024                 for (idx = 0; idx < read_len; idx++) {
3025                         ((unsigned char *)read_data)[idx] =
3026                                 hdw->ctl_read_buffer[idx];
3027                 }
3028         }
3029
3030  done:
3031
3032         hdw->cmd_debug_state = 0;
3033         if ((status < 0) && (!probe_fl)) {
3034                 pvr2_hdw_render_useless(hdw);
3035         }
3036         return status;
3037 }
3038
3039
3040 int pvr2_send_request(struct pvr2_hdw *hdw,
3041                       void *write_data,unsigned int write_len,
3042                       void *read_data,unsigned int read_len)
3043 {
3044         return pvr2_send_request_ex(hdw,HZ*4,0,
3045                                     write_data,write_len,
3046                                     read_data,read_len);
3047 }
3048
3049 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3050 {
3051         int ret;
3052
3053         LOCK_TAKE(hdw->ctl_lock);
3054
3055         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3056         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3057         hdw->cmd_buffer[5] = 0;
3058         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3059         hdw->cmd_buffer[7] = reg & 0xff;
3060
3061
3062         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3063
3064         LOCK_GIVE(hdw->ctl_lock);
3065
3066         return ret;
3067 }
3068
3069
3070 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3071 {
3072         int ret = 0;
3073
3074         LOCK_TAKE(hdw->ctl_lock);
3075
3076         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3077         hdw->cmd_buffer[1] = 0;
3078         hdw->cmd_buffer[2] = 0;
3079         hdw->cmd_buffer[3] = 0;
3080         hdw->cmd_buffer[4] = 0;
3081         hdw->cmd_buffer[5] = 0;
3082         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3083         hdw->cmd_buffer[7] = reg & 0xff;
3084
3085         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3086         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3087
3088         LOCK_GIVE(hdw->ctl_lock);
3089
3090         return ret;
3091 }
3092
3093
3094 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3095 {
3096         if (!hdw->flag_ok) return;
3097         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3098                    "Device being rendered inoperable");
3099         if (hdw->vid_stream) {
3100                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3101         }
3102         hdw->flag_ok = 0;
3103         trace_stbit("flag_ok",hdw->flag_ok);
3104         pvr2_hdw_state_sched(hdw);
3105 }
3106
3107
3108 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3109 {
3110         int ret;
3111         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3112         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3113         if (ret == 1) {
3114                 ret = usb_reset_device(hdw->usb_dev);
3115                 usb_unlock_device(hdw->usb_dev);
3116         } else {
3117                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3118                            "Failed to lock USB device ret=%d",ret);
3119         }
3120         if (init_pause_msec) {
3121                 pvr2_trace(PVR2_TRACE_INFO,
3122                            "Waiting %u msec for hardware to settle",
3123                            init_pause_msec);
3124                 msleep(init_pause_msec);
3125         }
3126
3127 }
3128
3129
3130 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3131 {
3132         char da[1];
3133         unsigned int pipe;
3134         int ret;
3135
3136         if (!hdw->usb_dev) return;
3137
3138         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3139
3140         da[0] = val ? 0x01 : 0x00;
3141
3142         /* Write the CPUCS register on the 8051.  The lsb of the register
3143            is the reset bit; a 1 asserts reset while a 0 clears it. */
3144         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3145         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3146         if (ret < 0) {
3147                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3148                            "cpureset_assert(%d) error=%d",val,ret);
3149                 pvr2_hdw_render_useless(hdw);
3150         }
3151 }
3152
3153
3154 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3155 {
3156         int status;
3157         LOCK_TAKE(hdw->ctl_lock); do {
3158                 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
3159                 hdw->cmd_buffer[0] = FX2CMD_DEEP_RESET;
3160                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3161         } while (0); LOCK_GIVE(hdw->ctl_lock);
3162         return status;
3163 }
3164
3165
3166 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3167 {
3168         int status;
3169         LOCK_TAKE(hdw->ctl_lock); do {
3170                 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
3171                 hdw->cmd_buffer[0] = FX2CMD_POWER_ON;
3172                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3173         } while (0); LOCK_GIVE(hdw->ctl_lock);
3174         return status;
3175 }
3176
3177
3178 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3179 {
3180         if (!hdw->decoder_ctrl) {
3181                 pvr2_trace(PVR2_TRACE_INIT,
3182                            "Unable to reset decoder: nothing attached");
3183                 return -ENOTTY;
3184         }
3185
3186         if (!hdw->decoder_ctrl->force_reset) {
3187                 pvr2_trace(PVR2_TRACE_INIT,
3188                            "Unable to reset decoder: not implemented");
3189                 return -ENOTTY;
3190         }
3191
3192         pvr2_trace(PVR2_TRACE_INIT,
3193                    "Requesting decoder reset");
3194         hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3195         return 0;
3196 }
3197
3198
3199 /* Stop / start video stream transport */
3200 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
3201 {
3202         int status;
3203         LOCK_TAKE(hdw->ctl_lock); do {
3204                 hdw->cmd_buffer[0] =
3205                         (runFl ? FX2CMD_STREAMING_ON : FX2CMD_STREAMING_OFF);
3206                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3207         } while (0); LOCK_GIVE(hdw->ctl_lock);
3208         return status;
3209 }
3210
3211
3212 /* Evaluate whether or not state_encoder_ok can change */
3213 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
3214 {
3215         if (hdw->state_encoder_ok) return 0;
3216         if (hdw->flag_tripped) return 0;
3217         if (hdw->state_encoder_run) return 0;
3218         if (hdw->state_encoder_config) return 0;
3219         if (hdw->state_decoder_run) return 0;
3220         if (hdw->state_usbstream_run) return 0;
3221         if (pvr2_upload_firmware2(hdw) < 0) {
3222                 hdw->flag_tripped = !0;
3223                 trace_stbit("flag_tripped",hdw->flag_tripped);
3224                 return !0;
3225         }
3226         hdw->state_encoder_ok = !0;
3227         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
3228         return !0;
3229 }
3230
3231
3232 /* Evaluate whether or not state_encoder_config can change */
3233 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
3234 {
3235         if (hdw->state_encoder_config) {
3236                 if (hdw->state_encoder_ok) {
3237                         if (hdw->state_pipeline_req &&
3238                             !hdw->state_pipeline_pause) return 0;
3239                 }
3240                 hdw->state_encoder_config = 0;
3241                 hdw->state_encoder_waitok = 0;
3242                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3243                 /* paranoia - solve race if timer just completed */
3244                 del_timer_sync(&hdw->encoder_wait_timer);
3245         } else {
3246                 if (!hdw->state_encoder_ok ||
3247                     !hdw->state_pipeline_idle ||
3248                     hdw->state_pipeline_pause ||
3249                     !hdw->state_pipeline_req ||
3250                     !hdw->state_pipeline_config) {
3251                         /* We must reset the enforced wait interval if
3252                            anything has happened that might have disturbed
3253                            the encoder.  This should be a rare case. */
3254                         if (timer_pending(&hdw->encoder_wait_timer)) {
3255                                 del_timer_sync(&hdw->encoder_wait_timer);
3256                         }
3257                         if (hdw->state_encoder_waitok) {
3258                                 /* Must clear the state - therefore we did
3259                                    something to a state bit and must also
3260                                    return true. */
3261                                 hdw->state_encoder_waitok = 0;
3262                                 trace_stbit("state_encoder_waitok",
3263                                             hdw->state_encoder_waitok);
3264                                 return !0;
3265                         }
3266                         return 0;
3267                 }
3268                 if (!hdw->state_encoder_waitok) {
3269                         if (!timer_pending(&hdw->encoder_wait_timer)) {
3270                                 /* waitok flag wasn't set and timer isn't
3271                                    running.  Check flag once more to avoid
3272                                    a race then start the timer.  This is
3273                                    the point when we measure out a minimal
3274                                    quiet interval before doing something to
3275                                    the encoder. */
3276                                 if (!hdw->state_encoder_waitok) {
3277                                         hdw->encoder_wait_timer.expires =
3278                                                 jiffies + (HZ*50/1000);
3279                                         add_timer(&hdw->encoder_wait_timer);
3280                                 }
3281                         }
3282                         /* We can't continue until we know we have been
3283                            quiet for the interval measured by this
3284                            timer. */
3285                         return 0;
3286                 }
3287                 pvr2_encoder_configure(hdw);
3288                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
3289         }
3290         trace_stbit("state_encoder_config",hdw->state_encoder_config);
3291         return !0;
3292 }
3293
3294
3295 /* Evaluate whether or not state_encoder_run can change */
3296 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
3297 {
3298         if (hdw->state_encoder_run) {
3299                 if (hdw->state_encoder_ok) {
3300                         if (hdw->state_decoder_run) return 0;
3301                         if (pvr2_encoder_stop(hdw) < 0) return !0;
3302                 }
3303                 hdw->state_encoder_run = 0;
3304         } else {
3305                 if (!hdw->state_encoder_ok) return 0;
3306                 if (!hdw->state_decoder_run) return 0;
3307                 if (pvr2_encoder_start(hdw) < 0) return !0;
3308                 hdw->state_encoder_run = !0;
3309         }
3310         trace_stbit("state_encoder_run",hdw->state_encoder_run);
3311         return !0;
3312 }
3313
3314
3315 /* Timeout function for quiescent timer. */
3316 static void pvr2_hdw_quiescent_timeout(unsigned long data)
3317 {
3318         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3319         hdw->state_decoder_quiescent = !0;
3320         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3321         hdw->state_stale = !0;
3322         queue_work(hdw->workqueue,&hdw->workpoll);
3323 }
3324
3325
3326 /* Timeout function for encoder wait timer. */
3327 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
3328 {
3329         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3330         hdw->state_encoder_waitok = !0;
3331         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3332         hdw->state_stale = !0;
3333         queue_work(hdw->workqueue,&hdw->workpoll);
3334 }
3335
3336
3337 /* Evaluate whether or not state_decoder_run can change */
3338 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
3339 {
3340         if (hdw->state_decoder_run) {
3341                 if (hdw->state_encoder_ok) {
3342                         if (hdw->state_pipeline_req &&
3343                             !hdw->state_pipeline_pause) return 0;
3344                 }
3345                 if (!hdw->flag_decoder_missed) {
3346                         pvr2_decoder_enable(hdw,0);
3347                 }
3348                 hdw->state_decoder_quiescent = 0;
3349                 hdw->state_decoder_run = 0;
3350                 /* paranoia - solve race if timer just completed */
3351                 del_timer_sync(&hdw->quiescent_timer);
3352         } else {
3353                 if (!hdw->state_decoder_quiescent) {
3354                         if (!timer_pending(&hdw->quiescent_timer)) {
3355                                 /* We don't do something about the
3356                                    quiescent timer until right here because
3357                                    we also want to catch cases where the
3358                                    decoder was already not running (like
3359                                    after initialization) as opposed to
3360                                    knowing that we had just stopped it.
3361                                    The second flag check is here to cover a
3362                                    race - the timer could have run and set
3363                                    this flag just after the previous check
3364                                    but before we did the pending check. */
3365                                 if (!hdw->state_decoder_quiescent) {
3366                                         hdw->quiescent_timer.expires =
3367                                                 jiffies + (HZ*50/1000);
3368                                         add_timer(&hdw->quiescent_timer);
3369                                 }
3370                         }
3371                         /* Don't allow decoder to start again until it has
3372                            been quiesced first.  This little detail should
3373                            hopefully further stabilize the encoder. */
3374                         return 0;
3375                 }
3376                 if (!hdw->state_pipeline_req ||
3377                     hdw->state_pipeline_pause ||
3378                     !hdw->state_pipeline_config ||
3379                     !hdw->state_encoder_config ||
3380                     !hdw->state_encoder_ok) return 0;
3381                 del_timer_sync(&hdw->quiescent_timer);
3382                 if (hdw->flag_decoder_missed) return 0;
3383                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
3384                 hdw->state_decoder_quiescent = 0;
3385                 hdw->state_decoder_run = !0;
3386         }
3387         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3388         trace_stbit("state_decoder_run",hdw->state_decoder_run);
3389         return !0;
3390 }
3391
3392
3393 /* Evaluate whether or not state_usbstream_run can change */
3394 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
3395 {
3396         if (hdw->state_usbstream_run) {
3397                 if (hdw->state_encoder_ok) {
3398                         if (hdw->state_encoder_run) return 0;
3399                 }
3400                 pvr2_hdw_cmd_usbstream(hdw,0);
3401                 hdw->state_usbstream_run = 0;
3402         } else {
3403                 if (!hdw->state_encoder_ok ||
3404                     !hdw->state_encoder_run ||
3405                     !hdw->state_pipeline_req ||
3406                     hdw->state_pipeline_pause) return 0;
3407                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
3408                 hdw->state_usbstream_run = !0;
3409         }
3410         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
3411         return !0;
3412 }
3413
3414
3415 /* Attempt to configure pipeline, if needed */
3416 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
3417 {
3418         if (hdw->state_pipeline_config ||
3419             hdw->state_pipeline_pause) return 0;
3420         pvr2_hdw_commit_execute(hdw);
3421         return !0;
3422 }
3423
3424
3425 /* Update pipeline idle and pipeline pause tracking states based on other
3426    inputs.  This must be called whenever the other relevant inputs have
3427    changed. */
3428 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
3429 {
3430         unsigned int st;
3431         int updatedFl = 0;
3432         /* Update pipeline state */
3433         st = !(hdw->state_encoder_run ||
3434                hdw->state_decoder_run ||
3435                hdw->state_usbstream_run ||
3436                (!hdw->state_decoder_quiescent));
3437         if (!st != !hdw->state_pipeline_idle) {
3438                 hdw->state_pipeline_idle = st;
3439                 updatedFl = !0;
3440         }
3441         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
3442                 hdw->state_pipeline_pause = 0;
3443                 updatedFl = !0;
3444         }
3445         return updatedFl;
3446 }
3447
3448
3449 typedef int (*state_eval_func)(struct pvr2_hdw *);
3450
3451 /* Set of functions to be run to evaluate various states in the driver. */
3452 const static state_eval_func eval_funcs[] = {
3453         state_eval_pipeline_config,
3454         state_eval_encoder_ok,
3455         state_eval_encoder_config,
3456         state_eval_decoder_run,
3457         state_eval_encoder_run,
3458         state_eval_usbstream_run,
3459 };
3460
3461
3462 /* Process various states and return true if we did anything interesting. */
3463 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
3464 {
3465         unsigned int i;
3466         int state_updated = 0;
3467         int check_flag;
3468
3469         if (!hdw->state_stale) return 0;
3470         if ((hdw->fw1_state != FW1_STATE_OK) ||
3471             !hdw->flag_ok) {
3472                 hdw->state_stale = 0;
3473                 return !0;
3474         }
3475         /* This loop is the heart of the entire driver.  It keeps trying to
3476            evaluate various bits of driver state until nothing changes for
3477            one full iteration.  Each "bit of state" tracks some global
3478            aspect of the driver, e.g. whether decoder should run, if
3479            pipeline is configured, usb streaming is on, etc.  We separately
3480            evaluate each of those questions based on other driver state to
3481            arrive at the correct running configuration. */
3482         do {
3483                 check_flag = 0;
3484                 state_update_pipeline_state(hdw);
3485                 /* Iterate over each bit of state */
3486                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
3487                         if ((*eval_funcs[i])(hdw)) {
3488                                 check_flag = !0;
3489                                 state_updated = !0;
3490                                 state_update_pipeline_state(hdw);
3491                         }
3492                 }
3493         } while (check_flag && hdw->flag_ok);
3494         hdw->state_stale = 0;
3495         trace_stbit("state_stale",hdw->state_stale);
3496         return state_updated;
3497 }
3498
3499
3500 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
3501                                              char *buf,unsigned int acnt)
3502 {
3503         switch (which) {
3504         case 0:
3505                 return scnprintf(
3506                         buf,acnt,
3507                         "driver:%s%s%s%s%s",
3508                         (hdw->flag_ok ? " <ok>" : " <fail>"),
3509                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
3510                         (hdw->flag_disconnected ? " <disconnected>" :
3511                          " <connected>"),
3512                         (hdw->flag_tripped ? " <tripped>" : ""),
3513                         (hdw->flag_decoder_missed ? " <no decoder>" : ""));
3514         case 1:
3515                 return scnprintf(
3516                         buf,acnt,
3517                         "pipeline:%s%s%s%s",
3518                         (hdw->state_pipeline_idle ? " <idle>" : ""),
3519                         (hdw->state_pipeline_config ?
3520                          " <configok>" : " <stale>"),
3521                         (hdw->state_pipeline_req ? " <req>" : ""),
3522                         (hdw->state_pipeline_pause ? " <pause>" : ""));
3523         case 2:
3524                 return scnprintf(
3525                         buf,acnt,
3526                         "worker:%s%s%s%s%s%s",
3527                         (hdw->state_decoder_run ?
3528                          " <decode:run>" :
3529                          (hdw->state_decoder_quiescent ?
3530                           "" : " <decode:stop>")),
3531                         (hdw->state_decoder_quiescent ?
3532                          " <decode:quiescent>" : ""),
3533                         (hdw->state_encoder_ok ?
3534                          "" : " <encode:init>"),
3535                         (hdw->state_encoder_run ?
3536                          " <encode:run>" : " <encode:stop>"),
3537                         (hdw->state_encoder_config ?
3538                          " <encode:configok>" :
3539                          (hdw->state_encoder_waitok ?
3540                           "" : " <encode:wait>")),
3541                         (hdw->state_usbstream_run ?
3542                          " <usb:run>" : " <usb:stop>"));
3543                 break;
3544         case 3:
3545                 return scnprintf(
3546                         buf,acnt,
3547                         "state: %s",
3548                         pvr2_get_state_name(hdw->master_state));
3549                 break;
3550         default: break;
3551         }
3552         return 0;
3553 }
3554
3555
3556 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
3557                                    char *buf,unsigned int acnt)
3558 {
3559         unsigned int bcnt,ccnt,idx;
3560         bcnt = 0;
3561         LOCK_TAKE(hdw->big_lock);
3562         for (idx = 0; ; idx++) {
3563                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
3564                 if (!ccnt) break;
3565                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
3566                 if (!acnt) break;
3567                 buf[0] = '\n'; ccnt = 1;
3568                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
3569         }
3570         LOCK_GIVE(hdw->big_lock);
3571         return bcnt;
3572 }
3573
3574
3575 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
3576 {
3577         char buf[128];
3578         unsigned int idx,ccnt;
3579
3580         for (idx = 0; ; idx++) {
3581                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
3582                 if (!ccnt) break;
3583                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
3584         }
3585 }
3586
3587
3588 /* Evaluate and update the driver's current state, taking various actions
3589    as appropriate for the update. */
3590 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
3591 {
3592         unsigned int st;
3593         int state_updated = 0;
3594         int callback_flag = 0;
3595
3596         pvr2_trace(PVR2_TRACE_STBITS,
3597                    "Drive state check START");
3598         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
3599                 pvr2_hdw_state_log_state(hdw);
3600         }
3601
3602         /* Process all state and get back over disposition */
3603         state_updated = pvr2_hdw_state_update(hdw);
3604
3605         /* Update master state based upon all other states. */
3606         if (!hdw->flag_ok) {
3607                 st = PVR2_STATE_DEAD;
3608         } else if (hdw->fw1_state != FW1_STATE_OK) {
3609                 st = PVR2_STATE_COLD;
3610         } else if (!hdw->state_encoder_ok) {
3611                 st = PVR2_STATE_WARM;
3612         } else if (hdw->flag_tripped || hdw->flag_decoder_missed) {
3613                 st = PVR2_STATE_ERROR;
3614         } else if (hdw->state_encoder_run &&
3615                    hdw->state_decoder_run &&
3616                    hdw->state_usbstream_run) {
3617                 st = PVR2_STATE_RUN;
3618         } else {
3619                 st = PVR2_STATE_READY;
3620         }
3621         if (hdw->master_state != st) {
3622                 pvr2_trace(PVR2_TRACE_STATE,
3623                            "Device state change from %s to %s",
3624                            pvr2_get_state_name(hdw->master_state),
3625                            pvr2_get_state_name(st));
3626                 hdw->master_state = st;
3627                 state_updated = !0;
3628                 callback_flag = !0;
3629         }
3630         if (state_updated) {
3631                 /* Trigger anyone waiting on any state changes here. */
3632                 wake_up(&hdw->state_wait_data);
3633         }
3634
3635         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
3636                 pvr2_hdw_state_log_state(hdw);
3637         }
3638         pvr2_trace(PVR2_TRACE_STBITS,
3639                    "Drive state check DONE callback=%d",callback_flag);
3640
3641         return callback_flag;
3642 }
3643
3644
3645 /* Cause kernel thread to check / update driver state */
3646 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
3647 {
3648         if (hdw->state_stale) return;
3649         hdw->state_stale = !0;
3650         trace_stbit("state_stale",hdw->state_stale);
3651         queue_work(hdw->workqueue,&hdw->workpoll);
3652 }
3653
3654
3655 void pvr2_hdw_get_debug_info_unlocked(const struct pvr2_hdw *hdw,
3656                                       struct pvr2_hdw_debug_info *ptr)
3657 {
3658         ptr->big_lock_held = hdw->big_lock_held;
3659         ptr->ctl_lock_held = hdw->ctl_lock_held;
3660         ptr->flag_disconnected = hdw->flag_disconnected;
3661         ptr->flag_init_ok = hdw->flag_init_ok;
3662         ptr->flag_ok = hdw->flag_ok;
3663         ptr->fw1_state = hdw->fw1_state;
3664         ptr->flag_decoder_missed = hdw->flag_decoder_missed;
3665         ptr->flag_tripped = hdw->flag_tripped;
3666         ptr->state_encoder_ok = hdw->state_encoder_ok;
3667         ptr->state_encoder_run = hdw->state_encoder_run;
3668         ptr->state_decoder_run = hdw->state_decoder_run;
3669         ptr->state_usbstream_run = hdw->state_usbstream_run;
3670         ptr->state_decoder_quiescent = hdw->state_decoder_quiescent;
3671         ptr->state_pipeline_config = hdw->state_pipeline_config;
3672         ptr->state_pipeline_req = hdw->state_pipeline_req;
3673         ptr->state_pipeline_pause = hdw->state_pipeline_pause;
3674         ptr->state_pipeline_idle = hdw->state_pipeline_idle;
3675         ptr->cmd_debug_state = hdw->cmd_debug_state;
3676         ptr->cmd_code = hdw->cmd_debug_code;
3677         ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
3678         ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
3679         ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
3680         ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
3681         ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
3682         ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
3683         ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
3684 }
3685
3686
3687 void pvr2_hdw_get_debug_info_locked(struct pvr2_hdw *hdw,
3688                                     struct pvr2_hdw_debug_info *ptr)
3689 {
3690         LOCK_TAKE(hdw->ctl_lock); do {
3691                 pvr2_hdw_get_debug_info_unlocked(hdw,ptr);
3692         } while(0); LOCK_GIVE(hdw->ctl_lock);
3693 }
3694
3695
3696 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
3697 {
3698         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
3699 }
3700
3701
3702 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
3703 {
3704         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
3705 }
3706
3707
3708 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
3709 {
3710         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
3711 }
3712
3713
3714 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
3715 {
3716         u32 cval,nval;
3717         int ret;
3718         if (~msk) {
3719                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
3720                 if (ret) return ret;
3721                 nval = (cval & ~msk) | (val & msk);
3722                 pvr2_trace(PVR2_TRACE_GPIO,
3723                            "GPIO direction changing 0x%x:0x%x"
3724                            " from 0x%x to 0x%x",
3725                            msk,val,cval,nval);
3726         } else {
3727                 nval = val;
3728                 pvr2_trace(PVR2_TRACE_GPIO,
3729                            "GPIO direction changing to 0x%x",nval);
3730         }
3731         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
3732 }
3733
3734
3735 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
3736 {
3737         u32 cval,nval;
3738         int ret;
3739         if (~msk) {
3740                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
3741                 if (ret) return ret;
3742                 nval = (cval & ~msk) | (val & msk);
3743                 pvr2_trace(PVR2_TRACE_GPIO,
3744                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
3745                            msk,val,cval,nval);
3746         } else {
3747                 nval = val;
3748                 pvr2_trace(PVR2_TRACE_GPIO,
3749                            "GPIO output changing to 0x%x",nval);
3750         }
3751         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
3752 }
3753
3754
3755 /* Find I2C address of eeprom */
3756 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
3757 {
3758         int result;
3759         LOCK_TAKE(hdw->ctl_lock); do {
3760                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
3761                 result = pvr2_send_request(hdw,
3762                                            hdw->cmd_buffer,1,
3763                                            hdw->cmd_buffer,1);
3764                 if (result < 0) break;
3765                 result = hdw->cmd_buffer[0];
3766         } while(0); LOCK_GIVE(hdw->ctl_lock);
3767         return result;
3768 }
3769
3770
3771 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
3772                              u32 match_type, u32 match_chip, u64 reg_id,
3773                              int setFl,u64 *val_ptr)
3774 {
3775 #ifdef CONFIG_VIDEO_ADV_DEBUG
3776         struct pvr2_i2c_client *cp;
3777         struct v4l2_register req;
3778         int stat = 0;
3779         int okFl = 0;
3780
3781         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
3782
3783         req.match_type = match_type;
3784         req.match_chip = match_chip;
3785         req.reg = reg_id;
3786         if (setFl) req.val = *val_ptr;
3787         mutex_lock(&hdw->i2c_list_lock); do {
3788                 list_for_each_entry(cp, &hdw->i2c_clients, list) {
3789                         if (!v4l2_chip_match_i2c_client(
3790                                     cp->client,
3791                                     req.match_type, req.match_chip)) {
3792                                 continue;
3793                         }
3794                         stat = pvr2_i2c_client_cmd(
3795                                 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
3796                                     VIDIOC_DBG_G_REGISTER),&req);
3797                         if (!setFl) *val_ptr = req.val;
3798                         okFl = !0;
3799                         break;
3800                 }
3801         } while (0); mutex_unlock(&hdw->i2c_list_lock);
3802         if (okFl) {
3803                 return stat;
3804         }
3805         return -EINVAL;
3806 #else
3807         return -ENOSYS;
3808 #endif
3809 }
3810
3811
3812 /*
3813   Stuff for Emacs to see, in order to encourage consistent editing style:
3814   *** Local Variables: ***
3815   *** mode: c ***
3816   *** fill-column: 75 ***
3817   *** tab-width: 8 ***
3818   *** c-basic-offset: 8 ***
3819   *** End: ***
3820   */