SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  *
  19  */
  20
  21 #include <linux/errno.h>
  22 #include <linux/string.h>
  23 #include <linux/slab.h>
  24 #include <linux/firmware.h>
  25 #include <linux/videodev2.h>
  26 #include <media/v4l2-common.h>
  27 #include <media/tuner.h>
  28 #include "pvrusb2.h"
  29 #include "pvrusb2-std.h"
  30 #include "pvrusb2-util.h"
  31 #include "pvrusb2-hdw.h"
  32 #include "pvrusb2-i2c-core.h"
  33 #include "pvrusb2-i2c-track.h"
  34 #include "pvrusb2-tuner.h"
  35 #include "pvrusb2-eeprom.h"
  36 #include "pvrusb2-hdw-internal.h"
  37 #include "pvrusb2-encoder.h"
  38 #include "pvrusb2-debug.h"
  39 #include "pvrusb2-fx2-cmd.h"
  40 #include "pvrusb2-wm8775.h"
  41 #include "pvrusb2-video-v4l.h"
  42 #include "pvrusb2-cx2584x-v4l.h"
  43 #include "pvrusb2-audio.h"
  44
  45 #define TV_MIN_FREQ     55250000L
  46 #define TV_MAX_FREQ    850000000L
  47
  48 /* This defines a minimum interval that the decoder must remain quiet
  49    before we are allowed to start it running. */
  50 #define TIME_MSEC_DECODER_WAIT 50
  51
  52 /* This defines a minimum interval that the encoder must remain quiet
  53    before we are allowed to configure it.  I had this originally set to
  54    50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
  55    things work better when it's set to 100msec. */
  56 #define TIME_MSEC_ENCODER_WAIT 100
  57
  58 /* This defines the minimum interval that the encoder must successfully run
  59    before we consider that the encoder has run at least once since its
  60    firmware has been loaded.  This measurement is in important for cases
  61    where we can't do something until we know that the encoder has been run
  62    at least once. */
  63 #define TIME_MSEC_ENCODER_OK 250
  64
  65 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  66 static DEFINE_MUTEX(pvr2_unit_mtx);
  67
  68 static int ctlchg;
  69 static int procreload;
  70 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  71 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  72 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  73 static int init_pause_msec;
  74
  75 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  76 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  77 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  78 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  79 module_param(procreload, int, S_IRUGO|S_IWUSR);
  80 MODULE_PARM_DESC(procreload,
  81                  "Attempt init failure recovery with firmware reload");
  82 module_param_array(tuner,    int, NULL, 0444);
  83 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  84 module_param_array(video_std,    int, NULL, 0444);
  85 MODULE_PARM_DESC(video_std,"specify initial video standard");
  86 module_param_array(tolerance,    int, NULL, 0444);
  87 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  88
  89 /* US Broadcast channel 7 (175.25 MHz) */
  90 static int default_tv_freq    = 175250000L;
  91 /* 104.3 MHz, a usable FM station for my area */
  92 static int default_radio_freq = 104300000L;
  93
  94 module_param_named(tv_freq, default_tv_freq, int, 0444);
  95 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  96 module_param_named(radio_freq, default_radio_freq, int, 0444);
  97 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  98
  99 #define PVR2_CTL_WRITE_ENDPOINT  0x01
 100 #define PVR2_CTL_READ_ENDPOINT   0x81
 101
 102 #define PVR2_GPIO_IN 0x9008
 103 #define PVR2_GPIO_OUT 0x900c
 104 #define PVR2_GPIO_DIR 0x9020
 105
 106 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 107
 108 #define PVR2_FIRMWARE_ENDPOINT   0x02
 109
 110 /* size of a firmware chunk */
 111 #define FIRMWARE_CHUNK_SIZE 0x2000
 112
 113 typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
 114                                         struct v4l2_subdev *);
 115
 116 static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
 117         [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
 118         [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
 119         [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
 120         [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
 121 };
 122
 123 static const char *module_names[] = {
 124         [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 125         [PVR2_CLIENT_ID_CX25840] = "cx25840",
 126         [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 127         [PVR2_CLIENT_ID_TUNER] = "tuner",
 128         [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
 129         [PVR2_CLIENT_ID_WM8775] = "wm8775",
 130 };
 131
 132
 133 static const unsigned char *module_i2c_addresses[] = {
 134         [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 135         [PVR2_CLIENT_ID_MSP3400] = "\x40",
 136         [PVR2_CLIENT_ID_SAA7115] = "\x21",
 137         [PVR2_CLIENT_ID_WM8775] = "\x1b",
 138         [PVR2_CLIENT_ID_CX25840] = "\x44",
 139 };
 140
 141
 142 /* Define the list of additional controls we'll dynamically construct based
 143    on query of the cx2341x module. */
 144 struct pvr2_mpeg_ids {
 145         const char *strid;
 146         int id;
 147 };
 148 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 149         {
 150                 .strid = "audio_layer",
 151                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 152         },{
 153                 .strid = "audio_bitrate",
 154                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 155         },{
 156                 /* Already using audio_mode elsewhere :-( */
 157                 .strid = "mpeg_audio_mode",
 158                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 159         },{
 160                 .strid = "mpeg_audio_mode_extension",
 161                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 162         },{
 163                 .strid = "audio_emphasis",
 164                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 165         },{
 166                 .strid = "audio_crc",
 167                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 168         },{
 169                 .strid = "video_aspect",
 170                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 171         },{
 172                 .strid = "video_b_frames",
 173                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 174         },{
 175                 .strid = "video_gop_size",
 176                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 177         },{
 178                 .strid = "video_gop_closure",
 179                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 180         },{
 181                 .strid = "video_bitrate_mode",
 182                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 183         },{
 184                 .strid = "video_bitrate",
 185                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 186         },{
 187                 .strid = "video_bitrate_peak",
 188                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 189         },{
 190                 .strid = "video_temporal_decimation",
 191                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 192         },{
 193                 .strid = "stream_type",
 194                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 195         },{
 196                 .strid = "video_spatial_filter_mode",
 197                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 198         },{
 199                 .strid = "video_spatial_filter",
 200                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 201         },{
 202                 .strid = "video_luma_spatial_filter_type",
 203                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 204         },{
 205                 .strid = "video_chroma_spatial_filter_type",
 206                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 207         },{
 208                 .strid = "video_temporal_filter_mode",
 209                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 210         },{
 211                 .strid = "video_temporal_filter",
 212                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 213         },{
 214                 .strid = "video_median_filter_type",
 215                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 216         },{
 217                 .strid = "video_luma_median_filter_top",
 218                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 219         },{
 220                 .strid = "video_luma_median_filter_bottom",
 221                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 222         },{
 223                 .strid = "video_chroma_median_filter_top",
 224                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 225         },{
 226                 .strid = "video_chroma_median_filter_bottom",
 227                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 228         }
 229 };
 230 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 231
 232
 233 static const char *control_values_srate[] = {
 234         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 235         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 236         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 237 };
 238
 239
 240
 241 static const char *control_values_input[] = {
 242         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 243         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 244         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 245         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 246         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 247 };
 248
 249
 250 static const char *control_values_audiomode[] = {
 251         [V4L2_TUNER_MODE_MONO]   = "Mono",
 252         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 253         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 254         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 255         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 256 };
 257
 258
 259 static const char *control_values_hsm[] = {
 260         [PVR2_CVAL_HSM_FAIL] = "Fail",
 261         [PVR2_CVAL_HSM_HIGH] = "High",
 262         [PVR2_CVAL_HSM_FULL] = "Full",
 263 };
 264
 265
 266 static const char *pvr2_state_names[] = {
 267         [PVR2_STATE_NONE] =    "none",
 268         [PVR2_STATE_DEAD] =    "dead",
 269         [PVR2_STATE_COLD] =    "cold",
 270         [PVR2_STATE_WARM] =    "warm",
 271         [PVR2_STATE_ERROR] =   "error",
 272         [PVR2_STATE_READY] =   "ready",
 273         [PVR2_STATE_RUN] =     "run",
 274 };
 275
 276
 277 struct pvr2_fx2cmd_descdef {
 278         unsigned char id;
 279         unsigned char *desc;
 280 };
 281
 282 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 283         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 284         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 285         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 286         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 287         {FX2CMD_REG_WRITE, "write encoder register"},
 288         {FX2CMD_REG_READ, "read encoder register"},
 289         {FX2CMD_MEMSEL, "encoder memsel"},
 290         {FX2CMD_I2C_WRITE, "i2c write"},
 291         {FX2CMD_I2C_READ, "i2c read"},
 292         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 293         {FX2CMD_STREAMING_ON, "stream on"},
 294         {FX2CMD_STREAMING_OFF, "stream off"},
 295         {FX2CMD_FWPOST1, "fwpost1"},
 296         {FX2CMD_POWER_OFF, "power off"},
 297         {FX2CMD_POWER_ON, "power on"},
 298         {FX2CMD_DEEP_RESET, "deep reset"},
 299         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 300         {FX2CMD_GET_IR_CODE, "get IR code"},
 301         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 302         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 303         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 304         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 305         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 306         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 307         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 308 };
 309
 310
 311 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 312 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 313 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 314 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 315 static void pvr2_hdw_worker_i2c(struct work_struct *work);
 316 static void pvr2_hdw_worker_poll(struct work_struct *work);
 317 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 318 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 319 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 320 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 321 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 322 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 323 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 324 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 325 static void pvr2_hdw_quiescent_timeout(unsigned long);
 326 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 327 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 328 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 329 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 330                                 unsigned int timeout,int probe_fl,
 331                                 void *write_data,unsigned int write_len,
 332                                 void *read_data,unsigned int read_len);
 333 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 334
 335
 336 static void trace_stbit(const char *name,int val)
 337 {
 338         pvr2_trace(PVR2_TRACE_STBITS,
 339                    "State bit %s <-- %s",
 340                    name,(val ? "true" : "false"));
 341 }
 342
 343 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 344 {
 345         struct pvr2_hdw *hdw = cptr->hdw;
 346         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 347                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 348         } else {
 349                 *vp = 0;
 350         }
 351         return 0;
 352 }
 353
 354 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 355 {
 356         struct pvr2_hdw *hdw = cptr->hdw;
 357         unsigned int slotId = hdw->freqProgSlot;
 358         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 359                 hdw->freqTable[slotId-1] = v;
 360                 /* Handle side effects correctly - if we're tuned to this
 361                    slot, then forgot the slot id relation since the stored
 362                    frequency has been changed. */
 363                 if (hdw->freqSelector) {
 364                         if (hdw->freqSlotRadio == slotId) {
 365                                 hdw->freqSlotRadio = 0;
 366                         }
 367                 } else {
 368                         if (hdw->freqSlotTelevision == slotId) {
 369                                 hdw->freqSlotTelevision = 0;
 370                         }
 371                 }
 372         }
 373         return 0;
 374 }
 375
 376 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 377 {
 378         *vp = cptr->hdw->freqProgSlot;
 379         return 0;
 380 }
 381
 382 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 383 {
 384         struct pvr2_hdw *hdw = cptr->hdw;
 385         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 386                 hdw->freqProgSlot = v;
 387         }
 388         return 0;
 389 }
 390
 391 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 392 {
 393         struct pvr2_hdw *hdw = cptr->hdw;
 394         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 395         return 0;
 396 }
 397
 398 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 399 {
 400         unsigned freq = 0;
 401         struct pvr2_hdw *hdw = cptr->hdw;
 402         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 403         if (slotId > 0) {
 404                 freq = hdw->freqTable[slotId-1];
 405                 if (!freq) return 0;
 406                 pvr2_hdw_set_cur_freq(hdw,freq);
 407         }
 408         if (hdw->freqSelector) {
 409                 hdw->freqSlotRadio = slotId;
 410         } else {
 411                 hdw->freqSlotTelevision = slotId;
 412         }
 413         return 0;
 414 }
 415
 416 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 417 {
 418         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 419         return 0;
 420 }
 421
 422 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 423 {
 424         return cptr->hdw->freqDirty != 0;
 425 }
 426
 427 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 428 {
 429         cptr->hdw->freqDirty = 0;
 430 }
 431
 432 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 433 {
 434         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 435         return 0;
 436 }
 437
 438 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 439 {
 440         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 441         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 442         if (stat != 0) {
 443                 return stat;
 444         }
 445         *left = cap->bounds.left;
 446         return 0;
 447 }
 448
 449 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 450 {
 451         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 452         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 453         if (stat != 0) {
 454                 return stat;
 455         }
 456         *left = cap->bounds.left;
 457         if (cap->bounds.width > cptr->hdw->cropw_val) {
 458                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 459         }
 460         return 0;
 461 }
 462
 463 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 464 {
 465         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 466         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 467         if (stat != 0) {
 468                 return stat;
 469         }
 470         *top = cap->bounds.top;
 471         return 0;
 472 }
 473
 474 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 475 {
 476         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 477         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 478         if (stat != 0) {
 479                 return stat;
 480         }
 481         *top = cap->bounds.top;
 482         if (cap->bounds.height > cptr->hdw->croph_val) {
 483                 *top += cap->bounds.height - cptr->hdw->croph_val;
 484         }
 485         return 0;
 486 }
 487
 488 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
 489 {
 490         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 491         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 492         if (stat != 0) {
 493                 return stat;
 494         }
 495         *val = 0;
 496         if (cap->bounds.width > cptr->hdw->cropl_val) {
 497                 *val = cap->bounds.width - cptr->hdw->cropl_val;
 498         }
 499         return 0;
 500 }
 501
 502 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
 503 {
 504         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 505         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 506         if (stat != 0) {
 507                 return stat;
 508         }
 509         *val = 0;
 510         if (cap->bounds.height > cptr->hdw->cropt_val) {
 511                 *val = cap->bounds.height - cptr->hdw->cropt_val;
 512         }
 513         return 0;
 514 }
 515
 516 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 517 {
 518         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 519         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 520         if (stat != 0) {
 521                 return stat;
 522         }
 523         *val = cap->bounds.left;
 524         return 0;
 525 }
 526
 527 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 528 {
 529         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 530         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 531         if (stat != 0) {
 532                 return stat;
 533         }
 534         *val = cap->bounds.top;
 535         return 0;
 536 }
 537
 538 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 539 {
 540         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 541         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 542         if (stat != 0) {
 543                 return stat;
 544         }
 545         *val = cap->bounds.width;
 546         return 0;
 547 }
 548
 549 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 550 {
 551         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 552         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 553         if (stat != 0) {
 554                 return stat;
 555         }
 556         *val = cap->bounds.height;
 557         return 0;
 558 }
 559
 560 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 561 {
 562         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 563         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 564         if (stat != 0) {
 565                 return stat;
 566         }
 567         *val = cap->defrect.left;
 568         return 0;
 569 }
 570
 571 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 572 {
 573         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 574         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 575         if (stat != 0) {
 576                 return stat;
 577         }
 578         *val = cap->defrect.top;
 579         return 0;
 580 }
 581
 582 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 583 {
 584         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 585         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 586         if (stat != 0) {
 587                 return stat;
 588         }
 589         *val = cap->defrect.width;
 590         return 0;
 591 }
 592
 593 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 594 {
 595         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 596         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 597         if (stat != 0) {
 598                 return stat;
 599         }
 600         *val = cap->defrect.height;
 601         return 0;
 602 }
 603
 604 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 605 {
 606         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 607         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 608         if (stat != 0) {
 609                 return stat;
 610         }
 611         *val = cap->pixelaspect.numerator;
 612         return 0;
 613 }
 614
 615 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 616 {
 617         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 618         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 619         if (stat != 0) {
 620                 return stat;
 621         }
 622         *val = cap->pixelaspect.denominator;
 623         return 0;
 624 }
 625
 626 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 627 {
 628         /* Actual maximum depends on the video standard in effect. */
 629         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 630                 *vp = 480;
 631         } else {
 632                 *vp = 576;
 633         }
 634         return 0;
 635 }
 636
 637 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 638 {
 639         /* Actual minimum depends on device digitizer type. */
 640         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 641                 *vp = 75;
 642         } else {
 643                 *vp = 17;
 644         }
 645         return 0;
 646 }
 647
 648 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 649 {
 650         *vp = cptr->hdw->input_val;
 651         return 0;
 652 }
 653
 654 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 655 {
 656         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 657 }
 658
 659 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 660 {
 661         return pvr2_hdw_set_input(cptr->hdw,v);
 662 }
 663
 664 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 665 {
 666         return cptr->hdw->input_dirty != 0;
 667 }
 668
 669 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 670 {
 671         cptr->hdw->input_dirty = 0;
 672 }
 673
 674
 675 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 676 {
 677         unsigned long fv;
 678         struct pvr2_hdw *hdw = cptr->hdw;
 679         if (hdw->tuner_signal_stale) {
 680                 pvr2_hdw_status_poll(hdw);
 681         }
 682         fv = hdw->tuner_signal_info.rangehigh;
 683         if (!fv) {
 684                 /* Safety fallback */
 685                 *vp = TV_MAX_FREQ;
 686                 return 0;
 687         }
 688         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 689                 fv = (fv * 125) / 2;
 690         } else {
 691                 fv = fv * 62500;
 692         }
 693         *vp = fv;
 694         return 0;
 695 }
 696
 697 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 698 {
 699         unsigned long fv;
 700         struct pvr2_hdw *hdw = cptr->hdw;
 701         if (hdw->tuner_signal_stale) {
 702                 pvr2_hdw_status_poll(hdw);
 703         }
 704         fv = hdw->tuner_signal_info.rangelow;
 705         if (!fv) {
 706                 /* Safety fallback */
 707                 *vp = TV_MIN_FREQ;
 708                 return 0;
 709         }
 710         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 711                 fv = (fv * 125) / 2;
 712         } else {
 713                 fv = fv * 62500;
 714         }
 715         *vp = fv;
 716         return 0;
 717 }
 718
 719 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 720 {
 721         return cptr->hdw->enc_stale != 0;
 722 }
 723
 724 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 725 {
 726         cptr->hdw->enc_stale = 0;
 727         cptr->hdw->enc_unsafe_stale = 0;
 728 }
 729
 730 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 731 {
 732         int ret;
 733         struct v4l2_ext_controls cs;
 734         struct v4l2_ext_control c1;
 735         memset(&cs,0,sizeof(cs));
 736         memset(&c1,0,sizeof(c1));
 737         cs.controls = &c1;
 738         cs.count = 1;
 739         c1.id = cptr->info->v4l_id;
 740         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 741                                 VIDIOC_G_EXT_CTRLS);
 742         if (ret) return ret;
 743         *vp = c1.value;
 744         return 0;
 745 }
 746
 747 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 748 {
 749         int ret;
 750         struct pvr2_hdw *hdw = cptr->hdw;
 751         struct v4l2_ext_controls cs;
 752         struct v4l2_ext_control c1;
 753         memset(&cs,0,sizeof(cs));
 754         memset(&c1,0,sizeof(c1));
 755         cs.controls = &c1;
 756         cs.count = 1;
 757         c1.id = cptr->info->v4l_id;
 758         c1.value = v;
 759         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 760                                 hdw->state_encoder_run, &cs,
 761                                 VIDIOC_S_EXT_CTRLS);
 762         if (ret == -EBUSY) {
 763                 /* Oops.  cx2341x is telling us it's not safe to change
 764                    this control while we're capturing.  Make a note of this
 765                    fact so that the pipeline will be stopped the next time
 766                    controls are committed.  Then go on ahead and store this
 767                    change anyway. */
 768                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 769                                         0, &cs,
 770                                         VIDIOC_S_EXT_CTRLS);
 771                 if (!ret) hdw->enc_unsafe_stale = !0;
 772         }
 773         if (ret) return ret;
 774         hdw->enc_stale = !0;
 775         return 0;
 776 }
 777
 778 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 779 {
 780         struct v4l2_queryctrl qctrl;
 781         struct pvr2_ctl_info *info;
 782         qctrl.id = cptr->info->v4l_id;
 783         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 784         /* Strip out the const so we can adjust a function pointer.  It's
 785            OK to do this here because we know this is a dynamically created
 786            control, so the underlying storage for the info pointer is (a)
 787            private to us, and (b) not in read-only storage.  Either we do
 788            this or we significantly complicate the underlying control
 789            implementation. */
 790         info = (struct pvr2_ctl_info *)(cptr->info);
 791         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 792                 if (info->set_value) {
 793                         info->set_value = NULL;
 794                 }
 795         } else {
 796                 if (!(info->set_value)) {
 797                         info->set_value = ctrl_cx2341x_set;
 798                 }
 799         }
 800         return qctrl.flags;
 801 }
 802
 803 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 804 {
 805         *vp = cptr->hdw->state_pipeline_req;
 806         return 0;
 807 }
 808
 809 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 810 {
 811         *vp = cptr->hdw->master_state;
 812         return 0;
 813 }
 814
 815 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 816 {
 817         int result = pvr2_hdw_is_hsm(cptr->hdw);
 818         *vp = PVR2_CVAL_HSM_FULL;
 819         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 820         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 821         return 0;
 822 }
 823
 824 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 825 {
 826         *vp = cptr->hdw->std_mask_avail;
 827         return 0;
 828 }
 829
 830 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 831 {
 832         struct pvr2_hdw *hdw = cptr->hdw;
 833         v4l2_std_id ns;
 834         ns = hdw->std_mask_avail;
 835         ns = (ns & ~m) | (v & m);
 836         if (ns == hdw->std_mask_avail) return 0;
 837         hdw->std_mask_avail = ns;
 838         pvr2_hdw_internal_set_std_avail(hdw);
 839         pvr2_hdw_internal_find_stdenum(hdw);
 840         return 0;
 841 }
 842
 843 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 844                                char *bufPtr,unsigned int bufSize,
 845                                unsigned int *len)
 846 {
 847         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 848         return 0;
 849 }
 850
 851 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 852                                const char *bufPtr,unsigned int bufSize,
 853                                int *mskp,int *valp)
 854 {
 855         int ret;
 856         v4l2_std_id id;
 857         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 858         if (ret < 0) return ret;
 859         if (mskp) *mskp = id;
 860         if (valp) *valp = id;
 861         return 0;
 862 }
 863
 864 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 865 {
 866         *vp = cptr->hdw->std_mask_cur;
 867         return 0;
 868 }
 869
 870 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 871 {
 872         struct pvr2_hdw *hdw = cptr->hdw;
 873         v4l2_std_id ns;
 874         ns = hdw->std_mask_cur;
 875         ns = (ns & ~m) | (v & m);
 876         if (ns == hdw->std_mask_cur) return 0;
 877         hdw->std_mask_cur = ns;
 878         hdw->std_dirty = !0;
 879         pvr2_hdw_internal_find_stdenum(hdw);
 880         return 0;
 881 }
 882
 883 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 884 {
 885         return cptr->hdw->std_dirty != 0;
 886 }
 887
 888 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 889 {
 890         cptr->hdw->std_dirty = 0;
 891 }
 892
 893 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 894 {
 895         struct pvr2_hdw *hdw = cptr->hdw;
 896         pvr2_hdw_status_poll(hdw);
 897         *vp = hdw->tuner_signal_info.signal;
 898         return 0;
 899 }
 900
 901 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 902 {
 903         int val = 0;
 904         unsigned int subchan;
 905         struct pvr2_hdw *hdw = cptr->hdw;
 906         pvr2_hdw_status_poll(hdw);
 907         subchan = hdw->tuner_signal_info.rxsubchans;
 908         if (subchan & V4L2_TUNER_SUB_MONO) {
 909                 val |= (1 << V4L2_TUNER_MODE_MONO);
 910         }
 911         if (subchan & V4L2_TUNER_SUB_STEREO) {
 912                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 913         }
 914         if (subchan & V4L2_TUNER_SUB_LANG1) {
 915                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 916         }
 917         if (subchan & V4L2_TUNER_SUB_LANG2) {
 918                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 919         }
 920         *vp = val;
 921         return 0;
 922 }
 923
 924
 925 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 926 {
 927         struct pvr2_hdw *hdw = cptr->hdw;
 928         if (v < 0) return -EINVAL;
 929         if (v > hdw->std_enum_cnt) return -EINVAL;
 930         hdw->std_enum_cur = v;
 931         if (!v) return 0;
 932         v--;
 933         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 934         hdw->std_mask_cur = hdw->std_defs[v].id;
 935         hdw->std_dirty = !0;
 936         return 0;
 937 }
 938
 939
 940 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 941 {
 942         *vp = cptr->hdw->std_enum_cur;
 943         return 0;
 944 }
 945
 946
 947 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 948 {
 949         return cptr->hdw->std_dirty != 0;
 950 }
 951
 952
 953 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 954 {
 955         cptr->hdw->std_dirty = 0;
 956 }
 957
 958
 959 #define DEFINT(vmin,vmax) \
 960         .type = pvr2_ctl_int, \
 961         .def.type_int.min_value = vmin, \
 962         .def.type_int.max_value = vmax
 963
 964 #define DEFENUM(tab) \
 965         .type = pvr2_ctl_enum, \
 966         .def.type_enum.count = ARRAY_SIZE(tab), \
 967         .def.type_enum.value_names = tab
 968
 969 #define DEFBOOL \
 970         .type = pvr2_ctl_bool
 971
 972 #define DEFMASK(msk,tab) \
 973         .type = pvr2_ctl_bitmask, \
 974         .def.type_bitmask.valid_bits = msk, \
 975         .def.type_bitmask.bit_names = tab
 976
 977 #define DEFREF(vname) \
 978         .set_value = ctrl_set_##vname, \
 979         .get_value = ctrl_get_##vname, \
 980         .is_dirty = ctrl_isdirty_##vname, \
 981         .clear_dirty = ctrl_cleardirty_##vname
 982
 983
 984 #define VCREATE_FUNCS(vname) \
 985 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 986 {*vp = cptr->hdw->vname##_val; return 0;} \
 987 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 988 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 989 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 990 {return cptr->hdw->vname##_dirty != 0;} \
 991 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 992 {cptr->hdw->vname##_dirty = 0;}
 993
 994 VCREATE_FUNCS(brightness)
 995 VCREATE_FUNCS(contrast)
 996 VCREATE_FUNCS(saturation)
 997 VCREATE_FUNCS(hue)
 998 VCREATE_FUNCS(volume)
 999 VCREATE_FUNCS(balance)
1000 VCREATE_FUNCS(bass)
1001 VCREATE_FUNCS(treble)
1002 VCREATE_FUNCS(mute)
1003 VCREATE_FUNCS(cropl)
1004 VCREATE_FUNCS(cropt)
1005 VCREATE_FUNCS(cropw)
1006 VCREATE_FUNCS(croph)
1007 VCREATE_FUNCS(audiomode)
1008 VCREATE_FUNCS(res_hor)
1009 VCREATE_FUNCS(res_ver)
1010 VCREATE_FUNCS(srate)
1011
1012 /* Table definition of all controls which can be manipulated */
1013 static const struct pvr2_ctl_info control_defs[] = {
1014         {
1015                 .v4l_id = V4L2_CID_BRIGHTNESS,
1016                 .desc = "Brightness",
1017                 .name = "brightness",
1018                 .default_value = 128,
1019                 DEFREF(brightness),
1020                 DEFINT(0,255),
1021         },{
1022                 .v4l_id = V4L2_CID_CONTRAST,
1023                 .desc = "Contrast",
1024                 .name = "contrast",
1025                 .default_value = 68,
1026                 DEFREF(contrast),
1027                 DEFINT(0,127),
1028         },{
1029                 .v4l_id = V4L2_CID_SATURATION,
1030                 .desc = "Saturation",
1031                 .name = "saturation",
1032                 .default_value = 64,
1033                 DEFREF(saturation),
1034                 DEFINT(0,127),
1035         },{
1036                 .v4l_id = V4L2_CID_HUE,
1037                 .desc = "Hue",
1038                 .name = "hue",
1039                 .default_value = 0,
1040                 DEFREF(hue),
1041                 DEFINT(-128,127),
1042         },{
1043                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1044                 .desc = "Volume",
1045                 .name = "volume",
1046                 .default_value = 62000,
1047                 DEFREF(volume),
1048                 DEFINT(0,65535),
1049         },{
1050                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1051                 .desc = "Balance",
1052                 .name = "balance",
1053                 .default_value = 0,
1054                 DEFREF(balance),
1055                 DEFINT(-32768,32767),
1056         },{
1057                 .v4l_id = V4L2_CID_AUDIO_BASS,
1058                 .desc = "Bass",
1059                 .name = "bass",
1060                 .default_value = 0,
1061                 DEFREF(bass),
1062                 DEFINT(-32768,32767),
1063         },{
1064                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1065                 .desc = "Treble",
1066                 .name = "treble",
1067                 .default_value = 0,
1068                 DEFREF(treble),
1069                 DEFINT(-32768,32767),
1070         },{
1071                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1072                 .desc = "Mute",
1073                 .name = "mute",
1074                 .default_value = 0,
1075                 DEFREF(mute),
1076                 DEFBOOL,
1077         }, {
1078                 .desc = "Capture crop left margin",
1079                 .name = "crop_left",
1080                 .internal_id = PVR2_CID_CROPL,
1081                 .default_value = 0,
1082                 DEFREF(cropl),
1083                 DEFINT(-129, 340),
1084                 .get_min_value = ctrl_cropl_min_get,
1085                 .get_max_value = ctrl_cropl_max_get,
1086                 .get_def_value = ctrl_get_cropcapdl,
1087         }, {
1088                 .desc = "Capture crop top margin",
1089                 .name = "crop_top",
1090                 .internal_id = PVR2_CID_CROPT,
1091                 .default_value = 0,
1092                 DEFREF(cropt),
1093                 DEFINT(-35, 544),
1094                 .get_min_value = ctrl_cropt_min_get,
1095                 .get_max_value = ctrl_cropt_max_get,
1096                 .get_def_value = ctrl_get_cropcapdt,
1097         }, {
1098                 .desc = "Capture crop width",
1099                 .name = "crop_width",
1100                 .internal_id = PVR2_CID_CROPW,
1101                 .default_value = 720,
1102                 DEFREF(cropw),
1103                 .get_max_value = ctrl_cropw_max_get,
1104                 .get_def_value = ctrl_get_cropcapdw,
1105         }, {
1106                 .desc = "Capture crop height",
1107                 .name = "crop_height",
1108                 .internal_id = PVR2_CID_CROPH,
1109                 .default_value = 480,
1110                 DEFREF(croph),
1111                 .get_max_value = ctrl_croph_max_get,
1112                 .get_def_value = ctrl_get_cropcapdh,
1113         }, {
1114                 .desc = "Capture capability pixel aspect numerator",
1115                 .name = "cropcap_pixel_numerator",
1116                 .internal_id = PVR2_CID_CROPCAPPAN,
1117                 .get_value = ctrl_get_cropcappan,
1118         }, {
1119                 .desc = "Capture capability pixel aspect denominator",
1120                 .name = "cropcap_pixel_denominator",
1121                 .internal_id = PVR2_CID_CROPCAPPAD,
1122                 .get_value = ctrl_get_cropcappad,
1123         }, {
1124                 .desc = "Capture capability bounds top",
1125                 .name = "cropcap_bounds_top",
1126                 .internal_id = PVR2_CID_CROPCAPBT,
1127                 .get_value = ctrl_get_cropcapbt,
1128         }, {
1129                 .desc = "Capture capability bounds left",
1130                 .name = "cropcap_bounds_left",
1131                 .internal_id = PVR2_CID_CROPCAPBL,
1132                 .get_value = ctrl_get_cropcapbl,
1133         }, {
1134                 .desc = "Capture capability bounds width",
1135                 .name = "cropcap_bounds_width",
1136                 .internal_id = PVR2_CID_CROPCAPBW,
1137                 .get_value = ctrl_get_cropcapbw,
1138         }, {
1139                 .desc = "Capture capability bounds height",
1140                 .name = "cropcap_bounds_height",
1141                 .internal_id = PVR2_CID_CROPCAPBH,
1142                 .get_value = ctrl_get_cropcapbh,
1143         },{
1144                 .desc = "Video Source",
1145                 .name = "input",
1146                 .internal_id = PVR2_CID_INPUT,
1147                 .default_value = PVR2_CVAL_INPUT_TV,
1148                 .check_value = ctrl_check_input,
1149                 DEFREF(input),
1150                 DEFENUM(control_values_input),
1151         },{
1152                 .desc = "Audio Mode",
1153                 .name = "audio_mode",
1154                 .internal_id = PVR2_CID_AUDIOMODE,
1155                 .default_value = V4L2_TUNER_MODE_STEREO,
1156                 DEFREF(audiomode),
1157                 DEFENUM(control_values_audiomode),
1158         },{
1159                 .desc = "Horizontal capture resolution",
1160                 .name = "resolution_hor",
1161                 .internal_id = PVR2_CID_HRES,
1162                 .default_value = 720,
1163                 DEFREF(res_hor),
1164                 DEFINT(19,720),
1165         },{
1166                 .desc = "Vertical capture resolution",
1167                 .name = "resolution_ver",
1168                 .internal_id = PVR2_CID_VRES,
1169                 .default_value = 480,
1170                 DEFREF(res_ver),
1171                 DEFINT(17,576),
1172                 /* Hook in check for video standard and adjust maximum
1173                    depending on the standard. */
1174                 .get_max_value = ctrl_vres_max_get,
1175                 .get_min_value = ctrl_vres_min_get,
1176         },{
1177                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1178                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1179                 .desc = "Audio Sampling Frequency",
1180                 .name = "srate",
1181                 DEFREF(srate),
1182                 DEFENUM(control_values_srate),
1183         },{
1184                 .desc = "Tuner Frequency (Hz)",
1185                 .name = "frequency",
1186                 .internal_id = PVR2_CID_FREQUENCY,
1187                 .default_value = 0,
1188                 .set_value = ctrl_freq_set,
1189                 .get_value = ctrl_freq_get,
1190                 .is_dirty = ctrl_freq_is_dirty,
1191                 .clear_dirty = ctrl_freq_clear_dirty,
1192                 DEFINT(0,0),
1193                 /* Hook in check for input value (tv/radio) and adjust
1194                    max/min values accordingly */
1195                 .get_max_value = ctrl_freq_max_get,
1196                 .get_min_value = ctrl_freq_min_get,
1197         },{
1198                 .desc = "Channel",
1199                 .name = "channel",
1200                 .set_value = ctrl_channel_set,
1201                 .get_value = ctrl_channel_get,
1202                 DEFINT(0,FREQTABLE_SIZE),
1203         },{
1204                 .desc = "Channel Program Frequency",
1205                 .name = "freq_table_value",
1206                 .set_value = ctrl_channelfreq_set,
1207                 .get_value = ctrl_channelfreq_get,
1208                 DEFINT(0,0),
1209                 /* Hook in check for input value (tv/radio) and adjust
1210                    max/min values accordingly */
1211                 .get_max_value = ctrl_freq_max_get,
1212                 .get_min_value = ctrl_freq_min_get,
1213         },{
1214                 .desc = "Channel Program ID",
1215                 .name = "freq_table_channel",
1216                 .set_value = ctrl_channelprog_set,
1217                 .get_value = ctrl_channelprog_get,
1218                 DEFINT(0,FREQTABLE_SIZE),
1219         },{
1220                 .desc = "Streaming Enabled",
1221                 .name = "streaming_enabled",
1222                 .get_value = ctrl_streamingenabled_get,
1223                 DEFBOOL,
1224         },{
1225                 .desc = "USB Speed",
1226                 .name = "usb_speed",
1227                 .get_value = ctrl_hsm_get,
1228                 DEFENUM(control_values_hsm),
1229         },{
1230                 .desc = "Master State",
1231                 .name = "master_state",
1232                 .get_value = ctrl_masterstate_get,
1233                 DEFENUM(pvr2_state_names),
1234         },{
1235                 .desc = "Signal Present",
1236                 .name = "signal_present",
1237                 .get_value = ctrl_signal_get,
1238                 DEFINT(0,65535),
1239         },{
1240                 .desc = "Audio Modes Present",
1241                 .name = "audio_modes_present",
1242                 .get_value = ctrl_audio_modes_present_get,
1243                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1244                    v4l.  Nothing outside of this module cares about this,
1245                    but I reuse it in order to also reuse the
1246                    control_values_audiomode string table. */
1247                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1248                          (1 << V4L2_TUNER_MODE_STEREO)|
1249                          (1 << V4L2_TUNER_MODE_LANG1)|
1250                          (1 << V4L2_TUNER_MODE_LANG2)),
1251                         control_values_audiomode),
1252         },{
1253                 .desc = "Video Standards Available Mask",
1254                 .name = "video_standard_mask_available",
1255                 .internal_id = PVR2_CID_STDAVAIL,
1256                 .skip_init = !0,
1257                 .get_value = ctrl_stdavail_get,
1258                 .set_value = ctrl_stdavail_set,
1259                 .val_to_sym = ctrl_std_val_to_sym,
1260                 .sym_to_val = ctrl_std_sym_to_val,
1261                 .type = pvr2_ctl_bitmask,
1262         },{
1263                 .desc = "Video Standards In Use Mask",
1264                 .name = "video_standard_mask_active",
1265                 .internal_id = PVR2_CID_STDCUR,
1266                 .skip_init = !0,
1267                 .get_value = ctrl_stdcur_get,
1268                 .set_value = ctrl_stdcur_set,
1269                 .is_dirty = ctrl_stdcur_is_dirty,
1270                 .clear_dirty = ctrl_stdcur_clear_dirty,
1271                 .val_to_sym = ctrl_std_val_to_sym,
1272                 .sym_to_val = ctrl_std_sym_to_val,
1273                 .type = pvr2_ctl_bitmask,
1274         },{
1275                 .desc = "Video Standard Name",
1276                 .name = "video_standard",
1277                 .internal_id = PVR2_CID_STDENUM,
1278                 .skip_init = !0,
1279                 .get_value = ctrl_stdenumcur_get,
1280                 .set_value = ctrl_stdenumcur_set,
1281                 .is_dirty = ctrl_stdenumcur_is_dirty,
1282                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1283                 .type = pvr2_ctl_enum,
1284         }
1285 };
1286
1287 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1288
1289
1290 const char *pvr2_config_get_name(enum pvr2_config cfg)
1291 {
1292         switch (cfg) {
1293         case pvr2_config_empty: return "empty";
1294         case pvr2_config_mpeg: return "mpeg";
1295         case pvr2_config_vbi: return "vbi";
1296         case pvr2_config_pcm: return "pcm";
1297         case pvr2_config_rawvideo: return "raw video";
1298         }
1299         return "<unknown>";
1300 }
1301
1302
1303 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1304 {
1305         return hdw->usb_dev;
1306 }
1307
1308
1309 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1310 {
1311         return hdw->serial_number;
1312 }
1313
1314
1315 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1316 {
1317         return hdw->bus_info;
1318 }
1319
1320
1321 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1322 {
1323         return hdw->identifier;
1324 }
1325
1326
1327 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1328 {
1329         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1330 }
1331
1332 /* Set the currently tuned frequency and account for all possible
1333    driver-core side effects of this action. */
1334 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1335 {
1336         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1337                 if (hdw->freqSelector) {
1338                         /* Swing over to radio frequency selection */
1339                         hdw->freqSelector = 0;
1340                         hdw->freqDirty = !0;
1341                 }
1342                 if (hdw->freqValRadio != val) {
1343                         hdw->freqValRadio = val;
1344                         hdw->freqSlotRadio = 0;
1345                         hdw->freqDirty = !0;
1346                 }
1347         } else {
1348                 if (!(hdw->freqSelector)) {
1349                         /* Swing over to television frequency selection */
1350                         hdw->freqSelector = 1;
1351                         hdw->freqDirty = !0;
1352                 }
1353                 if (hdw->freqValTelevision != val) {
1354                         hdw->freqValTelevision = val;
1355                         hdw->freqSlotTelevision = 0;
1356                         hdw->freqDirty = !0;
1357                 }
1358         }
1359 }
1360
1361 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1362 {
1363         return hdw->unit_number;
1364 }
1365
1366
1367 /* Attempt to locate one of the given set of files.  Messages are logged
1368    appropriate to what has been found.  The return value will be 0 or
1369    greater on success (it will be the index of the file name found) and
1370    fw_entry will be filled in.  Otherwise a negative error is returned on
1371    failure.  If the return value is -ENOENT then no viable firmware file
1372    could be located. */
1373 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1374                                 const struct firmware **fw_entry,
1375                                 const char *fwtypename,
1376                                 unsigned int fwcount,
1377                                 const char *fwnames[])
1378 {
1379         unsigned int idx;
1380         int ret = -EINVAL;
1381         for (idx = 0; idx < fwcount; idx++) {
1382                 ret = request_firmware(fw_entry,
1383                                        fwnames[idx],
1384                                        &hdw->usb_dev->dev);
1385                 if (!ret) {
1386                         trace_firmware("Located %s firmware: %s;"
1387                                        " uploading...",
1388                                        fwtypename,
1389                                        fwnames[idx]);
1390                         return idx;
1391                 }
1392                 if (ret == -ENOENT) continue;
1393                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1394                            "request_firmware fatal error with code=%d",ret);
1395                 return ret;
1396         }
1397         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1398                    "***WARNING***"
1399                    " Device %s firmware"
1400                    " seems to be missing.",
1401                    fwtypename);
1402         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1403                    "Did you install the pvrusb2 firmware files"
1404                    " in their proper location?");
1405         if (fwcount == 1) {
1406                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1407                            "request_firmware unable to locate %s file %s",
1408                            fwtypename,fwnames[0]);
1409         } else {
1410                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1411                            "request_firmware unable to locate"
1412                            " one of the following %s files:",
1413                            fwtypename);
1414                 for (idx = 0; idx < fwcount; idx++) {
1415                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1416                                    "request_firmware: Failed to find %s",
1417                                    fwnames[idx]);
1418                 }
1419         }
1420         return ret;
1421 }
1422
1423
1424 /*
1425  * pvr2_upload_firmware1().
1426  *
1427  * Send the 8051 firmware to the device.  After the upload, arrange for
1428  * device to re-enumerate.
1429  *
1430  * NOTE : the pointer to the firmware data given by request_firmware()
1431  * is not suitable for an usb transaction.
1432  *
1433  */
1434 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1435 {
1436         const struct firmware *fw_entry = NULL;
1437         void  *fw_ptr;
1438         unsigned int pipe;
1439         int ret;
1440         u16 address;
1441
1442         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1443                 hdw->fw1_state = FW1_STATE_OK;
1444                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1445                            "Connected device type defines"
1446                            " no firmware to upload; ignoring firmware");
1447                 return -ENOTTY;
1448         }
1449
1450         hdw->fw1_state = FW1_STATE_FAILED; // default result
1451
1452         trace_firmware("pvr2_upload_firmware1");
1453
1454         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1455                                    hdw->hdw_desc->fx2_firmware.cnt,
1456                                    hdw->hdw_desc->fx2_firmware.lst);
1457         if (ret < 0) {
1458                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1459                 return ret;
1460         }
1461
1462         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1463         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1464
1465         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1466
1467         if (fw_entry->size != 0x2000){
1468                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1469                 release_firmware(fw_entry);
1470                 return -ENOMEM;
1471         }
1472
1473         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1474         if (fw_ptr == NULL){
1475                 release_firmware(fw_entry);
1476                 return -ENOMEM;
1477         }
1478
1479         /* We have to hold the CPU during firmware upload. */
1480         pvr2_hdw_cpureset_assert(hdw,1);
1481
1482         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1483            chunk. */
1484
1485         ret = 0;
1486         for(address = 0; address < fw_entry->size; address += 0x800) {
1487                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1488                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1489                                        0, fw_ptr, 0x800, HZ);
1490         }
1491
1492         trace_firmware("Upload done, releasing device's CPU");
1493
1494         /* Now release the CPU.  It will disconnect and reconnect later. */
1495         pvr2_hdw_cpureset_assert(hdw,0);
1496
1497         kfree(fw_ptr);
1498         release_firmware(fw_entry);
1499
1500         trace_firmware("Upload done (%d bytes sent)",ret);
1501
1502         /* We should have written 8192 bytes */
1503         if (ret == 8192) {
1504                 hdw->fw1_state = FW1_STATE_RELOAD;
1505                 return 0;
1506         }
1507
1508         return -EIO;
1509 }
1510
1511
1512 /*
1513  * pvr2_upload_firmware2()
1514  *
1515  * This uploads encoder firmware on endpoint 2.
1516  *
1517  */
1518
1519 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1520 {
1521         const struct firmware *fw_entry = NULL;
1522         void  *fw_ptr;
1523         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1524         int actual_length;
1525         int ret = 0;
1526         int fwidx;
1527         static const char *fw_files[] = {
1528                 CX2341X_FIRM_ENC_FILENAME,
1529         };
1530
1531         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1532                 return 0;
1533         }
1534
1535         trace_firmware("pvr2_upload_firmware2");
1536
1537         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1538                                    ARRAY_SIZE(fw_files), fw_files);
1539         if (ret < 0) return ret;
1540         fwidx = ret;
1541         ret = 0;
1542         /* Since we're about to completely reinitialize the encoder,
1543            invalidate our cached copy of its configuration state.  Next
1544            time we configure the encoder, then we'll fully configure it. */
1545         hdw->enc_cur_valid = 0;
1546
1547         /* Encoder is about to be reset so note that as far as we're
1548            concerned now, the encoder has never been run. */
1549         del_timer_sync(&hdw->encoder_run_timer);
1550         if (hdw->state_encoder_runok) {
1551                 hdw->state_encoder_runok = 0;
1552                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1553         }
1554
1555         /* First prepare firmware loading */
1556         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1557         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1558         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1559         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1560         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1561         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1562         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1563         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1564         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1565         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1566         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1567         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1568         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1569         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1570         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1571         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1572         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1573         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1574
1575         if (ret) {
1576                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1577                            "firmware2 upload prep failed, ret=%d",ret);
1578                 release_firmware(fw_entry);
1579                 goto done;
1580         }
1581
1582         /* Now send firmware */
1583
1584         fw_len = fw_entry->size;
1585
1586         if (fw_len % sizeof(u32)) {
1587                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1588                            "size of %s firmware"
1589                            " must be a multiple of %zu bytes",
1590                            fw_files[fwidx],sizeof(u32));
1591                 release_firmware(fw_entry);
1592                 ret = -EINVAL;
1593                 goto done;
1594         }
1595
1596         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1597         if (fw_ptr == NULL){
1598                 release_firmware(fw_entry);
1599                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1600                            "failed to allocate memory for firmware2 upload");
1601                 ret = -ENOMEM;
1602                 goto done;
1603         }
1604
1605         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1606
1607         fw_done = 0;
1608         for (fw_done = 0; fw_done < fw_len;) {
1609                 bcnt = fw_len - fw_done;
1610                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1611                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1612                 /* Usbsnoop log shows that we must swap bytes... */
1613                 /* Some background info: The data being swapped here is a
1614                    firmware image destined for the mpeg encoder chip that
1615                    lives at the other end of a USB endpoint.  The encoder
1616                    chip always talks in 32 bit chunks and its storage is
1617                    organized into 32 bit words.  However from the file
1618                    system to the encoder chip everything is purely a byte
1619                    stream.  The firmware file's contents are always 32 bit
1620                    swapped from what the encoder expects.  Thus the need
1621                    always exists to swap the bytes regardless of the endian
1622                    type of the host processor and therefore swab32() makes
1623                    the most sense. */
1624                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1625                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1626
1627                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1628                                     &actual_length, HZ);
1629                 ret |= (actual_length != bcnt);
1630                 if (ret) break;
1631                 fw_done += bcnt;
1632         }
1633
1634         trace_firmware("upload of %s : %i / %i ",
1635                        fw_files[fwidx],fw_done,fw_len);
1636
1637         kfree(fw_ptr);
1638         release_firmware(fw_entry);
1639
1640         if (ret) {
1641                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1642                            "firmware2 upload transfer failure");
1643                 goto done;
1644         }
1645
1646         /* Finish upload */
1647
1648         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1649         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1650         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1651
1652         if (ret) {
1653                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1654                            "firmware2 upload post-proc failure");
1655         }
1656
1657  done:
1658         if (hdw->hdw_desc->signal_routing_scheme ==
1659             PVR2_ROUTING_SCHEME_GOTVIEW) {
1660                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1661                    hardware. */
1662                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1663         }
1664         return ret;
1665 }
1666
1667
1668 static const char *pvr2_get_state_name(unsigned int st)
1669 {
1670         if (st < ARRAY_SIZE(pvr2_state_names)) {
1671                 return pvr2_state_names[st];
1672         }
1673         return "???";
1674 }
1675
1676 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1677 {
1678         if (hdw->decoder_ctrl) {
1679                 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt, enablefl);
1680                 return 0;
1681         }
1682         /* Even though we really only care about the video decoder chip at
1683            this point, we'll broadcast stream on/off to all sub-devices
1684            anyway, just in case somebody else wants to hear the
1685            command... */
1686         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1687                    (enablefl ? "on" : "off"));
1688         v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1689         if (hdw->decoder_client_id) {
1690                 /* We get here if the encoder has been noticed.  Otherwise
1691                    we'll issue a warning to the user (which should
1692                    normally never happen). */
1693                 return 0;
1694         }
1695         if (!hdw->flag_decoder_missed) {
1696                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1697                            "WARNING: No decoder present");
1698                 hdw->flag_decoder_missed = !0;
1699                 trace_stbit("flag_decoder_missed",
1700                             hdw->flag_decoder_missed);
1701         }
1702         return -EIO;
1703 }
1704
1705
1706 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1707 {
1708         if (hdw->decoder_ctrl == ptr) return;
1709         hdw->decoder_ctrl = ptr;
1710         if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1711                 hdw->flag_decoder_missed = 0;
1712                 trace_stbit("flag_decoder_missed",
1713                             hdw->flag_decoder_missed);
1714                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1715                            "Decoder has appeared");
1716                 pvr2_hdw_state_sched(hdw);
1717         }
1718 }
1719
1720
1721 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1722 {
1723         return hdw->master_state;
1724 }
1725
1726
1727 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1728 {
1729         if (!hdw->flag_tripped) return 0;
1730         hdw->flag_tripped = 0;
1731         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1732                    "Clearing driver error statuss");
1733         return !0;
1734 }
1735
1736
1737 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1738 {
1739         int fl;
1740         LOCK_TAKE(hdw->big_lock); do {
1741                 fl = pvr2_hdw_untrip_unlocked(hdw);
1742         } while (0); LOCK_GIVE(hdw->big_lock);
1743         if (fl) pvr2_hdw_state_sched(hdw);
1744         return 0;
1745 }
1746
1747
1748
1749
1750 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1751 {
1752         return hdw->state_pipeline_req != 0;
1753 }
1754
1755
1756 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1757 {
1758         int ret,st;
1759         LOCK_TAKE(hdw->big_lock); do {
1760                 pvr2_hdw_untrip_unlocked(hdw);
1761                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1762                         hdw->state_pipeline_req = enable_flag != 0;
1763                         pvr2_trace(PVR2_TRACE_START_STOP,
1764                                    "/*--TRACE_STREAM--*/ %s",
1765                                    enable_flag ? "enable" : "disable");
1766                 }
1767                 pvr2_hdw_state_sched(hdw);
1768         } while (0); LOCK_GIVE(hdw->big_lock);
1769         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1770         if (enable_flag) {
1771                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1772                         if (st != PVR2_STATE_READY) return -EIO;
1773                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1774                 }
1775         }
1776         return 0;
1777 }
1778
1779
1780 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1781 {
1782         int fl;
1783         LOCK_TAKE(hdw->big_lock);
1784         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1785                 hdw->desired_stream_type = config;
1786                 hdw->state_pipeline_config = 0;
1787                 trace_stbit("state_pipeline_config",
1788                             hdw->state_pipeline_config);
1789                 pvr2_hdw_state_sched(hdw);
1790         }
1791         LOCK_GIVE(hdw->big_lock);
1792         if (fl) return 0;
1793         return pvr2_hdw_wait(hdw,0);
1794 }
1795
1796
1797 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1798 {
1799         int unit_number = hdw->unit_number;
1800         int tp = -1;
1801         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1802                 tp = tuner[unit_number];
1803         }
1804         if (tp < 0) return -EINVAL;
1805         hdw->tuner_type = tp;
1806         hdw->tuner_updated = !0;
1807         return 0;
1808 }
1809
1810
1811 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1812 {
1813         int unit_number = hdw->unit_number;
1814         int tp = 0;
1815         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1816                 tp = video_std[unit_number];
1817                 if (tp) return tp;
1818         }
1819         return 0;
1820 }
1821
1822
1823 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1824 {
1825         int unit_number = hdw->unit_number;
1826         int tp = 0;
1827         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1828                 tp = tolerance[unit_number];
1829         }
1830         return tp;
1831 }
1832
1833
1834 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1835 {
1836         /* Try a harmless request to fetch the eeprom's address over
1837            endpoint 1.  See what happens.  Only the full FX2 image can
1838            respond to this.  If this probe fails then likely the FX2
1839            firmware needs be loaded. */
1840         int result;
1841         LOCK_TAKE(hdw->ctl_lock); do {
1842                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1843                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1844                                            hdw->cmd_buffer,1,
1845                                            hdw->cmd_buffer,1);
1846                 if (result < 0) break;
1847         } while(0); LOCK_GIVE(hdw->ctl_lock);
1848         if (result) {
1849                 pvr2_trace(PVR2_TRACE_INIT,
1850                            "Probe of device endpoint 1 result status %d",
1851                            result);
1852         } else {
1853                 pvr2_trace(PVR2_TRACE_INIT,
1854                            "Probe of device endpoint 1 succeeded");
1855         }
1856         return result == 0;
1857 }
1858
1859 struct pvr2_std_hack {
1860         v4l2_std_id pat;  /* Pattern to match */
1861         v4l2_std_id msk;  /* Which bits we care about */
1862         v4l2_std_id std;  /* What additional standards or default to set */
1863 };
1864
1865 /* This data structure labels specific combinations of standards from
1866    tveeprom that we'll try to recognize.  If we recognize one, then assume
1867    a specified default standard to use.  This is here because tveeprom only
1868    tells us about available standards not the intended default standard (if
1869    any) for the device in question.  We guess the default based on what has
1870    been reported as available.  Note that this is only for guessing a
1871    default - which can always be overridden explicitly - and if the user
1872    has otherwise named a default then that default will always be used in
1873    place of this table. */
1874 static const struct pvr2_std_hack std_eeprom_maps[] = {
1875         {       /* PAL(B/G) */
1876                 .pat = V4L2_STD_B|V4L2_STD_GH,
1877                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1878         },
1879         {       /* NTSC(M) */
1880                 .pat = V4L2_STD_MN,
1881                 .std = V4L2_STD_NTSC_M,
1882         },
1883         {       /* PAL(I) */
1884                 .pat = V4L2_STD_PAL_I,
1885                 .std = V4L2_STD_PAL_I,
1886         },
1887         {       /* SECAM(L/L') */
1888                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1889                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1890         },
1891         {       /* PAL(D/D1/K) */
1892                 .pat = V4L2_STD_DK,
1893                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1894         },
1895 };
1896
1897 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1898 {
1899         char buf[40];
1900         unsigned int bcnt;
1901         v4l2_std_id std1,std2,std3;
1902
1903         std1 = get_default_standard(hdw);
1904         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1905
1906         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1907         pvr2_trace(PVR2_TRACE_STD,
1908                    "Supported video standard(s) reported available"
1909                    " in hardware: %.*s",
1910                    bcnt,buf);
1911
1912         hdw->std_mask_avail = hdw->std_mask_eeprom;
1913
1914         std2 = (std1|std3) & ~hdw->std_mask_avail;
1915         if (std2) {
1916                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1917                 pvr2_trace(PVR2_TRACE_STD,
1918                            "Expanding supported video standards"
1919                            " to include: %.*s",
1920                            bcnt,buf);
1921                 hdw->std_mask_avail |= std2;
1922         }
1923
1924         pvr2_hdw_internal_set_std_avail(hdw);
1925
1926         if (std1) {
1927                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1928                 pvr2_trace(PVR2_TRACE_STD,
1929                            "Initial video standard forced to %.*s",
1930                            bcnt,buf);
1931                 hdw->std_mask_cur = std1;
1932                 hdw->std_dirty = !0;
1933                 pvr2_hdw_internal_find_stdenum(hdw);
1934                 return;
1935         }
1936         if (std3) {
1937                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1938                 pvr2_trace(PVR2_TRACE_STD,
1939                            "Initial video standard"
1940                            " (determined by device type): %.*s",bcnt,buf);
1941                 hdw->std_mask_cur = std3;
1942                 hdw->std_dirty = !0;
1943                 pvr2_hdw_internal_find_stdenum(hdw);
1944                 return;
1945         }
1946
1947         {
1948                 unsigned int idx;
1949                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1950                         if (std_eeprom_maps[idx].msk ?
1951                             ((std_eeprom_maps[idx].pat ^
1952                              hdw->std_mask_eeprom) &
1953                              std_eeprom_maps[idx].msk) :
1954                             (std_eeprom_maps[idx].pat !=
1955                              hdw->std_mask_eeprom)) continue;
1956                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1957                                                   std_eeprom_maps[idx].std);
1958                         pvr2_trace(PVR2_TRACE_STD,
1959                                    "Initial video standard guessed as %.*s",
1960                                    bcnt,buf);
1961                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1962                         hdw->std_dirty = !0;
1963                         pvr2_hdw_internal_find_stdenum(hdw);
1964                         return;
1965                 }
1966         }
1967
1968         if (hdw->std_enum_cnt > 1) {
1969                 // Autoselect the first listed standard
1970                 hdw->std_enum_cur = 1;
1971                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1972                 hdw->std_dirty = !0;
1973                 pvr2_trace(PVR2_TRACE_STD,
1974                            "Initial video standard auto-selected to %s",
1975                            hdw->std_defs[hdw->std_enum_cur-1].name);
1976                 return;
1977         }
1978
1979         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1980                    "Unable to select a viable initial video standard");
1981 }
1982
1983
1984 static unsigned int pvr2_copy_i2c_addr_list(
1985         unsigned short *dst, const unsigned char *src,
1986         unsigned int dst_max)
1987 {
1988         unsigned int cnt = 0;
1989         if (!src) return 0;
1990         while (src[cnt] && (cnt + 1) < dst_max) {
1991                 dst[cnt] = src[cnt];
1992                 cnt++;
1993         }
1994         dst[cnt] = I2C_CLIENT_END;
1995         return cnt;
1996 }
1997
1998
1999 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
2000                                 const struct pvr2_device_client_desc *cd)
2001 {
2002         const char *fname;
2003         unsigned char mid;
2004         struct v4l2_subdev *sd;
2005         unsigned int i2ccnt;
2006         const unsigned char *p;
2007         /* Arbitrary count - max # i2c addresses we will probe */
2008         unsigned short i2caddr[25];
2009
2010         mid = cd->module_id;
2011         fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2012         if (!fname) {
2013                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2014                            "Module ID %u for device %s has no name",
2015                            mid,
2016                            hdw->hdw_desc->description);
2017                 return -EINVAL;
2018         }
2019         pvr2_trace(PVR2_TRACE_INIT,
2020                    "Module ID %u (%s) for device %s being loaded...",
2021                    mid, fname,
2022                    hdw->hdw_desc->description);
2023
2024         i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2025                                          ARRAY_SIZE(i2caddr));
2026         if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2027                          module_i2c_addresses[mid] : NULL) != NULL)) {
2028                 /* Second chance: Try default i2c address list */
2029                 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2030                                                  ARRAY_SIZE(i2caddr));
2031                 if (i2ccnt) {
2032                         pvr2_trace(PVR2_TRACE_INIT,
2033                                    "Module ID %u:"
2034                                    " Using default i2c address list",
2035                                    mid);
2036                 }
2037         }
2038
2039         if (!i2ccnt) {
2040                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2041                            "Module ID %u (%s) for device %s:"
2042                            " No i2c addresses",
2043                            mid, fname, hdw->hdw_desc->description);
2044                 return -EINVAL;
2045         }
2046
2047         /* Note how the 2nd and 3rd arguments are the same for both
2048          * v4l2_i2c_new_subdev() and v4l2_i2c_new_probed_subdev().  Why?
2049          * Well the 2nd argument is the module name to load, while the 3rd
2050          * argument is documented in the framework as being the "chipid" -
2051          * and every other place where I can find examples of this, the
2052          * "chipid" appears to just be the module name again.  So here we
2053          * just do the same thing. */
2054         hdw->i2c_adap.class = 0;
2055         if (i2ccnt == 1) {
2056                 pvr2_trace(PVR2_TRACE_INIT,
2057                            "Module ID %u:"
2058                            " Setting up with specified i2c address 0x%x",
2059                            mid, i2caddr[0]);
2060                 sd = v4l2_i2c_new_subdev(&hdw->i2c_adap,
2061                                          fname, fname,
2062                                          i2caddr[0]);
2063         } else {
2064                 pvr2_trace(PVR2_TRACE_INIT,
2065                            "Module ID %u:"
2066                            " Setting up with address probe list",
2067                            mid);
2068                 sd = v4l2_i2c_new_probed_subdev(&hdw->i2c_adap,
2069                                                 fname, fname,
2070                                                 i2caddr);
2071         }
2072         hdw->i2c_adap.class = I2C_CLASS_TV_ANALOG;
2073
2074         if (!sd) {
2075                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2076                            "Module ID %u (%s) for device %s failed to load",
2077                            mid, fname, hdw->hdw_desc->description);
2078                 return -EIO;
2079         }
2080
2081         /* Tag this sub-device instance with the module ID we know about.
2082            In other places we'll use that tag to determine if the instance
2083            requires special handling. */
2084         sd->grp_id = mid;
2085
2086         /* If we have both old and new i2c layers enabled, make sure that
2087            old layer isn't also tracking this module.  This is a debugging
2088            aid, in normal situations there's no reason for both mechanisms
2089            to be enabled. */
2090         pvr2_i2c_untrack_subdev(hdw, sd);
2091         pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
2092
2093
2094         /* client-specific setup... */
2095         switch (mid) {
2096         case PVR2_CLIENT_ID_CX25840:
2097                 hdw->decoder_client_id = mid;
2098                 {
2099                         /*
2100                           Mike Isely <isely@pobox.com> 19-Nov-2006 - This
2101                           bit of nuttiness for cx25840 causes that module
2102                           to correctly set up its video scaling.  This is
2103                           really a problem in the cx25840 module itself,
2104                           but we work around it here.  The problem has not
2105                           been seen in ivtv because there VBI is supported
2106                           and set up.  We don't do VBI here (at least not
2107                           yet) and thus we never attempted to even set it
2108                           up.
2109                         */
2110                         struct v4l2_format fmt;
2111                         pvr2_trace(PVR2_TRACE_INIT,
2112                                    "Module ID %u:"
2113                                    " Executing cx25840 VBI hack",
2114                                    mid);
2115                         memset(&fmt, 0, sizeof(fmt));
2116                         fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2117                         v4l2_device_call_all(&hdw->v4l2_dev, mid,
2118                                              video, s_fmt, &fmt);
2119                 }
2120                 break;
2121         case PVR2_CLIENT_ID_SAA7115:
2122                 hdw->decoder_client_id = mid;
2123                 break;
2124         default: break;
2125         }
2126
2127         return 0;
2128 }
2129
2130
2131 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2132 {
2133         unsigned int idx;
2134         const struct pvr2_string_table *cm;
2135         const struct pvr2_device_client_table *ct;
2136         int okFl = !0;
2137
2138         cm = &hdw->hdw_desc->client_modules;
2139         for (idx = 0; idx < cm->cnt; idx++) {
2140                 request_module(cm->lst[idx]);
2141         }
2142
2143         ct = &hdw->hdw_desc->client_table;
2144         for (idx = 0; idx < ct->cnt; idx++) {
2145                 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
2146         }
2147         if (!okFl) pvr2_hdw_render_useless(hdw);
2148 }
2149
2150
2151 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2152 {
2153         int ret;
2154         unsigned int idx;
2155         struct pvr2_ctrl *cptr;
2156         int reloadFl = 0;
2157         if (hdw->hdw_desc->fx2_firmware.cnt) {
2158                 if (!reloadFl) {
2159                         reloadFl =
2160                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2161                                  == 0);
2162                         if (reloadFl) {
2163                                 pvr2_trace(PVR2_TRACE_INIT,
2164                                            "USB endpoint config looks strange"
2165                                            "; possibly firmware needs to be"
2166                                            " loaded");
2167                         }
2168                 }
2169                 if (!reloadFl) {
2170                         reloadFl = !pvr2_hdw_check_firmware(hdw);
2171                         if (reloadFl) {
2172                                 pvr2_trace(PVR2_TRACE_INIT,
2173                                            "Check for FX2 firmware failed"
2174                                            "; possibly firmware needs to be"
2175                                            " loaded");
2176                         }
2177                 }
2178                 if (reloadFl) {
2179                         if (pvr2_upload_firmware1(hdw) != 0) {
2180                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2181                                            "Failure uploading firmware1");
2182                         }
2183                         return;
2184                 }
2185         }
2186         hdw->fw1_state = FW1_STATE_OK;
2187
2188         if (!pvr2_hdw_dev_ok(hdw)) return;
2189
2190         hdw->force_dirty = !0;
2191
2192         if (!hdw->hdw_desc->flag_no_powerup) {
2193                 pvr2_hdw_cmd_powerup(hdw);
2194                 if (!pvr2_hdw_dev_ok(hdw)) return;
2195         }
2196
2197         /* Take the IR chip out of reset, if appropriate */
2198         if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
2199                 pvr2_issue_simple_cmd(hdw,
2200                                       FX2CMD_HCW_ZILOG_RESET |
2201                                       (1 << 8) |
2202                                       ((0) << 16));
2203         }
2204
2205         // This step MUST happen after the earlier powerup step.
2206         pvr2_i2c_track_init(hdw);
2207         pvr2_i2c_core_init(hdw);
2208         if (!pvr2_hdw_dev_ok(hdw)) return;
2209
2210         pvr2_hdw_load_modules(hdw);
2211         if (!pvr2_hdw_dev_ok(hdw)) return;
2212
2213         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, init, 0);
2214
2215         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2216                 cptr = hdw->controls + idx;
2217                 if (cptr->info->skip_init) continue;
2218                 if (!cptr->info->set_value) continue;
2219                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2220         }
2221
2222         /* Set up special default values for the television and radio
2223            frequencies here.  It's not really important what these defaults
2224            are, but I set them to something usable in the Chicago area just
2225            to make driver testing a little easier. */
2226
2227         hdw->freqValTelevision = default_tv_freq;
2228         hdw->freqValRadio = default_radio_freq;
2229
2230         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2231         // thread-safe against the normal pvr2_send_request() mechanism.
2232         // (We should make it thread safe).
2233
2234         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2235                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2236                 if (!pvr2_hdw_dev_ok(hdw)) return;
2237                 if (ret < 0) {
2238                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2239                                    "Unable to determine location of eeprom,"
2240                                    " skipping");
2241                 } else {
2242                         hdw->eeprom_addr = ret;
2243                         pvr2_eeprom_analyze(hdw);
2244                         if (!pvr2_hdw_dev_ok(hdw)) return;
2245                 }
2246         } else {
2247                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2248                 hdw->tuner_updated = !0;
2249                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2250         }
2251
2252         if (hdw->serial_number) {
2253                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2254                                 "sn-%lu", hdw->serial_number);
2255         } else if (hdw->unit_number >= 0) {
2256                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2257                                 "unit-%c",
2258                                 hdw->unit_number + 'a');
2259         } else {
2260                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2261                                 "unit-??");
2262         }
2263         hdw->identifier[idx] = 0;
2264
2265         pvr2_hdw_setup_std(hdw);
2266
2267         if (!get_default_tuner_type(hdw)) {
2268                 pvr2_trace(PVR2_TRACE_INIT,
2269                            "pvr2_hdw_setup: Tuner type overridden to %d",
2270                            hdw->tuner_type);
2271         }
2272
2273         pvr2_i2c_core_check_stale(hdw);
2274
2275         if (!pvr2_hdw_dev_ok(hdw)) return;
2276
2277         if (hdw->hdw_desc->signal_routing_scheme ==
2278             PVR2_ROUTING_SCHEME_GOTVIEW) {
2279                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2280                    hardware. */
2281                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2282         }
2283
2284         pvr2_hdw_commit_setup(hdw);
2285
2286         hdw->vid_stream = pvr2_stream_create();
2287         if (!pvr2_hdw_dev_ok(hdw)) return;
2288         pvr2_trace(PVR2_TRACE_INIT,
2289                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2290         if (hdw->vid_stream) {
2291                 idx = get_default_error_tolerance(hdw);
2292                 if (idx) {
2293                         pvr2_trace(PVR2_TRACE_INIT,
2294                                    "pvr2_hdw_setup: video stream %p"
2295                                    " setting tolerance %u",
2296                                    hdw->vid_stream,idx);
2297                 }
2298                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2299                                   PVR2_VID_ENDPOINT,idx);
2300         }
2301
2302         if (!pvr2_hdw_dev_ok(hdw)) return;
2303
2304         hdw->flag_init_ok = !0;
2305
2306         pvr2_hdw_state_sched(hdw);
2307 }
2308
2309
2310 /* Set up the structure and attempt to put the device into a usable state.
2311    This can be a time-consuming operation, which is why it is not done
2312    internally as part of the create() step. */
2313 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2314 {
2315         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2316         do {
2317                 pvr2_hdw_setup_low(hdw);
2318                 pvr2_trace(PVR2_TRACE_INIT,
2319                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2320                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2321                 if (pvr2_hdw_dev_ok(hdw)) {
2322                         if (hdw->flag_init_ok) {
2323                                 pvr2_trace(
2324                                         PVR2_TRACE_INFO,
2325                                         "Device initialization"
2326                                         " completed successfully.");
2327                                 break;
2328                         }
2329                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2330                                 pvr2_trace(
2331                                         PVR2_TRACE_INFO,
2332                                         "Device microcontroller firmware"
2333                                         " (re)loaded; it should now reset"
2334                                         " and reconnect.");
2335                                 break;
2336                         }
2337                         pvr2_trace(
2338                                 PVR2_TRACE_ERROR_LEGS,
2339                                 "Device initialization was not successful.");
2340                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2341                                 pvr2_trace(
2342                                         PVR2_TRACE_ERROR_LEGS,
2343                                         "Giving up since device"
2344                                         " microcontroller firmware"
2345                                         " appears to be missing.");
2346                                 break;
2347                         }
2348                 }
2349                 if (procreload) {
2350                         pvr2_trace(
2351                                 PVR2_TRACE_ERROR_LEGS,
2352                                 "Attempting pvrusb2 recovery by reloading"
2353                                 " primary firmware.");
2354                         pvr2_trace(
2355                                 PVR2_TRACE_ERROR_LEGS,
2356                                 "If this works, device should disconnect"
2357                                 " and reconnect in a sane state.");
2358                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2359                         pvr2_upload_firmware1(hdw);
2360                 } else {
2361                         pvr2_trace(
2362                                 PVR2_TRACE_ERROR_LEGS,
2363                                 "***WARNING*** pvrusb2 device hardware"
2364                                 " appears to be jammed"
2365                                 " and I can't clear it.");
2366                         pvr2_trace(
2367                                 PVR2_TRACE_ERROR_LEGS,
2368                                 "You might need to power cycle"
2369                                 " the pvrusb2 device"
2370                                 " in order to recover.");
2371                 }
2372         } while (0);
2373         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2374 }
2375
2376
2377 /* Perform second stage initialization.  Set callback pointer first so that
2378    we can avoid a possible initialization race (if the kernel thread runs
2379    before the callback has been set). */
2380 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2381                         void (*callback_func)(void *),
2382                         void *callback_data)
2383 {
2384         LOCK_TAKE(hdw->big_lock); do {
2385                 if (hdw->flag_disconnected) {
2386                         /* Handle a race here: If we're already
2387                            disconnected by this point, then give up.  If we
2388                            get past this then we'll remain connected for
2389                            the duration of initialization since the entire
2390                            initialization sequence is now protected by the
2391                            big_lock. */
2392                         break;
2393                 }
2394                 hdw->state_data = callback_data;
2395                 hdw->state_func = callback_func;
2396                 pvr2_hdw_setup(hdw);
2397         } while (0); LOCK_GIVE(hdw->big_lock);
2398         return hdw->flag_init_ok;
2399 }
2400
2401
2402 /* Create, set up, and return a structure for interacting with the
2403    underlying hardware.  */
2404 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2405                                  const struct usb_device_id *devid)
2406 {
2407         unsigned int idx,cnt1,cnt2,m;
2408         struct pvr2_hdw *hdw = NULL;
2409         int valid_std_mask;
2410         struct pvr2_ctrl *cptr;
2411         struct usb_device *usb_dev;
2412         const struct pvr2_device_desc *hdw_desc;
2413         __u8 ifnum;
2414         struct v4l2_queryctrl qctrl;
2415         struct pvr2_ctl_info *ciptr;
2416
2417         usb_dev = interface_to_usbdev(intf);
2418
2419         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2420
2421         if (hdw_desc == NULL) {
2422                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2423                            " No device description pointer,"
2424                            " unable to continue.");
2425                 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2426                            " please contact Mike Isely <isely@pobox.com>"
2427                            " to get it included in the driver\n");
2428                 goto fail;
2429         }
2430
2431         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2432         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2433                    hdw,hdw_desc->description);
2434         if (!hdw) goto fail;
2435
2436         init_timer(&hdw->quiescent_timer);
2437         hdw->quiescent_timer.data = (unsigned long)hdw;
2438         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2439
2440         init_timer(&hdw->encoder_wait_timer);
2441         hdw->encoder_wait_timer.data = (unsigned long)hdw;
2442         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2443
2444         init_timer(&hdw->encoder_run_timer);
2445         hdw->encoder_run_timer.data = (unsigned long)hdw;
2446         hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2447
2448         hdw->master_state = PVR2_STATE_DEAD;
2449
2450         init_waitqueue_head(&hdw->state_wait_data);
2451
2452         hdw->tuner_signal_stale = !0;
2453         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2454
2455         /* Calculate which inputs are OK */
2456         m = 0;
2457         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2458         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2459                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2460         }
2461         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2462         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2463         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2464         hdw->input_avail_mask = m;
2465         hdw->input_allowed_mask = hdw->input_avail_mask;
2466
2467         /* If not a hybrid device, pathway_state never changes.  So
2468            initialize it here to what it should forever be. */
2469         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2470                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2471         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2472                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2473         }
2474
2475         hdw->control_cnt = CTRLDEF_COUNT;
2476         hdw->control_cnt += MPEGDEF_COUNT;
2477         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2478                                 GFP_KERNEL);
2479         if (!hdw->controls) goto fail;
2480         hdw->hdw_desc = hdw_desc;
2481         for (idx = 0; idx < hdw->control_cnt; idx++) {
2482                 cptr = hdw->controls + idx;
2483                 cptr->hdw = hdw;
2484         }
2485         for (idx = 0; idx < 32; idx++) {
2486                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2487         }
2488         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2489                 cptr = hdw->controls + idx;
2490                 cptr->info = control_defs+idx;
2491         }
2492
2493         /* Ensure that default input choice is a valid one. */
2494         m = hdw->input_avail_mask;
2495         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2496                 if (!((1 << idx) & m)) continue;
2497                 hdw->input_val = idx;
2498                 break;
2499         }
2500
2501         /* Define and configure additional controls from cx2341x module. */
2502         hdw->mpeg_ctrl_info = kzalloc(
2503                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2504         if (!hdw->mpeg_ctrl_info) goto fail;
2505         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2506                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2507                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2508                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2509                 ciptr->name = mpeg_ids[idx].strid;
2510                 ciptr->v4l_id = mpeg_ids[idx].id;
2511                 ciptr->skip_init = !0;
2512                 ciptr->get_value = ctrl_cx2341x_get;
2513                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2514                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2515                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2516                 qctrl.id = ciptr->v4l_id;
2517                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2518                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2519                         ciptr->set_value = ctrl_cx2341x_set;
2520                 }
2521                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2522                         PVR2_CTLD_INFO_DESC_SIZE);
2523                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2524                 ciptr->default_value = qctrl.default_value;
2525                 switch (qctrl.type) {
2526                 default:
2527                 case V4L2_CTRL_TYPE_INTEGER:
2528                         ciptr->type = pvr2_ctl_int;
2529                         ciptr->def.type_int.min_value = qctrl.minimum;
2530                         ciptr->def.type_int.max_value = qctrl.maximum;
2531                         break;
2532                 case V4L2_CTRL_TYPE_BOOLEAN:
2533                         ciptr->type = pvr2_ctl_bool;
2534                         break;
2535                 case V4L2_CTRL_TYPE_MENU:
2536                         ciptr->type = pvr2_ctl_enum;
2537                         ciptr->def.type_enum.value_names =
2538                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2539                                                                 ciptr->v4l_id);
2540                         for (cnt1 = 0;
2541                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2542                              cnt1++) { }
2543                         ciptr->def.type_enum.count = cnt1;
2544                         break;
2545                 }
2546                 cptr->info = ciptr;
2547         }
2548
2549         // Initialize video standard enum dynamic control
2550         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2551         if (cptr) {
2552                 memcpy(&hdw->std_info_enum,cptr->info,
2553                        sizeof(hdw->std_info_enum));
2554                 cptr->info = &hdw->std_info_enum;
2555
2556         }
2557         // Initialize control data regarding video standard masks
2558         valid_std_mask = pvr2_std_get_usable();
2559         for (idx = 0; idx < 32; idx++) {
2560                 if (!(valid_std_mask & (1 << idx))) continue;
2561                 cnt1 = pvr2_std_id_to_str(
2562                         hdw->std_mask_names[idx],
2563                         sizeof(hdw->std_mask_names[idx])-1,
2564                         1 << idx);
2565                 hdw->std_mask_names[idx][cnt1] = 0;
2566         }
2567         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2568         if (cptr) {
2569                 memcpy(&hdw->std_info_avail,cptr->info,
2570                        sizeof(hdw->std_info_avail));
2571                 cptr->info = &hdw->std_info_avail;
2572                 hdw->std_info_avail.def.type_bitmask.bit_names =
2573                         hdw->std_mask_ptrs;
2574                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2575                         valid_std_mask;
2576         }
2577         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2578         if (cptr) {
2579                 memcpy(&hdw->std_info_cur,cptr->info,
2580                        sizeof(hdw->std_info_cur));
2581                 cptr->info = &hdw->std_info_cur;
2582                 hdw->std_info_cur.def.type_bitmask.bit_names =
2583                         hdw->std_mask_ptrs;
2584                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2585                         valid_std_mask;
2586         }
2587
2588         hdw->cropcap_stale = !0;
2589         hdw->eeprom_addr = -1;
2590         hdw->unit_number = -1;
2591         hdw->v4l_minor_number_video = -1;
2592         hdw->v4l_minor_number_vbi = -1;
2593         hdw->v4l_minor_number_radio = -1;
2594         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2595         if (!hdw->ctl_write_buffer) goto fail;
2596         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2597         if (!hdw->ctl_read_buffer) goto fail;
2598         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2599         if (!hdw->ctl_write_urb) goto fail;
2600         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2601         if (!hdw->ctl_read_urb) goto fail;
2602
2603         if (v4l2_device_register(&usb_dev->dev, &hdw->v4l2_dev) != 0) {
2604                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2605                            "Error registering with v4l core, giving up");
2606                 goto fail;
2607         }
2608         mutex_lock(&pvr2_unit_mtx); do {
2609                 for (idx = 0; idx < PVR_NUM; idx++) {
2610                         if (unit_pointers[idx]) continue;
2611                         hdw->unit_number = idx;
2612                         unit_pointers[idx] = hdw;
2613                         break;
2614                 }
2615         } while (0); mutex_unlock(&pvr2_unit_mtx);
2616
2617         cnt1 = 0;
2618         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2619         cnt1 += cnt2;
2620         if (hdw->unit_number >= 0) {
2621                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2622                                  ('a' + hdw->unit_number));
2623                 cnt1 += cnt2;
2624         }
2625         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2626         hdw->name[cnt1] = 0;
2627
2628         hdw->workqueue = create_singlethread_workqueue(hdw->name);
2629         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2630         INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2631
2632         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2633                    hdw->unit_number,hdw->name);
2634
2635         hdw->tuner_type = -1;
2636         hdw->flag_ok = !0;
2637
2638         hdw->usb_intf = intf;
2639         hdw->usb_dev = usb_dev;
2640
2641         usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2642
2643         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2644         usb_set_interface(hdw->usb_dev,ifnum,0);
2645
2646         mutex_init(&hdw->ctl_lock_mutex);
2647         mutex_init(&hdw->big_lock_mutex);
2648
2649         return hdw;
2650  fail:
2651         if (hdw) {
2652                 del_timer_sync(&hdw->quiescent_timer);
2653                 del_timer_sync(&hdw->encoder_run_timer);
2654                 del_timer_sync(&hdw->encoder_wait_timer);
2655                 if (hdw->workqueue) {
2656                         flush_workqueue(hdw->workqueue);
2657                         destroy_workqueue(hdw->workqueue);
2658                         hdw->workqueue = NULL;
2659                 }
2660                 usb_free_urb(hdw->ctl_read_urb);
2661                 usb_free_urb(hdw->ctl_write_urb);
2662                 kfree(hdw->ctl_read_buffer);
2663                 kfree(hdw->ctl_write_buffer);
2664                 kfree(hdw->controls);
2665                 kfree(hdw->mpeg_ctrl_info);
2666                 kfree(hdw->std_defs);
2667                 kfree(hdw->std_enum_names);
2668                 kfree(hdw);
2669         }
2670         return NULL;
2671 }
2672
2673
2674 /* Remove _all_ associations between this driver and the underlying USB
2675    layer. */
2676 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2677 {
2678         if (hdw->flag_disconnected) return;
2679         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2680         if (hdw->ctl_read_urb) {
2681                 usb_kill_urb(hdw->ctl_read_urb);
2682                 usb_free_urb(hdw->ctl_read_urb);
2683                 hdw->ctl_read_urb = NULL;
2684         }
2685         if (hdw->ctl_write_urb) {
2686                 usb_kill_urb(hdw->ctl_write_urb);
2687                 usb_free_urb(hdw->ctl_write_urb);
2688                 hdw->ctl_write_urb = NULL;
2689         }
2690         if (hdw->ctl_read_buffer) {
2691                 kfree(hdw->ctl_read_buffer);
2692                 hdw->ctl_read_buffer = NULL;
2693         }
2694         if (hdw->ctl_write_buffer) {
2695                 kfree(hdw->ctl_write_buffer);
2696                 hdw->ctl_write_buffer = NULL;
2697         }
2698         hdw->flag_disconnected = !0;
2699         /* If we don't do this, then there will be a dangling struct device
2700            reference to our disappearing device persisting inside the V4L
2701            core... */
2702         if (hdw->v4l2_dev.dev) {
2703                 dev_set_drvdata(hdw->v4l2_dev.dev, NULL);
2704                 hdw->v4l2_dev.dev = NULL;
2705         }
2706         hdw->usb_dev = NULL;
2707         hdw->usb_intf = NULL;
2708         pvr2_hdw_render_useless(hdw);
2709 }
2710
2711
2712 /* Destroy hardware interaction structure */
2713 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2714 {
2715         if (!hdw) return;
2716         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2717         if (hdw->workqueue) {
2718                 flush_workqueue(hdw->workqueue);
2719                 destroy_workqueue(hdw->workqueue);
2720                 hdw->workqueue = NULL;
2721         }
2722         del_timer_sync(&hdw->quiescent_timer);
2723         del_timer_sync(&hdw->encoder_run_timer);
2724         del_timer_sync(&hdw->encoder_wait_timer);
2725         if (hdw->fw_buffer) {
2726                 kfree(hdw->fw_buffer);
2727                 hdw->fw_buffer = NULL;
2728         }
2729         if (hdw->vid_stream) {
2730                 pvr2_stream_destroy(hdw->vid_stream);
2731                 hdw->vid_stream = NULL;
2732         }
2733         if (hdw->decoder_ctrl) {
2734                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2735         }
2736         pvr2_i2c_core_done(hdw);
2737         pvr2_i2c_track_done(hdw);
2738         v4l2_device_unregister(&hdw->v4l2_dev);
2739         pvr2_hdw_remove_usb_stuff(hdw);
2740         mutex_lock(&pvr2_unit_mtx); do {
2741                 if ((hdw->unit_number >= 0) &&
2742                     (hdw->unit_number < PVR_NUM) &&
2743                     (unit_pointers[hdw->unit_number] == hdw)) {
2744                         unit_pointers[hdw->unit_number] = NULL;
2745                 }
2746         } while (0); mutex_unlock(&pvr2_unit_mtx);
2747         kfree(hdw->controls);
2748         kfree(hdw->mpeg_ctrl_info);
2749         kfree(hdw->std_defs);
2750         kfree(hdw->std_enum_names);
2751         kfree(hdw);
2752 }
2753
2754
2755 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2756 {
2757         return (hdw && hdw->flag_ok);
2758 }
2759
2760
2761 /* Called when hardware has been unplugged */
2762 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2763 {
2764         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2765         LOCK_TAKE(hdw->big_lock);
2766         LOCK_TAKE(hdw->ctl_lock);
2767         pvr2_hdw_remove_usb_stuff(hdw);
2768         LOCK_GIVE(hdw->ctl_lock);
2769         LOCK_GIVE(hdw->big_lock);
2770 }
2771
2772
2773 // Attempt to autoselect an appropriate value for std_enum_cur given
2774 // whatever is currently in std_mask_cur
2775 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2776 {
2777         unsigned int idx;
2778         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2779                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2780                         hdw->std_enum_cur = idx;
2781                         return;
2782                 }
2783         }
2784         hdw->std_enum_cur = 0;
2785 }
2786
2787
2788 // Calculate correct set of enumerated standards based on currently known
2789 // set of available standards bits.
2790 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2791 {
2792         struct v4l2_standard *newstd;
2793         unsigned int std_cnt;
2794         unsigned int idx;
2795
2796         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2797
2798         if (hdw->std_defs) {
2799                 kfree(hdw->std_defs);
2800                 hdw->std_defs = NULL;
2801         }
2802         hdw->std_enum_cnt = 0;
2803         if (hdw->std_enum_names) {
2804                 kfree(hdw->std_enum_names);
2805                 hdw->std_enum_names = NULL;
2806         }
2807
2808         if (!std_cnt) {
2809                 pvr2_trace(
2810                         PVR2_TRACE_ERROR_LEGS,
2811                         "WARNING: Failed to identify any viable standards");
2812         }
2813         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2814         hdw->std_enum_names[0] = "none";
2815         for (idx = 0; idx < std_cnt; idx++) {
2816                 hdw->std_enum_names[idx+1] =
2817                         newstd[idx].name;
2818         }
2819         // Set up the dynamic control for this standard
2820         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2821         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2822         hdw->std_defs = newstd;
2823         hdw->std_enum_cnt = std_cnt+1;
2824         hdw->std_enum_cur = 0;
2825         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2826 }
2827
2828
2829 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2830                                struct v4l2_standard *std,
2831                                unsigned int idx)
2832 {
2833         int ret = -EINVAL;
2834         if (!idx) return ret;
2835         LOCK_TAKE(hdw->big_lock); do {
2836                 if (idx >= hdw->std_enum_cnt) break;
2837                 idx--;
2838                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2839                 ret = 0;
2840         } while (0); LOCK_GIVE(hdw->big_lock);
2841         return ret;
2842 }
2843
2844
2845 /* Get the number of defined controls */
2846 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2847 {
2848         return hdw->control_cnt;
2849 }
2850
2851
2852 /* Retrieve a control handle given its index (0..count-1) */
2853 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2854                                              unsigned int idx)
2855 {
2856         if (idx >= hdw->control_cnt) return NULL;
2857         return hdw->controls + idx;
2858 }
2859
2860
2861 /* Retrieve a control handle given its index (0..count-1) */
2862 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2863                                           unsigned int ctl_id)
2864 {
2865         struct pvr2_ctrl *cptr;
2866         unsigned int idx;
2867         int i;
2868
2869         /* This could be made a lot more efficient, but for now... */
2870         for (idx = 0; idx < hdw->control_cnt; idx++) {
2871                 cptr = hdw->controls + idx;
2872                 i = cptr->info->internal_id;
2873                 if (i && (i == ctl_id)) return cptr;
2874         }
2875         return NULL;
2876 }
2877
2878
2879 /* Given a V4L ID, retrieve the control structure associated with it. */
2880 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2881 {
2882         struct pvr2_ctrl *cptr;
2883         unsigned int idx;
2884         int i;
2885
2886         /* This could be made a lot more efficient, but for now... */
2887         for (idx = 0; idx < hdw->control_cnt; idx++) {
2888                 cptr = hdw->controls + idx;
2889                 i = cptr->info->v4l_id;
2890                 if (i && (i == ctl_id)) return cptr;
2891         }
2892         return NULL;
2893 }
2894
2895
2896 /* Given a V4L ID for its immediate predecessor, retrieve the control
2897    structure associated with it. */
2898 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2899                                             unsigned int ctl_id)
2900 {
2901         struct pvr2_ctrl *cptr,*cp2;
2902         unsigned int idx;
2903         int i;
2904
2905         /* This could be made a lot more efficient, but for now... */
2906         cp2 = NULL;
2907         for (idx = 0; idx < hdw->control_cnt; idx++) {
2908                 cptr = hdw->controls + idx;
2909                 i = cptr->info->v4l_id;
2910                 if (!i) continue;
2911                 if (i <= ctl_id) continue;
2912                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2913                 cp2 = cptr;
2914         }
2915         return cp2;
2916         return NULL;
2917 }
2918
2919
2920 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2921 {
2922         switch (tp) {
2923         case pvr2_ctl_int: return "integer";
2924         case pvr2_ctl_enum: return "enum";
2925         case pvr2_ctl_bool: return "boolean";
2926         case pvr2_ctl_bitmask: return "bitmask";
2927         }
2928         return "";
2929 }
2930
2931
2932 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2933                                     const char *name, int val)
2934 {
2935         struct v4l2_control ctrl;
2936         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2937         memset(&ctrl, 0, sizeof(ctrl));
2938         ctrl.id = id;
2939         ctrl.value = val;
2940         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2941 }
2942
2943 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2944         if ((hdw)->lab##_dirty || (hdw)->force_dirty) {         \
2945                 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2946         }
2947
2948 /* Execute whatever commands are required to update the state of all the
2949    sub-devices so that they match our current control values. */
2950 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2951 {
2952         struct v4l2_subdev *sd;
2953         unsigned int id;
2954         pvr2_subdev_update_func fp;
2955
2956         pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2957
2958         if (hdw->tuner_updated || hdw->force_dirty) {
2959                 struct tuner_setup setup;
2960                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2961                            hdw->tuner_type);
2962                 if (((int)(hdw->tuner_type)) >= 0) {
2963                         setup.addr = ADDR_UNSET;
2964                         setup.type = hdw->tuner_type;
2965                         setup.mode_mask = T_RADIO | T_ANALOG_TV;
2966                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2967                                              tuner, s_type_addr, &setup);
2968                 }
2969         }
2970
2971         if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
2972                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2973                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2974                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2975                                              tuner, s_radio);
2976                 } else {
2977                         v4l2_std_id vs;
2978                         vs = hdw->std_mask_cur;
2979                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2980                                              tuner, s_std, vs);
2981                 }
2982                 hdw->tuner_signal_stale = !0;
2983                 hdw->cropcap_stale = !0;
2984         }
2985
2986         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2987         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2988         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2989         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2990         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2991         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2992         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2993         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2994         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2995
2996         if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2997                 struct v4l2_tuner vt;
2998                 memset(&vt, 0, sizeof(vt));
2999                 vt.audmode = hdw->audiomode_val;
3000                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
3001         }
3002
3003         if (hdw->freqDirty || hdw->force_dirty) {
3004                 unsigned long fv;
3005                 struct v4l2_frequency freq;
3006                 fv = pvr2_hdw_get_cur_freq(hdw);
3007                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
3008                 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
3009                 memset(&freq, 0, sizeof(freq));
3010                 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
3011                         /* ((fv * 1000) / 62500) */
3012                         freq.frequency = (fv * 2) / 125;
3013                 } else {
3014                         freq.frequency = fv / 62500;
3015                 }
3016                 /* tuner-core currently doesn't seem to care about this, but
3017                    let's set it anyway for completeness. */
3018                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3019                         freq.type = V4L2_TUNER_RADIO;
3020                 } else {
3021                         freq.type = V4L2_TUNER_ANALOG_TV;
3022                 }
3023                 freq.tuner = 0;
3024                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
3025                                      s_frequency, &freq);
3026         }
3027
3028         if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
3029                 struct v4l2_format fmt;
3030                 memset(&fmt, 0, sizeof(fmt));
3031                 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
3032                 fmt.fmt.pix.width = hdw->res_hor_val;
3033                 fmt.fmt.pix.height = hdw->res_ver_val;
3034                 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_size(%dx%d)",
3035                            fmt.fmt.pix.width, fmt.fmt.pix.height);
3036                 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
3037         }
3038
3039         if (hdw->srate_dirty || hdw->force_dirty) {
3040                 u32 val;
3041                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3042                            hdw->srate_val);
3043                 switch (hdw->srate_val) {
3044                 default:
3045                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3046                         val = 48000;
3047                         break;
3048                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3049                         val = 44100;
3050                         break;
3051                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3052                         val = 32000;
3053                         break;
3054                 }
3055                 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3056                                      audio, s_clock_freq, val);
3057         }
3058
3059         /* Unable to set crop parameters; there is apparently no equivalent
3060            for VIDIOC_S_CROP */
3061
3062         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3063                 id = sd->grp_id;
3064                 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3065                 fp = pvr2_module_update_functions[id];
3066                 if (!fp) continue;
3067                 (*fp)(hdw, sd);
3068         }
3069
3070         if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
3071                 pvr2_hdw_status_poll(hdw);
3072         }
3073 }
3074
3075
3076 /* Figure out if we need to commit control changes.  If so, mark internal
3077    state flags to indicate this fact and return true.  Otherwise do nothing
3078    else and return false. */
3079 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
3080 {
3081         unsigned int idx;
3082         struct pvr2_ctrl *cptr;
3083         int value;
3084         int commit_flag = hdw->force_dirty;
3085         char buf[100];
3086         unsigned int bcnt,ccnt;
3087
3088         for (idx = 0; idx < hdw->control_cnt; idx++) {
3089                 cptr = hdw->controls + idx;
3090                 if (!cptr->info->is_dirty) continue;
3091                 if (!cptr->info->is_dirty(cptr)) continue;
3092                 commit_flag = !0;
3093
3094                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
3095                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3096                                  cptr->info->name);
3097                 value = 0;
3098                 cptr->info->get_value(cptr,&value);
3099                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3100                                                 buf+bcnt,
3101                                                 sizeof(buf)-bcnt,&ccnt);
3102                 bcnt += ccnt;
3103                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3104                                   get_ctrl_typename(cptr->info->type));
3105                 pvr2_trace(PVR2_TRACE_CTL,
3106                            "/*--TRACE_COMMIT--*/ %.*s",
3107                            bcnt,buf);
3108         }
3109
3110         if (!commit_flag) {
3111                 /* Nothing has changed */
3112                 return 0;
3113         }
3114
3115         hdw->state_pipeline_config = 0;
3116         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3117         pvr2_hdw_state_sched(hdw);
3118
3119         return !0;
3120 }
3121
3122
3123 /* Perform all operations needed to commit all control changes.  This must
3124    be performed in synchronization with the pipeline state and is thus
3125    expected to be called as part of the driver's worker thread.  Return
3126    true if commit successful, otherwise return false to indicate that
3127    commit isn't possible at this time. */
3128 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3129 {
3130         unsigned int idx;
3131         struct pvr2_ctrl *cptr;
3132         int disruptive_change;
3133
3134         /* Handle some required side effects when the video standard is
3135            changed.... */
3136         if (hdw->std_dirty) {
3137                 int nvres;
3138                 int gop_size;
3139                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3140                         nvres = 480;
3141                         gop_size = 15;
3142                 } else {
3143                         nvres = 576;
3144                         gop_size = 12;
3145                 }
3146                 /* Rewrite the vertical resolution to be appropriate to the
3147                    video standard that has been selected. */
3148                 if (nvres != hdw->res_ver_val) {
3149                         hdw->res_ver_val = nvres;
3150                         hdw->res_ver_dirty = !0;
3151                 }
3152                 /* Rewrite the GOP size to be appropriate to the video
3153                    standard that has been selected. */
3154                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3155                         struct v4l2_ext_controls cs;
3156                         struct v4l2_ext_control c1;
3157                         memset(&cs, 0, sizeof(cs));
3158                         memset(&c1, 0, sizeof(c1));
3159                         cs.controls = &c1;
3160                         cs.count = 1;
3161                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3162                         c1.value = gop_size;
3163                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3164                                           VIDIOC_S_EXT_CTRLS);
3165                 }
3166         }
3167
3168         if (hdw->input_dirty && hdw->state_pathway_ok &&
3169             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3170               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3171              hdw->pathway_state)) {
3172                 /* Change of mode being asked for... */
3173                 hdw->state_pathway_ok = 0;
3174                 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3175         }
3176         if (!hdw->state_pathway_ok) {
3177                 /* Can't commit anything until pathway is ok. */
3178                 return 0;
3179         }
3180         /* The broadcast decoder can only scale down, so if
3181          * res_*_dirty && crop window < output format ==> enlarge crop.
3182          *
3183          * The mpeg encoder receives fields of res_hor_val dots and
3184          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3185          */
3186         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3187                 hdw->cropw_val = hdw->res_hor_val;
3188                 hdw->cropw_dirty = !0;
3189         } else if (hdw->cropw_dirty) {
3190                 hdw->res_hor_dirty = !0;           /* must rescale */
3191                 hdw->res_hor_val = min(720, hdw->cropw_val);
3192         }
3193         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3194                 hdw->croph_val = hdw->res_ver_val;
3195                 hdw->croph_dirty = !0;
3196         } else if (hdw->croph_dirty) {
3197                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3198                 hdw->res_ver_dirty = !0;
3199                 hdw->res_ver_val = min(nvres, hdw->croph_val);
3200         }
3201
3202         /* If any of the below has changed, then we can't do the update
3203            while the pipeline is running.  Pipeline must be paused first
3204            and decoder -> encoder connection be made quiescent before we
3205            can proceed. */
3206         disruptive_change =
3207                 (hdw->std_dirty ||
3208                  hdw->enc_unsafe_stale ||
3209                  hdw->srate_dirty ||
3210                  hdw->res_ver_dirty ||
3211                  hdw->res_hor_dirty ||
3212                  hdw->cropw_dirty ||
3213                  hdw->croph_dirty ||
3214                  hdw->input_dirty ||
3215                  (hdw->active_stream_type != hdw->desired_stream_type));
3216         if (disruptive_change && !hdw->state_pipeline_idle) {
3217                 /* Pipeline is not idle; we can't proceed.  Arrange to
3218                    cause pipeline to stop so that we can try this again
3219                    later.... */
3220                 hdw->state_pipeline_pause = !0;
3221                 return 0;
3222         }
3223
3224         if (hdw->srate_dirty) {
3225                 /* Write new sample rate into control structure since
3226                  * the master copy is stale.  We must track srate
3227                  * separate from the mpeg control structure because
3228                  * other logic also uses this value. */
3229                 struct v4l2_ext_controls cs;
3230                 struct v4l2_ext_control c1;
3231                 memset(&cs,0,sizeof(cs));
3232                 memset(&c1,0,sizeof(c1));
3233                 cs.controls = &c1;
3234                 cs.count = 1;
3235                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3236                 c1.value = hdw->srate_val;
3237                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3238         }
3239
3240         /* Scan i2c core at this point - before we clear all the dirty
3241            bits.  Various parts of the i2c core will notice dirty bits as
3242            appropriate and arrange to broadcast or directly send updates to
3243            the client drivers in order to keep everything in sync */
3244         pvr2_i2c_core_check_stale(hdw);
3245
3246         if (hdw->active_stream_type != hdw->desired_stream_type) {
3247                 /* Handle any side effects of stream config here */
3248                 hdw->active_stream_type = hdw->desired_stream_type;
3249         }
3250
3251         if (hdw->hdw_desc->signal_routing_scheme ==
3252             PVR2_ROUTING_SCHEME_GOTVIEW) {
3253                 u32 b;
3254                 /* Handle GOTVIEW audio switching */
3255                 pvr2_hdw_gpio_get_out(hdw,&b);
3256                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3257                         /* Set GPIO 11 */
3258                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3259                 } else {
3260                         /* Clear GPIO 11 */
3261                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3262                 }
3263         }
3264
3265         /* Check and update state for all sub-devices. */
3266         pvr2_subdev_update(hdw);
3267
3268         hdw->tuner_updated = 0;
3269         hdw->force_dirty = 0;
3270         for (idx = 0; idx < hdw->control_cnt; idx++) {
3271                 cptr = hdw->controls + idx;
3272                 if (!cptr->info->clear_dirty) continue;
3273                 cptr->info->clear_dirty(cptr);
3274         }
3275
3276         /* Now execute i2c core update */
3277         pvr2_i2c_core_sync(hdw);
3278
3279         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3280             hdw->state_encoder_run) {
3281                 /* If encoder isn't running or it can't be touched, then
3282                    this will get worked out later when we start the
3283                    encoder. */
3284                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3285         }
3286
3287         hdw->state_pipeline_config = !0;
3288         /* Hardware state may have changed in a way to cause the cropping
3289            capabilities to have changed.  So mark it stale, which will
3290            cause a later re-fetch. */
3291         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3292         return !0;
3293 }
3294
3295
3296 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3297 {
3298         int fl;
3299         LOCK_TAKE(hdw->big_lock);
3300         fl = pvr2_hdw_commit_setup(hdw);
3301         LOCK_GIVE(hdw->big_lock);
3302         if (!fl) return 0;
3303         return pvr2_hdw_wait(hdw,0);
3304 }
3305
3306
3307 static void pvr2_hdw_worker_i2c(struct work_struct *work)
3308 {
3309         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
3310         LOCK_TAKE(hdw->big_lock); do {
3311                 pvr2_i2c_core_sync(hdw);
3312         } while (0); LOCK_GIVE(hdw->big_lock);
3313 }
3314
3315
3316 static void pvr2_hdw_worker_poll(struct work_struct *work)
3317 {
3318         int fl = 0;
3319         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3320         LOCK_TAKE(hdw->big_lock); do {
3321                 fl = pvr2_hdw_state_eval(hdw);
3322         } while (0); LOCK_GIVE(hdw->big_lock);
3323         if (fl && hdw->state_func) {
3324                 hdw->state_func(hdw->state_data);
3325         }
3326 }
3327
3328
3329 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3330 {
3331         return wait_event_interruptible(
3332                 hdw->state_wait_data,
3333                 (hdw->state_stale == 0) &&
3334                 (!state || (hdw->master_state != state)));
3335 }
3336
3337
3338 /* Return name for this driver instance */
3339 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3340 {
3341         return hdw->name;
3342 }
3343
3344
3345 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3346 {
3347         return hdw->hdw_desc->description;
3348 }
3349
3350
3351 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3352 {
3353         return hdw->hdw_desc->shortname;
3354 }
3355
3356
3357 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3358 {
3359         int result;
3360         LOCK_TAKE(hdw->ctl_lock); do {
3361                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3362                 result = pvr2_send_request(hdw,
3363                                            hdw->cmd_buffer,1,
3364                                            hdw->cmd_buffer,1);
3365                 if (result < 0) break;
3366                 result = (hdw->cmd_buffer[0] != 0);
3367         } while(0); LOCK_GIVE(hdw->ctl_lock);
3368         return result;
3369 }
3370
3371
3372 /* Execute poll of tuner status */
3373 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3374 {
3375         LOCK_TAKE(hdw->big_lock); do {
3376                 pvr2_hdw_status_poll(hdw);
3377         } while (0); LOCK_GIVE(hdw->big_lock);
3378 }
3379
3380
3381 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3382 {
3383         if (!hdw->cropcap_stale) {
3384                 return 0;
3385         }
3386         pvr2_hdw_status_poll(hdw);
3387         if (hdw->cropcap_stale) {
3388                 return -EIO;
3389         }
3390         return 0;
3391 }
3392
3393
3394 /* Return information about cropping capabilities */
3395 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3396 {
3397         int stat = 0;
3398         LOCK_TAKE(hdw->big_lock);
3399         stat = pvr2_hdw_check_cropcap(hdw);
3400         if (!stat) {
3401                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3402         }
3403         LOCK_GIVE(hdw->big_lock);
3404         return stat;
3405 }
3406
3407
3408 /* Return information about the tuner */
3409 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3410 {
3411         LOCK_TAKE(hdw->big_lock); do {
3412                 if (hdw->tuner_signal_stale) {
3413                         pvr2_hdw_status_poll(hdw);
3414                 }
3415                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3416         } while (0); LOCK_GIVE(hdw->big_lock);
3417         return 0;
3418 }
3419
3420
3421 /* Get handle to video output stream */
3422 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3423 {
3424         return hp->vid_stream;
3425 }
3426
3427
3428 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3429 {
3430         int nr = pvr2_hdw_get_unit_number(hdw);
3431         LOCK_TAKE(hdw->big_lock); do {
3432                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3433                 hdw->log_requested = !0;
3434                 pvr2_i2c_core_check_stale(hdw);
3435                 pvr2_i2c_core_sync(hdw);
3436                 hdw->log_requested = 0;
3437                 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3438                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3439                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3440                 pvr2_hdw_state_log_state(hdw);
3441                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3442         } while (0); LOCK_GIVE(hdw->big_lock);
3443 }
3444
3445
3446 /* Grab EEPROM contents, needed for direct method. */
3447 #define EEPROM_SIZE 8192
3448 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3449 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3450 {
3451         struct i2c_msg msg[2];
3452         u8 *eeprom;
3453         u8 iadd[2];
3454         u8 addr;
3455         u16 eepromSize;
3456         unsigned int offs;
3457         int ret;
3458         int mode16 = 0;
3459         unsigned pcnt,tcnt;
3460         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3461         if (!eeprom) {
3462                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3463                            "Failed to allocate memory"
3464                            " required to read eeprom");
3465                 return NULL;
3466         }
3467
3468         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3469                      hdw->eeprom_addr);
3470         addr = hdw->eeprom_addr;
3471         /* Seems that if the high bit is set, then the *real* eeprom
3472            address is shifted right now bit position (noticed this in
3473            newer PVR USB2 hardware) */
3474         if (addr & 0x80) addr >>= 1;
3475
3476         /* FX2 documentation states that a 16bit-addressed eeprom is
3477            expected if the I2C address is an odd number (yeah, this is
3478            strange but it's what they do) */
3479         mode16 = (addr & 1);
3480         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3481         trace_eeprom("Examining %d byte eeprom at location 0x%x"
3482                      " using %d bit addressing",eepromSize,addr,
3483                      mode16 ? 16 : 8);
3484
3485         msg[0].addr = addr;
3486         msg[0].flags = 0;
3487         msg[0].len = mode16 ? 2 : 1;
3488         msg[0].buf = iadd;
3489         msg[1].addr = addr;
3490         msg[1].flags = I2C_M_RD;
3491
3492         /* We have to do the actual eeprom data fetch ourselves, because
3493            (1) we're only fetching part of the eeprom, and (2) if we were
3494            getting the whole thing our I2C driver can't grab it in one
3495            pass - which is what tveeprom is otherwise going to attempt */
3496         memset(eeprom,0,EEPROM_SIZE);
3497         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3498                 pcnt = 16;
3499                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3500                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3501                 if (mode16) {
3502                         iadd[0] = offs >> 8;
3503                         iadd[1] = offs;
3504                 } else {
3505                         iadd[0] = offs;
3506                 }
3507                 msg[1].len = pcnt;
3508                 msg[1].buf = eeprom+tcnt;
3509                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3510                                         msg,ARRAY_SIZE(msg))) != 2) {
3511                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3512                                    "eeprom fetch set offs err=%d",ret);
3513                         kfree(eeprom);
3514                         return NULL;
3515                 }
3516         }
3517         return eeprom;
3518 }
3519
3520
3521 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3522                                 int prom_flag,
3523                                 int enable_flag)
3524 {
3525         int ret;
3526         u16 address;
3527         unsigned int pipe;
3528         LOCK_TAKE(hdw->big_lock); do {
3529                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3530
3531                 if (!enable_flag) {
3532                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3533                                    "Cleaning up after CPU firmware fetch");
3534                         kfree(hdw->fw_buffer);
3535                         hdw->fw_buffer = NULL;
3536                         hdw->fw_size = 0;
3537                         if (hdw->fw_cpu_flag) {
3538                                 /* Now release the CPU.  It will disconnect
3539                                    and reconnect later. */
3540                                 pvr2_hdw_cpureset_assert(hdw,0);
3541                         }
3542                         break;
3543                 }
3544
3545                 hdw->fw_cpu_flag = (prom_flag == 0);
3546                 if (hdw->fw_cpu_flag) {
3547                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3548                                    "Preparing to suck out CPU firmware");
3549                         hdw->fw_size = 0x2000;
3550                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3551                         if (!hdw->fw_buffer) {
3552                                 hdw->fw_size = 0;
3553                                 break;
3554                         }
3555
3556                         /* We have to hold the CPU during firmware upload. */
3557                         pvr2_hdw_cpureset_assert(hdw,1);
3558
3559                         /* download the firmware from address 0000-1fff in 2048
3560                            (=0x800) bytes chunk. */
3561
3562                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3563                                    "Grabbing CPU firmware");
3564                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3565                         for(address = 0; address < hdw->fw_size;
3566                             address += 0x800) {
3567                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3568                                                       0xa0,0xc0,
3569                                                       address,0,
3570                                                       hdw->fw_buffer+address,
3571                                                       0x800,HZ);
3572                                 if (ret < 0) break;
3573                         }
3574
3575                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3576                                    "Done grabbing CPU firmware");
3577                 } else {
3578                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3579                                    "Sucking down EEPROM contents");
3580                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3581                         if (!hdw->fw_buffer) {
3582                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3583                                            "EEPROM content suck failed.");
3584                                 break;
3585                         }
3586                         hdw->fw_size = EEPROM_SIZE;
3587                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3588                                    "Done sucking down EEPROM contents");
3589                 }
3590
3591         } while (0); LOCK_GIVE(hdw->big_lock);
3592 }
3593
3594
3595 /* Return true if we're in a mode for retrieval CPU firmware */
3596 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3597 {
3598         return hdw->fw_buffer != NULL;
3599 }
3600
3601
3602 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3603                        char *buf,unsigned int cnt)
3604 {
3605         int ret = -EINVAL;
3606         LOCK_TAKE(hdw->big_lock); do {
3607                 if (!buf) break;
3608                 if (!cnt) break;
3609
3610                 if (!hdw->fw_buffer) {
3611                         ret = -EIO;
3612                         break;
3613                 }
3614
3615                 if (offs >= hdw->fw_size) {
3616                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3617                                    "Read firmware data offs=%d EOF",
3618                                    offs);
3619                         ret = 0;
3620                         break;
3621                 }
3622
3623                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3624
3625                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3626
3627                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3628                            "Read firmware data offs=%d cnt=%d",
3629                            offs,cnt);
3630                 ret = cnt;
3631         } while (0); LOCK_GIVE(hdw->big_lock);
3632
3633         return ret;
3634 }
3635
3636
3637 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3638                                   enum pvr2_v4l_type index)
3639 {
3640         switch (index) {
3641         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3642         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3643         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3644         default: return -1;
3645         }
3646 }
3647
3648
3649 /* Store a v4l minor device number */
3650 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3651                                      enum pvr2_v4l_type index,int v)
3652 {
3653         switch (index) {
3654         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3655         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3656         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
3657         default: break;
3658         }
3659 }
3660
3661
3662 static void pvr2_ctl_write_complete(struct urb *urb)
3663 {
3664         struct pvr2_hdw *hdw = urb->context;
3665         hdw->ctl_write_pend_flag = 0;
3666         if (hdw->ctl_read_pend_flag) return;
3667         complete(&hdw->ctl_done);
3668 }
3669
3670
3671 static void pvr2_ctl_read_complete(struct urb *urb)
3672 {
3673         struct pvr2_hdw *hdw = urb->context;
3674         hdw->ctl_read_pend_flag = 0;
3675         if (hdw->ctl_write_pend_flag) return;
3676         complete(&hdw->ctl_done);
3677 }
3678
3679
3680 static void pvr2_ctl_timeout(unsigned long data)
3681 {
3682         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3683         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3684                 hdw->ctl_timeout_flag = !0;
3685                 if (hdw->ctl_write_pend_flag)
3686                         usb_unlink_urb(hdw->ctl_write_urb);
3687                 if (hdw->ctl_read_pend_flag)
3688                         usb_unlink_urb(hdw->ctl_read_urb);
3689         }
3690 }
3691
3692
3693 /* Issue a command and get a response from the device.  This extended
3694    version includes a probe flag (which if set means that device errors
3695    should not be logged or treated as fatal) and a timeout in jiffies.
3696    This can be used to non-lethally probe the health of endpoint 1. */
3697 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3698                                 unsigned int timeout,int probe_fl,
3699                                 void *write_data,unsigned int write_len,
3700                                 void *read_data,unsigned int read_len)
3701 {
3702         unsigned int idx;
3703         int status = 0;
3704         struct timer_list timer;
3705         if (!hdw->ctl_lock_held) {
3706                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3707                            "Attempted to execute control transfer"
3708                            " without lock!!");
3709                 return -EDEADLK;
3710         }
3711         if (!hdw->flag_ok && !probe_fl) {
3712                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3713                            "Attempted to execute control transfer"
3714                            " when device not ok");
3715                 return -EIO;
3716         }
3717         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3718                 if (!probe_fl) {
3719                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3720                                    "Attempted to execute control transfer"
3721                                    " when USB is disconnected");
3722                 }
3723                 return -ENOTTY;
3724         }
3725
3726         /* Ensure that we have sane parameters */
3727         if (!write_data) write_len = 0;
3728         if (!read_data) read_len = 0;
3729         if (write_len > PVR2_CTL_BUFFSIZE) {
3730                 pvr2_trace(
3731                         PVR2_TRACE_ERROR_LEGS,
3732                         "Attempted to execute %d byte"
3733                         " control-write transfer (limit=%d)",
3734                         write_len,PVR2_CTL_BUFFSIZE);
3735                 return -EINVAL;
3736         }
3737         if (read_len > PVR2_CTL_BUFFSIZE) {
3738                 pvr2_trace(
3739                         PVR2_TRACE_ERROR_LEGS,
3740                         "Attempted to execute %d byte"
3741                         " control-read transfer (limit=%d)",
3742                         write_len,PVR2_CTL_BUFFSIZE);
3743                 return -EINVAL;
3744         }
3745         if ((!write_len) && (!read_len)) {
3746                 pvr2_trace(
3747                         PVR2_TRACE_ERROR_LEGS,
3748                         "Attempted to execute null control transfer?");
3749                 return -EINVAL;
3750         }
3751
3752
3753         hdw->cmd_debug_state = 1;
3754         if (write_len) {
3755                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3756         } else {
3757                 hdw->cmd_debug_code = 0;
3758         }
3759         hdw->cmd_debug_write_len = write_len;
3760         hdw->cmd_debug_read_len = read_len;
3761
3762         /* Initialize common stuff */
3763         init_completion(&hdw->ctl_done);
3764         hdw->ctl_timeout_flag = 0;
3765         hdw->ctl_write_pend_flag = 0;
3766         hdw->ctl_read_pend_flag = 0;
3767         init_timer(&timer);
3768         timer.expires = jiffies + timeout;
3769         timer.data = (unsigned long)hdw;
3770         timer.function = pvr2_ctl_timeout;
3771
3772         if (write_len) {
3773                 hdw->cmd_debug_state = 2;
3774                 /* Transfer write data to internal buffer */
3775                 for (idx = 0; idx < write_len; idx++) {
3776                         hdw->ctl_write_buffer[idx] =
3777                                 ((unsigned char *)write_data)[idx];
3778                 }
3779                 /* Initiate a write request */
3780                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3781                                   hdw->usb_dev,
3782                                   usb_sndbulkpipe(hdw->usb_dev,
3783                                                   PVR2_CTL_WRITE_ENDPOINT),
3784                                   hdw->ctl_write_buffer,
3785                                   write_len,
3786                                   pvr2_ctl_write_complete,
3787                                   hdw);
3788                 hdw->ctl_write_urb->actual_length = 0;
3789                 hdw->ctl_write_pend_flag = !0;
3790                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3791                 if (status < 0) {
3792                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3793                                    "Failed to submit write-control"
3794                                    " URB status=%d",status);
3795                         hdw->ctl_write_pend_flag = 0;
3796                         goto done;
3797                 }
3798         }
3799
3800         if (read_len) {
3801                 hdw->cmd_debug_state = 3;
3802                 memset(hdw->ctl_read_buffer,0x43,read_len);
3803                 /* Initiate a read request */
3804                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3805                                   hdw->usb_dev,
3806                                   usb_rcvbulkpipe(hdw->usb_dev,
3807                                                   PVR2_CTL_READ_ENDPOINT),
3808                                   hdw->ctl_read_buffer,
3809                                   read_len,
3810                                   pvr2_ctl_read_complete,
3811                                   hdw);
3812                 hdw->ctl_read_urb->actual_length = 0;
3813                 hdw->ctl_read_pend_flag = !0;
3814                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3815                 if (status < 0) {
3816                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3817                                    "Failed to submit read-control"
3818                                    " URB status=%d",status);
3819                         hdw->ctl_read_pend_flag = 0;
3820                         goto done;
3821                 }
3822         }
3823
3824         /* Start timer */
3825         add_timer(&timer);
3826
3827         /* Now wait for all I/O to complete */
3828         hdw->cmd_debug_state = 4;
3829         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3830                 wait_for_completion(&hdw->ctl_done);
3831         }
3832         hdw->cmd_debug_state = 5;
3833
3834         /* Stop timer */
3835         del_timer_sync(&timer);
3836
3837         hdw->cmd_debug_state = 6;
3838         status = 0;
3839
3840         if (hdw->ctl_timeout_flag) {
3841                 status = -ETIMEDOUT;
3842                 if (!probe_fl) {
3843                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3844                                    "Timed out control-write");
3845                 }
3846                 goto done;
3847         }
3848
3849         if (write_len) {
3850                 /* Validate results of write request */
3851                 if ((hdw->ctl_write_urb->status != 0) &&
3852                     (hdw->ctl_write_urb->status != -ENOENT) &&
3853                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3854                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3855                         /* USB subsystem is reporting some kind of failure
3856                            on the write */
3857                         status = hdw->ctl_write_urb->status;
3858                         if (!probe_fl) {
3859                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3860                                            "control-write URB failure,"
3861                                            " status=%d",
3862                                            status);
3863                         }
3864                         goto done;
3865                 }
3866                 if (hdw->ctl_write_urb->actual_length < write_len) {
3867                         /* Failed to write enough data */
3868                         status = -EIO;
3869                         if (!probe_fl) {
3870                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3871                                            "control-write URB short,"
3872                                            " expected=%d got=%d",
3873                                            write_len,
3874                                            hdw->ctl_write_urb->actual_length);
3875                         }
3876                         goto done;
3877                 }
3878         }
3879         if (read_len) {
3880                 /* Validate results of read request */
3881                 if ((hdw->ctl_read_urb->status != 0) &&
3882                     (hdw->ctl_read_urb->status != -ENOENT) &&
3883                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3884                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3885                         /* USB subsystem is reporting some kind of failure
3886                            on the read */
3887                         status = hdw->ctl_read_urb->status;
3888                         if (!probe_fl) {
3889                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3890                                            "control-read URB failure,"
3891                                            " status=%d",
3892                                            status);
3893                         }
3894                         goto done;
3895                 }
3896                 if (hdw->ctl_read_urb->actual_length < read_len) {
3897                         /* Failed to read enough data */
3898                         status = -EIO;
3899                         if (!probe_fl) {
3900                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3901                                            "control-read URB short,"
3902                                            " expected=%d got=%d",
3903                                            read_len,
3904                                            hdw->ctl_read_urb->actual_length);
3905                         }
3906                         goto done;
3907                 }
3908                 /* Transfer retrieved data out from internal buffer */
3909                 for (idx = 0; idx < read_len; idx++) {
3910                         ((unsigned char *)read_data)[idx] =
3911                                 hdw->ctl_read_buffer[idx];
3912                 }
3913         }
3914
3915  done:
3916
3917         hdw->cmd_debug_state = 0;
3918         if ((status < 0) && (!probe_fl)) {
3919                 pvr2_hdw_render_useless(hdw);
3920         }
3921         return status;
3922 }
3923
3924
3925 int pvr2_send_request(struct pvr2_hdw *hdw,
3926                       void *write_data,unsigned int write_len,
3927                       void *read_data,unsigned int read_len)
3928 {
3929         return pvr2_send_request_ex(hdw,HZ*4,0,
3930                                     write_data,write_len,
3931                                     read_data,read_len);
3932 }
3933
3934
3935 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3936 {
3937         int ret;
3938         unsigned int cnt = 1;
3939         unsigned int args = 0;
3940         LOCK_TAKE(hdw->ctl_lock);
3941         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3942         args = (cmdcode >> 8) & 0xffu;
3943         args = (args > 2) ? 2 : args;
3944         if (args) {
3945                 cnt += args;
3946                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3947                 if (args > 1) {
3948                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3949                 }
3950         }
3951         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3952                 unsigned int idx;
3953                 unsigned int ccnt,bcnt;
3954                 char tbuf[50];
3955                 cmdcode &= 0xffu;
3956                 bcnt = 0;
3957                 ccnt = scnprintf(tbuf+bcnt,
3958                                  sizeof(tbuf)-bcnt,
3959                                  "Sending FX2 command 0x%x",cmdcode);
3960                 bcnt += ccnt;
3961                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3962                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3963                                 ccnt = scnprintf(tbuf+bcnt,
3964                                                  sizeof(tbuf)-bcnt,
3965                                                  " \"%s\"",
3966                                                  pvr2_fx2cmd_desc[idx].desc);
3967                                 bcnt += ccnt;
3968                                 break;
3969                         }
3970                 }
3971                 if (args) {
3972                         ccnt = scnprintf(tbuf+bcnt,
3973                                          sizeof(tbuf)-bcnt,
3974                                          " (%u",hdw->cmd_buffer[1]);
3975                         bcnt += ccnt;
3976                         if (args > 1) {
3977                                 ccnt = scnprintf(tbuf+bcnt,
3978                                                  sizeof(tbuf)-bcnt,
3979                                                  ",%u",hdw->cmd_buffer[2]);
3980                                 bcnt += ccnt;
3981                         }
3982                         ccnt = scnprintf(tbuf+bcnt,
3983                                          sizeof(tbuf)-bcnt,
3984                                          ")");
3985                         bcnt += ccnt;
3986                 }
3987                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3988         }
3989         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3990         LOCK_GIVE(hdw->ctl_lock);
3991         return ret;
3992 }
3993
3994
3995 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3996 {
3997         int ret;
3998
3999         LOCK_TAKE(hdw->ctl_lock);
4000
4001         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
4002         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
4003         hdw->cmd_buffer[5] = 0;
4004         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4005         hdw->cmd_buffer[7] = reg & 0xff;
4006
4007
4008         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
4009
4010         LOCK_GIVE(hdw->ctl_lock);
4011
4012         return ret;
4013 }
4014
4015
4016 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
4017 {
4018         int ret = 0;
4019
4020         LOCK_TAKE(hdw->ctl_lock);
4021
4022         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
4023         hdw->cmd_buffer[1] = 0;
4024         hdw->cmd_buffer[2] = 0;
4025         hdw->cmd_buffer[3] = 0;
4026         hdw->cmd_buffer[4] = 0;
4027         hdw->cmd_buffer[5] = 0;
4028         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4029         hdw->cmd_buffer[7] = reg & 0xff;
4030
4031         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
4032         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
4033
4034         LOCK_GIVE(hdw->ctl_lock);
4035
4036         return ret;
4037 }
4038
4039
4040 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
4041 {
4042         if (!hdw->flag_ok) return;
4043         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4044                    "Device being rendered inoperable");
4045         if (hdw->vid_stream) {
4046                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
4047         }
4048         hdw->flag_ok = 0;
4049         trace_stbit("flag_ok",hdw->flag_ok);
4050         pvr2_hdw_state_sched(hdw);
4051 }
4052
4053
4054 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4055 {
4056         int ret;
4057         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
4058         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
4059         if (ret == 0) {
4060                 ret = usb_reset_device(hdw->usb_dev);
4061                 usb_unlock_device(hdw->usb_dev);
4062         } else {
4063                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4064                            "Failed to lock USB device ret=%d",ret);
4065         }
4066         if (init_pause_msec) {
4067                 pvr2_trace(PVR2_TRACE_INFO,
4068                            "Waiting %u msec for hardware to settle",
4069                            init_pause_msec);
4070                 msleep(init_pause_msec);
4071         }
4072
4073 }
4074
4075
4076 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4077 {
4078         char da[1];
4079         unsigned int pipe;
4080         int ret;
4081
4082         if (!hdw->usb_dev) return;
4083
4084         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4085
4086         da[0] = val ? 0x01 : 0x00;
4087
4088         /* Write the CPUCS register on the 8051.  The lsb of the register
4089            is the reset bit; a 1 asserts reset while a 0 clears it. */
4090         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4091         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4092         if (ret < 0) {
4093                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4094                            "cpureset_assert(%d) error=%d",val,ret);
4095                 pvr2_hdw_render_useless(hdw);
4096         }
4097 }
4098
4099
4100 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4101 {
4102         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
4103 }
4104
4105
4106 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4107 {
4108         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4109 }
4110
4111
4112 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4113 {
4114         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
4115 }
4116
4117
4118 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4119 {
4120         pvr2_trace(PVR2_TRACE_INIT,
4121                    "Requesting decoder reset");
4122         if (hdw->decoder_ctrl) {
4123                 if (!hdw->decoder_ctrl->force_reset) {
4124                         pvr2_trace(PVR2_TRACE_INIT,
4125                                    "Unable to reset decoder: not implemented");
4126                         return -ENOTTY;
4127                 }
4128                 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
4129                 return 0;
4130         } else {
4131         }
4132         if (hdw->decoder_client_id) {
4133                 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4134                                      core, reset, 0);
4135                 return 0;
4136         }
4137         pvr2_trace(PVR2_TRACE_INIT,
4138                    "Unable to reset decoder: nothing attached");
4139         return -ENOTTY;
4140 }
4141
4142
4143 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4144 {
4145         hdw->flag_ok = !0;
4146         return pvr2_issue_simple_cmd(hdw,
4147                                      FX2CMD_HCW_DEMOD_RESETIN |
4148                                      (1 << 8) |
4149                                      ((onoff ? 1 : 0) << 16));
4150 }
4151
4152
4153 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4154 {
4155         hdw->flag_ok = !0;
4156         return pvr2_issue_simple_cmd(hdw,(onoff ?
4157                                           FX2CMD_ONAIR_DTV_POWER_ON :
4158                                           FX2CMD_ONAIR_DTV_POWER_OFF));
4159 }
4160
4161
4162 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4163                                                 int onoff)
4164 {
4165         return pvr2_issue_simple_cmd(hdw,(onoff ?
4166                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
4167                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
4168 }
4169
4170
4171 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4172 {
4173         int cmode;
4174         /* Compare digital/analog desired setting with current setting.  If
4175            they don't match, fix it... */
4176         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4177         if (cmode == hdw->pathway_state) {
4178                 /* They match; nothing to do */
4179                 return;
4180         }
4181
4182         switch (hdw->hdw_desc->digital_control_scheme) {
4183         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4184                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4185                 if (cmode == PVR2_PATHWAY_ANALOG) {
4186                         /* If moving to analog mode, also force the decoder
4187                            to reset.  If no decoder is attached, then it's
4188                            ok to ignore this because if/when the decoder
4189                            attaches, it will reset itself at that time. */
4190                         pvr2_hdw_cmd_decoder_reset(hdw);
4191                 }
4192                 break;
4193         case PVR2_DIGITAL_SCHEME_ONAIR:
4194                 /* Supposedly we should always have the power on whether in
4195                    digital or analog mode.  But for now do what appears to
4196                    work... */
4197                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4198                 break;
4199         default: break;
4200         }
4201
4202         pvr2_hdw_untrip_unlocked(hdw);
4203         hdw->pathway_state = cmode;
4204 }
4205
4206
4207 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4208 {
4209         /* change some GPIO data
4210          *
4211          * note: bit d7 of dir appears to control the LED,
4212          * so we shut it off here.
4213          *
4214          */
4215         if (onoff) {
4216                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4217         } else {
4218                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4219         }
4220         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4221 }
4222
4223
4224 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4225
4226 static led_method_func led_methods[] = {
4227         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4228 };
4229
4230
4231 /* Toggle LED */
4232 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4233 {
4234         unsigned int scheme_id;
4235         led_method_func fp;
4236
4237         if ((!onoff) == (!hdw->led_on)) return;
4238
4239         hdw->led_on = onoff != 0;
4240
4241         scheme_id = hdw->hdw_desc->led_scheme;
4242         if (scheme_id < ARRAY_SIZE(led_methods)) {
4243                 fp = led_methods[scheme_id];
4244         } else {
4245                 fp = NULL;
4246         }
4247
4248         if (fp) (*fp)(hdw,onoff);
4249 }
4250
4251
4252 /* Stop / start video stream transport */
4253 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4254 {
4255         int ret;
4256
4257         /* If we're in analog mode, then just issue the usual analog
4258            command. */
4259         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4260                 return pvr2_issue_simple_cmd(hdw,
4261                                              (runFl ?
4262                                               FX2CMD_STREAMING_ON :
4263                                               FX2CMD_STREAMING_OFF));
4264                 /*Note: Not reached */
4265         }
4266
4267         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4268                 /* Whoops, we don't know what mode we're in... */
4269                 return -EINVAL;
4270         }
4271
4272         /* To get here we have to be in digital mode.  The mechanism here
4273            is unfortunately different for different vendors.  So we switch
4274            on the device's digital scheme attribute in order to figure out
4275            what to do. */
4276         switch (hdw->hdw_desc->digital_control_scheme) {
4277         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4278                 return pvr2_issue_simple_cmd(hdw,
4279                                              (runFl ?
4280                                               FX2CMD_HCW_DTV_STREAMING_ON :
4281                                               FX2CMD_HCW_DTV_STREAMING_OFF));
4282         case PVR2_DIGITAL_SCHEME_ONAIR:
4283                 ret = pvr2_issue_simple_cmd(hdw,
4284                                             (runFl ?
4285                                              FX2CMD_STREAMING_ON :
4286                                              FX2CMD_STREAMING_OFF));
4287                 if (ret) return ret;
4288                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4289         default:
4290                 return -EINVAL;
4291         }
4292 }
4293
4294
4295 /* Evaluate whether or not state_pathway_ok can change */
4296 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4297 {
4298         if (hdw->state_pathway_ok) {
4299                 /* Nothing to do if pathway is already ok */
4300                 return 0;
4301         }
4302         if (!hdw->state_pipeline_idle) {
4303                 /* Not allowed to change anything if pipeline is not idle */
4304                 return 0;
4305         }
4306         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4307         hdw->state_pathway_ok = !0;
4308         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4309         return !0;
4310 }
4311
4312
4313 /* Evaluate whether or not state_encoder_ok can change */
4314 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4315 {
4316         if (hdw->state_encoder_ok) return 0;
4317         if (hdw->flag_tripped) return 0;
4318         if (hdw->state_encoder_run) return 0;
4319         if (hdw->state_encoder_config) return 0;
4320         if (hdw->state_decoder_run) return 0;
4321         if (hdw->state_usbstream_run) return 0;
4322         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4323                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4324         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4325                 return 0;
4326         }
4327
4328         if (pvr2_upload_firmware2(hdw) < 0) {
4329                 hdw->flag_tripped = !0;
4330                 trace_stbit("flag_tripped",hdw->flag_tripped);
4331                 return !0;
4332         }
4333         hdw->state_encoder_ok = !0;
4334         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4335         return !0;
4336 }
4337
4338
4339 /* Evaluate whether or not state_encoder_config can change */
4340 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4341 {
4342         if (hdw->state_encoder_config) {
4343                 if (hdw->state_encoder_ok) {
4344                         if (hdw->state_pipeline_req &&
4345                             !hdw->state_pipeline_pause) return 0;
4346                 }
4347                 hdw->state_encoder_config = 0;
4348                 hdw->state_encoder_waitok = 0;
4349                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4350                 /* paranoia - solve race if timer just completed */
4351                 del_timer_sync(&hdw->encoder_wait_timer);
4352         } else {
4353                 if (!hdw->state_pathway_ok ||
4354                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4355                     !hdw->state_encoder_ok ||
4356                     !hdw->state_pipeline_idle ||
4357                     hdw->state_pipeline_pause ||
4358                     !hdw->state_pipeline_req ||
4359                     !hdw->state_pipeline_config) {
4360                         /* We must reset the enforced wait interval if
4361                            anything has happened that might have disturbed
4362                            the encoder.  This should be a rare case. */
4363                         if (timer_pending(&hdw->encoder_wait_timer)) {
4364                                 del_timer_sync(&hdw->encoder_wait_timer);
4365                         }
4366                         if (hdw->state_encoder_waitok) {
4367                                 /* Must clear the state - therefore we did
4368                                    something to a state bit and must also
4369                                    return true. */
4370                                 hdw->state_encoder_waitok = 0;
4371                                 trace_stbit("state_encoder_waitok",
4372                                             hdw->state_encoder_waitok);
4373                                 return !0;
4374                         }
4375                         return 0;
4376                 }
4377                 if (!hdw->state_encoder_waitok) {
4378                         if (!timer_pending(&hdw->encoder_wait_timer)) {
4379                                 /* waitok flag wasn't set and timer isn't
4380                                    running.  Check flag once more to avoid
4381                                    a race then start the timer.  This is
4382                                    the point when we measure out a minimal
4383                                    quiet interval before doing something to
4384                                    the encoder. */
4385                                 if (!hdw->state_encoder_waitok) {
4386                                         hdw->encoder_wait_timer.expires =
4387                                                 jiffies +
4388                                                 (HZ * TIME_MSEC_ENCODER_WAIT
4389                                                  / 1000);
4390                                         add_timer(&hdw->encoder_wait_timer);
4391                                 }
4392                         }
4393                         /* We can't continue until we know we have been
4394                            quiet for the interval measured by this
4395                            timer. */
4396                         return 0;
4397                 }
4398                 pvr2_encoder_configure(hdw);
4399                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4400         }
4401         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4402         return !0;
4403 }
4404
4405
4406 /* Return true if the encoder should not be running. */
4407 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4408 {
4409         if (!hdw->state_encoder_ok) {
4410                 /* Encoder isn't healthy at the moment, so stop it. */
4411                 return !0;
4412         }
4413         if (!hdw->state_pathway_ok) {
4414                 /* Mode is not understood at the moment (i.e. it wants to
4415                    change), so encoder must be stopped. */
4416                 return !0;
4417         }
4418
4419         switch (hdw->pathway_state) {
4420         case PVR2_PATHWAY_ANALOG:
4421                 if (!hdw->state_decoder_run) {
4422                         /* We're in analog mode and the decoder is not
4423                            running; thus the encoder should be stopped as
4424                            well. */
4425                         return !0;
4426                 }
4427                 break;
4428         case PVR2_PATHWAY_DIGITAL:
4429                 if (hdw->state_encoder_runok) {
4430                         /* This is a funny case.  We're in digital mode so
4431                            really the encoder should be stopped.  However
4432                            if it really is running, only kill it after
4433                            runok has been set.  This gives a chance for the
4434                            onair quirk to function (encoder must run
4435                            briefly first, at least once, before onair
4436                            digital streaming can work). */
4437                         return !0;
4438                 }
4439                 break;
4440         default:
4441                 /* Unknown mode; so encoder should be stopped. */
4442                 return !0;
4443         }
4444
4445         /* If we get here, we haven't found a reason to stop the
4446            encoder. */
4447         return 0;
4448 }
4449
4450
4451 /* Return true if the encoder should be running. */
4452 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4453 {
4454         if (!hdw->state_encoder_ok) {
4455                 /* Don't run the encoder if it isn't healthy... */
4456                 return 0;
4457         }
4458         if (!hdw->state_pathway_ok) {
4459                 /* Don't run the encoder if we don't (yet) know what mode
4460                    we need to be in... */
4461                 return 0;
4462         }
4463
4464         switch (hdw->pathway_state) {
4465         case PVR2_PATHWAY_ANALOG:
4466                 if (hdw->state_decoder_run) {
4467                         /* In analog mode, if the decoder is running, then
4468                            run the encoder. */
4469                         return !0;
4470                 }
4471                 break;
4472         case PVR2_PATHWAY_DIGITAL:
4473                 if ((hdw->hdw_desc->digital_control_scheme ==
4474                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4475                     !hdw->state_encoder_runok) {
4476                         /* This is a quirk.  OnAir hardware won't stream
4477                            digital until the encoder has been run at least
4478                            once, for a minimal period of time (empiricially
4479                            measured to be 1/4 second).  So if we're on
4480                            OnAir hardware and the encoder has never been
4481                            run at all, then start the encoder.  Normal
4482                            state machine logic in the driver will
4483                            automatically handle the remaining bits. */
4484                         return !0;
4485                 }
4486                 break;
4487         default:
4488                 /* For completeness (unknown mode; encoder won't run ever) */
4489                 break;
4490         }
4491         /* If we get here, then we haven't found any reason to run the
4492            encoder, so don't run it. */
4493         return 0;
4494 }
4495
4496
4497 /* Evaluate whether or not state_encoder_run can change */
4498 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4499 {
4500         if (hdw->state_encoder_run) {
4501                 if (!state_check_disable_encoder_run(hdw)) return 0;
4502                 if (hdw->state_encoder_ok) {
4503                         del_timer_sync(&hdw->encoder_run_timer);
4504                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4505                 }
4506                 hdw->state_encoder_run = 0;
4507         } else {
4508                 if (!state_check_enable_encoder_run(hdw)) return 0;
4509                 if (pvr2_encoder_start(hdw) < 0) return !0;
4510                 hdw->state_encoder_run = !0;
4511                 if (!hdw->state_encoder_runok) {
4512                         hdw->encoder_run_timer.expires =
4513                                 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4514                         add_timer(&hdw->encoder_run_timer);
4515                 }
4516         }
4517         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4518         return !0;
4519 }
4520
4521
4522 /* Timeout function for quiescent timer. */
4523 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4524 {
4525         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4526         hdw->state_decoder_quiescent = !0;
4527         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4528         hdw->state_stale = !0;
4529         queue_work(hdw->workqueue,&hdw->workpoll);
4530 }
4531
4532
4533 /* Timeout function for encoder wait timer. */
4534 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4535 {
4536         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4537         hdw->state_encoder_waitok = !0;
4538         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4539         hdw->state_stale = !0;
4540         queue_work(hdw->workqueue,&hdw->workpoll);
4541 }
4542
4543
4544 /* Timeout function for encoder run timer. */
4545 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4546 {
4547         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4548         if (!hdw->state_encoder_runok) {
4549                 hdw->state_encoder_runok = !0;
4550                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4551                 hdw->state_stale = !0;
4552                 queue_work(hdw->workqueue,&hdw->workpoll);
4553         }
4554 }
4555
4556
4557 /* Evaluate whether or not state_decoder_run can change */
4558 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4559 {
4560         if (hdw->state_decoder_run) {
4561                 if (hdw->state_encoder_ok) {
4562                         if (hdw->state_pipeline_req &&
4563                             !hdw->state_pipeline_pause &&
4564                             hdw->state_pathway_ok) return 0;
4565                 }
4566                 if (!hdw->flag_decoder_missed) {
4567                         pvr2_decoder_enable(hdw,0);
4568                 }
4569                 hdw->state_decoder_quiescent = 0;
4570                 hdw->state_decoder_run = 0;
4571                 /* paranoia - solve race if timer just completed */
4572                 del_timer_sync(&hdw->quiescent_timer);
4573         } else {
4574                 if (!hdw->state_decoder_quiescent) {
4575                         if (!timer_pending(&hdw->quiescent_timer)) {
4576                                 /* We don't do something about the
4577                                    quiescent timer until right here because
4578                                    we also want to catch cases where the
4579                                    decoder was already not running (like
4580                                    after initialization) as opposed to
4581                                    knowing that we had just stopped it.
4582                                    The second flag check is here to cover a
4583                                    race - the timer could have run and set
4584                                    this flag just after the previous check
4585                                    but before we did the pending check. */
4586                                 if (!hdw->state_decoder_quiescent) {
4587                                         hdw->quiescent_timer.expires =
4588                                                 jiffies +
4589                                                 (HZ * TIME_MSEC_DECODER_WAIT
4590                                                  / 1000);
4591                                         add_timer(&hdw->quiescent_timer);
4592                                 }
4593                         }
4594                         /* Don't allow decoder to start again until it has
4595                            been quiesced first.  This little detail should
4596                            hopefully further stabilize the encoder. */
4597                         return 0;
4598                 }
4599                 if (!hdw->state_pathway_ok ||
4600                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4601                     !hdw->state_pipeline_req ||
4602                     hdw->state_pipeline_pause ||
4603                     !hdw->state_pipeline_config ||
4604                     !hdw->state_encoder_config ||
4605                     !hdw->state_encoder_ok) return 0;
4606                 del_timer_sync(&hdw->quiescent_timer);
4607                 if (hdw->flag_decoder_missed) return 0;
4608                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4609                 hdw->state_decoder_quiescent = 0;
4610                 hdw->state_decoder_run = !0;
4611         }
4612         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4613         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4614         return !0;
4615 }
4616
4617
4618 /* Evaluate whether or not state_usbstream_run can change */
4619 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4620 {
4621         if (hdw->state_usbstream_run) {
4622                 int fl = !0;
4623                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4624                         fl = (hdw->state_encoder_ok &&
4625                               hdw->state_encoder_run);
4626                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4627                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4628                         fl = hdw->state_encoder_ok;
4629                 }
4630                 if (fl &&
4631                     hdw->state_pipeline_req &&
4632                     !hdw->state_pipeline_pause &&
4633                     hdw->state_pathway_ok) {
4634                         return 0;
4635                 }
4636                 pvr2_hdw_cmd_usbstream(hdw,0);
4637                 hdw->state_usbstream_run = 0;
4638         } else {
4639                 if (!hdw->state_pipeline_req ||
4640                     hdw->state_pipeline_pause ||
4641                     !hdw->state_pathway_ok) return 0;
4642                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4643                         if (!hdw->state_encoder_ok ||
4644                             !hdw->state_encoder_run) return 0;
4645                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4646                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4647                         if (!hdw->state_encoder_ok) return 0;
4648                         if (hdw->state_encoder_run) return 0;
4649                         if (hdw->hdw_desc->digital_control_scheme ==
4650                             PVR2_DIGITAL_SCHEME_ONAIR) {
4651                                 /* OnAir digital receivers won't stream
4652                                    unless the analog encoder has run first.
4653                                    Why?  I have no idea.  But don't even
4654                                    try until we know the analog side is
4655                                    known to have run. */
4656                                 if (!hdw->state_encoder_runok) return 0;
4657                         }
4658                 }
4659                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4660                 hdw->state_usbstream_run = !0;
4661         }
4662         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4663         return !0;
4664 }
4665
4666
4667 /* Attempt to configure pipeline, if needed */
4668 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4669 {
4670         if (hdw->state_pipeline_config ||
4671             hdw->state_pipeline_pause) return 0;
4672         pvr2_hdw_commit_execute(hdw);
4673         return !0;
4674 }
4675
4676
4677 /* Update pipeline idle and pipeline pause tracking states based on other
4678    inputs.  This must be called whenever the other relevant inputs have
4679    changed. */
4680 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4681 {
4682         unsigned int st;
4683         int updatedFl = 0;
4684         /* Update pipeline state */
4685         st = !(hdw->state_encoder_run ||
4686                hdw->state_decoder_run ||
4687                hdw->state_usbstream_run ||
4688                (!hdw->state_decoder_quiescent));
4689         if (!st != !hdw->state_pipeline_idle) {
4690                 hdw->state_pipeline_idle = st;
4691                 updatedFl = !0;
4692         }
4693         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4694                 hdw->state_pipeline_pause = 0;
4695                 updatedFl = !0;
4696         }
4697         return updatedFl;
4698 }
4699
4700
4701 typedef int (*state_eval_func)(struct pvr2_hdw *);
4702
4703 /* Set of functions to be run to evaluate various states in the driver. */
4704 static const state_eval_func eval_funcs[] = {
4705         state_eval_pathway_ok,
4706         state_eval_pipeline_config,
4707         state_eval_encoder_ok,
4708         state_eval_encoder_config,
4709         state_eval_decoder_run,
4710         state_eval_encoder_run,
4711         state_eval_usbstream_run,
4712 };
4713
4714
4715 /* Process various states and return true if we did anything interesting. */
4716 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4717 {
4718         unsigned int i;
4719         int state_updated = 0;
4720         int check_flag;
4721
4722         if (!hdw->state_stale) return 0;
4723         if ((hdw->fw1_state != FW1_STATE_OK) ||
4724             !hdw->flag_ok) {
4725                 hdw->state_stale = 0;
4726                 return !0;
4727         }
4728         /* This loop is the heart of the entire driver.  It keeps trying to
4729            evaluate various bits of driver state until nothing changes for
4730            one full iteration.  Each "bit of state" tracks some global
4731            aspect of the driver, e.g. whether decoder should run, if
4732            pipeline is configured, usb streaming is on, etc.  We separately
4733            evaluate each of those questions based on other driver state to
4734            arrive at the correct running configuration. */
4735         do {
4736                 check_flag = 0;
4737                 state_update_pipeline_state(hdw);
4738                 /* Iterate over each bit of state */
4739                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4740                         if ((*eval_funcs[i])(hdw)) {
4741                                 check_flag = !0;
4742                                 state_updated = !0;
4743                                 state_update_pipeline_state(hdw);
4744                         }
4745                 }
4746         } while (check_flag && hdw->flag_ok);
4747         hdw->state_stale = 0;
4748         trace_stbit("state_stale",hdw->state_stale);
4749         return state_updated;
4750 }
4751
4752
4753 static unsigned int print_input_mask(unsigned int msk,
4754                                      char *buf,unsigned int acnt)
4755 {
4756         unsigned int idx,ccnt;
4757         unsigned int tcnt = 0;
4758         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4759                 if (!((1 << idx) & msk)) continue;
4760                 ccnt = scnprintf(buf+tcnt,
4761                                  acnt-tcnt,
4762                                  "%s%s",
4763                                  (tcnt ? ", " : ""),
4764                                  control_values_input[idx]);
4765                 tcnt += ccnt;
4766         }
4767         return tcnt;
4768 }
4769
4770
4771 static const char *pvr2_pathway_state_name(int id)
4772 {
4773         switch (id) {
4774         case PVR2_PATHWAY_ANALOG: return "analog";
4775         case PVR2_PATHWAY_DIGITAL: return "digital";
4776         default: return "unknown";
4777         }
4778 }
4779
4780
4781 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4782                                              char *buf,unsigned int acnt)
4783 {
4784         switch (which) {
4785         case 0:
4786                 return scnprintf(
4787                         buf,acnt,
4788                         "driver:%s%s%s%s%s <mode=%s>",
4789                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4790                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4791                         (hdw->flag_disconnected ? " <disconnected>" :
4792                          " <connected>"),
4793                         (hdw->flag_tripped ? " <tripped>" : ""),
4794                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4795                         pvr2_pathway_state_name(hdw->pathway_state));
4796
4797         case 1:
4798                 return scnprintf(
4799                         buf,acnt,
4800                         "pipeline:%s%s%s%s",
4801                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4802                         (hdw->state_pipeline_config ?
4803                          " <configok>" : " <stale>"),
4804                         (hdw->state_pipeline_req ? " <req>" : ""),
4805                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4806         case 2:
4807                 return scnprintf(
4808                         buf,acnt,
4809                         "worker:%s%s%s%s%s%s%s",
4810                         (hdw->state_decoder_run ?
4811                          " <decode:run>" :
4812                          (hdw->state_decoder_quiescent ?
4813                           "" : " <decode:stop>")),
4814                         (hdw->state_decoder_quiescent ?
4815                          " <decode:quiescent>" : ""),
4816                         (hdw->state_encoder_ok ?
4817                          "" : " <encode:init>"),
4818                         (hdw->state_encoder_run ?
4819                          (hdw->state_encoder_runok ?
4820                           " <encode:run>" :
4821                           " <encode:firstrun>") :
4822                          (hdw->state_encoder_runok ?
4823                           " <encode:stop>" :
4824                           " <encode:virgin>")),
4825                         (hdw->state_encoder_config ?
4826                          " <encode:configok>" :
4827                          (hdw->state_encoder_waitok ?
4828                           "" : " <encode:waitok>")),
4829                         (hdw->state_usbstream_run ?
4830                          " <usb:run>" : " <usb:stop>"),
4831                         (hdw->state_pathway_ok ?
4832                          " <pathway:ok>" : ""));
4833         case 3:
4834                 return scnprintf(
4835                         buf,acnt,
4836                         "state: %s",
4837                         pvr2_get_state_name(hdw->master_state));
4838         case 4: {
4839                 unsigned int tcnt = 0;
4840                 unsigned int ccnt;
4841
4842                 ccnt = scnprintf(buf,
4843                                  acnt,
4844                                  "Hardware supported inputs: ");
4845                 tcnt += ccnt;
4846                 tcnt += print_input_mask(hdw->input_avail_mask,
4847                                          buf+tcnt,
4848                                          acnt-tcnt);
4849                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4850                         ccnt = scnprintf(buf+tcnt,
4851                                          acnt-tcnt,
4852                                          "; allowed inputs: ");
4853                         tcnt += ccnt;
4854                         tcnt += print_input_mask(hdw->input_allowed_mask,
4855                                                  buf+tcnt,
4856                                                  acnt-tcnt);
4857                 }
4858                 return tcnt;
4859         }
4860         case 5: {
4861                 struct pvr2_stream_stats stats;
4862                 if (!hdw->vid_stream) break;
4863                 pvr2_stream_get_stats(hdw->vid_stream,
4864                                       &stats,
4865                                       0);
4866                 return scnprintf(
4867                         buf,acnt,
4868                         "Bytes streamed=%u"
4869                         " URBs: queued=%u idle=%u ready=%u"
4870                         " processed=%u failed=%u",
4871                         stats.bytes_processed,
4872                         stats.buffers_in_queue,
4873                         stats.buffers_in_idle,
4874                         stats.buffers_in_ready,
4875                         stats.buffers_processed,
4876                         stats.buffers_failed);
4877         }
4878         case 6: {
4879                 struct v4l2_subdev *sd;
4880                 unsigned int tcnt = 0;
4881                 unsigned int ccnt;
4882                 const char *p;
4883                 unsigned int id;
4884                 ccnt = scnprintf(buf,
4885                                  acnt,
4886                                  "Associated v4l2_subdev drivers:");
4887                 tcnt += ccnt;
4888                 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4889                         id = sd->grp_id;
4890                         p = NULL;
4891                         if (id < ARRAY_SIZE(module_names)) {
4892                                 p = module_names[id];
4893                         }
4894                         if (p) {
4895                                 ccnt = scnprintf(buf + tcnt,
4896                                                  acnt - tcnt,
4897                                                  " %s", p);
4898                         } else {
4899                                 ccnt = scnprintf(buf + tcnt,
4900                                                  acnt - tcnt,
4901                                                  " (unknown id=%u)", id);
4902                         }
4903                         tcnt += ccnt;
4904                 }
4905                 return tcnt;
4906         }
4907         default: break;
4908         }
4909         return 0;
4910 }
4911
4912
4913 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4914                                    char *buf,unsigned int acnt)
4915 {
4916         unsigned int bcnt,ccnt,idx;
4917         bcnt = 0;
4918         LOCK_TAKE(hdw->big_lock);
4919         for (idx = 0; ; idx++) {
4920                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4921                 if (!ccnt) break;
4922                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4923                 if (!acnt) break;
4924                 buf[0] = '\n'; ccnt = 1;
4925                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4926         }
4927         LOCK_GIVE(hdw->big_lock);
4928         return bcnt;
4929 }
4930
4931
4932 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4933 {
4934         char buf[128];
4935         unsigned int idx,ccnt;
4936
4937         for (idx = 0; ; idx++) {
4938                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4939                 if (!ccnt) break;
4940                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4941         }
4942 }
4943
4944
4945 /* Evaluate and update the driver's current state, taking various actions
4946    as appropriate for the update. */
4947 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4948 {
4949         unsigned int st;
4950         int state_updated = 0;
4951         int callback_flag = 0;
4952         int analog_mode;
4953
4954         pvr2_trace(PVR2_TRACE_STBITS,
4955                    "Drive state check START");
4956         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4957                 pvr2_hdw_state_log_state(hdw);
4958         }
4959
4960         /* Process all state and get back over disposition */
4961         state_updated = pvr2_hdw_state_update(hdw);
4962
4963         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4964
4965         /* Update master state based upon all other states. */
4966         if (!hdw->flag_ok) {
4967                 st = PVR2_STATE_DEAD;
4968         } else if (hdw->fw1_state != FW1_STATE_OK) {
4969                 st = PVR2_STATE_COLD;
4970         } else if ((analog_mode ||
4971                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4972                    !hdw->state_encoder_ok) {
4973                 st = PVR2_STATE_WARM;
4974         } else if (hdw->flag_tripped ||
4975                    (analog_mode && hdw->flag_decoder_missed)) {
4976                 st = PVR2_STATE_ERROR;
4977         } else if (hdw->state_usbstream_run &&
4978                    (!analog_mode ||
4979                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4980                 st = PVR2_STATE_RUN;
4981         } else {
4982                 st = PVR2_STATE_READY;
4983         }
4984         if (hdw->master_state != st) {
4985                 pvr2_trace(PVR2_TRACE_STATE,
4986                            "Device state change from %s to %s",
4987                            pvr2_get_state_name(hdw->master_state),
4988                            pvr2_get_state_name(st));
4989                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4990                 hdw->master_state = st;
4991                 state_updated = !0;
4992                 callback_flag = !0;
4993         }
4994         if (state_updated) {
4995                 /* Trigger anyone waiting on any state changes here. */
4996                 wake_up(&hdw->state_wait_data);
4997         }
4998
4999         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5000                 pvr2_hdw_state_log_state(hdw);
5001         }
5002         pvr2_trace(PVR2_TRACE_STBITS,
5003                    "Drive state check DONE callback=%d",callback_flag);
5004
5005         return callback_flag;
5006 }
5007
5008
5009 /* Cause kernel thread to check / update driver state */
5010 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
5011 {
5012         if (hdw->state_stale) return;
5013         hdw->state_stale = !0;
5014         trace_stbit("state_stale",hdw->state_stale);
5015         queue_work(hdw->workqueue,&hdw->workpoll);
5016 }
5017
5018
5019 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
5020 {
5021         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5022 }
5023
5024
5025 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5026 {
5027         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5028 }
5029
5030
5031 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5032 {
5033         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5034 }
5035
5036
5037 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5038 {
5039         u32 cval,nval;
5040         int ret;
5041         if (~msk) {
5042                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5043                 if (ret) return ret;
5044                 nval = (cval & ~msk) | (val & msk);
5045                 pvr2_trace(PVR2_TRACE_GPIO,
5046                            "GPIO direction changing 0x%x:0x%x"
5047                            " from 0x%x to 0x%x",
5048                            msk,val,cval,nval);
5049         } else {
5050                 nval = val;
5051                 pvr2_trace(PVR2_TRACE_GPIO,
5052                            "GPIO direction changing to 0x%x",nval);
5053         }
5054         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5055 }
5056
5057
5058 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5059 {
5060         u32 cval,nval;
5061         int ret;
5062         if (~msk) {
5063                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5064                 if (ret) return ret;
5065                 nval = (cval & ~msk) | (val & msk);
5066                 pvr2_trace(PVR2_TRACE_GPIO,
5067                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5068                            msk,val,cval,nval);
5069         } else {
5070                 nval = val;
5071                 pvr2_trace(PVR2_TRACE_GPIO,
5072                            "GPIO output changing to 0x%x",nval);
5073         }
5074         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5075 }
5076
5077
5078 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5079 {
5080         struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5081         memset(vtp, 0, sizeof(*vtp));
5082         hdw->tuner_signal_stale = 0;
5083         pvr2_i2c_core_status_poll(hdw);
5084         /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5085            using v4l2-subdev - therefore we can't support that AT ALL right
5086            now.  (Of course, no sub-drivers seem to implement it either.
5087            But now it's a a chicken and egg problem...) */
5088         v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5089                              &hdw->tuner_signal_info);
5090         pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
5091                    " type=%u strength=%u audio=0x%x cap=0x%x"
5092                    " low=%u hi=%u",
5093                    vtp->type,
5094                    vtp->signal, vtp->rxsubchans, vtp->capability,
5095                    vtp->rangelow, vtp->rangehigh);
5096
5097         /* We have to do this to avoid getting into constant polling if
5098            there's nobody to answer a poll of cropcap info. */
5099         hdw->cropcap_stale = 0;
5100 }
5101
5102
5103 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5104 {
5105         return hdw->input_avail_mask;
5106 }
5107
5108
5109 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5110 {
5111         return hdw->input_allowed_mask;
5112 }
5113
5114
5115 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5116 {
5117         if (hdw->input_val != v) {
5118                 hdw->input_val = v;
5119                 hdw->input_dirty = !0;
5120         }
5121
5122         /* Handle side effects - if we switch to a mode that needs the RF
5123            tuner, then select the right frequency choice as well and mark
5124            it dirty. */
5125         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5126                 hdw->freqSelector = 0;
5127                 hdw->freqDirty = !0;
5128         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5129                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5130                 hdw->freqSelector = 1;
5131                 hdw->freqDirty = !0;
5132         }
5133         return 0;
5134 }
5135
5136
5137 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5138                                unsigned int change_mask,
5139                                unsigned int change_val)
5140 {
5141         int ret = 0;
5142         unsigned int nv,m,idx;
5143         LOCK_TAKE(hdw->big_lock);
5144         do {
5145                 nv = hdw->input_allowed_mask & ~change_mask;
5146                 nv |= (change_val & change_mask);
5147                 nv &= hdw->input_avail_mask;
5148                 if (!nv) {
5149                         /* No legal modes left; return error instead. */
5150                         ret = -EPERM;
5151                         break;
5152                 }
5153                 hdw->input_allowed_mask = nv;
5154                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5155                         /* Current mode is still in the allowed mask, so
5156                            we're done. */
5157                         break;
5158                 }
5159                 /* Select and switch to a mode that is still in the allowed
5160                    mask */
5161                 if (!hdw->input_allowed_mask) {
5162                         /* Nothing legal; give up */
5163                         break;
5164                 }
5165                 m = hdw->input_allowed_mask;
5166                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5167                         if (!((1 << idx) & m)) continue;
5168                         pvr2_hdw_set_input(hdw,idx);
5169                         break;
5170                 }
5171         } while (0);
5172         LOCK_GIVE(hdw->big_lock);
5173         return ret;
5174 }
5175
5176
5177 /* Find I2C address of eeprom */
5178 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5179 {
5180         int result;
5181         LOCK_TAKE(hdw->ctl_lock); do {
5182                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5183                 result = pvr2_send_request(hdw,
5184                                            hdw->cmd_buffer,1,
5185                                            hdw->cmd_buffer,1);
5186                 if (result < 0) break;
5187                 result = hdw->cmd_buffer[0];
5188         } while(0); LOCK_GIVE(hdw->ctl_lock);
5189         return result;
5190 }
5191
5192
5193 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
5194                              struct v4l2_dbg_match *match, u64 reg_id,
5195                              int setFl, u64 *val_ptr)
5196 {
5197 #ifdef CONFIG_VIDEO_ADV_DEBUG
5198         struct pvr2_i2c_client *cp;
5199         struct v4l2_dbg_register req;
5200         int stat = 0;
5201         int okFl = 0;
5202
5203         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5204
5205         req.match = *match;
5206         req.reg = reg_id;
5207         if (setFl) req.val = *val_ptr;
5208         /* It would be nice to know if a sub-device answered the request */
5209         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5210         if (!setFl) *val_ptr = req.val;
5211         if (!okFl) mutex_lock(&hdw->i2c_list_lock); do {
5212                 list_for_each_entry(cp, &hdw->i2c_clients, list) {
5213                         if (!v4l2_chip_match_i2c_client(
5214                                     cp->client,
5215                                     &req.match)) {
5216                                 continue;
5217                         }
5218                         stat = pvr2_i2c_client_cmd(
5219                                 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
5220                                     VIDIOC_DBG_G_REGISTER),&req);
5221                         if (!setFl) *val_ptr = req.val;
5222                         okFl = !0;
5223                         break;
5224                 }
5225         } while (0); mutex_unlock(&hdw->i2c_list_lock);
5226         if (okFl) {
5227                 return stat;
5228         }
5229         return -EINVAL;
5230 #else
5231         return -ENOSYS;
5232 #endif
5233 }
5234
5235
5236 /*
5237   Stuff for Emacs to see, in order to encourage consistent editing style:
5238   *** Local Variables: ***
5239   *** mode: c ***
5240   *** fill-column: 75 ***
5241   *** tab-width: 8 ***
5242   *** c-basic-offset: 8 ***
5243   *** End: ***
5244   */