SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  *
  19  */
  20
  21 #include <linux/errno.h>
  22 #include <linux/string.h>
  23 #include <linux/slab.h>
  24 #include <linux/firmware.h>
  25 #include <linux/videodev2.h>
  26 #include <media/v4l2-common.h>
  27 #include "pvrusb2.h"
  28 #include "pvrusb2-std.h"
  29 #include "pvrusb2-util.h"
  30 #include "pvrusb2-hdw.h"
  31 #include "pvrusb2-i2c-core.h"
  32 #include "pvrusb2-i2c-track.h"
  33 #include "pvrusb2-tuner.h"
  34 #include "pvrusb2-eeprom.h"
  35 #include "pvrusb2-hdw-internal.h"
  36 #include "pvrusb2-encoder.h"
  37 #include "pvrusb2-debug.h"
  38 #include "pvrusb2-fx2-cmd.h"
  39 #include "pvrusb2-wm8775.h"
  40 #include "pvrusb2-video-v4l.h"
  41 #include "pvrusb2-audio.h"
  42
  43 #define TV_MIN_FREQ     55250000L
  44 #define TV_MAX_FREQ    850000000L
  45
  46 /* This defines a minimum interval that the decoder must remain quiet
  47    before we are allowed to start it running. */
  48 #define TIME_MSEC_DECODER_WAIT 50
  49
  50 /* This defines a minimum interval that the encoder must remain quiet
  51    before we are allowed to configure it.  I had this originally set to
  52    50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
  53    things work better when it's set to 100msec. */
  54 #define TIME_MSEC_ENCODER_WAIT 100
  55
  56 /* This defines the minimum interval that the encoder must successfully run
  57    before we consider that the encoder has run at least once since its
  58    firmware has been loaded.  This measurement is in important for cases
  59    where we can't do something until we know that the encoder has been run
  60    at least once. */
  61 #define TIME_MSEC_ENCODER_OK 250
  62
  63 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  64 static DEFINE_MUTEX(pvr2_unit_mtx);
  65
  66 static int ctlchg;
  67 static int procreload;
  68 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  69 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  70 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  71 static int init_pause_msec;
  72
  73 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  74 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  75 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  76 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  77 module_param(procreload, int, S_IRUGO|S_IWUSR);
  78 MODULE_PARM_DESC(procreload,
  79                  "Attempt init failure recovery with firmware reload");
  80 module_param_array(tuner,    int, NULL, 0444);
  81 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  82 module_param_array(video_std,    int, NULL, 0444);
  83 MODULE_PARM_DESC(video_std,"specify initial video standard");
  84 module_param_array(tolerance,    int, NULL, 0444);
  85 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  86
  87 /* US Broadcast channel 7 (175.25 MHz) */
  88 static int default_tv_freq    = 175250000L;
  89 /* 104.3 MHz, a usable FM station for my area */
  90 static int default_radio_freq = 104300000L;
  91
  92 module_param_named(tv_freq, default_tv_freq, int, 0444);
  93 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  94 module_param_named(radio_freq, default_radio_freq, int, 0444);
  95 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  96
  97 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  98 #define PVR2_CTL_READ_ENDPOINT   0x81
  99
 100 #define PVR2_GPIO_IN 0x9008
 101 #define PVR2_GPIO_OUT 0x900c
 102 #define PVR2_GPIO_DIR 0x9020
 103
 104 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 105
 106 #define PVR2_FIRMWARE_ENDPOINT   0x02
 107
 108 /* size of a firmware chunk */
 109 #define FIRMWARE_CHUNK_SIZE 0x2000
 110
 111 typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
 112                                         struct v4l2_subdev *);
 113
 114 static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
 115         [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
 116         [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
 117         [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
 118 };
 119
 120 static const char *module_names[] = {
 121         [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 122         [PVR2_CLIENT_ID_CX25840] = "cx25840",
 123         [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 124         [PVR2_CLIENT_ID_TUNER] = "tuner",
 125         [PVR2_CLIENT_ID_CS53132A] = "cs53132a",
 126         [PVR2_CLIENT_ID_WM8775] = "wm8775",
 127 };
 128
 129
 130 static const unsigned char *module_i2c_addresses[] = {
 131         [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 132 };
 133
 134
 135 /* Define the list of additional controls we'll dynamically construct based
 136    on query of the cx2341x module. */
 137 struct pvr2_mpeg_ids {
 138         const char *strid;
 139         int id;
 140 };
 141 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 142         {
 143                 .strid = "audio_layer",
 144                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 145         },{
 146                 .strid = "audio_bitrate",
 147                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 148         },{
 149                 /* Already using audio_mode elsewhere :-( */
 150                 .strid = "mpeg_audio_mode",
 151                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 152         },{
 153                 .strid = "mpeg_audio_mode_extension",
 154                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 155         },{
 156                 .strid = "audio_emphasis",
 157                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 158         },{
 159                 .strid = "audio_crc",
 160                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 161         },{
 162                 .strid = "video_aspect",
 163                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 164         },{
 165                 .strid = "video_b_frames",
 166                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 167         },{
 168                 .strid = "video_gop_size",
 169                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 170         },{
 171                 .strid = "video_gop_closure",
 172                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 173         },{
 174                 .strid = "video_bitrate_mode",
 175                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 176         },{
 177                 .strid = "video_bitrate",
 178                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 179         },{
 180                 .strid = "video_bitrate_peak",
 181                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 182         },{
 183                 .strid = "video_temporal_decimation",
 184                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 185         },{
 186                 .strid = "stream_type",
 187                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 188         },{
 189                 .strid = "video_spatial_filter_mode",
 190                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 191         },{
 192                 .strid = "video_spatial_filter",
 193                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 194         },{
 195                 .strid = "video_luma_spatial_filter_type",
 196                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 197         },{
 198                 .strid = "video_chroma_spatial_filter_type",
 199                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 200         },{
 201                 .strid = "video_temporal_filter_mode",
 202                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 203         },{
 204                 .strid = "video_temporal_filter",
 205                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 206         },{
 207                 .strid = "video_median_filter_type",
 208                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 209         },{
 210                 .strid = "video_luma_median_filter_top",
 211                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 212         },{
 213                 .strid = "video_luma_median_filter_bottom",
 214                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 215         },{
 216                 .strid = "video_chroma_median_filter_top",
 217                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 218         },{
 219                 .strid = "video_chroma_median_filter_bottom",
 220                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 221         }
 222 };
 223 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 224
 225
 226 static const char *control_values_srate[] = {
 227         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 228         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 229         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 230 };
 231
 232
 233
 234 static const char *control_values_input[] = {
 235         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 236         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 237         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 238         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 239         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 240 };
 241
 242
 243 static const char *control_values_audiomode[] = {
 244         [V4L2_TUNER_MODE_MONO]   = "Mono",
 245         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 246         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 247         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 248         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 249 };
 250
 251
 252 static const char *control_values_hsm[] = {
 253         [PVR2_CVAL_HSM_FAIL] = "Fail",
 254         [PVR2_CVAL_HSM_HIGH] = "High",
 255         [PVR2_CVAL_HSM_FULL] = "Full",
 256 };
 257
 258
 259 static const char *pvr2_state_names[] = {
 260         [PVR2_STATE_NONE] =    "none",
 261         [PVR2_STATE_DEAD] =    "dead",
 262         [PVR2_STATE_COLD] =    "cold",
 263         [PVR2_STATE_WARM] =    "warm",
 264         [PVR2_STATE_ERROR] =   "error",
 265         [PVR2_STATE_READY] =   "ready",
 266         [PVR2_STATE_RUN] =     "run",
 267 };
 268
 269
 270 struct pvr2_fx2cmd_descdef {
 271         unsigned char id;
 272         unsigned char *desc;
 273 };
 274
 275 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 276         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 277         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 278         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 279         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 280         {FX2CMD_REG_WRITE, "write encoder register"},
 281         {FX2CMD_REG_READ, "read encoder register"},
 282         {FX2CMD_MEMSEL, "encoder memsel"},
 283         {FX2CMD_I2C_WRITE, "i2c write"},
 284         {FX2CMD_I2C_READ, "i2c read"},
 285         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 286         {FX2CMD_STREAMING_ON, "stream on"},
 287         {FX2CMD_STREAMING_OFF, "stream off"},
 288         {FX2CMD_FWPOST1, "fwpost1"},
 289         {FX2CMD_POWER_OFF, "power off"},
 290         {FX2CMD_POWER_ON, "power on"},
 291         {FX2CMD_DEEP_RESET, "deep reset"},
 292         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 293         {FX2CMD_GET_IR_CODE, "get IR code"},
 294         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 295         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 296         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 297         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 298         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 299         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 300         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 301 };
 302
 303
 304 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 305 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 306 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 307 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 308 static void pvr2_hdw_worker_i2c(struct work_struct *work);
 309 static void pvr2_hdw_worker_poll(struct work_struct *work);
 310 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 311 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 312 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 313 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 314 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 315 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 316 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 317 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 318 static void pvr2_hdw_quiescent_timeout(unsigned long);
 319 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 320 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 321 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 322 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 323                                 unsigned int timeout,int probe_fl,
 324                                 void *write_data,unsigned int write_len,
 325                                 void *read_data,unsigned int read_len);
 326 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 327
 328
 329 static void trace_stbit(const char *name,int val)
 330 {
 331         pvr2_trace(PVR2_TRACE_STBITS,
 332                    "State bit %s <-- %s",
 333                    name,(val ? "true" : "false"));
 334 }
 335
 336 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 337 {
 338         struct pvr2_hdw *hdw = cptr->hdw;
 339         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 340                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 341         } else {
 342                 *vp = 0;
 343         }
 344         return 0;
 345 }
 346
 347 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 348 {
 349         struct pvr2_hdw *hdw = cptr->hdw;
 350         unsigned int slotId = hdw->freqProgSlot;
 351         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 352                 hdw->freqTable[slotId-1] = v;
 353                 /* Handle side effects correctly - if we're tuned to this
 354                    slot, then forgot the slot id relation since the stored
 355                    frequency has been changed. */
 356                 if (hdw->freqSelector) {
 357                         if (hdw->freqSlotRadio == slotId) {
 358                                 hdw->freqSlotRadio = 0;
 359                         }
 360                 } else {
 361                         if (hdw->freqSlotTelevision == slotId) {
 362                                 hdw->freqSlotTelevision = 0;
 363                         }
 364                 }
 365         }
 366         return 0;
 367 }
 368
 369 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 370 {
 371         *vp = cptr->hdw->freqProgSlot;
 372         return 0;
 373 }
 374
 375 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 376 {
 377         struct pvr2_hdw *hdw = cptr->hdw;
 378         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 379                 hdw->freqProgSlot = v;
 380         }
 381         return 0;
 382 }
 383
 384 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 385 {
 386         struct pvr2_hdw *hdw = cptr->hdw;
 387         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 388         return 0;
 389 }
 390
 391 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 392 {
 393         unsigned freq = 0;
 394         struct pvr2_hdw *hdw = cptr->hdw;
 395         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 396         if (slotId > 0) {
 397                 freq = hdw->freqTable[slotId-1];
 398                 if (!freq) return 0;
 399                 pvr2_hdw_set_cur_freq(hdw,freq);
 400         }
 401         if (hdw->freqSelector) {
 402                 hdw->freqSlotRadio = slotId;
 403         } else {
 404                 hdw->freqSlotTelevision = slotId;
 405         }
 406         return 0;
 407 }
 408
 409 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 410 {
 411         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 412         return 0;
 413 }
 414
 415 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 416 {
 417         return cptr->hdw->freqDirty != 0;
 418 }
 419
 420 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 421 {
 422         cptr->hdw->freqDirty = 0;
 423 }
 424
 425 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 426 {
 427         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 428         return 0;
 429 }
 430
 431 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 432 {
 433         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 434         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 435         if (stat != 0) {
 436                 return stat;
 437         }
 438         *left = cap->bounds.left;
 439         return 0;
 440 }
 441
 442 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 443 {
 444         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 445         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 446         if (stat != 0) {
 447                 return stat;
 448         }
 449         *left = cap->bounds.left;
 450         if (cap->bounds.width > cptr->hdw->cropw_val) {
 451                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 452         }
 453         return 0;
 454 }
 455
 456 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 457 {
 458         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 459         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 460         if (stat != 0) {
 461                 return stat;
 462         }
 463         *top = cap->bounds.top;
 464         return 0;
 465 }
 466
 467 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 468 {
 469         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 470         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 471         if (stat != 0) {
 472                 return stat;
 473         }
 474         *top = cap->bounds.top;
 475         if (cap->bounds.height > cptr->hdw->croph_val) {
 476                 *top += cap->bounds.height - cptr->hdw->croph_val;
 477         }
 478         return 0;
 479 }
 480
 481 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
 482 {
 483         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 484         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 485         if (stat != 0) {
 486                 return stat;
 487         }
 488         *val = 0;
 489         if (cap->bounds.width > cptr->hdw->cropl_val) {
 490                 *val = cap->bounds.width - cptr->hdw->cropl_val;
 491         }
 492         return 0;
 493 }
 494
 495 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
 496 {
 497         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 498         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 499         if (stat != 0) {
 500                 return stat;
 501         }
 502         *val = 0;
 503         if (cap->bounds.height > cptr->hdw->cropt_val) {
 504                 *val = cap->bounds.height - cptr->hdw->cropt_val;
 505         }
 506         return 0;
 507 }
 508
 509 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 510 {
 511         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 512         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 513         if (stat != 0) {
 514                 return stat;
 515         }
 516         *val = cap->bounds.left;
 517         return 0;
 518 }
 519
 520 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 521 {
 522         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 523         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 524         if (stat != 0) {
 525                 return stat;
 526         }
 527         *val = cap->bounds.top;
 528         return 0;
 529 }
 530
 531 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 532 {
 533         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 534         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 535         if (stat != 0) {
 536                 return stat;
 537         }
 538         *val = cap->bounds.width;
 539         return 0;
 540 }
 541
 542 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 543 {
 544         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 545         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 546         if (stat != 0) {
 547                 return stat;
 548         }
 549         *val = cap->bounds.height;
 550         return 0;
 551 }
 552
 553 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 554 {
 555         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 556         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 557         if (stat != 0) {
 558                 return stat;
 559         }
 560         *val = cap->defrect.left;
 561         return 0;
 562 }
 563
 564 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 565 {
 566         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 567         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 568         if (stat != 0) {
 569                 return stat;
 570         }
 571         *val = cap->defrect.top;
 572         return 0;
 573 }
 574
 575 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 576 {
 577         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 578         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 579         if (stat != 0) {
 580                 return stat;
 581         }
 582         *val = cap->defrect.width;
 583         return 0;
 584 }
 585
 586 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 587 {
 588         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 589         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 590         if (stat != 0) {
 591                 return stat;
 592         }
 593         *val = cap->defrect.height;
 594         return 0;
 595 }
 596
 597 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 598 {
 599         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 600         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 601         if (stat != 0) {
 602                 return stat;
 603         }
 604         *val = cap->pixelaspect.numerator;
 605         return 0;
 606 }
 607
 608 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 609 {
 610         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 611         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 612         if (stat != 0) {
 613                 return stat;
 614         }
 615         *val = cap->pixelaspect.denominator;
 616         return 0;
 617 }
 618
 619 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 620 {
 621         /* Actual maximum depends on the video standard in effect. */
 622         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 623                 *vp = 480;
 624         } else {
 625                 *vp = 576;
 626         }
 627         return 0;
 628 }
 629
 630 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 631 {
 632         /* Actual minimum depends on device digitizer type. */
 633         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 634                 *vp = 75;
 635         } else {
 636                 *vp = 17;
 637         }
 638         return 0;
 639 }
 640
 641 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 642 {
 643         *vp = cptr->hdw->input_val;
 644         return 0;
 645 }
 646
 647 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 648 {
 649         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 650 }
 651
 652 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 653 {
 654         return pvr2_hdw_set_input(cptr->hdw,v);
 655 }
 656
 657 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 658 {
 659         return cptr->hdw->input_dirty != 0;
 660 }
 661
 662 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 663 {
 664         cptr->hdw->input_dirty = 0;
 665 }
 666
 667
 668 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 669 {
 670         unsigned long fv;
 671         struct pvr2_hdw *hdw = cptr->hdw;
 672         if (hdw->tuner_signal_stale) {
 673                 pvr2_hdw_status_poll(hdw);
 674         }
 675         fv = hdw->tuner_signal_info.rangehigh;
 676         if (!fv) {
 677                 /* Safety fallback */
 678                 *vp = TV_MAX_FREQ;
 679                 return 0;
 680         }
 681         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 682                 fv = (fv * 125) / 2;
 683         } else {
 684                 fv = fv * 62500;
 685         }
 686         *vp = fv;
 687         return 0;
 688 }
 689
 690 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 691 {
 692         unsigned long fv;
 693         struct pvr2_hdw *hdw = cptr->hdw;
 694         if (hdw->tuner_signal_stale) {
 695                 pvr2_hdw_status_poll(hdw);
 696         }
 697         fv = hdw->tuner_signal_info.rangelow;
 698         if (!fv) {
 699                 /* Safety fallback */
 700                 *vp = TV_MIN_FREQ;
 701                 return 0;
 702         }
 703         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 704                 fv = (fv * 125) / 2;
 705         } else {
 706                 fv = fv * 62500;
 707         }
 708         *vp = fv;
 709         return 0;
 710 }
 711
 712 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 713 {
 714         return cptr->hdw->enc_stale != 0;
 715 }
 716
 717 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 718 {
 719         cptr->hdw->enc_stale = 0;
 720         cptr->hdw->enc_unsafe_stale = 0;
 721 }
 722
 723 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 724 {
 725         int ret;
 726         struct v4l2_ext_controls cs;
 727         struct v4l2_ext_control c1;
 728         memset(&cs,0,sizeof(cs));
 729         memset(&c1,0,sizeof(c1));
 730         cs.controls = &c1;
 731         cs.count = 1;
 732         c1.id = cptr->info->v4l_id;
 733         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 734                                 VIDIOC_G_EXT_CTRLS);
 735         if (ret) return ret;
 736         *vp = c1.value;
 737         return 0;
 738 }
 739
 740 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 741 {
 742         int ret;
 743         struct pvr2_hdw *hdw = cptr->hdw;
 744         struct v4l2_ext_controls cs;
 745         struct v4l2_ext_control c1;
 746         memset(&cs,0,sizeof(cs));
 747         memset(&c1,0,sizeof(c1));
 748         cs.controls = &c1;
 749         cs.count = 1;
 750         c1.id = cptr->info->v4l_id;
 751         c1.value = v;
 752         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 753                                 hdw->state_encoder_run, &cs,
 754                                 VIDIOC_S_EXT_CTRLS);
 755         if (ret == -EBUSY) {
 756                 /* Oops.  cx2341x is telling us it's not safe to change
 757                    this control while we're capturing.  Make a note of this
 758                    fact so that the pipeline will be stopped the next time
 759                    controls are committed.  Then go on ahead and store this
 760                    change anyway. */
 761                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 762                                         0, &cs,
 763                                         VIDIOC_S_EXT_CTRLS);
 764                 if (!ret) hdw->enc_unsafe_stale = !0;
 765         }
 766         if (ret) return ret;
 767         hdw->enc_stale = !0;
 768         return 0;
 769 }
 770
 771 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 772 {
 773         struct v4l2_queryctrl qctrl;
 774         struct pvr2_ctl_info *info;
 775         qctrl.id = cptr->info->v4l_id;
 776         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 777         /* Strip out the const so we can adjust a function pointer.  It's
 778            OK to do this here because we know this is a dynamically created
 779            control, so the underlying storage for the info pointer is (a)
 780            private to us, and (b) not in read-only storage.  Either we do
 781            this or we significantly complicate the underlying control
 782            implementation. */
 783         info = (struct pvr2_ctl_info *)(cptr->info);
 784         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 785                 if (info->set_value) {
 786                         info->set_value = NULL;
 787                 }
 788         } else {
 789                 if (!(info->set_value)) {
 790                         info->set_value = ctrl_cx2341x_set;
 791                 }
 792         }
 793         return qctrl.flags;
 794 }
 795
 796 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 797 {
 798         *vp = cptr->hdw->state_pipeline_req;
 799         return 0;
 800 }
 801
 802 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 803 {
 804         *vp = cptr->hdw->master_state;
 805         return 0;
 806 }
 807
 808 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 809 {
 810         int result = pvr2_hdw_is_hsm(cptr->hdw);
 811         *vp = PVR2_CVAL_HSM_FULL;
 812         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 813         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 814         return 0;
 815 }
 816
 817 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 818 {
 819         *vp = cptr->hdw->std_mask_avail;
 820         return 0;
 821 }
 822
 823 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 824 {
 825         struct pvr2_hdw *hdw = cptr->hdw;
 826         v4l2_std_id ns;
 827         ns = hdw->std_mask_avail;
 828         ns = (ns & ~m) | (v & m);
 829         if (ns == hdw->std_mask_avail) return 0;
 830         hdw->std_mask_avail = ns;
 831         pvr2_hdw_internal_set_std_avail(hdw);
 832         pvr2_hdw_internal_find_stdenum(hdw);
 833         return 0;
 834 }
 835
 836 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 837                                char *bufPtr,unsigned int bufSize,
 838                                unsigned int *len)
 839 {
 840         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 841         return 0;
 842 }
 843
 844 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 845                                const char *bufPtr,unsigned int bufSize,
 846                                int *mskp,int *valp)
 847 {
 848         int ret;
 849         v4l2_std_id id;
 850         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 851         if (ret < 0) return ret;
 852         if (mskp) *mskp = id;
 853         if (valp) *valp = id;
 854         return 0;
 855 }
 856
 857 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 858 {
 859         *vp = cptr->hdw->std_mask_cur;
 860         return 0;
 861 }
 862
 863 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 864 {
 865         struct pvr2_hdw *hdw = cptr->hdw;
 866         v4l2_std_id ns;
 867         ns = hdw->std_mask_cur;
 868         ns = (ns & ~m) | (v & m);
 869         if (ns == hdw->std_mask_cur) return 0;
 870         hdw->std_mask_cur = ns;
 871         hdw->std_dirty = !0;
 872         pvr2_hdw_internal_find_stdenum(hdw);
 873         return 0;
 874 }
 875
 876 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 877 {
 878         return cptr->hdw->std_dirty != 0;
 879 }
 880
 881 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 882 {
 883         cptr->hdw->std_dirty = 0;
 884 }
 885
 886 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 887 {
 888         struct pvr2_hdw *hdw = cptr->hdw;
 889         pvr2_hdw_status_poll(hdw);
 890         *vp = hdw->tuner_signal_info.signal;
 891         return 0;
 892 }
 893
 894 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 895 {
 896         int val = 0;
 897         unsigned int subchan;
 898         struct pvr2_hdw *hdw = cptr->hdw;
 899         pvr2_hdw_status_poll(hdw);
 900         subchan = hdw->tuner_signal_info.rxsubchans;
 901         if (subchan & V4L2_TUNER_SUB_MONO) {
 902                 val |= (1 << V4L2_TUNER_MODE_MONO);
 903         }
 904         if (subchan & V4L2_TUNER_SUB_STEREO) {
 905                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 906         }
 907         if (subchan & V4L2_TUNER_SUB_LANG1) {
 908                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 909         }
 910         if (subchan & V4L2_TUNER_SUB_LANG2) {
 911                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 912         }
 913         *vp = val;
 914         return 0;
 915 }
 916
 917
 918 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 919 {
 920         struct pvr2_hdw *hdw = cptr->hdw;
 921         if (v < 0) return -EINVAL;
 922         if (v > hdw->std_enum_cnt) return -EINVAL;
 923         hdw->std_enum_cur = v;
 924         if (!v) return 0;
 925         v--;
 926         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 927         hdw->std_mask_cur = hdw->std_defs[v].id;
 928         hdw->std_dirty = !0;
 929         return 0;
 930 }
 931
 932
 933 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 934 {
 935         *vp = cptr->hdw->std_enum_cur;
 936         return 0;
 937 }
 938
 939
 940 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 941 {
 942         return cptr->hdw->std_dirty != 0;
 943 }
 944
 945
 946 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 947 {
 948         cptr->hdw->std_dirty = 0;
 949 }
 950
 951
 952 #define DEFINT(vmin,vmax) \
 953         .type = pvr2_ctl_int, \
 954         .def.type_int.min_value = vmin, \
 955         .def.type_int.max_value = vmax
 956
 957 #define DEFENUM(tab) \
 958         .type = pvr2_ctl_enum, \
 959         .def.type_enum.count = ARRAY_SIZE(tab), \
 960         .def.type_enum.value_names = tab
 961
 962 #define DEFBOOL \
 963         .type = pvr2_ctl_bool
 964
 965 #define DEFMASK(msk,tab) \
 966         .type = pvr2_ctl_bitmask, \
 967         .def.type_bitmask.valid_bits = msk, \
 968         .def.type_bitmask.bit_names = tab
 969
 970 #define DEFREF(vname) \
 971         .set_value = ctrl_set_##vname, \
 972         .get_value = ctrl_get_##vname, \
 973         .is_dirty = ctrl_isdirty_##vname, \
 974         .clear_dirty = ctrl_cleardirty_##vname
 975
 976
 977 #define VCREATE_FUNCS(vname) \
 978 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 979 {*vp = cptr->hdw->vname##_val; return 0;} \
 980 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 981 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 982 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 983 {return cptr->hdw->vname##_dirty != 0;} \
 984 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 985 {cptr->hdw->vname##_dirty = 0;}
 986
 987 VCREATE_FUNCS(brightness)
 988 VCREATE_FUNCS(contrast)
 989 VCREATE_FUNCS(saturation)
 990 VCREATE_FUNCS(hue)
 991 VCREATE_FUNCS(volume)
 992 VCREATE_FUNCS(balance)
 993 VCREATE_FUNCS(bass)
 994 VCREATE_FUNCS(treble)
 995 VCREATE_FUNCS(mute)
 996 VCREATE_FUNCS(cropl)
 997 VCREATE_FUNCS(cropt)
 998 VCREATE_FUNCS(cropw)
 999 VCREATE_FUNCS(croph)
1000 VCREATE_FUNCS(audiomode)
1001 VCREATE_FUNCS(res_hor)
1002 VCREATE_FUNCS(res_ver)
1003 VCREATE_FUNCS(srate)
1004
1005 /* Table definition of all controls which can be manipulated */
1006 static const struct pvr2_ctl_info control_defs[] = {
1007         {
1008                 .v4l_id = V4L2_CID_BRIGHTNESS,
1009                 .desc = "Brightness",
1010                 .name = "brightness",
1011                 .default_value = 128,
1012                 DEFREF(brightness),
1013                 DEFINT(0,255),
1014         },{
1015                 .v4l_id = V4L2_CID_CONTRAST,
1016                 .desc = "Contrast",
1017                 .name = "contrast",
1018                 .default_value = 68,
1019                 DEFREF(contrast),
1020                 DEFINT(0,127),
1021         },{
1022                 .v4l_id = V4L2_CID_SATURATION,
1023                 .desc = "Saturation",
1024                 .name = "saturation",
1025                 .default_value = 64,
1026                 DEFREF(saturation),
1027                 DEFINT(0,127),
1028         },{
1029                 .v4l_id = V4L2_CID_HUE,
1030                 .desc = "Hue",
1031                 .name = "hue",
1032                 .default_value = 0,
1033                 DEFREF(hue),
1034                 DEFINT(-128,127),
1035         },{
1036                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1037                 .desc = "Volume",
1038                 .name = "volume",
1039                 .default_value = 62000,
1040                 DEFREF(volume),
1041                 DEFINT(0,65535),
1042         },{
1043                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1044                 .desc = "Balance",
1045                 .name = "balance",
1046                 .default_value = 0,
1047                 DEFREF(balance),
1048                 DEFINT(-32768,32767),
1049         },{
1050                 .v4l_id = V4L2_CID_AUDIO_BASS,
1051                 .desc = "Bass",
1052                 .name = "bass",
1053                 .default_value = 0,
1054                 DEFREF(bass),
1055                 DEFINT(-32768,32767),
1056         },{
1057                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1058                 .desc = "Treble",
1059                 .name = "treble",
1060                 .default_value = 0,
1061                 DEFREF(treble),
1062                 DEFINT(-32768,32767),
1063         },{
1064                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1065                 .desc = "Mute",
1066                 .name = "mute",
1067                 .default_value = 0,
1068                 DEFREF(mute),
1069                 DEFBOOL,
1070         }, {
1071                 .desc = "Capture crop left margin",
1072                 .name = "crop_left",
1073                 .internal_id = PVR2_CID_CROPL,
1074                 .default_value = 0,
1075                 DEFREF(cropl),
1076                 DEFINT(-129, 340),
1077                 .get_min_value = ctrl_cropl_min_get,
1078                 .get_max_value = ctrl_cropl_max_get,
1079                 .get_def_value = ctrl_get_cropcapdl,
1080         }, {
1081                 .desc = "Capture crop top margin",
1082                 .name = "crop_top",
1083                 .internal_id = PVR2_CID_CROPT,
1084                 .default_value = 0,
1085                 DEFREF(cropt),
1086                 DEFINT(-35, 544),
1087                 .get_min_value = ctrl_cropt_min_get,
1088                 .get_max_value = ctrl_cropt_max_get,
1089                 .get_def_value = ctrl_get_cropcapdt,
1090         }, {
1091                 .desc = "Capture crop width",
1092                 .name = "crop_width",
1093                 .internal_id = PVR2_CID_CROPW,
1094                 .default_value = 720,
1095                 DEFREF(cropw),
1096                 .get_max_value = ctrl_cropw_max_get,
1097                 .get_def_value = ctrl_get_cropcapdw,
1098         }, {
1099                 .desc = "Capture crop height",
1100                 .name = "crop_height",
1101                 .internal_id = PVR2_CID_CROPH,
1102                 .default_value = 480,
1103                 DEFREF(croph),
1104                 .get_max_value = ctrl_croph_max_get,
1105                 .get_def_value = ctrl_get_cropcapdh,
1106         }, {
1107                 .desc = "Capture capability pixel aspect numerator",
1108                 .name = "cropcap_pixel_numerator",
1109                 .internal_id = PVR2_CID_CROPCAPPAN,
1110                 .get_value = ctrl_get_cropcappan,
1111         }, {
1112                 .desc = "Capture capability pixel aspect denominator",
1113                 .name = "cropcap_pixel_denominator",
1114                 .internal_id = PVR2_CID_CROPCAPPAD,
1115                 .get_value = ctrl_get_cropcappad,
1116         }, {
1117                 .desc = "Capture capability bounds top",
1118                 .name = "cropcap_bounds_top",
1119                 .internal_id = PVR2_CID_CROPCAPBT,
1120                 .get_value = ctrl_get_cropcapbt,
1121         }, {
1122                 .desc = "Capture capability bounds left",
1123                 .name = "cropcap_bounds_left",
1124                 .internal_id = PVR2_CID_CROPCAPBL,
1125                 .get_value = ctrl_get_cropcapbl,
1126         }, {
1127                 .desc = "Capture capability bounds width",
1128                 .name = "cropcap_bounds_width",
1129                 .internal_id = PVR2_CID_CROPCAPBW,
1130                 .get_value = ctrl_get_cropcapbw,
1131         }, {
1132                 .desc = "Capture capability bounds height",
1133                 .name = "cropcap_bounds_height",
1134                 .internal_id = PVR2_CID_CROPCAPBH,
1135                 .get_value = ctrl_get_cropcapbh,
1136         },{
1137                 .desc = "Video Source",
1138                 .name = "input",
1139                 .internal_id = PVR2_CID_INPUT,
1140                 .default_value = PVR2_CVAL_INPUT_TV,
1141                 .check_value = ctrl_check_input,
1142                 DEFREF(input),
1143                 DEFENUM(control_values_input),
1144         },{
1145                 .desc = "Audio Mode",
1146                 .name = "audio_mode",
1147                 .internal_id = PVR2_CID_AUDIOMODE,
1148                 .default_value = V4L2_TUNER_MODE_STEREO,
1149                 DEFREF(audiomode),
1150                 DEFENUM(control_values_audiomode),
1151         },{
1152                 .desc = "Horizontal capture resolution",
1153                 .name = "resolution_hor",
1154                 .internal_id = PVR2_CID_HRES,
1155                 .default_value = 720,
1156                 DEFREF(res_hor),
1157                 DEFINT(19,720),
1158         },{
1159                 .desc = "Vertical capture resolution",
1160                 .name = "resolution_ver",
1161                 .internal_id = PVR2_CID_VRES,
1162                 .default_value = 480,
1163                 DEFREF(res_ver),
1164                 DEFINT(17,576),
1165                 /* Hook in check for video standard and adjust maximum
1166                    depending on the standard. */
1167                 .get_max_value = ctrl_vres_max_get,
1168                 .get_min_value = ctrl_vres_min_get,
1169         },{
1170                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1171                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1172                 .desc = "Audio Sampling Frequency",
1173                 .name = "srate",
1174                 DEFREF(srate),
1175                 DEFENUM(control_values_srate),
1176         },{
1177                 .desc = "Tuner Frequency (Hz)",
1178                 .name = "frequency",
1179                 .internal_id = PVR2_CID_FREQUENCY,
1180                 .default_value = 0,
1181                 .set_value = ctrl_freq_set,
1182                 .get_value = ctrl_freq_get,
1183                 .is_dirty = ctrl_freq_is_dirty,
1184                 .clear_dirty = ctrl_freq_clear_dirty,
1185                 DEFINT(0,0),
1186                 /* Hook in check for input value (tv/radio) and adjust
1187                    max/min values accordingly */
1188                 .get_max_value = ctrl_freq_max_get,
1189                 .get_min_value = ctrl_freq_min_get,
1190         },{
1191                 .desc = "Channel",
1192                 .name = "channel",
1193                 .set_value = ctrl_channel_set,
1194                 .get_value = ctrl_channel_get,
1195                 DEFINT(0,FREQTABLE_SIZE),
1196         },{
1197                 .desc = "Channel Program Frequency",
1198                 .name = "freq_table_value",
1199                 .set_value = ctrl_channelfreq_set,
1200                 .get_value = ctrl_channelfreq_get,
1201                 DEFINT(0,0),
1202                 /* Hook in check for input value (tv/radio) and adjust
1203                    max/min values accordingly */
1204                 .get_max_value = ctrl_freq_max_get,
1205                 .get_min_value = ctrl_freq_min_get,
1206         },{
1207                 .desc = "Channel Program ID",
1208                 .name = "freq_table_channel",
1209                 .set_value = ctrl_channelprog_set,
1210                 .get_value = ctrl_channelprog_get,
1211                 DEFINT(0,FREQTABLE_SIZE),
1212         },{
1213                 .desc = "Streaming Enabled",
1214                 .name = "streaming_enabled",
1215                 .get_value = ctrl_streamingenabled_get,
1216                 DEFBOOL,
1217         },{
1218                 .desc = "USB Speed",
1219                 .name = "usb_speed",
1220                 .get_value = ctrl_hsm_get,
1221                 DEFENUM(control_values_hsm),
1222         },{
1223                 .desc = "Master State",
1224                 .name = "master_state",
1225                 .get_value = ctrl_masterstate_get,
1226                 DEFENUM(pvr2_state_names),
1227         },{
1228                 .desc = "Signal Present",
1229                 .name = "signal_present",
1230                 .get_value = ctrl_signal_get,
1231                 DEFINT(0,65535),
1232         },{
1233                 .desc = "Audio Modes Present",
1234                 .name = "audio_modes_present",
1235                 .get_value = ctrl_audio_modes_present_get,
1236                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1237                    v4l.  Nothing outside of this module cares about this,
1238                    but I reuse it in order to also reuse the
1239                    control_values_audiomode string table. */
1240                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1241                          (1 << V4L2_TUNER_MODE_STEREO)|
1242                          (1 << V4L2_TUNER_MODE_LANG1)|
1243                          (1 << V4L2_TUNER_MODE_LANG2)),
1244                         control_values_audiomode),
1245         },{
1246                 .desc = "Video Standards Available Mask",
1247                 .name = "video_standard_mask_available",
1248                 .internal_id = PVR2_CID_STDAVAIL,
1249                 .skip_init = !0,
1250                 .get_value = ctrl_stdavail_get,
1251                 .set_value = ctrl_stdavail_set,
1252                 .val_to_sym = ctrl_std_val_to_sym,
1253                 .sym_to_val = ctrl_std_sym_to_val,
1254                 .type = pvr2_ctl_bitmask,
1255         },{
1256                 .desc = "Video Standards In Use Mask",
1257                 .name = "video_standard_mask_active",
1258                 .internal_id = PVR2_CID_STDCUR,
1259                 .skip_init = !0,
1260                 .get_value = ctrl_stdcur_get,
1261                 .set_value = ctrl_stdcur_set,
1262                 .is_dirty = ctrl_stdcur_is_dirty,
1263                 .clear_dirty = ctrl_stdcur_clear_dirty,
1264                 .val_to_sym = ctrl_std_val_to_sym,
1265                 .sym_to_val = ctrl_std_sym_to_val,
1266                 .type = pvr2_ctl_bitmask,
1267         },{
1268                 .desc = "Video Standard Name",
1269                 .name = "video_standard",
1270                 .internal_id = PVR2_CID_STDENUM,
1271                 .skip_init = !0,
1272                 .get_value = ctrl_stdenumcur_get,
1273                 .set_value = ctrl_stdenumcur_set,
1274                 .is_dirty = ctrl_stdenumcur_is_dirty,
1275                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1276                 .type = pvr2_ctl_enum,
1277         }
1278 };
1279
1280 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1281
1282
1283 const char *pvr2_config_get_name(enum pvr2_config cfg)
1284 {
1285         switch (cfg) {
1286         case pvr2_config_empty: return "empty";
1287         case pvr2_config_mpeg: return "mpeg";
1288         case pvr2_config_vbi: return "vbi";
1289         case pvr2_config_pcm: return "pcm";
1290         case pvr2_config_rawvideo: return "raw video";
1291         }
1292         return "<unknown>";
1293 }
1294
1295
1296 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1297 {
1298         return hdw->usb_dev;
1299 }
1300
1301
1302 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1303 {
1304         return hdw->serial_number;
1305 }
1306
1307
1308 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1309 {
1310         return hdw->bus_info;
1311 }
1312
1313
1314 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1315 {
1316         return hdw->identifier;
1317 }
1318
1319
1320 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1321 {
1322         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1323 }
1324
1325 /* Set the currently tuned frequency and account for all possible
1326    driver-core side effects of this action. */
1327 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1328 {
1329         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1330                 if (hdw->freqSelector) {
1331                         /* Swing over to radio frequency selection */
1332                         hdw->freqSelector = 0;
1333                         hdw->freqDirty = !0;
1334                 }
1335                 if (hdw->freqValRadio != val) {
1336                         hdw->freqValRadio = val;
1337                         hdw->freqSlotRadio = 0;
1338                         hdw->freqDirty = !0;
1339                 }
1340         } else {
1341                 if (!(hdw->freqSelector)) {
1342                         /* Swing over to television frequency selection */
1343                         hdw->freqSelector = 1;
1344                         hdw->freqDirty = !0;
1345                 }
1346                 if (hdw->freqValTelevision != val) {
1347                         hdw->freqValTelevision = val;
1348                         hdw->freqSlotTelevision = 0;
1349                         hdw->freqDirty = !0;
1350                 }
1351         }
1352 }
1353
1354 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1355 {
1356         return hdw->unit_number;
1357 }
1358
1359
1360 /* Attempt to locate one of the given set of files.  Messages are logged
1361    appropriate to what has been found.  The return value will be 0 or
1362    greater on success (it will be the index of the file name found) and
1363    fw_entry will be filled in.  Otherwise a negative error is returned on
1364    failure.  If the return value is -ENOENT then no viable firmware file
1365    could be located. */
1366 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1367                                 const struct firmware **fw_entry,
1368                                 const char *fwtypename,
1369                                 unsigned int fwcount,
1370                                 const char *fwnames[])
1371 {
1372         unsigned int idx;
1373         int ret = -EINVAL;
1374         for (idx = 0; idx < fwcount; idx++) {
1375                 ret = request_firmware(fw_entry,
1376                                        fwnames[idx],
1377                                        &hdw->usb_dev->dev);
1378                 if (!ret) {
1379                         trace_firmware("Located %s firmware: %s;"
1380                                        " uploading...",
1381                                        fwtypename,
1382                                        fwnames[idx]);
1383                         return idx;
1384                 }
1385                 if (ret == -ENOENT) continue;
1386                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1387                            "request_firmware fatal error with code=%d",ret);
1388                 return ret;
1389         }
1390         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1391                    "***WARNING***"
1392                    " Device %s firmware"
1393                    " seems to be missing.",
1394                    fwtypename);
1395         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1396                    "Did you install the pvrusb2 firmware files"
1397                    " in their proper location?");
1398         if (fwcount == 1) {
1399                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1400                            "request_firmware unable to locate %s file %s",
1401                            fwtypename,fwnames[0]);
1402         } else {
1403                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1404                            "request_firmware unable to locate"
1405                            " one of the following %s files:",
1406                            fwtypename);
1407                 for (idx = 0; idx < fwcount; idx++) {
1408                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1409                                    "request_firmware: Failed to find %s",
1410                                    fwnames[idx]);
1411                 }
1412         }
1413         return ret;
1414 }
1415
1416
1417 /*
1418  * pvr2_upload_firmware1().
1419  *
1420  * Send the 8051 firmware to the device.  After the upload, arrange for
1421  * device to re-enumerate.
1422  *
1423  * NOTE : the pointer to the firmware data given by request_firmware()
1424  * is not suitable for an usb transaction.
1425  *
1426  */
1427 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1428 {
1429         const struct firmware *fw_entry = NULL;
1430         void  *fw_ptr;
1431         unsigned int pipe;
1432         int ret;
1433         u16 address;
1434
1435         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1436                 hdw->fw1_state = FW1_STATE_OK;
1437                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1438                            "Connected device type defines"
1439                            " no firmware to upload; ignoring firmware");
1440                 return -ENOTTY;
1441         }
1442
1443         hdw->fw1_state = FW1_STATE_FAILED; // default result
1444
1445         trace_firmware("pvr2_upload_firmware1");
1446
1447         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1448                                    hdw->hdw_desc->fx2_firmware.cnt,
1449                                    hdw->hdw_desc->fx2_firmware.lst);
1450         if (ret < 0) {
1451                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1452                 return ret;
1453         }
1454
1455         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1456         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1457
1458         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1459
1460         if (fw_entry->size != 0x2000){
1461                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1462                 release_firmware(fw_entry);
1463                 return -ENOMEM;
1464         }
1465
1466         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1467         if (fw_ptr == NULL){
1468                 release_firmware(fw_entry);
1469                 return -ENOMEM;
1470         }
1471
1472         /* We have to hold the CPU during firmware upload. */
1473         pvr2_hdw_cpureset_assert(hdw,1);
1474
1475         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1476            chunk. */
1477
1478         ret = 0;
1479         for(address = 0; address < fw_entry->size; address += 0x800) {
1480                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1481                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1482                                        0, fw_ptr, 0x800, HZ);
1483         }
1484
1485         trace_firmware("Upload done, releasing device's CPU");
1486
1487         /* Now release the CPU.  It will disconnect and reconnect later. */
1488         pvr2_hdw_cpureset_assert(hdw,0);
1489
1490         kfree(fw_ptr);
1491         release_firmware(fw_entry);
1492
1493         trace_firmware("Upload done (%d bytes sent)",ret);
1494
1495         /* We should have written 8192 bytes */
1496         if (ret == 8192) {
1497                 hdw->fw1_state = FW1_STATE_RELOAD;
1498                 return 0;
1499         }
1500
1501         return -EIO;
1502 }
1503
1504
1505 /*
1506  * pvr2_upload_firmware2()
1507  *
1508  * This uploads encoder firmware on endpoint 2.
1509  *
1510  */
1511
1512 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1513 {
1514         const struct firmware *fw_entry = NULL;
1515         void  *fw_ptr;
1516         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1517         int actual_length;
1518         int ret = 0;
1519         int fwidx;
1520         static const char *fw_files[] = {
1521                 CX2341X_FIRM_ENC_FILENAME,
1522         };
1523
1524         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1525                 return 0;
1526         }
1527
1528         trace_firmware("pvr2_upload_firmware2");
1529
1530         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1531                                    ARRAY_SIZE(fw_files), fw_files);
1532         if (ret < 0) return ret;
1533         fwidx = ret;
1534         ret = 0;
1535         /* Since we're about to completely reinitialize the encoder,
1536            invalidate our cached copy of its configuration state.  Next
1537            time we configure the encoder, then we'll fully configure it. */
1538         hdw->enc_cur_valid = 0;
1539
1540         /* Encoder is about to be reset so note that as far as we're
1541            concerned now, the encoder has never been run. */
1542         del_timer_sync(&hdw->encoder_run_timer);
1543         if (hdw->state_encoder_runok) {
1544                 hdw->state_encoder_runok = 0;
1545                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1546         }
1547
1548         /* First prepare firmware loading */
1549         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1550         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1551         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1552         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1553         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1554         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1555         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1556         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1557         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1558         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1559         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1560         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1561         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1562         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1563         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1564         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1565         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1566         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1567
1568         if (ret) {
1569                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1570                            "firmware2 upload prep failed, ret=%d",ret);
1571                 release_firmware(fw_entry);
1572                 goto done;
1573         }
1574
1575         /* Now send firmware */
1576
1577         fw_len = fw_entry->size;
1578
1579         if (fw_len % sizeof(u32)) {
1580                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1581                            "size of %s firmware"
1582                            " must be a multiple of %zu bytes",
1583                            fw_files[fwidx],sizeof(u32));
1584                 release_firmware(fw_entry);
1585                 ret = -EINVAL;
1586                 goto done;
1587         }
1588
1589         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1590         if (fw_ptr == NULL){
1591                 release_firmware(fw_entry);
1592                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1593                            "failed to allocate memory for firmware2 upload");
1594                 ret = -ENOMEM;
1595                 goto done;
1596         }
1597
1598         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1599
1600         fw_done = 0;
1601         for (fw_done = 0; fw_done < fw_len;) {
1602                 bcnt = fw_len - fw_done;
1603                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1604                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1605                 /* Usbsnoop log shows that we must swap bytes... */
1606                 /* Some background info: The data being swapped here is a
1607                    firmware image destined for the mpeg encoder chip that
1608                    lives at the other end of a USB endpoint.  The encoder
1609                    chip always talks in 32 bit chunks and its storage is
1610                    organized into 32 bit words.  However from the file
1611                    system to the encoder chip everything is purely a byte
1612                    stream.  The firmware file's contents are always 32 bit
1613                    swapped from what the encoder expects.  Thus the need
1614                    always exists to swap the bytes regardless of the endian
1615                    type of the host processor and therefore swab32() makes
1616                    the most sense. */
1617                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1618                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1619
1620                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1621                                     &actual_length, HZ);
1622                 ret |= (actual_length != bcnt);
1623                 if (ret) break;
1624                 fw_done += bcnt;
1625         }
1626
1627         trace_firmware("upload of %s : %i / %i ",
1628                        fw_files[fwidx],fw_done,fw_len);
1629
1630         kfree(fw_ptr);
1631         release_firmware(fw_entry);
1632
1633         if (ret) {
1634                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1635                            "firmware2 upload transfer failure");
1636                 goto done;
1637         }
1638
1639         /* Finish upload */
1640
1641         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1642         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1643         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1644
1645         if (ret) {
1646                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1647                            "firmware2 upload post-proc failure");
1648         }
1649
1650  done:
1651         if (hdw->hdw_desc->signal_routing_scheme ==
1652             PVR2_ROUTING_SCHEME_GOTVIEW) {
1653                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1654                    hardware. */
1655                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1656         }
1657         return ret;
1658 }
1659
1660
1661 static const char *pvr2_get_state_name(unsigned int st)
1662 {
1663         if (st < ARRAY_SIZE(pvr2_state_names)) {
1664                 return pvr2_state_names[st];
1665         }
1666         return "???";
1667 }
1668
1669 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1670 {
1671         if (hdw->decoder_ctrl) {
1672                 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt, enablefl);
1673                 return 0;
1674         }
1675         /* Even though we really only care about the video decoder chip at
1676            this point, we'll broadcast stream on/off to all sub-devices
1677            anyway, just in case somebody else wants to hear the
1678            command... */
1679         v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1680         if (hdw->decoder_client_id) {
1681                 /* We get here if the encoder has been noticed.  Otherwise
1682                    we'll issue a warning to the user (which should
1683                    normally never happen). */
1684                 return 0;
1685         }
1686         if (!hdw->flag_decoder_missed) {
1687                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1688                            "WARNING: No decoder present");
1689                 hdw->flag_decoder_missed = !0;
1690                 trace_stbit("flag_decoder_missed",
1691                             hdw->flag_decoder_missed);
1692         }
1693         return -EIO;
1694 }
1695
1696
1697 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1698 {
1699         if (hdw->decoder_ctrl == ptr) return;
1700         hdw->decoder_ctrl = ptr;
1701         if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1702                 hdw->flag_decoder_missed = 0;
1703                 trace_stbit("flag_decoder_missed",
1704                             hdw->flag_decoder_missed);
1705                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1706                            "Decoder has appeared");
1707                 pvr2_hdw_state_sched(hdw);
1708         }
1709 }
1710
1711
1712 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1713 {
1714         return hdw->master_state;
1715 }
1716
1717
1718 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1719 {
1720         if (!hdw->flag_tripped) return 0;
1721         hdw->flag_tripped = 0;
1722         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1723                    "Clearing driver error statuss");
1724         return !0;
1725 }
1726
1727
1728 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1729 {
1730         int fl;
1731         LOCK_TAKE(hdw->big_lock); do {
1732                 fl = pvr2_hdw_untrip_unlocked(hdw);
1733         } while (0); LOCK_GIVE(hdw->big_lock);
1734         if (fl) pvr2_hdw_state_sched(hdw);
1735         return 0;
1736 }
1737
1738
1739
1740
1741 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1742 {
1743         return hdw->state_pipeline_req != 0;
1744 }
1745
1746
1747 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1748 {
1749         int ret,st;
1750         LOCK_TAKE(hdw->big_lock); do {
1751                 pvr2_hdw_untrip_unlocked(hdw);
1752                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1753                         hdw->state_pipeline_req = enable_flag != 0;
1754                         pvr2_trace(PVR2_TRACE_START_STOP,
1755                                    "/*--TRACE_STREAM--*/ %s",
1756                                    enable_flag ? "enable" : "disable");
1757                 }
1758                 pvr2_hdw_state_sched(hdw);
1759         } while (0); LOCK_GIVE(hdw->big_lock);
1760         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1761         if (enable_flag) {
1762                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1763                         if (st != PVR2_STATE_READY) return -EIO;
1764                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1765                 }
1766         }
1767         return 0;
1768 }
1769
1770
1771 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1772 {
1773         int fl;
1774         LOCK_TAKE(hdw->big_lock);
1775         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1776                 hdw->desired_stream_type = config;
1777                 hdw->state_pipeline_config = 0;
1778                 trace_stbit("state_pipeline_config",
1779                             hdw->state_pipeline_config);
1780                 pvr2_hdw_state_sched(hdw);
1781         }
1782         LOCK_GIVE(hdw->big_lock);
1783         if (fl) return 0;
1784         return pvr2_hdw_wait(hdw,0);
1785 }
1786
1787
1788 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1789 {
1790         int unit_number = hdw->unit_number;
1791         int tp = -1;
1792         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1793                 tp = tuner[unit_number];
1794         }
1795         if (tp < 0) return -EINVAL;
1796         hdw->tuner_type = tp;
1797         hdw->tuner_updated = !0;
1798         return 0;
1799 }
1800
1801
1802 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1803 {
1804         int unit_number = hdw->unit_number;
1805         int tp = 0;
1806         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1807                 tp = video_std[unit_number];
1808                 if (tp) return tp;
1809         }
1810         return 0;
1811 }
1812
1813
1814 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1815 {
1816         int unit_number = hdw->unit_number;
1817         int tp = 0;
1818         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1819                 tp = tolerance[unit_number];
1820         }
1821         return tp;
1822 }
1823
1824
1825 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1826 {
1827         /* Try a harmless request to fetch the eeprom's address over
1828            endpoint 1.  See what happens.  Only the full FX2 image can
1829            respond to this.  If this probe fails then likely the FX2
1830            firmware needs be loaded. */
1831         int result;
1832         LOCK_TAKE(hdw->ctl_lock); do {
1833                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1834                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1835                                            hdw->cmd_buffer,1,
1836                                            hdw->cmd_buffer,1);
1837                 if (result < 0) break;
1838         } while(0); LOCK_GIVE(hdw->ctl_lock);
1839         if (result) {
1840                 pvr2_trace(PVR2_TRACE_INIT,
1841                            "Probe of device endpoint 1 result status %d",
1842                            result);
1843         } else {
1844                 pvr2_trace(PVR2_TRACE_INIT,
1845                            "Probe of device endpoint 1 succeeded");
1846         }
1847         return result == 0;
1848 }
1849
1850 struct pvr2_std_hack {
1851         v4l2_std_id pat;  /* Pattern to match */
1852         v4l2_std_id msk;  /* Which bits we care about */
1853         v4l2_std_id std;  /* What additional standards or default to set */
1854 };
1855
1856 /* This data structure labels specific combinations of standards from
1857    tveeprom that we'll try to recognize.  If we recognize one, then assume
1858    a specified default standard to use.  This is here because tveeprom only
1859    tells us about available standards not the intended default standard (if
1860    any) for the device in question.  We guess the default based on what has
1861    been reported as available.  Note that this is only for guessing a
1862    default - which can always be overridden explicitly - and if the user
1863    has otherwise named a default then that default will always be used in
1864    place of this table. */
1865 static const struct pvr2_std_hack std_eeprom_maps[] = {
1866         {       /* PAL(B/G) */
1867                 .pat = V4L2_STD_B|V4L2_STD_GH,
1868                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1869         },
1870         {       /* NTSC(M) */
1871                 .pat = V4L2_STD_MN,
1872                 .std = V4L2_STD_NTSC_M,
1873         },
1874         {       /* PAL(I) */
1875                 .pat = V4L2_STD_PAL_I,
1876                 .std = V4L2_STD_PAL_I,
1877         },
1878         {       /* SECAM(L/L') */
1879                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1880                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1881         },
1882         {       /* PAL(D/D1/K) */
1883                 .pat = V4L2_STD_DK,
1884                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1885         },
1886 };
1887
1888 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1889 {
1890         char buf[40];
1891         unsigned int bcnt;
1892         v4l2_std_id std1,std2,std3;
1893
1894         std1 = get_default_standard(hdw);
1895         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1896
1897         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1898         pvr2_trace(PVR2_TRACE_STD,
1899                    "Supported video standard(s) reported available"
1900                    " in hardware: %.*s",
1901                    bcnt,buf);
1902
1903         hdw->std_mask_avail = hdw->std_mask_eeprom;
1904
1905         std2 = (std1|std3) & ~hdw->std_mask_avail;
1906         if (std2) {
1907                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1908                 pvr2_trace(PVR2_TRACE_STD,
1909                            "Expanding supported video standards"
1910                            " to include: %.*s",
1911                            bcnt,buf);
1912                 hdw->std_mask_avail |= std2;
1913         }
1914
1915         pvr2_hdw_internal_set_std_avail(hdw);
1916
1917         if (std1) {
1918                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1919                 pvr2_trace(PVR2_TRACE_STD,
1920                            "Initial video standard forced to %.*s",
1921                            bcnt,buf);
1922                 hdw->std_mask_cur = std1;
1923                 hdw->std_dirty = !0;
1924                 pvr2_hdw_internal_find_stdenum(hdw);
1925                 return;
1926         }
1927         if (std3) {
1928                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1929                 pvr2_trace(PVR2_TRACE_STD,
1930                            "Initial video standard"
1931                            " (determined by device type): %.*s",bcnt,buf);
1932                 hdw->std_mask_cur = std3;
1933                 hdw->std_dirty = !0;
1934                 pvr2_hdw_internal_find_stdenum(hdw);
1935                 return;
1936         }
1937
1938         {
1939                 unsigned int idx;
1940                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1941                         if (std_eeprom_maps[idx].msk ?
1942                             ((std_eeprom_maps[idx].pat ^
1943                              hdw->std_mask_eeprom) &
1944                              std_eeprom_maps[idx].msk) :
1945                             (std_eeprom_maps[idx].pat !=
1946                              hdw->std_mask_eeprom)) continue;
1947                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1948                                                   std_eeprom_maps[idx].std);
1949                         pvr2_trace(PVR2_TRACE_STD,
1950                                    "Initial video standard guessed as %.*s",
1951                                    bcnt,buf);
1952                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1953                         hdw->std_dirty = !0;
1954                         pvr2_hdw_internal_find_stdenum(hdw);
1955                         return;
1956                 }
1957         }
1958
1959         if (hdw->std_enum_cnt > 1) {
1960                 // Autoselect the first listed standard
1961                 hdw->std_enum_cur = 1;
1962                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1963                 hdw->std_dirty = !0;
1964                 pvr2_trace(PVR2_TRACE_STD,
1965                            "Initial video standard auto-selected to %s",
1966                            hdw->std_defs[hdw->std_enum_cur-1].name);
1967                 return;
1968         }
1969
1970         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1971                    "Unable to select a viable initial video standard");
1972 }
1973
1974
1975 static unsigned int pvr2_copy_i2c_addr_list(
1976         unsigned short *dst, const unsigned char *src,
1977         unsigned int dst_max)
1978 {
1979         unsigned int cnt;
1980         if (!src) return 0;
1981         while (src[cnt] && (cnt + 1) < dst_max) {
1982                 dst[cnt] = src[cnt];
1983                 cnt++;
1984         }
1985         dst[cnt] = I2C_CLIENT_END;
1986         return cnt;
1987 }
1988
1989
1990 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1991                                 const struct pvr2_device_client_desc *cd)
1992 {
1993         const char *fname;
1994         unsigned char mid;
1995         struct v4l2_subdev *sd;
1996         unsigned int i2ccnt;
1997         const unsigned char *p;
1998         /* Arbitrary count - max # i2c addresses we will probe */
1999         unsigned short i2caddr[25];
2000
2001         mid = cd->module_id;
2002         fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2003         if (!fname) {
2004                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2005                            "Module ID %u for device %s has no name",
2006                            mid,
2007                            hdw->hdw_desc->description);
2008                 return -EINVAL;
2009         }
2010
2011         i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2012                                          ARRAY_SIZE(i2caddr));
2013         if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2014                          module_i2c_addresses[mid] : NULL) != NULL)) {
2015                 /* Second chance: Try default i2c address list */
2016                 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2017                                                  ARRAY_SIZE(i2caddr));
2018         }
2019
2020         if (!i2ccnt) {
2021                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2022                            "Module ID %u (%s) for device %s:"
2023                            " No i2c addresses",
2024                            mid, fname, hdw->hdw_desc->description);
2025                 return -EINVAL;
2026         }
2027
2028         /* Note how the 2nd and 3rd arguments are the same for both
2029          * v4l2_i2c_new_subdev() and v4l2_i2c_new_probed_subdev().  Why?
2030          * Well the 2nd argument is the module name to load, while the 3rd
2031          * argument is documented in the framework as being the "chipid" -
2032          * and every other place where I can find examples of this, the
2033          * "chipid" appears to just be the module name again.  So here we
2034          * just do the same thing. */
2035         if (i2ccnt == 1) {
2036                 sd = v4l2_i2c_new_subdev(&hdw->i2c_adap,
2037                                          fname, fname,
2038                                          i2caddr[0]);
2039         } else {
2040                 sd = v4l2_i2c_new_probed_subdev(&hdw->i2c_adap,
2041                                                 fname, fname,
2042                                                 i2caddr);
2043         }
2044
2045         if (!sd) {
2046                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2047                            "Module ID %u (%s) for device %s failed to load",
2048                            mid, fname, hdw->hdw_desc->description);
2049                 return -EIO;
2050         }
2051
2052         /* Tag this sub-device instance with the module ID we know about.
2053            In other places we'll use that tag to determine if the instance
2054            requires special handling. */
2055         sd->grp_id = mid;
2056
2057         /* If we have both old and new i2c layers enabled, make sure that
2058            old layer isn't also tracking this module.  This is a debugging
2059            aid, in normal situations there's no reason for both mechanisms
2060            to be enabled. */
2061         pvr2_i2c_untrack_subdev(hdw, sd);
2062         pvr2_trace(PVR2_TRACE_INIT, "Attached sub-driver %s", fname);
2063
2064
2065         /* client-specific setup... */
2066         switch (mid) {
2067         case PVR2_CLIENT_ID_CX25840:
2068                 hdw->decoder_client_id = mid;
2069                 {
2070                         /*
2071                           Mike Isely <isely@pobox.com> 19-Nov-2006 - This
2072                           bit of nuttiness for cx25840 causes that module
2073                           to correctly set up its video scaling.  This is
2074                           really a problem in the cx25840 module itself,
2075                           but we work around it here.  The problem has not
2076                           been seen in ivtv because there VBI is supported
2077                           and set up.  We don't do VBI here (at least not
2078                           yet) and thus we never attempted to even set it
2079                           up.
2080                         */
2081                         struct v4l2_format fmt;
2082                         memset(&fmt, 0, sizeof(fmt));
2083                         fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2084                         v4l2_device_call_all(&hdw->v4l2_dev, mid,
2085                                              video, s_fmt, &fmt);
2086                 }
2087                 break;
2088         case PVR2_CLIENT_ID_SAA7115:
2089                 hdw->decoder_client_id = mid;
2090                 break;
2091         default: break;
2092         }
2093
2094         return 0;
2095 }
2096
2097
2098 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2099 {
2100         unsigned int idx;
2101         const struct pvr2_string_table *cm;
2102         const struct pvr2_device_client_table *ct;
2103         int okFl = !0;
2104
2105         cm = &hdw->hdw_desc->client_modules;
2106         for (idx = 0; idx < cm->cnt; idx++) {
2107                 request_module(cm->lst[idx]);
2108         }
2109
2110         ct = &hdw->hdw_desc->client_table;
2111         for (idx = 0; idx < ct->cnt; idx++) {
2112                 if (!pvr2_hdw_load_subdev(hdw, &ct->lst[idx])) okFl = 0;
2113         }
2114         if (!okFl) pvr2_hdw_render_useless(hdw);
2115 }
2116
2117
2118 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2119 {
2120         int ret;
2121         unsigned int idx;
2122         struct pvr2_ctrl *cptr;
2123         int reloadFl = 0;
2124         if (hdw->hdw_desc->fx2_firmware.cnt) {
2125                 if (!reloadFl) {
2126                         reloadFl =
2127                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2128                                  == 0);
2129                         if (reloadFl) {
2130                                 pvr2_trace(PVR2_TRACE_INIT,
2131                                            "USB endpoint config looks strange"
2132                                            "; possibly firmware needs to be"
2133                                            " loaded");
2134                         }
2135                 }
2136                 if (!reloadFl) {
2137                         reloadFl = !pvr2_hdw_check_firmware(hdw);
2138                         if (reloadFl) {
2139                                 pvr2_trace(PVR2_TRACE_INIT,
2140                                            "Check for FX2 firmware failed"
2141                                            "; possibly firmware needs to be"
2142                                            " loaded");
2143                         }
2144                 }
2145                 if (reloadFl) {
2146                         if (pvr2_upload_firmware1(hdw) != 0) {
2147                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2148                                            "Failure uploading firmware1");
2149                         }
2150                         return;
2151                 }
2152         }
2153         hdw->fw1_state = FW1_STATE_OK;
2154
2155         if (!pvr2_hdw_dev_ok(hdw)) return;
2156
2157         if (!hdw->hdw_desc->flag_no_powerup) {
2158                 pvr2_hdw_cmd_powerup(hdw);
2159                 if (!pvr2_hdw_dev_ok(hdw)) return;
2160         }
2161
2162         /* Take the IR chip out of reset, if appropriate */
2163         if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
2164                 pvr2_issue_simple_cmd(hdw,
2165                                       FX2CMD_HCW_ZILOG_RESET |
2166                                       (1 << 8) |
2167                                       ((0) << 16));
2168         }
2169
2170         // This step MUST happen after the earlier powerup step.
2171         pvr2_i2c_track_init(hdw);
2172         pvr2_i2c_core_init(hdw);
2173         if (!pvr2_hdw_dev_ok(hdw)) return;
2174
2175         pvr2_hdw_load_modules(hdw);
2176         if (!pvr2_hdw_dev_ok(hdw)) return;
2177
2178         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2179                 cptr = hdw->controls + idx;
2180                 if (cptr->info->skip_init) continue;
2181                 if (!cptr->info->set_value) continue;
2182                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2183         }
2184
2185         /* Set up special default values for the television and radio
2186            frequencies here.  It's not really important what these defaults
2187            are, but I set them to something usable in the Chicago area just
2188            to make driver testing a little easier. */
2189
2190         hdw->freqValTelevision = default_tv_freq;
2191         hdw->freqValRadio = default_radio_freq;
2192
2193         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2194         // thread-safe against the normal pvr2_send_request() mechanism.
2195         // (We should make it thread safe).
2196
2197         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2198                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2199                 if (!pvr2_hdw_dev_ok(hdw)) return;
2200                 if (ret < 0) {
2201                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2202                                    "Unable to determine location of eeprom,"
2203                                    " skipping");
2204                 } else {
2205                         hdw->eeprom_addr = ret;
2206                         pvr2_eeprom_analyze(hdw);
2207                         if (!pvr2_hdw_dev_ok(hdw)) return;
2208                 }
2209         } else {
2210                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2211                 hdw->tuner_updated = !0;
2212                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2213         }
2214
2215         if (hdw->serial_number) {
2216                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2217                                 "sn-%lu", hdw->serial_number);
2218         } else if (hdw->unit_number >= 0) {
2219                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2220                                 "unit-%c",
2221                                 hdw->unit_number + 'a');
2222         } else {
2223                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2224                                 "unit-??");
2225         }
2226         hdw->identifier[idx] = 0;
2227
2228         pvr2_hdw_setup_std(hdw);
2229
2230         if (!get_default_tuner_type(hdw)) {
2231                 pvr2_trace(PVR2_TRACE_INIT,
2232                            "pvr2_hdw_setup: Tuner type overridden to %d",
2233                            hdw->tuner_type);
2234         }
2235
2236         pvr2_i2c_core_check_stale(hdw);
2237         hdw->tuner_updated = 0;
2238
2239         if (!pvr2_hdw_dev_ok(hdw)) return;
2240
2241         if (hdw->hdw_desc->signal_routing_scheme ==
2242             PVR2_ROUTING_SCHEME_GOTVIEW) {
2243                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2244                    hardware. */
2245                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2246         }
2247
2248         pvr2_hdw_commit_setup(hdw);
2249
2250         hdw->vid_stream = pvr2_stream_create();
2251         if (!pvr2_hdw_dev_ok(hdw)) return;
2252         pvr2_trace(PVR2_TRACE_INIT,
2253                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2254         if (hdw->vid_stream) {
2255                 idx = get_default_error_tolerance(hdw);
2256                 if (idx) {
2257                         pvr2_trace(PVR2_TRACE_INIT,
2258                                    "pvr2_hdw_setup: video stream %p"
2259                                    " setting tolerance %u",
2260                                    hdw->vid_stream,idx);
2261                 }
2262                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2263                                   PVR2_VID_ENDPOINT,idx);
2264         }
2265
2266         if (!pvr2_hdw_dev_ok(hdw)) return;
2267
2268         hdw->flag_init_ok = !0;
2269
2270         pvr2_hdw_state_sched(hdw);
2271 }
2272
2273
2274 /* Set up the structure and attempt to put the device into a usable state.
2275    This can be a time-consuming operation, which is why it is not done
2276    internally as part of the create() step. */
2277 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2278 {
2279         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2280         do {
2281                 pvr2_hdw_setup_low(hdw);
2282                 pvr2_trace(PVR2_TRACE_INIT,
2283                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2284                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2285                 if (pvr2_hdw_dev_ok(hdw)) {
2286                         if (hdw->flag_init_ok) {
2287                                 pvr2_trace(
2288                                         PVR2_TRACE_INFO,
2289                                         "Device initialization"
2290                                         " completed successfully.");
2291                                 break;
2292                         }
2293                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2294                                 pvr2_trace(
2295                                         PVR2_TRACE_INFO,
2296                                         "Device microcontroller firmware"
2297                                         " (re)loaded; it should now reset"
2298                                         " and reconnect.");
2299                                 break;
2300                         }
2301                         pvr2_trace(
2302                                 PVR2_TRACE_ERROR_LEGS,
2303                                 "Device initialization was not successful.");
2304                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2305                                 pvr2_trace(
2306                                         PVR2_TRACE_ERROR_LEGS,
2307                                         "Giving up since device"
2308                                         " microcontroller firmware"
2309                                         " appears to be missing.");
2310                                 break;
2311                         }
2312                 }
2313                 if (procreload) {
2314                         pvr2_trace(
2315                                 PVR2_TRACE_ERROR_LEGS,
2316                                 "Attempting pvrusb2 recovery by reloading"
2317                                 " primary firmware.");
2318                         pvr2_trace(
2319                                 PVR2_TRACE_ERROR_LEGS,
2320                                 "If this works, device should disconnect"
2321                                 " and reconnect in a sane state.");
2322                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2323                         pvr2_upload_firmware1(hdw);
2324                 } else {
2325                         pvr2_trace(
2326                                 PVR2_TRACE_ERROR_LEGS,
2327                                 "***WARNING*** pvrusb2 device hardware"
2328                                 " appears to be jammed"
2329                                 " and I can't clear it.");
2330                         pvr2_trace(
2331                                 PVR2_TRACE_ERROR_LEGS,
2332                                 "You might need to power cycle"
2333                                 " the pvrusb2 device"
2334                                 " in order to recover.");
2335                 }
2336         } while (0);
2337         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2338 }
2339
2340
2341 /* Perform second stage initialization.  Set callback pointer first so that
2342    we can avoid a possible initialization race (if the kernel thread runs
2343    before the callback has been set). */
2344 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2345                         void (*callback_func)(void *),
2346                         void *callback_data)
2347 {
2348         LOCK_TAKE(hdw->big_lock); do {
2349                 if (hdw->flag_disconnected) {
2350                         /* Handle a race here: If we're already
2351                            disconnected by this point, then give up.  If we
2352                            get past this then we'll remain connected for
2353                            the duration of initialization since the entire
2354                            initialization sequence is now protected by the
2355                            big_lock. */
2356                         break;
2357                 }
2358                 hdw->state_data = callback_data;
2359                 hdw->state_func = callback_func;
2360                 pvr2_hdw_setup(hdw);
2361         } while (0); LOCK_GIVE(hdw->big_lock);
2362         return hdw->flag_init_ok;
2363 }
2364
2365
2366 /* Create, set up, and return a structure for interacting with the
2367    underlying hardware.  */
2368 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2369                                  const struct usb_device_id *devid)
2370 {
2371         unsigned int idx,cnt1,cnt2,m;
2372         struct pvr2_hdw *hdw = NULL;
2373         int valid_std_mask;
2374         struct pvr2_ctrl *cptr;
2375         struct usb_device *usb_dev;
2376         const struct pvr2_device_desc *hdw_desc;
2377         __u8 ifnum;
2378         struct v4l2_queryctrl qctrl;
2379         struct pvr2_ctl_info *ciptr;
2380
2381         usb_dev = interface_to_usbdev(intf);
2382
2383         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2384
2385         if (hdw_desc == NULL) {
2386                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2387                            " No device description pointer,"
2388                            " unable to continue.");
2389                 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2390                            " please contact Mike Isely <isely@pobox.com>"
2391                            " to get it included in the driver\n");
2392                 goto fail;
2393         }
2394
2395         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2396         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2397                    hdw,hdw_desc->description);
2398         if (!hdw) goto fail;
2399
2400         init_timer(&hdw->quiescent_timer);
2401         hdw->quiescent_timer.data = (unsigned long)hdw;
2402         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2403
2404         init_timer(&hdw->encoder_wait_timer);
2405         hdw->encoder_wait_timer.data = (unsigned long)hdw;
2406         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2407
2408         init_timer(&hdw->encoder_run_timer);
2409         hdw->encoder_run_timer.data = (unsigned long)hdw;
2410         hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2411
2412         hdw->master_state = PVR2_STATE_DEAD;
2413
2414         init_waitqueue_head(&hdw->state_wait_data);
2415
2416         hdw->tuner_signal_stale = !0;
2417         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2418
2419         /* Calculate which inputs are OK */
2420         m = 0;
2421         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2422         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2423                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2424         }
2425         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2426         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2427         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2428         hdw->input_avail_mask = m;
2429         hdw->input_allowed_mask = hdw->input_avail_mask;
2430
2431         /* If not a hybrid device, pathway_state never changes.  So
2432            initialize it here to what it should forever be. */
2433         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2434                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2435         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2436                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2437         }
2438
2439         hdw->control_cnt = CTRLDEF_COUNT;
2440         hdw->control_cnt += MPEGDEF_COUNT;
2441         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2442                                 GFP_KERNEL);
2443         if (!hdw->controls) goto fail;
2444         hdw->hdw_desc = hdw_desc;
2445         for (idx = 0; idx < hdw->control_cnt; idx++) {
2446                 cptr = hdw->controls + idx;
2447                 cptr->hdw = hdw;
2448         }
2449         for (idx = 0; idx < 32; idx++) {
2450                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2451         }
2452         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2453                 cptr = hdw->controls + idx;
2454                 cptr->info = control_defs+idx;
2455         }
2456
2457         /* Ensure that default input choice is a valid one. */
2458         m = hdw->input_avail_mask;
2459         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2460                 if (!((1 << idx) & m)) continue;
2461                 hdw->input_val = idx;
2462                 break;
2463         }
2464
2465         /* Define and configure additional controls from cx2341x module. */
2466         hdw->mpeg_ctrl_info = kzalloc(
2467                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2468         if (!hdw->mpeg_ctrl_info) goto fail;
2469         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2470                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2471                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2472                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2473                 ciptr->name = mpeg_ids[idx].strid;
2474                 ciptr->v4l_id = mpeg_ids[idx].id;
2475                 ciptr->skip_init = !0;
2476                 ciptr->get_value = ctrl_cx2341x_get;
2477                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2478                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2479                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2480                 qctrl.id = ciptr->v4l_id;
2481                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2482                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2483                         ciptr->set_value = ctrl_cx2341x_set;
2484                 }
2485                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2486                         PVR2_CTLD_INFO_DESC_SIZE);
2487                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2488                 ciptr->default_value = qctrl.default_value;
2489                 switch (qctrl.type) {
2490                 default:
2491                 case V4L2_CTRL_TYPE_INTEGER:
2492                         ciptr->type = pvr2_ctl_int;
2493                         ciptr->def.type_int.min_value = qctrl.minimum;
2494                         ciptr->def.type_int.max_value = qctrl.maximum;
2495                         break;
2496                 case V4L2_CTRL_TYPE_BOOLEAN:
2497                         ciptr->type = pvr2_ctl_bool;
2498                         break;
2499                 case V4L2_CTRL_TYPE_MENU:
2500                         ciptr->type = pvr2_ctl_enum;
2501                         ciptr->def.type_enum.value_names =
2502                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2503                                                                 ciptr->v4l_id);
2504                         for (cnt1 = 0;
2505                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2506                              cnt1++) { }
2507                         ciptr->def.type_enum.count = cnt1;
2508                         break;
2509                 }
2510                 cptr->info = ciptr;
2511         }
2512
2513         // Initialize video standard enum dynamic control
2514         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2515         if (cptr) {
2516                 memcpy(&hdw->std_info_enum,cptr->info,
2517                        sizeof(hdw->std_info_enum));
2518                 cptr->info = &hdw->std_info_enum;
2519
2520         }
2521         // Initialize control data regarding video standard masks
2522         valid_std_mask = pvr2_std_get_usable();
2523         for (idx = 0; idx < 32; idx++) {
2524                 if (!(valid_std_mask & (1 << idx))) continue;
2525                 cnt1 = pvr2_std_id_to_str(
2526                         hdw->std_mask_names[idx],
2527                         sizeof(hdw->std_mask_names[idx])-1,
2528                         1 << idx);
2529                 hdw->std_mask_names[idx][cnt1] = 0;
2530         }
2531         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2532         if (cptr) {
2533                 memcpy(&hdw->std_info_avail,cptr->info,
2534                        sizeof(hdw->std_info_avail));
2535                 cptr->info = &hdw->std_info_avail;
2536                 hdw->std_info_avail.def.type_bitmask.bit_names =
2537                         hdw->std_mask_ptrs;
2538                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2539                         valid_std_mask;
2540         }
2541         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2542         if (cptr) {
2543                 memcpy(&hdw->std_info_cur,cptr->info,
2544                        sizeof(hdw->std_info_cur));
2545                 cptr->info = &hdw->std_info_cur;
2546                 hdw->std_info_cur.def.type_bitmask.bit_names =
2547                         hdw->std_mask_ptrs;
2548                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2549                         valid_std_mask;
2550         }
2551
2552         hdw->cropcap_stale = !0;
2553         hdw->eeprom_addr = -1;
2554         hdw->unit_number = -1;
2555         hdw->v4l_minor_number_video = -1;
2556         hdw->v4l_minor_number_vbi = -1;
2557         hdw->v4l_minor_number_radio = -1;
2558         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2559         if (!hdw->ctl_write_buffer) goto fail;
2560         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2561         if (!hdw->ctl_read_buffer) goto fail;
2562         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2563         if (!hdw->ctl_write_urb) goto fail;
2564         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2565         if (!hdw->ctl_read_urb) goto fail;
2566
2567         if (v4l2_device_register(&usb_dev->dev, &hdw->v4l2_dev) != 0) {
2568                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2569                            "Error registering with v4l core, giving up");
2570                 goto fail;
2571         }
2572         mutex_lock(&pvr2_unit_mtx); do {
2573                 for (idx = 0; idx < PVR_NUM; idx++) {
2574                         if (unit_pointers[idx]) continue;
2575                         hdw->unit_number = idx;
2576                         unit_pointers[idx] = hdw;
2577                         break;
2578                 }
2579         } while (0); mutex_unlock(&pvr2_unit_mtx);
2580
2581         cnt1 = 0;
2582         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2583         cnt1 += cnt2;
2584         if (hdw->unit_number >= 0) {
2585                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2586                                  ('a' + hdw->unit_number));
2587                 cnt1 += cnt2;
2588         }
2589         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2590         hdw->name[cnt1] = 0;
2591
2592         hdw->workqueue = create_singlethread_workqueue(hdw->name);
2593         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2594         INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2595
2596         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2597                    hdw->unit_number,hdw->name);
2598
2599         hdw->tuner_type = -1;
2600         hdw->flag_ok = !0;
2601
2602         hdw->usb_intf = intf;
2603         hdw->usb_dev = usb_dev;
2604
2605         usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2606
2607         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2608         usb_set_interface(hdw->usb_dev,ifnum,0);
2609
2610         mutex_init(&hdw->ctl_lock_mutex);
2611         mutex_init(&hdw->big_lock_mutex);
2612
2613         return hdw;
2614  fail:
2615         if (hdw) {
2616                 del_timer_sync(&hdw->quiescent_timer);
2617                 del_timer_sync(&hdw->encoder_run_timer);
2618                 del_timer_sync(&hdw->encoder_wait_timer);
2619                 if (hdw->workqueue) {
2620                         flush_workqueue(hdw->workqueue);
2621                         destroy_workqueue(hdw->workqueue);
2622                         hdw->workqueue = NULL;
2623                 }
2624                 usb_free_urb(hdw->ctl_read_urb);
2625                 usb_free_urb(hdw->ctl_write_urb);
2626                 kfree(hdw->ctl_read_buffer);
2627                 kfree(hdw->ctl_write_buffer);
2628                 kfree(hdw->controls);
2629                 kfree(hdw->mpeg_ctrl_info);
2630                 kfree(hdw->std_defs);
2631                 kfree(hdw->std_enum_names);
2632                 kfree(hdw);
2633         }
2634         return NULL;
2635 }
2636
2637
2638 /* Remove _all_ associations between this driver and the underlying USB
2639    layer. */
2640 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2641 {
2642         if (hdw->flag_disconnected) return;
2643         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2644         if (hdw->ctl_read_urb) {
2645                 usb_kill_urb(hdw->ctl_read_urb);
2646                 usb_free_urb(hdw->ctl_read_urb);
2647                 hdw->ctl_read_urb = NULL;
2648         }
2649         if (hdw->ctl_write_urb) {
2650                 usb_kill_urb(hdw->ctl_write_urb);
2651                 usb_free_urb(hdw->ctl_write_urb);
2652                 hdw->ctl_write_urb = NULL;
2653         }
2654         if (hdw->ctl_read_buffer) {
2655                 kfree(hdw->ctl_read_buffer);
2656                 hdw->ctl_read_buffer = NULL;
2657         }
2658         if (hdw->ctl_write_buffer) {
2659                 kfree(hdw->ctl_write_buffer);
2660                 hdw->ctl_write_buffer = NULL;
2661         }
2662         hdw->flag_disconnected = !0;
2663         /* If we don't do this, then there will be a dangling struct device
2664            reference to our disappearing device persisting inside the V4L
2665            core... */
2666         if (hdw->v4l2_dev.dev) {
2667                 dev_set_drvdata(hdw->v4l2_dev.dev, NULL);
2668                 hdw->v4l2_dev.dev = NULL;
2669         }
2670         hdw->usb_dev = NULL;
2671         hdw->usb_intf = NULL;
2672         pvr2_hdw_render_useless(hdw);
2673 }
2674
2675
2676 /* Destroy hardware interaction structure */
2677 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2678 {
2679         if (!hdw) return;
2680         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2681         if (hdw->workqueue) {
2682                 flush_workqueue(hdw->workqueue);
2683                 destroy_workqueue(hdw->workqueue);
2684                 hdw->workqueue = NULL;
2685         }
2686         del_timer_sync(&hdw->quiescent_timer);
2687         del_timer_sync(&hdw->encoder_run_timer);
2688         del_timer_sync(&hdw->encoder_wait_timer);
2689         if (hdw->fw_buffer) {
2690                 kfree(hdw->fw_buffer);
2691                 hdw->fw_buffer = NULL;
2692         }
2693         if (hdw->vid_stream) {
2694                 pvr2_stream_destroy(hdw->vid_stream);
2695                 hdw->vid_stream = NULL;
2696         }
2697         if (hdw->decoder_ctrl) {
2698                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2699         }
2700         pvr2_i2c_core_done(hdw);
2701         pvr2_i2c_track_done(hdw);
2702         v4l2_device_unregister(&hdw->v4l2_dev);
2703         pvr2_hdw_remove_usb_stuff(hdw);
2704         mutex_lock(&pvr2_unit_mtx); do {
2705                 if ((hdw->unit_number >= 0) &&
2706                     (hdw->unit_number < PVR_NUM) &&
2707                     (unit_pointers[hdw->unit_number] == hdw)) {
2708                         unit_pointers[hdw->unit_number] = NULL;
2709                 }
2710         } while (0); mutex_unlock(&pvr2_unit_mtx);
2711         kfree(hdw->controls);
2712         kfree(hdw->mpeg_ctrl_info);
2713         kfree(hdw->std_defs);
2714         kfree(hdw->std_enum_names);
2715         kfree(hdw);
2716 }
2717
2718
2719 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2720 {
2721         return (hdw && hdw->flag_ok);
2722 }
2723
2724
2725 /* Called when hardware has been unplugged */
2726 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2727 {
2728         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2729         LOCK_TAKE(hdw->big_lock);
2730         LOCK_TAKE(hdw->ctl_lock);
2731         pvr2_hdw_remove_usb_stuff(hdw);
2732         LOCK_GIVE(hdw->ctl_lock);
2733         LOCK_GIVE(hdw->big_lock);
2734 }
2735
2736
2737 // Attempt to autoselect an appropriate value for std_enum_cur given
2738 // whatever is currently in std_mask_cur
2739 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2740 {
2741         unsigned int idx;
2742         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2743                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2744                         hdw->std_enum_cur = idx;
2745                         return;
2746                 }
2747         }
2748         hdw->std_enum_cur = 0;
2749 }
2750
2751
2752 // Calculate correct set of enumerated standards based on currently known
2753 // set of available standards bits.
2754 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2755 {
2756         struct v4l2_standard *newstd;
2757         unsigned int std_cnt;
2758         unsigned int idx;
2759
2760         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2761
2762         if (hdw->std_defs) {
2763                 kfree(hdw->std_defs);
2764                 hdw->std_defs = NULL;
2765         }
2766         hdw->std_enum_cnt = 0;
2767         if (hdw->std_enum_names) {
2768                 kfree(hdw->std_enum_names);
2769                 hdw->std_enum_names = NULL;
2770         }
2771
2772         if (!std_cnt) {
2773                 pvr2_trace(
2774                         PVR2_TRACE_ERROR_LEGS,
2775                         "WARNING: Failed to identify any viable standards");
2776         }
2777         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2778         hdw->std_enum_names[0] = "none";
2779         for (idx = 0; idx < std_cnt; idx++) {
2780                 hdw->std_enum_names[idx+1] =
2781                         newstd[idx].name;
2782         }
2783         // Set up the dynamic control for this standard
2784         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2785         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2786         hdw->std_defs = newstd;
2787         hdw->std_enum_cnt = std_cnt+1;
2788         hdw->std_enum_cur = 0;
2789         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2790 }
2791
2792
2793 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2794                                struct v4l2_standard *std,
2795                                unsigned int idx)
2796 {
2797         int ret = -EINVAL;
2798         if (!idx) return ret;
2799         LOCK_TAKE(hdw->big_lock); do {
2800                 if (idx >= hdw->std_enum_cnt) break;
2801                 idx--;
2802                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2803                 ret = 0;
2804         } while (0); LOCK_GIVE(hdw->big_lock);
2805         return ret;
2806 }
2807
2808
2809 /* Get the number of defined controls */
2810 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2811 {
2812         return hdw->control_cnt;
2813 }
2814
2815
2816 /* Retrieve a control handle given its index (0..count-1) */
2817 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2818                                              unsigned int idx)
2819 {
2820         if (idx >= hdw->control_cnt) return NULL;
2821         return hdw->controls + idx;
2822 }
2823
2824
2825 /* Retrieve a control handle given its index (0..count-1) */
2826 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2827                                           unsigned int ctl_id)
2828 {
2829         struct pvr2_ctrl *cptr;
2830         unsigned int idx;
2831         int i;
2832
2833         /* This could be made a lot more efficient, but for now... */
2834         for (idx = 0; idx < hdw->control_cnt; idx++) {
2835                 cptr = hdw->controls + idx;
2836                 i = cptr->info->internal_id;
2837                 if (i && (i == ctl_id)) return cptr;
2838         }
2839         return NULL;
2840 }
2841
2842
2843 /* Given a V4L ID, retrieve the control structure associated with it. */
2844 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2845 {
2846         struct pvr2_ctrl *cptr;
2847         unsigned int idx;
2848         int i;
2849
2850         /* This could be made a lot more efficient, but for now... */
2851         for (idx = 0; idx < hdw->control_cnt; idx++) {
2852                 cptr = hdw->controls + idx;
2853                 i = cptr->info->v4l_id;
2854                 if (i && (i == ctl_id)) return cptr;
2855         }
2856         return NULL;
2857 }
2858
2859
2860 /* Given a V4L ID for its immediate predecessor, retrieve the control
2861    structure associated with it. */
2862 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2863                                             unsigned int ctl_id)
2864 {
2865         struct pvr2_ctrl *cptr,*cp2;
2866         unsigned int idx;
2867         int i;
2868
2869         /* This could be made a lot more efficient, but for now... */
2870         cp2 = NULL;
2871         for (idx = 0; idx < hdw->control_cnt; idx++) {
2872                 cptr = hdw->controls + idx;
2873                 i = cptr->info->v4l_id;
2874                 if (!i) continue;
2875                 if (i <= ctl_id) continue;
2876                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2877                 cp2 = cptr;
2878         }
2879         return cp2;
2880         return NULL;
2881 }
2882
2883
2884 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2885 {
2886         switch (tp) {
2887         case pvr2_ctl_int: return "integer";
2888         case pvr2_ctl_enum: return "enum";
2889         case pvr2_ctl_bool: return "boolean";
2890         case pvr2_ctl_bitmask: return "bitmask";
2891         }
2892         return "";
2893 }
2894
2895
2896 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2897                                     const char *name, int val)
2898 {
2899         struct v4l2_control ctrl;
2900         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2901         memset(&ctrl, 0, sizeof(ctrl));
2902         ctrl.id = id;
2903         ctrl.value = val;
2904         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2905 }
2906
2907 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2908         if ((hdw)->lab##_dirty) { \
2909                 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2910         }
2911
2912 /* Execute whatever commands are required to update the state of all the
2913    sub-devices so that they match our current control values. */
2914 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2915 {
2916         struct v4l2_subdev *sd;
2917         unsigned int id;
2918         pvr2_subdev_update_func fp;
2919
2920         if (hdw->input_dirty || hdw->std_dirty) {
2921                 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_standard");
2922                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2923                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2924                                              tuner, s_radio);
2925                 } else {
2926                         v4l2_std_id vs;
2927                         vs = hdw->std_mask_cur;
2928                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2929                                              tuner, s_std, vs);
2930                 }
2931                 hdw->tuner_signal_stale = !0;
2932                 hdw->cropcap_stale = !0;
2933         }
2934
2935         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2936         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2937         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2938         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2939         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2940         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2941         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2942         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2943         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2944
2945         if (hdw->input_dirty || hdw->audiomode_dirty) {
2946                 struct v4l2_tuner vt;
2947                 memset(&vt, 0, sizeof(vt));
2948                 vt.audmode = hdw->audiomode_val;
2949                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2950         }
2951
2952         if (hdw->freqDirty) {
2953                 unsigned long fv;
2954                 struct v4l2_frequency freq;
2955                 fv = pvr2_hdw_get_cur_freq(hdw);
2956                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2957                 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2958                 memset(&freq, 0, sizeof(freq));
2959                 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2960                         /* ((fv * 1000) / 62500) */
2961                         freq.frequency = (fv * 2) / 125;
2962                 } else {
2963                         freq.frequency = fv / 62500;
2964                 }
2965                 /* tuner-core currently doesn't seem to care about this, but
2966                    let's set it anyway for completeness. */
2967                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2968                         freq.type = V4L2_TUNER_RADIO;
2969                 } else {
2970                         freq.type = V4L2_TUNER_ANALOG_TV;
2971                 }
2972                 freq.tuner = 0;
2973                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2974                                      s_frequency, &freq);
2975         }
2976
2977         if (hdw->res_hor_dirty || hdw->res_ver_dirty) {
2978                 struct v4l2_format fmt;
2979                 memset(&fmt, 0, sizeof(fmt));
2980                 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2981                 fmt.fmt.pix.width = hdw->res_hor_val;
2982                 fmt.fmt.pix.height = hdw->res_ver_val;
2983                 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_size(%dx%d)",
2984                            fmt.fmt.pix.width, fmt.fmt.pix.height);
2985                 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
2986         }
2987
2988         if (hdw->srate_dirty) {
2989                 u32 val;
2990                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
2991                            hdw->srate_val);
2992                 switch (hdw->srate_val) {
2993                 default:
2994                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
2995                         val = 48000;
2996                         break;
2997                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
2998                         val = 44100;
2999                         break;
3000                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3001                         val = 32000;
3002                         break;
3003                 }
3004                 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3005                                      audio, s_clock_freq, val);
3006         }
3007
3008         /* Unable to set crop parameters; there is apparently no equivalent
3009            for VIDIOC_S_CROP */
3010
3011         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3012                 id = sd->grp_id;
3013                 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3014                 fp = pvr2_module_update_functions[id];
3015                 if (!fp) continue;
3016                 (*fp)(hdw, sd);
3017         }
3018
3019         if (hdw->tuner_signal_stale && hdw->cropcap_stale) {
3020                 pvr2_hdw_status_poll(hdw);
3021         }
3022 }
3023
3024
3025 /* Figure out if we need to commit control changes.  If so, mark internal
3026    state flags to indicate this fact and return true.  Otherwise do nothing
3027    else and return false. */
3028 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
3029 {
3030         unsigned int idx;
3031         struct pvr2_ctrl *cptr;
3032         int value;
3033         int commit_flag = 0;
3034         char buf[100];
3035         unsigned int bcnt,ccnt;
3036
3037         for (idx = 0; idx < hdw->control_cnt; idx++) {
3038                 cptr = hdw->controls + idx;
3039                 if (!cptr->info->is_dirty) continue;
3040                 if (!cptr->info->is_dirty(cptr)) continue;
3041                 commit_flag = !0;
3042
3043                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
3044                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3045                                  cptr->info->name);
3046                 value = 0;
3047                 cptr->info->get_value(cptr,&value);
3048                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3049                                                 buf+bcnt,
3050                                                 sizeof(buf)-bcnt,&ccnt);
3051                 bcnt += ccnt;
3052                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3053                                   get_ctrl_typename(cptr->info->type));
3054                 pvr2_trace(PVR2_TRACE_CTL,
3055                            "/*--TRACE_COMMIT--*/ %.*s",
3056                            bcnt,buf);
3057         }
3058
3059         if (!commit_flag) {
3060                 /* Nothing has changed */
3061                 return 0;
3062         }
3063
3064         hdw->state_pipeline_config = 0;
3065         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3066         pvr2_hdw_state_sched(hdw);
3067
3068         return !0;
3069 }
3070
3071
3072 /* Perform all operations needed to commit all control changes.  This must
3073    be performed in synchronization with the pipeline state and is thus
3074    expected to be called as part of the driver's worker thread.  Return
3075    true if commit successful, otherwise return false to indicate that
3076    commit isn't possible at this time. */
3077 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3078 {
3079         unsigned int idx;
3080         struct pvr2_ctrl *cptr;
3081         int disruptive_change;
3082
3083         /* Handle some required side effects when the video standard is
3084            changed.... */
3085         if (hdw->std_dirty) {
3086                 int nvres;
3087                 int gop_size;
3088                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3089                         nvres = 480;
3090                         gop_size = 15;
3091                 } else {
3092                         nvres = 576;
3093                         gop_size = 12;
3094                 }
3095                 /* Rewrite the vertical resolution to be appropriate to the
3096                    video standard that has been selected. */
3097                 if (nvres != hdw->res_ver_val) {
3098                         hdw->res_ver_val = nvres;
3099                         hdw->res_ver_dirty = !0;
3100                 }
3101                 /* Rewrite the GOP size to be appropriate to the video
3102                    standard that has been selected. */
3103                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3104                         struct v4l2_ext_controls cs;
3105                         struct v4l2_ext_control c1;
3106                         memset(&cs, 0, sizeof(cs));
3107                         memset(&c1, 0, sizeof(c1));
3108                         cs.controls = &c1;
3109                         cs.count = 1;
3110                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3111                         c1.value = gop_size;
3112                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3113                                           VIDIOC_S_EXT_CTRLS);
3114                 }
3115         }
3116
3117         if (hdw->input_dirty && hdw->state_pathway_ok &&
3118             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3119               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3120              hdw->pathway_state)) {
3121                 /* Change of mode being asked for... */
3122                 hdw->state_pathway_ok = 0;
3123                 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3124         }
3125         if (!hdw->state_pathway_ok) {
3126                 /* Can't commit anything until pathway is ok. */
3127                 return 0;
3128         }
3129         /* The broadcast decoder can only scale down, so if
3130          * res_*_dirty && crop window < output format ==> enlarge crop.
3131          *
3132          * The mpeg encoder receives fields of res_hor_val dots and
3133          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3134          */
3135         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3136                 hdw->cropw_val = hdw->res_hor_val;
3137                 hdw->cropw_dirty = !0;
3138         } else if (hdw->cropw_dirty) {
3139                 hdw->res_hor_dirty = !0;           /* must rescale */
3140                 hdw->res_hor_val = min(720, hdw->cropw_val);
3141         }
3142         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3143                 hdw->croph_val = hdw->res_ver_val;
3144                 hdw->croph_dirty = !0;
3145         } else if (hdw->croph_dirty) {
3146                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3147                 hdw->res_ver_dirty = !0;
3148                 hdw->res_ver_val = min(nvres, hdw->croph_val);
3149         }
3150
3151         /* If any of the below has changed, then we can't do the update
3152            while the pipeline is running.  Pipeline must be paused first
3153            and decoder -> encoder connection be made quiescent before we
3154            can proceed. */
3155         disruptive_change =
3156                 (hdw->std_dirty ||
3157                  hdw->enc_unsafe_stale ||
3158                  hdw->srate_dirty ||
3159                  hdw->res_ver_dirty ||
3160                  hdw->res_hor_dirty ||
3161                  hdw->cropw_dirty ||
3162                  hdw->croph_dirty ||
3163                  hdw->input_dirty ||
3164                  (hdw->active_stream_type != hdw->desired_stream_type));
3165         if (disruptive_change && !hdw->state_pipeline_idle) {
3166                 /* Pipeline is not idle; we can't proceed.  Arrange to
3167                    cause pipeline to stop so that we can try this again
3168                    later.... */
3169                 hdw->state_pipeline_pause = !0;
3170                 return 0;
3171         }
3172
3173         if (hdw->srate_dirty) {
3174                 /* Write new sample rate into control structure since
3175                  * the master copy is stale.  We must track srate
3176                  * separate from the mpeg control structure because
3177                  * other logic also uses this value. */
3178                 struct v4l2_ext_controls cs;
3179                 struct v4l2_ext_control c1;
3180                 memset(&cs,0,sizeof(cs));
3181                 memset(&c1,0,sizeof(c1));
3182                 cs.controls = &c1;
3183                 cs.count = 1;
3184                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3185                 c1.value = hdw->srate_val;
3186                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3187         }
3188
3189         /* Scan i2c core at this point - before we clear all the dirty
3190            bits.  Various parts of the i2c core will notice dirty bits as
3191            appropriate and arrange to broadcast or directly send updates to
3192            the client drivers in order to keep everything in sync */
3193         pvr2_i2c_core_check_stale(hdw);
3194
3195         if (hdw->active_stream_type != hdw->desired_stream_type) {
3196                 /* Handle any side effects of stream config here */
3197                 hdw->active_stream_type = hdw->desired_stream_type;
3198         }
3199
3200         if (hdw->hdw_desc->signal_routing_scheme ==
3201             PVR2_ROUTING_SCHEME_GOTVIEW) {
3202                 u32 b;
3203                 /* Handle GOTVIEW audio switching */
3204                 pvr2_hdw_gpio_get_out(hdw,&b);
3205                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3206                         /* Set GPIO 11 */
3207                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3208                 } else {
3209                         /* Clear GPIO 11 */
3210                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3211                 }
3212         }
3213
3214         for (idx = 0; idx < hdw->control_cnt; idx++) {
3215                 cptr = hdw->controls + idx;
3216                 if (!cptr->info->clear_dirty) continue;
3217                 cptr->info->clear_dirty(cptr);
3218         }
3219
3220         /* Check and update state for all sub-devices. */
3221         pvr2_subdev_update(hdw);
3222
3223         /* Now execute i2c core update */
3224         pvr2_i2c_core_sync(hdw);
3225
3226         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3227             hdw->state_encoder_run) {
3228                 /* If encoder isn't running or it can't be touched, then
3229                    this will get worked out later when we start the
3230                    encoder. */
3231                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3232         }
3233
3234         hdw->state_pipeline_config = !0;
3235         /* Hardware state may have changed in a way to cause the cropping
3236            capabilities to have changed.  So mark it stale, which will
3237            cause a later re-fetch. */
3238         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3239         return !0;
3240 }
3241
3242
3243 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3244 {
3245         int fl;
3246         LOCK_TAKE(hdw->big_lock);
3247         fl = pvr2_hdw_commit_setup(hdw);
3248         LOCK_GIVE(hdw->big_lock);
3249         if (!fl) return 0;
3250         return pvr2_hdw_wait(hdw,0);
3251 }
3252
3253
3254 static void pvr2_hdw_worker_i2c(struct work_struct *work)
3255 {
3256         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
3257         LOCK_TAKE(hdw->big_lock); do {
3258                 pvr2_i2c_core_sync(hdw);
3259         } while (0); LOCK_GIVE(hdw->big_lock);
3260 }
3261
3262
3263 static void pvr2_hdw_worker_poll(struct work_struct *work)
3264 {
3265         int fl = 0;
3266         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3267         LOCK_TAKE(hdw->big_lock); do {
3268                 fl = pvr2_hdw_state_eval(hdw);
3269         } while (0); LOCK_GIVE(hdw->big_lock);
3270         if (fl && hdw->state_func) {
3271                 hdw->state_func(hdw->state_data);
3272         }
3273 }
3274
3275
3276 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3277 {
3278         return wait_event_interruptible(
3279                 hdw->state_wait_data,
3280                 (hdw->state_stale == 0) &&
3281                 (!state || (hdw->master_state != state)));
3282 }
3283
3284
3285 /* Return name for this driver instance */
3286 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3287 {
3288         return hdw->name;
3289 }
3290
3291
3292 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3293 {
3294         return hdw->hdw_desc->description;
3295 }
3296
3297
3298 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3299 {
3300         return hdw->hdw_desc->shortname;
3301 }
3302
3303
3304 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3305 {
3306         int result;
3307         LOCK_TAKE(hdw->ctl_lock); do {
3308                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3309                 result = pvr2_send_request(hdw,
3310                                            hdw->cmd_buffer,1,
3311                                            hdw->cmd_buffer,1);
3312                 if (result < 0) break;
3313                 result = (hdw->cmd_buffer[0] != 0);
3314         } while(0); LOCK_GIVE(hdw->ctl_lock);
3315         return result;
3316 }
3317
3318
3319 /* Execute poll of tuner status */
3320 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3321 {
3322         LOCK_TAKE(hdw->big_lock); do {
3323                 pvr2_hdw_status_poll(hdw);
3324         } while (0); LOCK_GIVE(hdw->big_lock);
3325 }
3326
3327
3328 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3329 {
3330         if (!hdw->cropcap_stale) {
3331                 return 0;
3332         }
3333         pvr2_hdw_status_poll(hdw);
3334         if (hdw->cropcap_stale) {
3335                 return -EIO;
3336         }
3337         return 0;
3338 }
3339
3340
3341 /* Return information about cropping capabilities */
3342 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3343 {
3344         int stat = 0;
3345         LOCK_TAKE(hdw->big_lock);
3346         stat = pvr2_hdw_check_cropcap(hdw);
3347         if (!stat) {
3348                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3349         }
3350         LOCK_GIVE(hdw->big_lock);
3351         return stat;
3352 }
3353
3354
3355 /* Return information about the tuner */
3356 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3357 {
3358         LOCK_TAKE(hdw->big_lock); do {
3359                 if (hdw->tuner_signal_stale) {
3360                         pvr2_hdw_status_poll(hdw);
3361                 }
3362                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3363         } while (0); LOCK_GIVE(hdw->big_lock);
3364         return 0;
3365 }
3366
3367
3368 /* Get handle to video output stream */
3369 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3370 {
3371         return hp->vid_stream;
3372 }
3373
3374
3375 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3376 {
3377         int nr = pvr2_hdw_get_unit_number(hdw);
3378         LOCK_TAKE(hdw->big_lock); do {
3379                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3380                 hdw->log_requested = !0;
3381                 pvr2_i2c_core_check_stale(hdw);
3382                 pvr2_i2c_core_sync(hdw);
3383                 hdw->log_requested = 0;
3384                 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3385                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3386                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3387                 pvr2_hdw_state_log_state(hdw);
3388                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3389         } while (0); LOCK_GIVE(hdw->big_lock);
3390 }
3391
3392
3393 /* Grab EEPROM contents, needed for direct method. */
3394 #define EEPROM_SIZE 8192
3395 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3396 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3397 {
3398         struct i2c_msg msg[2];
3399         u8 *eeprom;
3400         u8 iadd[2];
3401         u8 addr;
3402         u16 eepromSize;
3403         unsigned int offs;
3404         int ret;
3405         int mode16 = 0;
3406         unsigned pcnt,tcnt;
3407         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3408         if (!eeprom) {
3409                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3410                            "Failed to allocate memory"
3411                            " required to read eeprom");
3412                 return NULL;
3413         }
3414
3415         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3416                      hdw->eeprom_addr);
3417         addr = hdw->eeprom_addr;
3418         /* Seems that if the high bit is set, then the *real* eeprom
3419            address is shifted right now bit position (noticed this in
3420            newer PVR USB2 hardware) */
3421         if (addr & 0x80) addr >>= 1;
3422
3423         /* FX2 documentation states that a 16bit-addressed eeprom is
3424            expected if the I2C address is an odd number (yeah, this is
3425            strange but it's what they do) */
3426         mode16 = (addr & 1);
3427         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3428         trace_eeprom("Examining %d byte eeprom at location 0x%x"
3429                      " using %d bit addressing",eepromSize,addr,
3430                      mode16 ? 16 : 8);
3431
3432         msg[0].addr = addr;
3433         msg[0].flags = 0;
3434         msg[0].len = mode16 ? 2 : 1;
3435         msg[0].buf = iadd;
3436         msg[1].addr = addr;
3437         msg[1].flags = I2C_M_RD;
3438
3439         /* We have to do the actual eeprom data fetch ourselves, because
3440            (1) we're only fetching part of the eeprom, and (2) if we were
3441            getting the whole thing our I2C driver can't grab it in one
3442            pass - which is what tveeprom is otherwise going to attempt */
3443         memset(eeprom,0,EEPROM_SIZE);
3444         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3445                 pcnt = 16;
3446                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3447                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3448                 if (mode16) {
3449                         iadd[0] = offs >> 8;
3450                         iadd[1] = offs;
3451                 } else {
3452                         iadd[0] = offs;
3453                 }
3454                 msg[1].len = pcnt;
3455                 msg[1].buf = eeprom+tcnt;
3456                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3457                                         msg,ARRAY_SIZE(msg))) != 2) {
3458                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3459                                    "eeprom fetch set offs err=%d",ret);
3460                         kfree(eeprom);
3461                         return NULL;
3462                 }
3463         }
3464         return eeprom;
3465 }
3466
3467
3468 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3469                                 int prom_flag,
3470                                 int enable_flag)
3471 {
3472         int ret;
3473         u16 address;
3474         unsigned int pipe;
3475         LOCK_TAKE(hdw->big_lock); do {
3476                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3477
3478                 if (!enable_flag) {
3479                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3480                                    "Cleaning up after CPU firmware fetch");
3481                         kfree(hdw->fw_buffer);
3482                         hdw->fw_buffer = NULL;
3483                         hdw->fw_size = 0;
3484                         if (hdw->fw_cpu_flag) {
3485                                 /* Now release the CPU.  It will disconnect
3486                                    and reconnect later. */
3487                                 pvr2_hdw_cpureset_assert(hdw,0);
3488                         }
3489                         break;
3490                 }
3491
3492                 hdw->fw_cpu_flag = (prom_flag == 0);
3493                 if (hdw->fw_cpu_flag) {
3494                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3495                                    "Preparing to suck out CPU firmware");
3496                         hdw->fw_size = 0x2000;
3497                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3498                         if (!hdw->fw_buffer) {
3499                                 hdw->fw_size = 0;
3500                                 break;
3501                         }
3502
3503                         /* We have to hold the CPU during firmware upload. */
3504                         pvr2_hdw_cpureset_assert(hdw,1);
3505
3506                         /* download the firmware from address 0000-1fff in 2048
3507                            (=0x800) bytes chunk. */
3508
3509                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3510                                    "Grabbing CPU firmware");
3511                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3512                         for(address = 0; address < hdw->fw_size;
3513                             address += 0x800) {
3514                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3515                                                       0xa0,0xc0,
3516                                                       address,0,
3517                                                       hdw->fw_buffer+address,
3518                                                       0x800,HZ);
3519                                 if (ret < 0) break;
3520                         }
3521
3522                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3523                                    "Done grabbing CPU firmware");
3524                 } else {
3525                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3526                                    "Sucking down EEPROM contents");
3527                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3528                         if (!hdw->fw_buffer) {
3529                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3530                                            "EEPROM content suck failed.");
3531                                 break;
3532                         }
3533                         hdw->fw_size = EEPROM_SIZE;
3534                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3535                                    "Done sucking down EEPROM contents");
3536                 }
3537
3538         } while (0); LOCK_GIVE(hdw->big_lock);
3539 }
3540
3541
3542 /* Return true if we're in a mode for retrieval CPU firmware */
3543 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3544 {
3545         return hdw->fw_buffer != NULL;
3546 }
3547
3548
3549 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3550                        char *buf,unsigned int cnt)
3551 {
3552         int ret = -EINVAL;
3553         LOCK_TAKE(hdw->big_lock); do {
3554                 if (!buf) break;
3555                 if (!cnt) break;
3556
3557                 if (!hdw->fw_buffer) {
3558                         ret = -EIO;
3559                         break;
3560                 }
3561
3562                 if (offs >= hdw->fw_size) {
3563                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3564                                    "Read firmware data offs=%d EOF",
3565                                    offs);
3566                         ret = 0;
3567                         break;
3568                 }
3569
3570                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3571
3572                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3573
3574                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3575                            "Read firmware data offs=%d cnt=%d",
3576                            offs,cnt);
3577                 ret = cnt;
3578         } while (0); LOCK_GIVE(hdw->big_lock);
3579
3580         return ret;
3581 }
3582
3583
3584 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3585                                   enum pvr2_v4l_type index)
3586 {
3587         switch (index) {
3588         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3589         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3590         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3591         default: return -1;
3592         }
3593 }
3594
3595
3596 /* Store a v4l minor device number */
3597 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3598                                      enum pvr2_v4l_type index,int v)
3599 {
3600         switch (index) {
3601         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3602         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3603         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
3604         default: break;
3605         }
3606 }
3607
3608
3609 static void pvr2_ctl_write_complete(struct urb *urb)
3610 {
3611         struct pvr2_hdw *hdw = urb->context;
3612         hdw->ctl_write_pend_flag = 0;
3613         if (hdw->ctl_read_pend_flag) return;
3614         complete(&hdw->ctl_done);
3615 }
3616
3617
3618 static void pvr2_ctl_read_complete(struct urb *urb)
3619 {
3620         struct pvr2_hdw *hdw = urb->context;
3621         hdw->ctl_read_pend_flag = 0;
3622         if (hdw->ctl_write_pend_flag) return;
3623         complete(&hdw->ctl_done);
3624 }
3625
3626
3627 static void pvr2_ctl_timeout(unsigned long data)
3628 {
3629         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3630         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3631                 hdw->ctl_timeout_flag = !0;
3632                 if (hdw->ctl_write_pend_flag)
3633                         usb_unlink_urb(hdw->ctl_write_urb);
3634                 if (hdw->ctl_read_pend_flag)
3635                         usb_unlink_urb(hdw->ctl_read_urb);
3636         }
3637 }
3638
3639
3640 /* Issue a command and get a response from the device.  This extended
3641    version includes a probe flag (which if set means that device errors
3642    should not be logged or treated as fatal) and a timeout in jiffies.
3643    This can be used to non-lethally probe the health of endpoint 1. */
3644 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3645                                 unsigned int timeout,int probe_fl,
3646                                 void *write_data,unsigned int write_len,
3647                                 void *read_data,unsigned int read_len)
3648 {
3649         unsigned int idx;
3650         int status = 0;
3651         struct timer_list timer;
3652         if (!hdw->ctl_lock_held) {
3653                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3654                            "Attempted to execute control transfer"
3655                            " without lock!!");
3656                 return -EDEADLK;
3657         }
3658         if (!hdw->flag_ok && !probe_fl) {
3659                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3660                            "Attempted to execute control transfer"
3661                            " when device not ok");
3662                 return -EIO;
3663         }
3664         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3665                 if (!probe_fl) {
3666                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3667                                    "Attempted to execute control transfer"
3668                                    " when USB is disconnected");
3669                 }
3670                 return -ENOTTY;
3671         }
3672
3673         /* Ensure that we have sane parameters */
3674         if (!write_data) write_len = 0;
3675         if (!read_data) read_len = 0;
3676         if (write_len > PVR2_CTL_BUFFSIZE) {
3677                 pvr2_trace(
3678                         PVR2_TRACE_ERROR_LEGS,
3679                         "Attempted to execute %d byte"
3680                         " control-write transfer (limit=%d)",
3681                         write_len,PVR2_CTL_BUFFSIZE);
3682                 return -EINVAL;
3683         }
3684         if (read_len > PVR2_CTL_BUFFSIZE) {
3685                 pvr2_trace(
3686                         PVR2_TRACE_ERROR_LEGS,
3687                         "Attempted to execute %d byte"
3688                         " control-read transfer (limit=%d)",
3689                         write_len,PVR2_CTL_BUFFSIZE);
3690                 return -EINVAL;
3691         }
3692         if ((!write_len) && (!read_len)) {
3693                 pvr2_trace(
3694                         PVR2_TRACE_ERROR_LEGS,
3695                         "Attempted to execute null control transfer?");
3696                 return -EINVAL;
3697         }
3698
3699
3700         hdw->cmd_debug_state = 1;
3701         if (write_len) {
3702                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3703         } else {
3704                 hdw->cmd_debug_code = 0;
3705         }
3706         hdw->cmd_debug_write_len = write_len;
3707         hdw->cmd_debug_read_len = read_len;
3708
3709         /* Initialize common stuff */
3710         init_completion(&hdw->ctl_done);
3711         hdw->ctl_timeout_flag = 0;
3712         hdw->ctl_write_pend_flag = 0;
3713         hdw->ctl_read_pend_flag = 0;
3714         init_timer(&timer);
3715         timer.expires = jiffies + timeout;
3716         timer.data = (unsigned long)hdw;
3717         timer.function = pvr2_ctl_timeout;
3718
3719         if (write_len) {
3720                 hdw->cmd_debug_state = 2;
3721                 /* Transfer write data to internal buffer */
3722                 for (idx = 0; idx < write_len; idx++) {
3723                         hdw->ctl_write_buffer[idx] =
3724                                 ((unsigned char *)write_data)[idx];
3725                 }
3726                 /* Initiate a write request */
3727                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3728                                   hdw->usb_dev,
3729                                   usb_sndbulkpipe(hdw->usb_dev,
3730                                                   PVR2_CTL_WRITE_ENDPOINT),
3731                                   hdw->ctl_write_buffer,
3732                                   write_len,
3733                                   pvr2_ctl_write_complete,
3734                                   hdw);
3735                 hdw->ctl_write_urb->actual_length = 0;
3736                 hdw->ctl_write_pend_flag = !0;
3737                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3738                 if (status < 0) {
3739                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3740                                    "Failed to submit write-control"
3741                                    " URB status=%d",status);
3742                         hdw->ctl_write_pend_flag = 0;
3743                         goto done;
3744                 }
3745         }
3746
3747         if (read_len) {
3748                 hdw->cmd_debug_state = 3;
3749                 memset(hdw->ctl_read_buffer,0x43,read_len);
3750                 /* Initiate a read request */
3751                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3752                                   hdw->usb_dev,
3753                                   usb_rcvbulkpipe(hdw->usb_dev,
3754                                                   PVR2_CTL_READ_ENDPOINT),
3755                                   hdw->ctl_read_buffer,
3756                                   read_len,
3757                                   pvr2_ctl_read_complete,
3758                                   hdw);
3759                 hdw->ctl_read_urb->actual_length = 0;
3760                 hdw->ctl_read_pend_flag = !0;
3761                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3762                 if (status < 0) {
3763                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3764                                    "Failed to submit read-control"
3765                                    " URB status=%d",status);
3766                         hdw->ctl_read_pend_flag = 0;
3767                         goto done;
3768                 }
3769         }
3770
3771         /* Start timer */
3772         add_timer(&timer);
3773
3774         /* Now wait for all I/O to complete */
3775         hdw->cmd_debug_state = 4;
3776         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3777                 wait_for_completion(&hdw->ctl_done);
3778         }
3779         hdw->cmd_debug_state = 5;
3780
3781         /* Stop timer */
3782         del_timer_sync(&timer);
3783
3784         hdw->cmd_debug_state = 6;
3785         status = 0;
3786
3787         if (hdw->ctl_timeout_flag) {
3788                 status = -ETIMEDOUT;
3789                 if (!probe_fl) {
3790                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3791                                    "Timed out control-write");
3792                 }
3793                 goto done;
3794         }
3795
3796         if (write_len) {
3797                 /* Validate results of write request */
3798                 if ((hdw->ctl_write_urb->status != 0) &&
3799                     (hdw->ctl_write_urb->status != -ENOENT) &&
3800                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3801                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3802                         /* USB subsystem is reporting some kind of failure
3803                            on the write */
3804                         status = hdw->ctl_write_urb->status;
3805                         if (!probe_fl) {
3806                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3807                                            "control-write URB failure,"
3808                                            " status=%d",
3809                                            status);
3810                         }
3811                         goto done;
3812                 }
3813                 if (hdw->ctl_write_urb->actual_length < write_len) {
3814                         /* Failed to write enough data */
3815                         status = -EIO;
3816                         if (!probe_fl) {
3817                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3818                                            "control-write URB short,"
3819                                            " expected=%d got=%d",
3820                                            write_len,
3821                                            hdw->ctl_write_urb->actual_length);
3822                         }
3823                         goto done;
3824                 }
3825         }
3826         if (read_len) {
3827                 /* Validate results of read request */
3828                 if ((hdw->ctl_read_urb->status != 0) &&
3829                     (hdw->ctl_read_urb->status != -ENOENT) &&
3830                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3831                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3832                         /* USB subsystem is reporting some kind of failure
3833                            on the read */
3834                         status = hdw->ctl_read_urb->status;
3835                         if (!probe_fl) {
3836                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3837                                            "control-read URB failure,"
3838                                            " status=%d",
3839                                            status);
3840                         }
3841                         goto done;
3842                 }
3843                 if (hdw->ctl_read_urb->actual_length < read_len) {
3844                         /* Failed to read enough data */
3845                         status = -EIO;
3846                         if (!probe_fl) {
3847                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3848                                            "control-read URB short,"
3849                                            " expected=%d got=%d",
3850                                            read_len,
3851                                            hdw->ctl_read_urb->actual_length);
3852                         }
3853                         goto done;
3854                 }
3855                 /* Transfer retrieved data out from internal buffer */
3856                 for (idx = 0; idx < read_len; idx++) {
3857                         ((unsigned char *)read_data)[idx] =
3858                                 hdw->ctl_read_buffer[idx];
3859                 }
3860         }
3861
3862  done:
3863
3864         hdw->cmd_debug_state = 0;
3865         if ((status < 0) && (!probe_fl)) {
3866                 pvr2_hdw_render_useless(hdw);
3867         }
3868         return status;
3869 }
3870
3871
3872 int pvr2_send_request(struct pvr2_hdw *hdw,
3873                       void *write_data,unsigned int write_len,
3874                       void *read_data,unsigned int read_len)
3875 {
3876         return pvr2_send_request_ex(hdw,HZ*4,0,
3877                                     write_data,write_len,
3878                                     read_data,read_len);
3879 }
3880
3881
3882 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3883 {
3884         int ret;
3885         unsigned int cnt = 1;
3886         unsigned int args = 0;
3887         LOCK_TAKE(hdw->ctl_lock);
3888         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3889         args = (cmdcode >> 8) & 0xffu;
3890         args = (args > 2) ? 2 : args;
3891         if (args) {
3892                 cnt += args;
3893                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3894                 if (args > 1) {
3895                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3896                 }
3897         }
3898         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3899                 unsigned int idx;
3900                 unsigned int ccnt,bcnt;
3901                 char tbuf[50];
3902                 cmdcode &= 0xffu;
3903                 bcnt = 0;
3904                 ccnt = scnprintf(tbuf+bcnt,
3905                                  sizeof(tbuf)-bcnt,
3906                                  "Sending FX2 command 0x%x",cmdcode);
3907                 bcnt += ccnt;
3908                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3909                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3910                                 ccnt = scnprintf(tbuf+bcnt,
3911                                                  sizeof(tbuf)-bcnt,
3912                                                  " \"%s\"",
3913                                                  pvr2_fx2cmd_desc[idx].desc);
3914                                 bcnt += ccnt;
3915                                 break;
3916                         }
3917                 }
3918                 if (args) {
3919                         ccnt = scnprintf(tbuf+bcnt,
3920                                          sizeof(tbuf)-bcnt,
3921                                          " (%u",hdw->cmd_buffer[1]);
3922                         bcnt += ccnt;
3923                         if (args > 1) {
3924                                 ccnt = scnprintf(tbuf+bcnt,
3925                                                  sizeof(tbuf)-bcnt,
3926                                                  ",%u",hdw->cmd_buffer[2]);
3927                                 bcnt += ccnt;
3928                         }
3929                         ccnt = scnprintf(tbuf+bcnt,
3930                                          sizeof(tbuf)-bcnt,
3931                                          ")");
3932                         bcnt += ccnt;
3933                 }
3934                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3935         }
3936         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3937         LOCK_GIVE(hdw->ctl_lock);
3938         return ret;
3939 }
3940
3941
3942 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3943 {
3944         int ret;
3945
3946         LOCK_TAKE(hdw->ctl_lock);
3947
3948         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3949         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3950         hdw->cmd_buffer[5] = 0;
3951         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3952         hdw->cmd_buffer[7] = reg & 0xff;
3953
3954
3955         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3956
3957         LOCK_GIVE(hdw->ctl_lock);
3958
3959         return ret;
3960 }
3961
3962
3963 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3964 {
3965         int ret = 0;
3966
3967         LOCK_TAKE(hdw->ctl_lock);
3968
3969         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3970         hdw->cmd_buffer[1] = 0;
3971         hdw->cmd_buffer[2] = 0;
3972         hdw->cmd_buffer[3] = 0;
3973         hdw->cmd_buffer[4] = 0;
3974         hdw->cmd_buffer[5] = 0;
3975         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3976         hdw->cmd_buffer[7] = reg & 0xff;
3977
3978         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3979         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3980
3981         LOCK_GIVE(hdw->ctl_lock);
3982
3983         return ret;
3984 }
3985
3986
3987 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3988 {
3989         if (!hdw->flag_ok) return;
3990         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3991                    "Device being rendered inoperable");
3992         if (hdw->vid_stream) {
3993                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3994         }
3995         hdw->flag_ok = 0;
3996         trace_stbit("flag_ok",hdw->flag_ok);
3997         pvr2_hdw_state_sched(hdw);
3998 }
3999
4000
4001 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4002 {
4003         int ret;
4004         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
4005         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
4006         if (ret == 0) {
4007                 ret = usb_reset_device(hdw->usb_dev);
4008                 usb_unlock_device(hdw->usb_dev);
4009         } else {
4010                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4011                            "Failed to lock USB device ret=%d",ret);
4012         }
4013         if (init_pause_msec) {
4014                 pvr2_trace(PVR2_TRACE_INFO,
4015                            "Waiting %u msec for hardware to settle",
4016                            init_pause_msec);
4017                 msleep(init_pause_msec);
4018         }
4019
4020 }
4021
4022
4023 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4024 {
4025         char da[1];
4026         unsigned int pipe;
4027         int ret;
4028
4029         if (!hdw->usb_dev) return;
4030
4031         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4032
4033         da[0] = val ? 0x01 : 0x00;
4034
4035         /* Write the CPUCS register on the 8051.  The lsb of the register
4036            is the reset bit; a 1 asserts reset while a 0 clears it. */
4037         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4038         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4039         if (ret < 0) {
4040                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4041                            "cpureset_assert(%d) error=%d",val,ret);
4042                 pvr2_hdw_render_useless(hdw);
4043         }
4044 }
4045
4046
4047 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4048 {
4049         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
4050 }
4051
4052
4053 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4054 {
4055         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4056 }
4057
4058
4059 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4060 {
4061         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
4062 }
4063
4064
4065 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4066 {
4067         pvr2_trace(PVR2_TRACE_INIT,
4068                    "Requesting decoder reset");
4069         if (hdw->decoder_ctrl) {
4070                 if (!hdw->decoder_ctrl->force_reset) {
4071                         pvr2_trace(PVR2_TRACE_INIT,
4072                                    "Unable to reset decoder: not implemented");
4073                         return -ENOTTY;
4074                 }
4075                 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
4076                 return 0;
4077         } else {
4078         }
4079         if (hdw->decoder_client_id) {
4080                 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4081                                      core, reset, 0);
4082                 return 0;
4083         }
4084         pvr2_trace(PVR2_TRACE_INIT,
4085                    "Unable to reset decoder: nothing attached");
4086         return -ENOTTY;
4087 }
4088
4089
4090 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4091 {
4092         hdw->flag_ok = !0;
4093         return pvr2_issue_simple_cmd(hdw,
4094                                      FX2CMD_HCW_DEMOD_RESETIN |
4095                                      (1 << 8) |
4096                                      ((onoff ? 1 : 0) << 16));
4097 }
4098
4099
4100 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4101 {
4102         hdw->flag_ok = !0;
4103         return pvr2_issue_simple_cmd(hdw,(onoff ?
4104                                           FX2CMD_ONAIR_DTV_POWER_ON :
4105                                           FX2CMD_ONAIR_DTV_POWER_OFF));
4106 }
4107
4108
4109 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4110                                                 int onoff)
4111 {
4112         return pvr2_issue_simple_cmd(hdw,(onoff ?
4113                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
4114                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
4115 }
4116
4117
4118 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4119 {
4120         int cmode;
4121         /* Compare digital/analog desired setting with current setting.  If
4122            they don't match, fix it... */
4123         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4124         if (cmode == hdw->pathway_state) {
4125                 /* They match; nothing to do */
4126                 return;
4127         }
4128
4129         switch (hdw->hdw_desc->digital_control_scheme) {
4130         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4131                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4132                 if (cmode == PVR2_PATHWAY_ANALOG) {
4133                         /* If moving to analog mode, also force the decoder
4134                            to reset.  If no decoder is attached, then it's
4135                            ok to ignore this because if/when the decoder
4136                            attaches, it will reset itself at that time. */
4137                         pvr2_hdw_cmd_decoder_reset(hdw);
4138                 }
4139                 break;
4140         case PVR2_DIGITAL_SCHEME_ONAIR:
4141                 /* Supposedly we should always have the power on whether in
4142                    digital or analog mode.  But for now do what appears to
4143                    work... */
4144                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4145                 break;
4146         default: break;
4147         }
4148
4149         pvr2_hdw_untrip_unlocked(hdw);
4150         hdw->pathway_state = cmode;
4151 }
4152
4153
4154 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4155 {
4156         /* change some GPIO data
4157          *
4158          * note: bit d7 of dir appears to control the LED,
4159          * so we shut it off here.
4160          *
4161          */
4162         if (onoff) {
4163                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4164         } else {
4165                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4166         }
4167         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4168 }
4169
4170
4171 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4172
4173 static led_method_func led_methods[] = {
4174         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4175 };
4176
4177
4178 /* Toggle LED */
4179 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4180 {
4181         unsigned int scheme_id;
4182         led_method_func fp;
4183
4184         if ((!onoff) == (!hdw->led_on)) return;
4185
4186         hdw->led_on = onoff != 0;
4187
4188         scheme_id = hdw->hdw_desc->led_scheme;
4189         if (scheme_id < ARRAY_SIZE(led_methods)) {
4190                 fp = led_methods[scheme_id];
4191         } else {
4192                 fp = NULL;
4193         }
4194
4195         if (fp) (*fp)(hdw,onoff);
4196 }
4197
4198
4199 /* Stop / start video stream transport */
4200 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4201 {
4202         int ret;
4203
4204         /* If we're in analog mode, then just issue the usual analog
4205            command. */
4206         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4207                 return pvr2_issue_simple_cmd(hdw,
4208                                              (runFl ?
4209                                               FX2CMD_STREAMING_ON :
4210                                               FX2CMD_STREAMING_OFF));
4211                 /*Note: Not reached */
4212         }
4213
4214         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4215                 /* Whoops, we don't know what mode we're in... */
4216                 return -EINVAL;
4217         }
4218
4219         /* To get here we have to be in digital mode.  The mechanism here
4220            is unfortunately different for different vendors.  So we switch
4221            on the device's digital scheme attribute in order to figure out
4222            what to do. */
4223         switch (hdw->hdw_desc->digital_control_scheme) {
4224         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4225                 return pvr2_issue_simple_cmd(hdw,
4226                                              (runFl ?
4227                                               FX2CMD_HCW_DTV_STREAMING_ON :
4228                                               FX2CMD_HCW_DTV_STREAMING_OFF));
4229         case PVR2_DIGITAL_SCHEME_ONAIR:
4230                 ret = pvr2_issue_simple_cmd(hdw,
4231                                             (runFl ?
4232                                              FX2CMD_STREAMING_ON :
4233                                              FX2CMD_STREAMING_OFF));
4234                 if (ret) return ret;
4235                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4236         default:
4237                 return -EINVAL;
4238         }
4239 }
4240
4241
4242 /* Evaluate whether or not state_pathway_ok can change */
4243 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4244 {
4245         if (hdw->state_pathway_ok) {
4246                 /* Nothing to do if pathway is already ok */
4247                 return 0;
4248         }
4249         if (!hdw->state_pipeline_idle) {
4250                 /* Not allowed to change anything if pipeline is not idle */
4251                 return 0;
4252         }
4253         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4254         hdw->state_pathway_ok = !0;
4255         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4256         return !0;
4257 }
4258
4259
4260 /* Evaluate whether or not state_encoder_ok can change */
4261 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4262 {
4263         if (hdw->state_encoder_ok) return 0;
4264         if (hdw->flag_tripped) return 0;
4265         if (hdw->state_encoder_run) return 0;
4266         if (hdw->state_encoder_config) return 0;
4267         if (hdw->state_decoder_run) return 0;
4268         if (hdw->state_usbstream_run) return 0;
4269         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4270                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4271         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4272                 return 0;
4273         }
4274
4275         if (pvr2_upload_firmware2(hdw) < 0) {
4276                 hdw->flag_tripped = !0;
4277                 trace_stbit("flag_tripped",hdw->flag_tripped);
4278                 return !0;
4279         }
4280         hdw->state_encoder_ok = !0;
4281         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4282         return !0;
4283 }
4284
4285
4286 /* Evaluate whether or not state_encoder_config can change */
4287 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4288 {
4289         if (hdw->state_encoder_config) {
4290                 if (hdw->state_encoder_ok) {
4291                         if (hdw->state_pipeline_req &&
4292                             !hdw->state_pipeline_pause) return 0;
4293                 }
4294                 hdw->state_encoder_config = 0;
4295                 hdw->state_encoder_waitok = 0;
4296                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4297                 /* paranoia - solve race if timer just completed */
4298                 del_timer_sync(&hdw->encoder_wait_timer);
4299         } else {
4300                 if (!hdw->state_pathway_ok ||
4301                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4302                     !hdw->state_encoder_ok ||
4303                     !hdw->state_pipeline_idle ||
4304                     hdw->state_pipeline_pause ||
4305                     !hdw->state_pipeline_req ||
4306                     !hdw->state_pipeline_config) {
4307                         /* We must reset the enforced wait interval if
4308                            anything has happened that might have disturbed
4309                            the encoder.  This should be a rare case. */
4310                         if (timer_pending(&hdw->encoder_wait_timer)) {
4311                                 del_timer_sync(&hdw->encoder_wait_timer);
4312                         }
4313                         if (hdw->state_encoder_waitok) {
4314                                 /* Must clear the state - therefore we did
4315                                    something to a state bit and must also
4316                                    return true. */
4317                                 hdw->state_encoder_waitok = 0;
4318                                 trace_stbit("state_encoder_waitok",
4319                                             hdw->state_encoder_waitok);
4320                                 return !0;
4321                         }
4322                         return 0;
4323                 }
4324                 if (!hdw->state_encoder_waitok) {
4325                         if (!timer_pending(&hdw->encoder_wait_timer)) {
4326                                 /* waitok flag wasn't set and timer isn't
4327                                    running.  Check flag once more to avoid
4328                                    a race then start the timer.  This is
4329                                    the point when we measure out a minimal
4330                                    quiet interval before doing something to
4331                                    the encoder. */
4332                                 if (!hdw->state_encoder_waitok) {
4333                                         hdw->encoder_wait_timer.expires =
4334                                                 jiffies +
4335                                                 (HZ * TIME_MSEC_ENCODER_WAIT
4336                                                  / 1000);
4337                                         add_timer(&hdw->encoder_wait_timer);
4338                                 }
4339                         }
4340                         /* We can't continue until we know we have been
4341                            quiet for the interval measured by this
4342                            timer. */
4343                         return 0;
4344                 }
4345                 pvr2_encoder_configure(hdw);
4346                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4347         }
4348         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4349         return !0;
4350 }
4351
4352
4353 /* Return true if the encoder should not be running. */
4354 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4355 {
4356         if (!hdw->state_encoder_ok) {
4357                 /* Encoder isn't healthy at the moment, so stop it. */
4358                 return !0;
4359         }
4360         if (!hdw->state_pathway_ok) {
4361                 /* Mode is not understood at the moment (i.e. it wants to
4362                    change), so encoder must be stopped. */
4363                 return !0;
4364         }
4365
4366         switch (hdw->pathway_state) {
4367         case PVR2_PATHWAY_ANALOG:
4368                 if (!hdw->state_decoder_run) {
4369                         /* We're in analog mode and the decoder is not
4370                            running; thus the encoder should be stopped as
4371                            well. */
4372                         return !0;
4373                 }
4374                 break;
4375         case PVR2_PATHWAY_DIGITAL:
4376                 if (hdw->state_encoder_runok) {
4377                         /* This is a funny case.  We're in digital mode so
4378                            really the encoder should be stopped.  However
4379                            if it really is running, only kill it after
4380                            runok has been set.  This gives a chance for the
4381                            onair quirk to function (encoder must run
4382                            briefly first, at least once, before onair
4383                            digital streaming can work). */
4384                         return !0;
4385                 }
4386                 break;
4387         default:
4388                 /* Unknown mode; so encoder should be stopped. */
4389                 return !0;
4390         }
4391
4392         /* If we get here, we haven't found a reason to stop the
4393            encoder. */
4394         return 0;
4395 }
4396
4397
4398 /* Return true if the encoder should be running. */
4399 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4400 {
4401         if (!hdw->state_encoder_ok) {
4402                 /* Don't run the encoder if it isn't healthy... */
4403                 return 0;
4404         }
4405         if (!hdw->state_pathway_ok) {
4406                 /* Don't run the encoder if we don't (yet) know what mode
4407                    we need to be in... */
4408                 return 0;
4409         }
4410
4411         switch (hdw->pathway_state) {
4412         case PVR2_PATHWAY_ANALOG:
4413                 if (hdw->state_decoder_run) {
4414                         /* In analog mode, if the decoder is running, then
4415                            run the encoder. */
4416                         return !0;
4417                 }
4418                 break;
4419         case PVR2_PATHWAY_DIGITAL:
4420                 if ((hdw->hdw_desc->digital_control_scheme ==
4421                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4422                     !hdw->state_encoder_runok) {
4423                         /* This is a quirk.  OnAir hardware won't stream
4424                            digital until the encoder has been run at least
4425                            once, for a minimal period of time (empiricially
4426                            measured to be 1/4 second).  So if we're on
4427                            OnAir hardware and the encoder has never been
4428                            run at all, then start the encoder.  Normal
4429                            state machine logic in the driver will
4430                            automatically handle the remaining bits. */
4431                         return !0;
4432                 }
4433                 break;
4434         default:
4435                 /* For completeness (unknown mode; encoder won't run ever) */
4436                 break;
4437         }
4438         /* If we get here, then we haven't found any reason to run the
4439            encoder, so don't run it. */
4440         return 0;
4441 }
4442
4443
4444 /* Evaluate whether or not state_encoder_run can change */
4445 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4446 {
4447         if (hdw->state_encoder_run) {
4448                 if (!state_check_disable_encoder_run(hdw)) return 0;
4449                 if (hdw->state_encoder_ok) {
4450                         del_timer_sync(&hdw->encoder_run_timer);
4451                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4452                 }
4453                 hdw->state_encoder_run = 0;
4454         } else {
4455                 if (!state_check_enable_encoder_run(hdw)) return 0;
4456                 if (pvr2_encoder_start(hdw) < 0) return !0;
4457                 hdw->state_encoder_run = !0;
4458                 if (!hdw->state_encoder_runok) {
4459                         hdw->encoder_run_timer.expires =
4460                                 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4461                         add_timer(&hdw->encoder_run_timer);
4462                 }
4463         }
4464         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4465         return !0;
4466 }
4467
4468
4469 /* Timeout function for quiescent timer. */
4470 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4471 {
4472         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4473         hdw->state_decoder_quiescent = !0;
4474         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4475         hdw->state_stale = !0;
4476         queue_work(hdw->workqueue,&hdw->workpoll);
4477 }
4478
4479
4480 /* Timeout function for encoder wait timer. */
4481 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4482 {
4483         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4484         hdw->state_encoder_waitok = !0;
4485         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4486         hdw->state_stale = !0;
4487         queue_work(hdw->workqueue,&hdw->workpoll);
4488 }
4489
4490
4491 /* Timeout function for encoder run timer. */
4492 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4493 {
4494         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4495         if (!hdw->state_encoder_runok) {
4496                 hdw->state_encoder_runok = !0;
4497                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4498                 hdw->state_stale = !0;
4499                 queue_work(hdw->workqueue,&hdw->workpoll);
4500         }
4501 }
4502
4503
4504 /* Evaluate whether or not state_decoder_run can change */
4505 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4506 {
4507         if (hdw->state_decoder_run) {
4508                 if (hdw->state_encoder_ok) {
4509                         if (hdw->state_pipeline_req &&
4510                             !hdw->state_pipeline_pause &&
4511                             hdw->state_pathway_ok) return 0;
4512                 }
4513                 if (!hdw->flag_decoder_missed) {
4514                         pvr2_decoder_enable(hdw,0);
4515                 }
4516                 hdw->state_decoder_quiescent = 0;
4517                 hdw->state_decoder_run = 0;
4518                 /* paranoia - solve race if timer just completed */
4519                 del_timer_sync(&hdw->quiescent_timer);
4520         } else {
4521                 if (!hdw->state_decoder_quiescent) {
4522                         if (!timer_pending(&hdw->quiescent_timer)) {
4523                                 /* We don't do something about the
4524                                    quiescent timer until right here because
4525                                    we also want to catch cases where the
4526                                    decoder was already not running (like
4527                                    after initialization) as opposed to
4528                                    knowing that we had just stopped it.
4529                                    The second flag check is here to cover a
4530                                    race - the timer could have run and set
4531                                    this flag just after the previous check
4532                                    but before we did the pending check. */
4533                                 if (!hdw->state_decoder_quiescent) {
4534                                         hdw->quiescent_timer.expires =
4535                                                 jiffies +
4536                                                 (HZ * TIME_MSEC_DECODER_WAIT
4537                                                  / 1000);
4538                                         add_timer(&hdw->quiescent_timer);
4539                                 }
4540                         }
4541                         /* Don't allow decoder to start again until it has
4542                            been quiesced first.  This little detail should
4543                            hopefully further stabilize the encoder. */
4544                         return 0;
4545                 }
4546                 if (!hdw->state_pathway_ok ||
4547                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4548                     !hdw->state_pipeline_req ||
4549                     hdw->state_pipeline_pause ||
4550                     !hdw->state_pipeline_config ||
4551                     !hdw->state_encoder_config ||
4552                     !hdw->state_encoder_ok) return 0;
4553                 del_timer_sync(&hdw->quiescent_timer);
4554                 if (hdw->flag_decoder_missed) return 0;
4555                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4556                 hdw->state_decoder_quiescent = 0;
4557                 hdw->state_decoder_run = !0;
4558         }
4559         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4560         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4561         return !0;
4562 }
4563
4564
4565 /* Evaluate whether or not state_usbstream_run can change */
4566 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4567 {
4568         if (hdw->state_usbstream_run) {
4569                 int fl = !0;
4570                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4571                         fl = (hdw->state_encoder_ok &&
4572                               hdw->state_encoder_run);
4573                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4574                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4575                         fl = hdw->state_encoder_ok;
4576                 }
4577                 if (fl &&
4578                     hdw->state_pipeline_req &&
4579                     !hdw->state_pipeline_pause &&
4580                     hdw->state_pathway_ok) {
4581                         return 0;
4582                 }
4583                 pvr2_hdw_cmd_usbstream(hdw,0);
4584                 hdw->state_usbstream_run = 0;
4585         } else {
4586                 if (!hdw->state_pipeline_req ||
4587                     hdw->state_pipeline_pause ||
4588                     !hdw->state_pathway_ok) return 0;
4589                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4590                         if (!hdw->state_encoder_ok ||
4591                             !hdw->state_encoder_run) return 0;
4592                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4593                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4594                         if (!hdw->state_encoder_ok) return 0;
4595                         if (hdw->state_encoder_run) return 0;
4596                         if (hdw->hdw_desc->digital_control_scheme ==
4597                             PVR2_DIGITAL_SCHEME_ONAIR) {
4598                                 /* OnAir digital receivers won't stream
4599                                    unless the analog encoder has run first.
4600                                    Why?  I have no idea.  But don't even
4601                                    try until we know the analog side is
4602                                    known to have run. */
4603                                 if (!hdw->state_encoder_runok) return 0;
4604                         }
4605                 }
4606                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4607                 hdw->state_usbstream_run = !0;
4608         }
4609         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4610         return !0;
4611 }
4612
4613
4614 /* Attempt to configure pipeline, if needed */
4615 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4616 {
4617         if (hdw->state_pipeline_config ||
4618             hdw->state_pipeline_pause) return 0;
4619         pvr2_hdw_commit_execute(hdw);
4620         return !0;
4621 }
4622
4623
4624 /* Update pipeline idle and pipeline pause tracking states based on other
4625    inputs.  This must be called whenever the other relevant inputs have
4626    changed. */
4627 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4628 {
4629         unsigned int st;
4630         int updatedFl = 0;
4631         /* Update pipeline state */
4632         st = !(hdw->state_encoder_run ||
4633                hdw->state_decoder_run ||
4634                hdw->state_usbstream_run ||
4635                (!hdw->state_decoder_quiescent));
4636         if (!st != !hdw->state_pipeline_idle) {
4637                 hdw->state_pipeline_idle = st;
4638                 updatedFl = !0;
4639         }
4640         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4641                 hdw->state_pipeline_pause = 0;
4642                 updatedFl = !0;
4643         }
4644         return updatedFl;
4645 }
4646
4647
4648 typedef int (*state_eval_func)(struct pvr2_hdw *);
4649
4650 /* Set of functions to be run to evaluate various states in the driver. */
4651 static const state_eval_func eval_funcs[] = {
4652         state_eval_pathway_ok,
4653         state_eval_pipeline_config,
4654         state_eval_encoder_ok,
4655         state_eval_encoder_config,
4656         state_eval_decoder_run,
4657         state_eval_encoder_run,
4658         state_eval_usbstream_run,
4659 };
4660
4661
4662 /* Process various states and return true if we did anything interesting. */
4663 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4664 {
4665         unsigned int i;
4666         int state_updated = 0;
4667         int check_flag;
4668
4669         if (!hdw->state_stale) return 0;
4670         if ((hdw->fw1_state != FW1_STATE_OK) ||
4671             !hdw->flag_ok) {
4672                 hdw->state_stale = 0;
4673                 return !0;
4674         }
4675         /* This loop is the heart of the entire driver.  It keeps trying to
4676            evaluate various bits of driver state until nothing changes for
4677            one full iteration.  Each "bit of state" tracks some global
4678            aspect of the driver, e.g. whether decoder should run, if
4679            pipeline is configured, usb streaming is on, etc.  We separately
4680            evaluate each of those questions based on other driver state to
4681            arrive at the correct running configuration. */
4682         do {
4683                 check_flag = 0;
4684                 state_update_pipeline_state(hdw);
4685                 /* Iterate over each bit of state */
4686                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4687                         if ((*eval_funcs[i])(hdw)) {
4688                                 check_flag = !0;
4689                                 state_updated = !0;
4690                                 state_update_pipeline_state(hdw);
4691                         }
4692                 }
4693         } while (check_flag && hdw->flag_ok);
4694         hdw->state_stale = 0;
4695         trace_stbit("state_stale",hdw->state_stale);
4696         return state_updated;
4697 }
4698
4699
4700 static unsigned int print_input_mask(unsigned int msk,
4701                                      char *buf,unsigned int acnt)
4702 {
4703         unsigned int idx,ccnt;
4704         unsigned int tcnt = 0;
4705         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4706                 if (!((1 << idx) & msk)) continue;
4707                 ccnt = scnprintf(buf+tcnt,
4708                                  acnt-tcnt,
4709                                  "%s%s",
4710                                  (tcnt ? ", " : ""),
4711                                  control_values_input[idx]);
4712                 tcnt += ccnt;
4713         }
4714         return tcnt;
4715 }
4716
4717
4718 static const char *pvr2_pathway_state_name(int id)
4719 {
4720         switch (id) {
4721         case PVR2_PATHWAY_ANALOG: return "analog";
4722         case PVR2_PATHWAY_DIGITAL: return "digital";
4723         default: return "unknown";
4724         }
4725 }
4726
4727
4728 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4729                                              char *buf,unsigned int acnt)
4730 {
4731         switch (which) {
4732         case 0:
4733                 return scnprintf(
4734                         buf,acnt,
4735                         "driver:%s%s%s%s%s <mode=%s>",
4736                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4737                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4738                         (hdw->flag_disconnected ? " <disconnected>" :
4739                          " <connected>"),
4740                         (hdw->flag_tripped ? " <tripped>" : ""),
4741                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4742                         pvr2_pathway_state_name(hdw->pathway_state));
4743
4744         case 1:
4745                 return scnprintf(
4746                         buf,acnt,
4747                         "pipeline:%s%s%s%s",
4748                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4749                         (hdw->state_pipeline_config ?
4750                          " <configok>" : " <stale>"),
4751                         (hdw->state_pipeline_req ? " <req>" : ""),
4752                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4753         case 2:
4754                 return scnprintf(
4755                         buf,acnt,
4756                         "worker:%s%s%s%s%s%s%s",
4757                         (hdw->state_decoder_run ?
4758                          " <decode:run>" :
4759                          (hdw->state_decoder_quiescent ?
4760                           "" : " <decode:stop>")),
4761                         (hdw->state_decoder_quiescent ?
4762                          " <decode:quiescent>" : ""),
4763                         (hdw->state_encoder_ok ?
4764                          "" : " <encode:init>"),
4765                         (hdw->state_encoder_run ?
4766                          (hdw->state_encoder_runok ?
4767                           " <encode:run>" :
4768                           " <encode:firstrun>") :
4769                          (hdw->state_encoder_runok ?
4770                           " <encode:stop>" :
4771                           " <encode:virgin>")),
4772                         (hdw->state_encoder_config ?
4773                          " <encode:configok>" :
4774                          (hdw->state_encoder_waitok ?
4775                           "" : " <encode:waitok>")),
4776                         (hdw->state_usbstream_run ?
4777                          " <usb:run>" : " <usb:stop>"),
4778                         (hdw->state_pathway_ok ?
4779                          " <pathway:ok>" : ""));
4780         case 3:
4781                 return scnprintf(
4782                         buf,acnt,
4783                         "state: %s",
4784                         pvr2_get_state_name(hdw->master_state));
4785         case 4: {
4786                 unsigned int tcnt = 0;
4787                 unsigned int ccnt;
4788
4789                 ccnt = scnprintf(buf,
4790                                  acnt,
4791                                  "Hardware supported inputs: ");
4792                 tcnt += ccnt;
4793                 tcnt += print_input_mask(hdw->input_avail_mask,
4794                                          buf+tcnt,
4795                                          acnt-tcnt);
4796                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4797                         ccnt = scnprintf(buf+tcnt,
4798                                          acnt-tcnt,
4799                                          "; allowed inputs: ");
4800                         tcnt += ccnt;
4801                         tcnt += print_input_mask(hdw->input_allowed_mask,
4802                                                  buf+tcnt,
4803                                                  acnt-tcnt);
4804                 }
4805                 return tcnt;
4806         }
4807         case 5: {
4808                 struct pvr2_stream_stats stats;
4809                 if (!hdw->vid_stream) break;
4810                 pvr2_stream_get_stats(hdw->vid_stream,
4811                                       &stats,
4812                                       0);
4813                 return scnprintf(
4814                         buf,acnt,
4815                         "Bytes streamed=%u"
4816                         " URBs: queued=%u idle=%u ready=%u"
4817                         " processed=%u failed=%u",
4818                         stats.bytes_processed,
4819                         stats.buffers_in_queue,
4820                         stats.buffers_in_idle,
4821                         stats.buffers_in_ready,
4822                         stats.buffers_processed,
4823                         stats.buffers_failed);
4824         }
4825         case 6: {
4826                 struct v4l2_subdev *sd;
4827                 unsigned int tcnt = 0;
4828                 unsigned int ccnt;
4829                 const char *p;
4830                 unsigned int id;
4831                 ccnt = scnprintf(buf,
4832                                  acnt,
4833                                  "Associted v4l2_subdev drivers:");
4834                 tcnt += ccnt;
4835                 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4836                         id = sd->grp_id;
4837                         p = NULL;
4838                         if (id < ARRAY_SIZE(module_names)) {
4839                                 p = module_names[id];
4840                         }
4841                         if (!p) p = "(unknown)";
4842                         ccnt = scnprintf(buf + tcnt,
4843                                          acnt - tcnt,
4844                                          " %s (%u)", p, id);
4845                 }
4846                 return tcnt;
4847         }
4848         default: break;
4849         }
4850         return 0;
4851 }
4852
4853
4854 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4855                                    char *buf,unsigned int acnt)
4856 {
4857         unsigned int bcnt,ccnt,idx;
4858         bcnt = 0;
4859         LOCK_TAKE(hdw->big_lock);
4860         for (idx = 0; ; idx++) {
4861                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4862                 if (!ccnt) break;
4863                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4864                 if (!acnt) break;
4865                 buf[0] = '\n'; ccnt = 1;
4866                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4867         }
4868         LOCK_GIVE(hdw->big_lock);
4869         return bcnt;
4870 }
4871
4872
4873 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4874 {
4875         char buf[128];
4876         unsigned int idx,ccnt;
4877
4878         for (idx = 0; ; idx++) {
4879                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4880                 if (!ccnt) break;
4881                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4882         }
4883 }
4884
4885
4886 /* Evaluate and update the driver's current state, taking various actions
4887    as appropriate for the update. */
4888 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4889 {
4890         unsigned int st;
4891         int state_updated = 0;
4892         int callback_flag = 0;
4893         int analog_mode;
4894
4895         pvr2_trace(PVR2_TRACE_STBITS,
4896                    "Drive state check START");
4897         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4898                 pvr2_hdw_state_log_state(hdw);
4899         }
4900
4901         /* Process all state and get back over disposition */
4902         state_updated = pvr2_hdw_state_update(hdw);
4903
4904         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4905
4906         /* Update master state based upon all other states. */
4907         if (!hdw->flag_ok) {
4908                 st = PVR2_STATE_DEAD;
4909         } else if (hdw->fw1_state != FW1_STATE_OK) {
4910                 st = PVR2_STATE_COLD;
4911         } else if ((analog_mode ||
4912                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4913                    !hdw->state_encoder_ok) {
4914                 st = PVR2_STATE_WARM;
4915         } else if (hdw->flag_tripped ||
4916                    (analog_mode && hdw->flag_decoder_missed)) {
4917                 st = PVR2_STATE_ERROR;
4918         } else if (hdw->state_usbstream_run &&
4919                    (!analog_mode ||
4920                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4921                 st = PVR2_STATE_RUN;
4922         } else {
4923                 st = PVR2_STATE_READY;
4924         }
4925         if (hdw->master_state != st) {
4926                 pvr2_trace(PVR2_TRACE_STATE,
4927                            "Device state change from %s to %s",
4928                            pvr2_get_state_name(hdw->master_state),
4929                            pvr2_get_state_name(st));
4930                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4931                 hdw->master_state = st;
4932                 state_updated = !0;
4933                 callback_flag = !0;
4934         }
4935         if (state_updated) {
4936                 /* Trigger anyone waiting on any state changes here. */
4937                 wake_up(&hdw->state_wait_data);
4938         }
4939
4940         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4941                 pvr2_hdw_state_log_state(hdw);
4942         }
4943         pvr2_trace(PVR2_TRACE_STBITS,
4944                    "Drive state check DONE callback=%d",callback_flag);
4945
4946         return callback_flag;
4947 }
4948
4949
4950 /* Cause kernel thread to check / update driver state */
4951 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4952 {
4953         if (hdw->state_stale) return;
4954         hdw->state_stale = !0;
4955         trace_stbit("state_stale",hdw->state_stale);
4956         queue_work(hdw->workqueue,&hdw->workpoll);
4957 }
4958
4959
4960 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4961 {
4962         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4963 }
4964
4965
4966 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4967 {
4968         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4969 }
4970
4971
4972 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4973 {
4974         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4975 }
4976
4977
4978 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4979 {
4980         u32 cval,nval;
4981         int ret;
4982         if (~msk) {
4983                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4984                 if (ret) return ret;
4985                 nval = (cval & ~msk) | (val & msk);
4986                 pvr2_trace(PVR2_TRACE_GPIO,
4987                            "GPIO direction changing 0x%x:0x%x"
4988                            " from 0x%x to 0x%x",
4989                            msk,val,cval,nval);
4990         } else {
4991                 nval = val;
4992                 pvr2_trace(PVR2_TRACE_GPIO,
4993                            "GPIO direction changing to 0x%x",nval);
4994         }
4995         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4996 }
4997
4998
4999 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5000 {
5001         u32 cval,nval;
5002         int ret;
5003         if (~msk) {
5004                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5005                 if (ret) return ret;
5006                 nval = (cval & ~msk) | (val & msk);
5007                 pvr2_trace(PVR2_TRACE_GPIO,
5008                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5009                            msk,val,cval,nval);
5010         } else {
5011                 nval = val;
5012                 pvr2_trace(PVR2_TRACE_GPIO,
5013                            "GPIO output changing to 0x%x",nval);
5014         }
5015         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5016 }
5017
5018
5019 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5020 {
5021         struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5022         memset(vtp, 0, sizeof(*vtp));
5023         hdw->tuner_signal_stale = 0;
5024         pvr2_i2c_core_status_poll(hdw);
5025         /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5026            using v4l2-subdev - therefore we can't support that AT ALL right
5027            now.  (Of course, no sub-drivers seem to implement it either.
5028            But now it's a a chicken and egg problem...) */
5029         v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5030                              &hdw->tuner_signal_info);
5031         pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
5032                    " type=%u strength=%u audio=0x%x cap=0x%x"
5033                    " low=%u hi=%u",
5034                    vtp->type,
5035                    vtp->signal, vtp->rxsubchans, vtp->capability,
5036                    vtp->rangelow, vtp->rangehigh);
5037
5038         /* We have to do this to avoid getting into constant polling if
5039            there's nobody to answer a poll of cropcap info. */
5040         hdw->cropcap_stale = 0;
5041 }
5042
5043
5044 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5045 {
5046         return hdw->input_avail_mask;
5047 }
5048
5049
5050 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5051 {
5052         return hdw->input_allowed_mask;
5053 }
5054
5055
5056 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5057 {
5058         if (hdw->input_val != v) {
5059                 hdw->input_val = v;
5060                 hdw->input_dirty = !0;
5061         }
5062
5063         /* Handle side effects - if we switch to a mode that needs the RF
5064            tuner, then select the right frequency choice as well and mark
5065            it dirty. */
5066         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5067                 hdw->freqSelector = 0;
5068                 hdw->freqDirty = !0;
5069         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5070                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5071                 hdw->freqSelector = 1;
5072                 hdw->freqDirty = !0;
5073         }
5074         return 0;
5075 }
5076
5077
5078 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5079                                unsigned int change_mask,
5080                                unsigned int change_val)
5081 {
5082         int ret = 0;
5083         unsigned int nv,m,idx;
5084         LOCK_TAKE(hdw->big_lock);
5085         do {
5086                 nv = hdw->input_allowed_mask & ~change_mask;
5087                 nv |= (change_val & change_mask);
5088                 nv &= hdw->input_avail_mask;
5089                 if (!nv) {
5090                         /* No legal modes left; return error instead. */
5091                         ret = -EPERM;
5092                         break;
5093                 }
5094                 hdw->input_allowed_mask = nv;
5095                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5096                         /* Current mode is still in the allowed mask, so
5097                            we're done. */
5098                         break;
5099                 }
5100                 /* Select and switch to a mode that is still in the allowed
5101                    mask */
5102                 if (!hdw->input_allowed_mask) {
5103                         /* Nothing legal; give up */
5104                         break;
5105                 }
5106                 m = hdw->input_allowed_mask;
5107                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5108                         if (!((1 << idx) & m)) continue;
5109                         pvr2_hdw_set_input(hdw,idx);
5110                         break;
5111                 }
5112         } while (0);
5113         LOCK_GIVE(hdw->big_lock);
5114         return ret;
5115 }
5116
5117
5118 /* Find I2C address of eeprom */
5119 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5120 {
5121         int result;
5122         LOCK_TAKE(hdw->ctl_lock); do {
5123                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5124                 result = pvr2_send_request(hdw,
5125                                            hdw->cmd_buffer,1,
5126                                            hdw->cmd_buffer,1);
5127                 if (result < 0) break;
5128                 result = hdw->cmd_buffer[0];
5129         } while(0); LOCK_GIVE(hdw->ctl_lock);
5130         return result;
5131 }
5132
5133
5134 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
5135                              struct v4l2_dbg_match *match, u64 reg_id,
5136                              int setFl, u64 *val_ptr)
5137 {
5138 #ifdef CONFIG_VIDEO_ADV_DEBUG
5139         struct pvr2_i2c_client *cp;
5140         struct v4l2_dbg_register req;
5141         int stat = 0;
5142         int okFl = 0;
5143
5144         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5145
5146         req.match = *match;
5147         req.reg = reg_id;
5148         if (setFl) req.val = *val_ptr;
5149         /* It would be nice to know if a sub-device answered the request */
5150         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5151         if (!setFl) *val_ptr = req.val;
5152         if (!okFl) mutex_lock(&hdw->i2c_list_lock); do {
5153                 list_for_each_entry(cp, &hdw->i2c_clients, list) {
5154                         if (!v4l2_chip_match_i2c_client(
5155                                     cp->client,
5156                                     &req.match)) {
5157                                 continue;
5158                         }
5159                         stat = pvr2_i2c_client_cmd(
5160                                 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
5161                                     VIDIOC_DBG_G_REGISTER),&req);
5162                         if (!setFl) *val_ptr = req.val;
5163                         okFl = !0;
5164                         break;
5165                 }
5166         } while (0); mutex_unlock(&hdw->i2c_list_lock);
5167         if (okFl) {
5168                 return stat;
5169         }
5170         return -EINVAL;
5171 #else
5172         return -ENOSYS;
5173 #endif
5174 }
5175
5176
5177 /*
5178   Stuff for Emacs to see, in order to encourage consistent editing style:
5179   *** Local Variables: ***
5180   *** mode: c ***
5181   *** fill-column: 75 ***
5182   *** tab-width: 8 ***
5183   *** c-basic-offset: 8 ***
5184   *** End: ***
5185   */