SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *  $Id$
   4  *
   5  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  *
  20  */
  21
  22 #include <linux/errno.h>
  23 #include <linux/string.h>
  24 #include <linux/slab.h>
  25 #include <linux/firmware.h>
  26 #include <linux/videodev2.h>
  27 #include <media/v4l2-common.h>
  28 #include <asm/semaphore.h>
  29 #include "pvrusb2.h"
  30 #include "pvrusb2-std.h"
  31 #include "pvrusb2-util.h"
  32 #include "pvrusb2-hdw.h"
  33 #include "pvrusb2-i2c-core.h"
  34 #include "pvrusb2-tuner.h"
  35 #include "pvrusb2-eeprom.h"
  36 #include "pvrusb2-hdw-internal.h"
  37 #include "pvrusb2-encoder.h"
  38 #include "pvrusb2-debug.h"
  39 #include "pvrusb2-fx2-cmd.h"
  40
  41 #define TV_MIN_FREQ     55250000L
  42 #define TV_MAX_FREQ    850000000L
  43
  44 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  45 static DEFINE_MUTEX(pvr2_unit_mtx);
  46
  47 static int ctlchg = 0;
  48 static int initusbreset = 1;
  49 static int procreload = 0;
  50 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  51 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  52 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  53 static int init_pause_msec = 0;
  54
  55 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  56 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  57 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  58 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  59 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
  60 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
  61 module_param(procreload, int, S_IRUGO|S_IWUSR);
  62 MODULE_PARM_DESC(procreload,
  63                  "Attempt init failure recovery with firmware reload");
  64 module_param_array(tuner,    int, NULL, 0444);
  65 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  66 module_param_array(video_std,    int, NULL, 0444);
  67 MODULE_PARM_DESC(video_std,"specify initial video standard");
  68 module_param_array(tolerance,    int, NULL, 0444);
  69 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  70
  71 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  72 #define PVR2_CTL_READ_ENDPOINT   0x81
  73
  74 #define PVR2_GPIO_IN 0x9008
  75 #define PVR2_GPIO_OUT 0x900c
  76 #define PVR2_GPIO_DIR 0x9020
  77
  78 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
  79
  80 #define PVR2_FIRMWARE_ENDPOINT   0x02
  81
  82 /* size of a firmware chunk */
  83 #define FIRMWARE_CHUNK_SIZE 0x2000
  84
  85 /* Define the list of additional controls we'll dynamically construct based
  86    on query of the cx2341x module. */
  87 struct pvr2_mpeg_ids {
  88         const char *strid;
  89         int id;
  90 };
  91 static const struct pvr2_mpeg_ids mpeg_ids[] = {
  92         {
  93                 .strid = "audio_layer",
  94                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
  95         },{
  96                 .strid = "audio_bitrate",
  97                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
  98         },{
  99                 /* Already using audio_mode elsewhere :-( */
 100                 .strid = "mpeg_audio_mode",
 101                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 102         },{
 103                 .strid = "mpeg_audio_mode_extension",
 104                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 105         },{
 106                 .strid = "audio_emphasis",
 107                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 108         },{
 109                 .strid = "audio_crc",
 110                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 111         },{
 112                 .strid = "video_aspect",
 113                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 114         },{
 115                 .strid = "video_b_frames",
 116                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 117         },{
 118                 .strid = "video_gop_size",
 119                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 120         },{
 121                 .strid = "video_gop_closure",
 122                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 123         },{
 124                 .strid = "video_bitrate_mode",
 125                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 126         },{
 127                 .strid = "video_bitrate",
 128                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 129         },{
 130                 .strid = "video_bitrate_peak",
 131                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 132         },{
 133                 .strid = "video_temporal_decimation",
 134                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 135         },{
 136                 .strid = "stream_type",
 137                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 138         },{
 139                 .strid = "video_spatial_filter_mode",
 140                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 141         },{
 142                 .strid = "video_spatial_filter",
 143                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 144         },{
 145                 .strid = "video_luma_spatial_filter_type",
 146                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 147         },{
 148                 .strid = "video_chroma_spatial_filter_type",
 149                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 150         },{
 151                 .strid = "video_temporal_filter_mode",
 152                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 153         },{
 154                 .strid = "video_temporal_filter",
 155                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 156         },{
 157                 .strid = "video_median_filter_type",
 158                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 159         },{
 160                 .strid = "video_luma_median_filter_top",
 161                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 162         },{
 163                 .strid = "video_luma_median_filter_bottom",
 164                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 165         },{
 166                 .strid = "video_chroma_median_filter_top",
 167                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 168         },{
 169                 .strid = "video_chroma_median_filter_bottom",
 170                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 171         }
 172 };
 173 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 174
 175
 176 static const char *control_values_srate[] = {
 177         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 178         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 179         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 180 };
 181
 182
 183
 184 static const char *control_values_input[] = {
 185         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 186         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 187         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 188         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 189 };
 190
 191
 192 static const char *control_values_audiomode[] = {
 193         [V4L2_TUNER_MODE_MONO]   = "Mono",
 194         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 195         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 196         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 197         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 198 };
 199
 200
 201 static const char *control_values_hsm[] = {
 202         [PVR2_CVAL_HSM_FAIL] = "Fail",
 203         [PVR2_CVAL_HSM_HIGH] = "High",
 204         [PVR2_CVAL_HSM_FULL] = "Full",
 205 };
 206
 207
 208 static const char *pvr2_state_names[] = {
 209         [PVR2_STATE_NONE] =    "none",
 210         [PVR2_STATE_DEAD] =    "dead",
 211         [PVR2_STATE_COLD] =    "cold",
 212         [PVR2_STATE_WARM] =    "warm",
 213         [PVR2_STATE_ERROR] =   "error",
 214         [PVR2_STATE_READY] =   "ready",
 215         [PVR2_STATE_RUN] =     "run",
 216 };
 217
 218
 219 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 220 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 221 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 222 static void pvr2_hdw_worker_i2c(struct work_struct *work);
 223 static void pvr2_hdw_worker_poll(struct work_struct *work);
 224 static void pvr2_hdw_worker_init(struct work_struct *work);
 225 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 226 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 227 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 228 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 229 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 230 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 231 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 232 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 233 static void pvr2_hdw_quiescent_timeout(unsigned long);
 234 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 235 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 236                                 unsigned int timeout,int probe_fl,
 237                                 void *write_data,unsigned int write_len,
 238                                 void *read_data,unsigned int read_len);
 239
 240
 241 static void trace_stbit(const char *name,int val)
 242 {
 243         pvr2_trace(PVR2_TRACE_STBITS,
 244                    "State bit %s <-- %s",
 245                    name,(val ? "true" : "false"));
 246 }
 247
 248 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 249 {
 250         struct pvr2_hdw *hdw = cptr->hdw;
 251         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 252                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 253         } else {
 254                 *vp = 0;
 255         }
 256         return 0;
 257 }
 258
 259 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 260 {
 261         struct pvr2_hdw *hdw = cptr->hdw;
 262         unsigned int slotId = hdw->freqProgSlot;
 263         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 264                 hdw->freqTable[slotId-1] = v;
 265                 /* Handle side effects correctly - if we're tuned to this
 266                    slot, then forgot the slot id relation since the stored
 267                    frequency has been changed. */
 268                 if (hdw->freqSelector) {
 269                         if (hdw->freqSlotRadio == slotId) {
 270                                 hdw->freqSlotRadio = 0;
 271                         }
 272                 } else {
 273                         if (hdw->freqSlotTelevision == slotId) {
 274                                 hdw->freqSlotTelevision = 0;
 275                         }
 276                 }
 277         }
 278         return 0;
 279 }
 280
 281 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 282 {
 283         *vp = cptr->hdw->freqProgSlot;
 284         return 0;
 285 }
 286
 287 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 288 {
 289         struct pvr2_hdw *hdw = cptr->hdw;
 290         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 291                 hdw->freqProgSlot = v;
 292         }
 293         return 0;
 294 }
 295
 296 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 297 {
 298         struct pvr2_hdw *hdw = cptr->hdw;
 299         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 300         return 0;
 301 }
 302
 303 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 304 {
 305         unsigned freq = 0;
 306         struct pvr2_hdw *hdw = cptr->hdw;
 307         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 308         if (slotId > 0) {
 309                 freq = hdw->freqTable[slotId-1];
 310                 if (!freq) return 0;
 311                 pvr2_hdw_set_cur_freq(hdw,freq);
 312         }
 313         if (hdw->freqSelector) {
 314                 hdw->freqSlotRadio = slotId;
 315         } else {
 316                 hdw->freqSlotTelevision = slotId;
 317         }
 318         return 0;
 319 }
 320
 321 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 322 {
 323         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 324         return 0;
 325 }
 326
 327 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 328 {
 329         return cptr->hdw->freqDirty != 0;
 330 }
 331
 332 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 333 {
 334         cptr->hdw->freqDirty = 0;
 335 }
 336
 337 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 338 {
 339         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 340         return 0;
 341 }
 342
 343 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 344 {
 345         /* Actual maximum depends on the video standard in effect. */
 346         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 347                 *vp = 480;
 348         } else {
 349                 *vp = 576;
 350         }
 351         return 0;
 352 }
 353
 354 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 355 {
 356         /* Actual minimum depends on device digitizer type. */
 357         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 358                 *vp = 75;
 359         } else {
 360                 *vp = 17;
 361         }
 362         return 0;
 363 }
 364
 365 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 366 {
 367         *vp = cptr->hdw->input_val;
 368         return 0;
 369 }
 370
 371 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 372 {
 373         struct pvr2_hdw *hdw = cptr->hdw;
 374
 375         if (hdw->input_val != v) {
 376                 hdw->input_val = v;
 377                 hdw->input_dirty = !0;
 378         }
 379
 380         /* Handle side effects - if we switch to a mode that needs the RF
 381            tuner, then select the right frequency choice as well and mark
 382            it dirty. */
 383         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
 384                 hdw->freqSelector = 0;
 385                 hdw->freqDirty = !0;
 386         } else if (hdw->input_val == PVR2_CVAL_INPUT_TV) {
 387                 hdw->freqSelector = 1;
 388                 hdw->freqDirty = !0;
 389         }
 390         return 0;
 391 }
 392
 393 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 394 {
 395         return cptr->hdw->input_dirty != 0;
 396 }
 397
 398 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 399 {
 400         cptr->hdw->input_dirty = 0;
 401 }
 402
 403
 404 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 405 {
 406         unsigned long fv;
 407         struct pvr2_hdw *hdw = cptr->hdw;
 408         if (hdw->tuner_signal_stale) {
 409                 pvr2_i2c_core_status_poll(hdw);
 410         }
 411         fv = hdw->tuner_signal_info.rangehigh;
 412         if (!fv) {
 413                 /* Safety fallback */
 414                 *vp = TV_MAX_FREQ;
 415                 return 0;
 416         }
 417         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 418                 fv = (fv * 125) / 2;
 419         } else {
 420                 fv = fv * 62500;
 421         }
 422         *vp = fv;
 423         return 0;
 424 }
 425
 426 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 427 {
 428         unsigned long fv;
 429         struct pvr2_hdw *hdw = cptr->hdw;
 430         if (hdw->tuner_signal_stale) {
 431                 pvr2_i2c_core_status_poll(hdw);
 432         }
 433         fv = hdw->tuner_signal_info.rangelow;
 434         if (!fv) {
 435                 /* Safety fallback */
 436                 *vp = TV_MIN_FREQ;
 437                 return 0;
 438         }
 439         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 440                 fv = (fv * 125) / 2;
 441         } else {
 442                 fv = fv * 62500;
 443         }
 444         *vp = fv;
 445         return 0;
 446 }
 447
 448 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 449 {
 450         return cptr->hdw->enc_stale != 0;
 451 }
 452
 453 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 454 {
 455         cptr->hdw->enc_stale = 0;
 456         cptr->hdw->enc_unsafe_stale = 0;
 457 }
 458
 459 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 460 {
 461         int ret;
 462         struct v4l2_ext_controls cs;
 463         struct v4l2_ext_control c1;
 464         memset(&cs,0,sizeof(cs));
 465         memset(&c1,0,sizeof(c1));
 466         cs.controls = &c1;
 467         cs.count = 1;
 468         c1.id = cptr->info->v4l_id;
 469         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 470                                 VIDIOC_G_EXT_CTRLS);
 471         if (ret) return ret;
 472         *vp = c1.value;
 473         return 0;
 474 }
 475
 476 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 477 {
 478         int ret;
 479         struct pvr2_hdw *hdw = cptr->hdw;
 480         struct v4l2_ext_controls cs;
 481         struct v4l2_ext_control c1;
 482         memset(&cs,0,sizeof(cs));
 483         memset(&c1,0,sizeof(c1));
 484         cs.controls = &c1;
 485         cs.count = 1;
 486         c1.id = cptr->info->v4l_id;
 487         c1.value = v;
 488         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 489                                 hdw->state_encoder_run, &cs,
 490                                 VIDIOC_S_EXT_CTRLS);
 491         if (ret == -EBUSY) {
 492                 /* Oops.  cx2341x is telling us it's not safe to change
 493                    this control while we're capturing.  Make a note of this
 494                    fact so that the pipeline will be stopped the next time
 495                    controls are committed.  Then go on ahead and store this
 496                    change anyway. */
 497                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 498                                         0, &cs,
 499                                         VIDIOC_S_EXT_CTRLS);
 500                 if (!ret) hdw->enc_unsafe_stale = !0;
 501         }
 502         if (ret) return ret;
 503         hdw->enc_stale = !0;
 504         return 0;
 505 }
 506
 507 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 508 {
 509         struct v4l2_queryctrl qctrl;
 510         struct pvr2_ctl_info *info;
 511         qctrl.id = cptr->info->v4l_id;
 512         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 513         /* Strip out the const so we can adjust a function pointer.  It's
 514            OK to do this here because we know this is a dynamically created
 515            control, so the underlying storage for the info pointer is (a)
 516            private to us, and (b) not in read-only storage.  Either we do
 517            this or we significantly complicate the underlying control
 518            implementation. */
 519         info = (struct pvr2_ctl_info *)(cptr->info);
 520         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 521                 if (info->set_value) {
 522                         info->set_value = NULL;
 523                 }
 524         } else {
 525                 if (!(info->set_value)) {
 526                         info->set_value = ctrl_cx2341x_set;
 527                 }
 528         }
 529         return qctrl.flags;
 530 }
 531
 532 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 533 {
 534         *vp = cptr->hdw->state_pipeline_req;
 535         return 0;
 536 }
 537
 538 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 539 {
 540         *vp = cptr->hdw->master_state;
 541         return 0;
 542 }
 543
 544 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 545 {
 546         int result = pvr2_hdw_is_hsm(cptr->hdw);
 547         *vp = PVR2_CVAL_HSM_FULL;
 548         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 549         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 550         return 0;
 551 }
 552
 553 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 554 {
 555         *vp = cptr->hdw->std_mask_avail;
 556         return 0;
 557 }
 558
 559 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 560 {
 561         struct pvr2_hdw *hdw = cptr->hdw;
 562         v4l2_std_id ns;
 563         ns = hdw->std_mask_avail;
 564         ns = (ns & ~m) | (v & m);
 565         if (ns == hdw->std_mask_avail) return 0;
 566         hdw->std_mask_avail = ns;
 567         pvr2_hdw_internal_set_std_avail(hdw);
 568         pvr2_hdw_internal_find_stdenum(hdw);
 569         return 0;
 570 }
 571
 572 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 573                                char *bufPtr,unsigned int bufSize,
 574                                unsigned int *len)
 575 {
 576         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 577         return 0;
 578 }
 579
 580 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 581                                const char *bufPtr,unsigned int bufSize,
 582                                int *mskp,int *valp)
 583 {
 584         int ret;
 585         v4l2_std_id id;
 586         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 587         if (ret < 0) return ret;
 588         if (mskp) *mskp = id;
 589         if (valp) *valp = id;
 590         return 0;
 591 }
 592
 593 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 594 {
 595         *vp = cptr->hdw->std_mask_cur;
 596         return 0;
 597 }
 598
 599 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 600 {
 601         struct pvr2_hdw *hdw = cptr->hdw;
 602         v4l2_std_id ns;
 603         ns = hdw->std_mask_cur;
 604         ns = (ns & ~m) | (v & m);
 605         if (ns == hdw->std_mask_cur) return 0;
 606         hdw->std_mask_cur = ns;
 607         hdw->std_dirty = !0;
 608         pvr2_hdw_internal_find_stdenum(hdw);
 609         return 0;
 610 }
 611
 612 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 613 {
 614         return cptr->hdw->std_dirty != 0;
 615 }
 616
 617 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 618 {
 619         cptr->hdw->std_dirty = 0;
 620 }
 621
 622 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 623 {
 624         struct pvr2_hdw *hdw = cptr->hdw;
 625         pvr2_i2c_core_status_poll(hdw);
 626         *vp = hdw->tuner_signal_info.signal;
 627         return 0;
 628 }
 629
 630 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 631 {
 632         int val = 0;
 633         unsigned int subchan;
 634         struct pvr2_hdw *hdw = cptr->hdw;
 635         pvr2_i2c_core_status_poll(hdw);
 636         subchan = hdw->tuner_signal_info.rxsubchans;
 637         if (subchan & V4L2_TUNER_SUB_MONO) {
 638                 val |= (1 << V4L2_TUNER_MODE_MONO);
 639         }
 640         if (subchan & V4L2_TUNER_SUB_STEREO) {
 641                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 642         }
 643         if (subchan & V4L2_TUNER_SUB_LANG1) {
 644                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 645         }
 646         if (subchan & V4L2_TUNER_SUB_LANG2) {
 647                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 648         }
 649         *vp = val;
 650         return 0;
 651 }
 652
 653
 654 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 655 {
 656         struct pvr2_hdw *hdw = cptr->hdw;
 657         if (v < 0) return -EINVAL;
 658         if (v > hdw->std_enum_cnt) return -EINVAL;
 659         hdw->std_enum_cur = v;
 660         if (!v) return 0;
 661         v--;
 662         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 663         hdw->std_mask_cur = hdw->std_defs[v].id;
 664         hdw->std_dirty = !0;
 665         return 0;
 666 }
 667
 668
 669 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 670 {
 671         *vp = cptr->hdw->std_enum_cur;
 672         return 0;
 673 }
 674
 675
 676 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 677 {
 678         return cptr->hdw->std_dirty != 0;
 679 }
 680
 681
 682 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 683 {
 684         cptr->hdw->std_dirty = 0;
 685 }
 686
 687
 688 #define DEFINT(vmin,vmax) \
 689         .type = pvr2_ctl_int, \
 690         .def.type_int.min_value = vmin, \
 691         .def.type_int.max_value = vmax
 692
 693 #define DEFENUM(tab) \
 694         .type = pvr2_ctl_enum, \
 695         .def.type_enum.count = ARRAY_SIZE(tab), \
 696         .def.type_enum.value_names = tab
 697
 698 #define DEFBOOL \
 699         .type = pvr2_ctl_bool
 700
 701 #define DEFMASK(msk,tab) \
 702         .type = pvr2_ctl_bitmask, \
 703         .def.type_bitmask.valid_bits = msk, \
 704         .def.type_bitmask.bit_names = tab
 705
 706 #define DEFREF(vname) \
 707         .set_value = ctrl_set_##vname, \
 708         .get_value = ctrl_get_##vname, \
 709         .is_dirty = ctrl_isdirty_##vname, \
 710         .clear_dirty = ctrl_cleardirty_##vname
 711
 712
 713 #define VCREATE_FUNCS(vname) \
 714 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 715 {*vp = cptr->hdw->vname##_val; return 0;} \
 716 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 717 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 718 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 719 {return cptr->hdw->vname##_dirty != 0;} \
 720 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 721 {cptr->hdw->vname##_dirty = 0;}
 722
 723 VCREATE_FUNCS(brightness)
 724 VCREATE_FUNCS(contrast)
 725 VCREATE_FUNCS(saturation)
 726 VCREATE_FUNCS(hue)
 727 VCREATE_FUNCS(volume)
 728 VCREATE_FUNCS(balance)
 729 VCREATE_FUNCS(bass)
 730 VCREATE_FUNCS(treble)
 731 VCREATE_FUNCS(mute)
 732 VCREATE_FUNCS(audiomode)
 733 VCREATE_FUNCS(res_hor)
 734 VCREATE_FUNCS(res_ver)
 735 VCREATE_FUNCS(srate)
 736
 737 /* Table definition of all controls which can be manipulated */
 738 static const struct pvr2_ctl_info control_defs[] = {
 739         {
 740                 .v4l_id = V4L2_CID_BRIGHTNESS,
 741                 .desc = "Brightness",
 742                 .name = "brightness",
 743                 .default_value = 128,
 744                 DEFREF(brightness),
 745                 DEFINT(0,255),
 746         },{
 747                 .v4l_id = V4L2_CID_CONTRAST,
 748                 .desc = "Contrast",
 749                 .name = "contrast",
 750                 .default_value = 68,
 751                 DEFREF(contrast),
 752                 DEFINT(0,127),
 753         },{
 754                 .v4l_id = V4L2_CID_SATURATION,
 755                 .desc = "Saturation",
 756                 .name = "saturation",
 757                 .default_value = 64,
 758                 DEFREF(saturation),
 759                 DEFINT(0,127),
 760         },{
 761                 .v4l_id = V4L2_CID_HUE,
 762                 .desc = "Hue",
 763                 .name = "hue",
 764                 .default_value = 0,
 765                 DEFREF(hue),
 766                 DEFINT(-128,127),
 767         },{
 768                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
 769                 .desc = "Volume",
 770                 .name = "volume",
 771                 .default_value = 62000,
 772                 DEFREF(volume),
 773                 DEFINT(0,65535),
 774         },{
 775                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
 776                 .desc = "Balance",
 777                 .name = "balance",
 778                 .default_value = 0,
 779                 DEFREF(balance),
 780                 DEFINT(-32768,32767),
 781         },{
 782                 .v4l_id = V4L2_CID_AUDIO_BASS,
 783                 .desc = "Bass",
 784                 .name = "bass",
 785                 .default_value = 0,
 786                 DEFREF(bass),
 787                 DEFINT(-32768,32767),
 788         },{
 789                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
 790                 .desc = "Treble",
 791                 .name = "treble",
 792                 .default_value = 0,
 793                 DEFREF(treble),
 794                 DEFINT(-32768,32767),
 795         },{
 796                 .v4l_id = V4L2_CID_AUDIO_MUTE,
 797                 .desc = "Mute",
 798                 .name = "mute",
 799                 .default_value = 0,
 800                 DEFREF(mute),
 801                 DEFBOOL,
 802         },{
 803                 .desc = "Video Source",
 804                 .name = "input",
 805                 .internal_id = PVR2_CID_INPUT,
 806                 .default_value = PVR2_CVAL_INPUT_TV,
 807                 DEFREF(input),
 808                 DEFENUM(control_values_input),
 809         },{
 810                 .desc = "Audio Mode",
 811                 .name = "audio_mode",
 812                 .internal_id = PVR2_CID_AUDIOMODE,
 813                 .default_value = V4L2_TUNER_MODE_STEREO,
 814                 DEFREF(audiomode),
 815                 DEFENUM(control_values_audiomode),
 816         },{
 817                 .desc = "Horizontal capture resolution",
 818                 .name = "resolution_hor",
 819                 .internal_id = PVR2_CID_HRES,
 820                 .default_value = 720,
 821                 DEFREF(res_hor),
 822                 DEFINT(19,720),
 823         },{
 824                 .desc = "Vertical capture resolution",
 825                 .name = "resolution_ver",
 826                 .internal_id = PVR2_CID_VRES,
 827                 .default_value = 480,
 828                 DEFREF(res_ver),
 829                 DEFINT(17,576),
 830                 /* Hook in check for video standard and adjust maximum
 831                    depending on the standard. */
 832                 .get_max_value = ctrl_vres_max_get,
 833                 .get_min_value = ctrl_vres_min_get,
 834         },{
 835                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
 836                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
 837                 .desc = "Audio Sampling Frequency",
 838                 .name = "srate",
 839                 DEFREF(srate),
 840                 DEFENUM(control_values_srate),
 841         },{
 842                 .desc = "Tuner Frequency (Hz)",
 843                 .name = "frequency",
 844                 .internal_id = PVR2_CID_FREQUENCY,
 845                 .default_value = 0,
 846                 .set_value = ctrl_freq_set,
 847                 .get_value = ctrl_freq_get,
 848                 .is_dirty = ctrl_freq_is_dirty,
 849                 .clear_dirty = ctrl_freq_clear_dirty,
 850                 DEFINT(0,0),
 851                 /* Hook in check for input value (tv/radio) and adjust
 852                    max/min values accordingly */
 853                 .get_max_value = ctrl_freq_max_get,
 854                 .get_min_value = ctrl_freq_min_get,
 855         },{
 856                 .desc = "Channel",
 857                 .name = "channel",
 858                 .set_value = ctrl_channel_set,
 859                 .get_value = ctrl_channel_get,
 860                 DEFINT(0,FREQTABLE_SIZE),
 861         },{
 862                 .desc = "Channel Program Frequency",
 863                 .name = "freq_table_value",
 864                 .set_value = ctrl_channelfreq_set,
 865                 .get_value = ctrl_channelfreq_get,
 866                 DEFINT(0,0),
 867                 /* Hook in check for input value (tv/radio) and adjust
 868                    max/min values accordingly */
 869                 .get_max_value = ctrl_freq_max_get,
 870                 .get_min_value = ctrl_freq_min_get,
 871         },{
 872                 .desc = "Channel Program ID",
 873                 .name = "freq_table_channel",
 874                 .set_value = ctrl_channelprog_set,
 875                 .get_value = ctrl_channelprog_get,
 876                 DEFINT(0,FREQTABLE_SIZE),
 877         },{
 878                 .desc = "Streaming Enabled",
 879                 .name = "streaming_enabled",
 880                 .get_value = ctrl_streamingenabled_get,
 881                 DEFBOOL,
 882         },{
 883                 .desc = "USB Speed",
 884                 .name = "usb_speed",
 885                 .get_value = ctrl_hsm_get,
 886                 DEFENUM(control_values_hsm),
 887         },{
 888                 .desc = "Master State",
 889                 .name = "master_state",
 890                 .get_value = ctrl_masterstate_get,
 891                 DEFENUM(pvr2_state_names),
 892         },{
 893                 .desc = "Signal Present",
 894                 .name = "signal_present",
 895                 .get_value = ctrl_signal_get,
 896                 DEFINT(0,65535),
 897         },{
 898                 .desc = "Audio Modes Present",
 899                 .name = "audio_modes_present",
 900                 .get_value = ctrl_audio_modes_present_get,
 901                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
 902                    v4l.  Nothing outside of this module cares about this,
 903                    but I reuse it in order to also reuse the
 904                    control_values_audiomode string table. */
 905                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
 906                          (1 << V4L2_TUNER_MODE_STEREO)|
 907                          (1 << V4L2_TUNER_MODE_LANG1)|
 908                          (1 << V4L2_TUNER_MODE_LANG2)),
 909                         control_values_audiomode),
 910         },{
 911                 .desc = "Video Standards Available Mask",
 912                 .name = "video_standard_mask_available",
 913                 .internal_id = PVR2_CID_STDAVAIL,
 914                 .skip_init = !0,
 915                 .get_value = ctrl_stdavail_get,
 916                 .set_value = ctrl_stdavail_set,
 917                 .val_to_sym = ctrl_std_val_to_sym,
 918                 .sym_to_val = ctrl_std_sym_to_val,
 919                 .type = pvr2_ctl_bitmask,
 920         },{
 921                 .desc = "Video Standards In Use Mask",
 922                 .name = "video_standard_mask_active",
 923                 .internal_id = PVR2_CID_STDCUR,
 924                 .skip_init = !0,
 925                 .get_value = ctrl_stdcur_get,
 926                 .set_value = ctrl_stdcur_set,
 927                 .is_dirty = ctrl_stdcur_is_dirty,
 928                 .clear_dirty = ctrl_stdcur_clear_dirty,
 929                 .val_to_sym = ctrl_std_val_to_sym,
 930                 .sym_to_val = ctrl_std_sym_to_val,
 931                 .type = pvr2_ctl_bitmask,
 932         },{
 933                 .desc = "Video Standard Name",
 934                 .name = "video_standard",
 935                 .internal_id = PVR2_CID_STDENUM,
 936                 .skip_init = !0,
 937                 .get_value = ctrl_stdenumcur_get,
 938                 .set_value = ctrl_stdenumcur_set,
 939                 .is_dirty = ctrl_stdenumcur_is_dirty,
 940                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
 941                 .type = pvr2_ctl_enum,
 942         }
 943 };
 944
 945 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
 946
 947
 948 const char *pvr2_config_get_name(enum pvr2_config cfg)
 949 {
 950         switch (cfg) {
 951         case pvr2_config_empty: return "empty";
 952         case pvr2_config_mpeg: return "mpeg";
 953         case pvr2_config_vbi: return "vbi";
 954         case pvr2_config_pcm: return "pcm";
 955         case pvr2_config_rawvideo: return "raw video";
 956         }
 957         return "<unknown>";
 958 }
 959
 960
 961 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
 962 {
 963         return hdw->usb_dev;
 964 }
 965
 966
 967 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
 968 {
 969         return hdw->serial_number;
 970 }
 971
 972
 973 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
 974 {
 975         return hdw->bus_info;
 976 }
 977
 978
 979 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
 980 {
 981         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
 982 }
 983
 984 /* Set the currently tuned frequency and account for all possible
 985    driver-core side effects of this action. */
 986 void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
 987 {
 988         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
 989                 if (hdw->freqSelector) {
 990                         /* Swing over to radio frequency selection */
 991                         hdw->freqSelector = 0;
 992                         hdw->freqDirty = !0;
 993                 }
 994                 if (hdw->freqValRadio != val) {
 995                         hdw->freqValRadio = val;
 996                         hdw->freqSlotRadio = 0;
 997                         hdw->freqDirty = !0;
 998                 }
 999         } else {
1000                 if (!(hdw->freqSelector)) {
1001                         /* Swing over to television frequency selection */
1002                         hdw->freqSelector = 1;
1003                         hdw->freqDirty = !0;
1004                 }
1005                 if (hdw->freqValTelevision != val) {
1006                         hdw->freqValTelevision = val;
1007                         hdw->freqSlotTelevision = 0;
1008                         hdw->freqDirty = !0;
1009                 }
1010         }
1011 }
1012
1013 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1014 {
1015         return hdw->unit_number;
1016 }
1017
1018
1019 /* Attempt to locate one of the given set of files.  Messages are logged
1020    appropriate to what has been found.  The return value will be 0 or
1021    greater on success (it will be the index of the file name found) and
1022    fw_entry will be filled in.  Otherwise a negative error is returned on
1023    failure.  If the return value is -ENOENT then no viable firmware file
1024    could be located. */
1025 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1026                                 const struct firmware **fw_entry,
1027                                 const char *fwtypename,
1028                                 unsigned int fwcount,
1029                                 const char *fwnames[])
1030 {
1031         unsigned int idx;
1032         int ret = -EINVAL;
1033         for (idx = 0; idx < fwcount; idx++) {
1034                 ret = request_firmware(fw_entry,
1035                                        fwnames[idx],
1036                                        &hdw->usb_dev->dev);
1037                 if (!ret) {
1038                         trace_firmware("Located %s firmware: %s;"
1039                                        " uploading...",
1040                                        fwtypename,
1041                                        fwnames[idx]);
1042                         return idx;
1043                 }
1044                 if (ret == -ENOENT) continue;
1045                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1046                            "request_firmware fatal error with code=%d",ret);
1047                 return ret;
1048         }
1049         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1050                    "***WARNING***"
1051                    " Device %s firmware"
1052                    " seems to be missing.",
1053                    fwtypename);
1054         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1055                    "Did you install the pvrusb2 firmware files"
1056                    " in their proper location?");
1057         if (fwcount == 1) {
1058                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1059                            "request_firmware unable to locate %s file %s",
1060                            fwtypename,fwnames[0]);
1061         } else {
1062                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1063                            "request_firmware unable to locate"
1064                            " one of the following %s files:",
1065                            fwtypename);
1066                 for (idx = 0; idx < fwcount; idx++) {
1067                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1068                                    "request_firmware: Failed to find %s",
1069                                    fwnames[idx]);
1070                 }
1071         }
1072         return ret;
1073 }
1074
1075
1076 /*
1077  * pvr2_upload_firmware1().
1078  *
1079  * Send the 8051 firmware to the device.  After the upload, arrange for
1080  * device to re-enumerate.
1081  *
1082  * NOTE : the pointer to the firmware data given by request_firmware()
1083  * is not suitable for an usb transaction.
1084  *
1085  */
1086 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1087 {
1088         const struct firmware *fw_entry = NULL;
1089         void  *fw_ptr;
1090         unsigned int pipe;
1091         int ret;
1092         u16 address;
1093
1094         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1095                 hdw->fw1_state = FW1_STATE_OK;
1096                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1097                            "Connected device type defines"
1098                            " no firmware to upload; ignoring firmware");
1099                 return -ENOTTY;
1100         }
1101
1102         hdw->fw1_state = FW1_STATE_FAILED; // default result
1103
1104         trace_firmware("pvr2_upload_firmware1");
1105
1106         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1107                                    hdw->hdw_desc->fx2_firmware.cnt,
1108                                    hdw->hdw_desc->fx2_firmware.lst);
1109         if (ret < 0) {
1110                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1111                 return ret;
1112         }
1113
1114         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1115         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1116
1117         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1118
1119         if (fw_entry->size != 0x2000){
1120                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1121                 release_firmware(fw_entry);
1122                 return -ENOMEM;
1123         }
1124
1125         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1126         if (fw_ptr == NULL){
1127                 release_firmware(fw_entry);
1128                 return -ENOMEM;
1129         }
1130
1131         /* We have to hold the CPU during firmware upload. */
1132         pvr2_hdw_cpureset_assert(hdw,1);
1133
1134         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1135            chunk. */
1136
1137         ret = 0;
1138         for(address = 0; address < fw_entry->size; address += 0x800) {
1139                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1140                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1141                                        0, fw_ptr, 0x800, HZ);
1142         }
1143
1144         trace_firmware("Upload done, releasing device's CPU");
1145
1146         /* Now release the CPU.  It will disconnect and reconnect later. */
1147         pvr2_hdw_cpureset_assert(hdw,0);
1148
1149         kfree(fw_ptr);
1150         release_firmware(fw_entry);
1151
1152         trace_firmware("Upload done (%d bytes sent)",ret);
1153
1154         /* We should have written 8192 bytes */
1155         if (ret == 8192) {
1156                 hdw->fw1_state = FW1_STATE_RELOAD;
1157                 return 0;
1158         }
1159
1160         return -EIO;
1161 }
1162
1163
1164 /*
1165  * pvr2_upload_firmware2()
1166  *
1167  * This uploads encoder firmware on endpoint 2.
1168  *
1169  */
1170
1171 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1172 {
1173         const struct firmware *fw_entry = NULL;
1174         void  *fw_ptr;
1175         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1176         int actual_length;
1177         int ret = 0;
1178         int fwidx;
1179         static const char *fw_files[] = {
1180                 CX2341X_FIRM_ENC_FILENAME,
1181         };
1182
1183         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1184                 return 0;
1185         }
1186
1187         trace_firmware("pvr2_upload_firmware2");
1188
1189         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1190                                    ARRAY_SIZE(fw_files), fw_files);
1191         if (ret < 0) return ret;
1192         fwidx = ret;
1193         ret = 0;
1194         /* Since we're about to completely reinitialize the encoder,
1195            invalidate our cached copy of its configuration state.  Next
1196            time we configure the encoder, then we'll fully configure it. */
1197         hdw->enc_cur_valid = 0;
1198
1199         /* First prepare firmware loading */
1200         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1201         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1202         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1203         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1204         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1205         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1206         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1207         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1208         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1209         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1210         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1211         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1212         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1213         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1214         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1215         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1216         LOCK_TAKE(hdw->ctl_lock); do {
1217                 hdw->cmd_buffer[0] = FX2CMD_FWPOST1;
1218                 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
1219                 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1220                 hdw->cmd_buffer[1] = 0;
1221                 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
1222         } while (0); LOCK_GIVE(hdw->ctl_lock);
1223
1224         if (ret) {
1225                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1226                            "firmware2 upload prep failed, ret=%d",ret);
1227                 release_firmware(fw_entry);
1228                 return ret;
1229         }
1230
1231         /* Now send firmware */
1232
1233         fw_len = fw_entry->size;
1234
1235         if (fw_len % sizeof(u32)) {
1236                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1237                            "size of %s firmware"
1238                            " must be a multiple of %zu bytes",
1239                            fw_files[fwidx],sizeof(u32));
1240                 release_firmware(fw_entry);
1241                 return -1;
1242         }
1243
1244         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1245         if (fw_ptr == NULL){
1246                 release_firmware(fw_entry);
1247                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1248                            "failed to allocate memory for firmware2 upload");
1249                 return -ENOMEM;
1250         }
1251
1252         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1253
1254         fw_done = 0;
1255         for (fw_done = 0; fw_done < fw_len;) {
1256                 bcnt = fw_len - fw_done;
1257                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1258                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1259                 /* Usbsnoop log shows that we must swap bytes... */
1260                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1261                         ((u32 *)fw_ptr)[icnt] =
1262                                 ___swab32(((u32 *)fw_ptr)[icnt]);
1263
1264                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1265                                     &actual_length, HZ);
1266                 ret |= (actual_length != bcnt);
1267                 if (ret) break;
1268                 fw_done += bcnt;
1269         }
1270
1271         trace_firmware("upload of %s : %i / %i ",
1272                        fw_files[fwidx],fw_done,fw_len);
1273
1274         kfree(fw_ptr);
1275         release_firmware(fw_entry);
1276
1277         if (ret) {
1278                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1279                            "firmware2 upload transfer failure");
1280                 return ret;
1281         }
1282
1283         /* Finish upload */
1284
1285         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1286         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1287         LOCK_TAKE(hdw->ctl_lock); do {
1288                 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1289                 hdw->cmd_buffer[1] = 0;
1290                 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
1291         } while (0); LOCK_GIVE(hdw->ctl_lock);
1292
1293         if (ret) {
1294                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1295                            "firmware2 upload post-proc failure");
1296         }
1297         return ret;
1298 }
1299
1300
1301 static const char *pvr2_get_state_name(unsigned int st)
1302 {
1303         if (st < ARRAY_SIZE(pvr2_state_names)) {
1304                 return pvr2_state_names[st];
1305         }
1306         return "???";
1307 }
1308
1309 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1310 {
1311         if (!hdw->decoder_ctrl) {
1312                 if (!hdw->flag_decoder_missed) {
1313                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1314                                    "WARNING: No decoder present");
1315                         hdw->flag_decoder_missed = !0;
1316                         trace_stbit("flag_decoder_missed",
1317                                     hdw->flag_decoder_missed);
1318                 }
1319                 return -EIO;
1320         }
1321         hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1322         return 0;
1323 }
1324
1325
1326 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1327 {
1328         if (hdw->decoder_ctrl == ptr) return;
1329         hdw->decoder_ctrl = ptr;
1330         if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1331                 hdw->flag_decoder_missed = 0;
1332                 trace_stbit("flag_decoder_missed",
1333                             hdw->flag_decoder_missed);
1334                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1335                            "Decoder has appeared");
1336                 pvr2_hdw_state_sched(hdw);
1337         }
1338 }
1339
1340
1341 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1342 {
1343         return hdw->master_state;
1344 }
1345
1346
1347 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1348 {
1349         if (!hdw->flag_tripped) return 0;
1350         hdw->flag_tripped = 0;
1351         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1352                    "Clearing driver error statuss");
1353         return !0;
1354 }
1355
1356
1357 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1358 {
1359         int fl;
1360         LOCK_TAKE(hdw->big_lock); do {
1361                 fl = pvr2_hdw_untrip_unlocked(hdw);
1362         } while (0); LOCK_GIVE(hdw->big_lock);
1363         if (fl) pvr2_hdw_state_sched(hdw);
1364         return 0;
1365 }
1366
1367
1368 const char *pvr2_hdw_get_state_name(unsigned int id)
1369 {
1370         if (id >= ARRAY_SIZE(pvr2_state_names)) return NULL;
1371         return pvr2_state_names[id];
1372 }
1373
1374
1375 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1376 {
1377         return hdw->state_pipeline_req != 0;
1378 }
1379
1380
1381 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1382 {
1383         int ret,st;
1384         LOCK_TAKE(hdw->big_lock); do {
1385                 pvr2_hdw_untrip_unlocked(hdw);
1386                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1387                         hdw->state_pipeline_req = enable_flag != 0;
1388                         pvr2_trace(PVR2_TRACE_START_STOP,
1389                                    "/*--TRACE_STREAM--*/ %s",
1390                                    enable_flag ? "enable" : "disable");
1391                 }
1392                 pvr2_hdw_state_sched(hdw);
1393         } while (0); LOCK_GIVE(hdw->big_lock);
1394         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1395         if (enable_flag) {
1396                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1397                         if (st != PVR2_STATE_READY) return -EIO;
1398                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1399                 }
1400         }
1401         return 0;
1402 }
1403
1404
1405 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1406 {
1407         int fl;
1408         LOCK_TAKE(hdw->big_lock);
1409         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1410                 hdw->desired_stream_type = config;
1411                 hdw->state_pipeline_config = 0;
1412                 trace_stbit("state_pipeline_config",
1413                             hdw->state_pipeline_config);
1414                 pvr2_hdw_state_sched(hdw);
1415         }
1416         LOCK_GIVE(hdw->big_lock);
1417         if (fl) return 0;
1418         return pvr2_hdw_wait(hdw,0);
1419 }
1420
1421
1422 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1423 {
1424         int unit_number = hdw->unit_number;
1425         int tp = -1;
1426         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1427                 tp = tuner[unit_number];
1428         }
1429         if (tp < 0) return -EINVAL;
1430         hdw->tuner_type = tp;
1431         hdw->tuner_updated = !0;
1432         return 0;
1433 }
1434
1435
1436 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1437 {
1438         int unit_number = hdw->unit_number;
1439         int tp = 0;
1440         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1441                 tp = video_std[unit_number];
1442                 if (tp) return tp;
1443         }
1444         if (hdw->hdw_desc->default_std_mask) {
1445                 return hdw->hdw_desc->default_std_mask;
1446         }
1447         return 0;
1448 }
1449
1450
1451 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1452 {
1453         int unit_number = hdw->unit_number;
1454         int tp = 0;
1455         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1456                 tp = tolerance[unit_number];
1457         }
1458         return tp;
1459 }
1460
1461
1462 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1463 {
1464         /* Try a harmless request to fetch the eeprom's address over
1465            endpoint 1.  See what happens.  Only the full FX2 image can
1466            respond to this.  If this probe fails then likely the FX2
1467            firmware needs be loaded. */
1468         int result;
1469         LOCK_TAKE(hdw->ctl_lock); do {
1470                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1471                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1472                                            hdw->cmd_buffer,1,
1473                                            hdw->cmd_buffer,1);
1474                 if (result < 0) break;
1475         } while(0); LOCK_GIVE(hdw->ctl_lock);
1476         if (result) {
1477                 pvr2_trace(PVR2_TRACE_INIT,
1478                            "Probe of device endpoint 1 result status %d",
1479                            result);
1480         } else {
1481                 pvr2_trace(PVR2_TRACE_INIT,
1482                            "Probe of device endpoint 1 succeeded");
1483         }
1484         return result == 0;
1485 }
1486
1487 struct pvr2_std_hack {
1488         v4l2_std_id pat;  /* Pattern to match */
1489         v4l2_std_id msk;  /* Which bits we care about */
1490         v4l2_std_id std;  /* What additional standards or default to set */
1491 };
1492
1493 /* This data structure labels specific combinations of standards from
1494    tveeprom that we'll try to recognize.  If we recognize one, then assume
1495    a specified default standard to use.  This is here because tveeprom only
1496    tells us about available standards not the intended default standard (if
1497    any) for the device in question.  We guess the default based on what has
1498    been reported as available.  Note that this is only for guessing a
1499    default - which can always be overridden explicitly - and if the user
1500    has otherwise named a default then that default will always be used in
1501    place of this table. */
1502 const static struct pvr2_std_hack std_eeprom_maps[] = {
1503         {       /* PAL(B/G) */
1504                 .pat = V4L2_STD_B|V4L2_STD_GH,
1505                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1506         },
1507         {       /* NTSC(M) */
1508                 .pat = V4L2_STD_MN,
1509                 .std = V4L2_STD_NTSC_M,
1510         },
1511         {       /* PAL(I) */
1512                 .pat = V4L2_STD_PAL_I,
1513                 .std = V4L2_STD_PAL_I,
1514         },
1515         {       /* SECAM(L/L') */
1516                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1517                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1518         },
1519         {       /* PAL(D/D1/K) */
1520                 .pat = V4L2_STD_DK,
1521                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1522         },
1523 };
1524
1525 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1526 {
1527         char buf[40];
1528         unsigned int bcnt;
1529         v4l2_std_id std1,std2;
1530
1531         std1 = get_default_standard(hdw);
1532
1533         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1534         pvr2_trace(PVR2_TRACE_STD,
1535                    "Supported video standard(s) reported available"
1536                    " in hardware: %.*s",
1537                    bcnt,buf);
1538
1539         hdw->std_mask_avail = hdw->std_mask_eeprom;
1540
1541         std2 = std1 & ~hdw->std_mask_avail;
1542         if (std2) {
1543                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1544                 pvr2_trace(PVR2_TRACE_STD,
1545                            "Expanding supported video standards"
1546                            " to include: %.*s",
1547                            bcnt,buf);
1548                 hdw->std_mask_avail |= std2;
1549         }
1550
1551         pvr2_hdw_internal_set_std_avail(hdw);
1552
1553         if (std1) {
1554                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1555                 pvr2_trace(PVR2_TRACE_STD,
1556                            "Initial video standard forced to %.*s",
1557                            bcnt,buf);
1558                 hdw->std_mask_cur = std1;
1559                 hdw->std_dirty = !0;
1560                 pvr2_hdw_internal_find_stdenum(hdw);
1561                 return;
1562         }
1563
1564         {
1565                 unsigned int idx;
1566                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1567                         if (std_eeprom_maps[idx].msk ?
1568                             ((std_eeprom_maps[idx].pat ^
1569                              hdw->std_mask_eeprom) &
1570                              std_eeprom_maps[idx].msk) :
1571                             (std_eeprom_maps[idx].pat !=
1572                              hdw->std_mask_eeprom)) continue;
1573                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1574                                                   std_eeprom_maps[idx].std);
1575                         pvr2_trace(PVR2_TRACE_STD,
1576                                    "Initial video standard guessed as %.*s",
1577                                    bcnt,buf);
1578                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1579                         hdw->std_dirty = !0;
1580                         pvr2_hdw_internal_find_stdenum(hdw);
1581                         return;
1582                 }
1583         }
1584
1585         if (hdw->std_enum_cnt > 1) {
1586                 // Autoselect the first listed standard
1587                 hdw->std_enum_cur = 1;
1588                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1589                 hdw->std_dirty = !0;
1590                 pvr2_trace(PVR2_TRACE_STD,
1591                            "Initial video standard auto-selected to %s",
1592                            hdw->std_defs[hdw->std_enum_cur-1].name);
1593                 return;
1594         }
1595
1596         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1597                    "Unable to select a viable initial video standard");
1598 }
1599
1600
1601 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1602 {
1603         int ret;
1604         unsigned int idx;
1605         struct pvr2_ctrl *cptr;
1606         int reloadFl = 0;
1607         if (hdw->hdw_desc->fx2_firmware.cnt) {
1608                 if (!reloadFl) {
1609                         reloadFl =
1610                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1611                                  == 0);
1612                         if (reloadFl) {
1613                                 pvr2_trace(PVR2_TRACE_INIT,
1614                                            "USB endpoint config looks strange"
1615                                            "; possibly firmware needs to be"
1616                                            " loaded");
1617                         }
1618                 }
1619                 if (!reloadFl) {
1620                         reloadFl = !pvr2_hdw_check_firmware(hdw);
1621                         if (reloadFl) {
1622                                 pvr2_trace(PVR2_TRACE_INIT,
1623                                            "Check for FX2 firmware failed"
1624                                            "; possibly firmware needs to be"
1625                                            " loaded");
1626                         }
1627                 }
1628                 if (reloadFl) {
1629                         if (pvr2_upload_firmware1(hdw) != 0) {
1630                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1631                                            "Failure uploading firmware1");
1632                         }
1633                         return;
1634                 }
1635         }
1636         hdw->fw1_state = FW1_STATE_OK;
1637
1638         if (initusbreset) {
1639                 pvr2_hdw_device_reset(hdw);
1640         }
1641         if (!pvr2_hdw_dev_ok(hdw)) return;
1642
1643         for (idx = 0; idx < hdw->hdw_desc->client_modules.cnt; idx++) {
1644                 request_module(hdw->hdw_desc->client_modules.lst[idx]);
1645         }
1646
1647         if (!hdw->hdw_desc->flag_no_powerup) {
1648                 pvr2_hdw_cmd_powerup(hdw);
1649                 if (!pvr2_hdw_dev_ok(hdw)) return;
1650         }
1651
1652         // This step MUST happen after the earlier powerup step.
1653         pvr2_i2c_core_init(hdw);
1654         if (!pvr2_hdw_dev_ok(hdw)) return;
1655
1656         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1657                 cptr = hdw->controls + idx;
1658                 if (cptr->info->skip_init) continue;
1659                 if (!cptr->info->set_value) continue;
1660                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1661         }
1662
1663         /* Set up special default values for the television and radio
1664            frequencies here.  It's not really important what these defaults
1665            are, but I set them to something usable in the Chicago area just
1666            to make driver testing a little easier. */
1667
1668         /* US Broadcast channel 7 (175.25 MHz) */
1669         hdw->freqValTelevision = 175250000L;
1670         /* 104.3 MHz, a usable FM station for my area */
1671         hdw->freqValRadio = 104300000L;
1672
1673         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
1674         // thread-safe against the normal pvr2_send_request() mechanism.
1675         // (We should make it thread safe).
1676
1677         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
1678                 ret = pvr2_hdw_get_eeprom_addr(hdw);
1679                 if (!pvr2_hdw_dev_ok(hdw)) return;
1680                 if (ret < 0) {
1681                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1682                                    "Unable to determine location of eeprom,"
1683                                    " skipping");
1684                 } else {
1685                         hdw->eeprom_addr = ret;
1686                         pvr2_eeprom_analyze(hdw);
1687                         if (!pvr2_hdw_dev_ok(hdw)) return;
1688                 }
1689         } else {
1690                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
1691                 hdw->tuner_updated = !0;
1692                 hdw->std_mask_eeprom = V4L2_STD_ALL;
1693         }
1694
1695         pvr2_hdw_setup_std(hdw);
1696
1697         if (!get_default_tuner_type(hdw)) {
1698                 pvr2_trace(PVR2_TRACE_INIT,
1699                            "pvr2_hdw_setup: Tuner type overridden to %d",
1700                            hdw->tuner_type);
1701         }
1702
1703         pvr2_i2c_core_check_stale(hdw);
1704         hdw->tuner_updated = 0;
1705
1706         if (!pvr2_hdw_dev_ok(hdw)) return;
1707
1708         pvr2_hdw_commit_setup(hdw);
1709
1710         hdw->vid_stream = pvr2_stream_create();
1711         if (!pvr2_hdw_dev_ok(hdw)) return;
1712         pvr2_trace(PVR2_TRACE_INIT,
1713                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1714         if (hdw->vid_stream) {
1715                 idx = get_default_error_tolerance(hdw);
1716                 if (idx) {
1717                         pvr2_trace(PVR2_TRACE_INIT,
1718                                    "pvr2_hdw_setup: video stream %p"
1719                                    " setting tolerance %u",
1720                                    hdw->vid_stream,idx);
1721                 }
1722                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1723                                   PVR2_VID_ENDPOINT,idx);
1724         }
1725
1726         if (!pvr2_hdw_dev_ok(hdw)) return;
1727
1728         hdw->flag_init_ok = !0;
1729
1730         pvr2_hdw_state_sched(hdw);
1731 }
1732
1733
1734 /* Set up the structure and attempt to put the device into a usable state.
1735    This can be a time-consuming operation, which is why it is not done
1736    internally as part of the create() step. */
1737 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
1738 {
1739         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1740         do {
1741                 pvr2_hdw_setup_low(hdw);
1742                 pvr2_trace(PVR2_TRACE_INIT,
1743                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1744                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
1745                 if (pvr2_hdw_dev_ok(hdw)) {
1746                         if (hdw->flag_init_ok) {
1747                                 pvr2_trace(
1748                                         PVR2_TRACE_INFO,
1749                                         "Device initialization"
1750                                         " completed successfully.");
1751                                 break;
1752                         }
1753                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
1754                                 pvr2_trace(
1755                                         PVR2_TRACE_INFO,
1756                                         "Device microcontroller firmware"
1757                                         " (re)loaded; it should now reset"
1758                                         " and reconnect.");
1759                                 break;
1760                         }
1761                         pvr2_trace(
1762                                 PVR2_TRACE_ERROR_LEGS,
1763                                 "Device initialization was not successful.");
1764                         if (hdw->fw1_state == FW1_STATE_MISSING) {
1765                                 pvr2_trace(
1766                                         PVR2_TRACE_ERROR_LEGS,
1767                                         "Giving up since device"
1768                                         " microcontroller firmware"
1769                                         " appears to be missing.");
1770                                 break;
1771                         }
1772                 }
1773                 if (procreload) {
1774                         pvr2_trace(
1775                                 PVR2_TRACE_ERROR_LEGS,
1776                                 "Attempting pvrusb2 recovery by reloading"
1777                                 " primary firmware.");
1778                         pvr2_trace(
1779                                 PVR2_TRACE_ERROR_LEGS,
1780                                 "If this works, device should disconnect"
1781                                 " and reconnect in a sane state.");
1782                         hdw->fw1_state = FW1_STATE_UNKNOWN;
1783                         pvr2_upload_firmware1(hdw);
1784                 } else {
1785                         pvr2_trace(
1786                                 PVR2_TRACE_ERROR_LEGS,
1787                                 "***WARNING*** pvrusb2 device hardware"
1788                                 " appears to be jammed"
1789                                 " and I can't clear it.");
1790                         pvr2_trace(
1791                                 PVR2_TRACE_ERROR_LEGS,
1792                                 "You might need to power cycle"
1793                                 " the pvrusb2 device"
1794                                 " in order to recover.");
1795                 }
1796         } while (0);
1797         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1798 }
1799
1800
1801 /* Create and return a structure for interacting with the underlying
1802    hardware */
1803 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1804                                  const struct usb_device_id *devid)
1805 {
1806         unsigned int idx,cnt1,cnt2;
1807         struct pvr2_hdw *hdw;
1808         unsigned int hdw_type;
1809         int valid_std_mask;
1810         struct pvr2_ctrl *cptr;
1811         const struct pvr2_device_desc *hdw_desc;
1812         __u8 ifnum;
1813         struct v4l2_queryctrl qctrl;
1814         struct pvr2_ctl_info *ciptr;
1815
1816         hdw_type = devid - pvr2_device_table;
1817         if (hdw_type >= pvr2_device_count) {
1818                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1819                            "Bogus device type of %u reported",hdw_type);
1820                 return NULL;
1821         }
1822         hdw_desc = pvr2_device_descriptions + hdw_type;
1823
1824         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
1825         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1826                    hdw,hdw_desc->description);
1827         if (!hdw) goto fail;
1828
1829         init_timer(&hdw->quiescent_timer);
1830         hdw->quiescent_timer.data = (unsigned long)hdw;
1831         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
1832
1833         init_timer(&hdw->encoder_wait_timer);
1834         hdw->encoder_wait_timer.data = (unsigned long)hdw;
1835         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
1836
1837         hdw->master_state = PVR2_STATE_DEAD;
1838
1839         init_waitqueue_head(&hdw->state_wait_data);
1840
1841         hdw->tuner_signal_stale = !0;
1842         cx2341x_fill_defaults(&hdw->enc_ctl_state);
1843
1844         hdw->control_cnt = CTRLDEF_COUNT;
1845         hdw->control_cnt += MPEGDEF_COUNT;
1846         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1847                                 GFP_KERNEL);
1848         if (!hdw->controls) goto fail;
1849         hdw->hdw_desc = hdw_desc;
1850         for (idx = 0; idx < hdw->control_cnt; idx++) {
1851                 cptr = hdw->controls + idx;
1852                 cptr->hdw = hdw;
1853         }
1854         for (idx = 0; idx < 32; idx++) {
1855                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1856         }
1857         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1858                 cptr = hdw->controls + idx;
1859                 cptr->info = control_defs+idx;
1860         }
1861         /* Define and configure additional controls from cx2341x module. */
1862         hdw->mpeg_ctrl_info = kzalloc(
1863                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1864         if (!hdw->mpeg_ctrl_info) goto fail;
1865         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1866                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1867                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1868                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1869                 ciptr->name = mpeg_ids[idx].strid;
1870                 ciptr->v4l_id = mpeg_ids[idx].id;
1871                 ciptr->skip_init = !0;
1872                 ciptr->get_value = ctrl_cx2341x_get;
1873                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1874                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1875                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1876                 qctrl.id = ciptr->v4l_id;
1877                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1878                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1879                         ciptr->set_value = ctrl_cx2341x_set;
1880                 }
1881                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1882                         PVR2_CTLD_INFO_DESC_SIZE);
1883                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
1884                 ciptr->default_value = qctrl.default_value;
1885                 switch (qctrl.type) {
1886                 default:
1887                 case V4L2_CTRL_TYPE_INTEGER:
1888                         ciptr->type = pvr2_ctl_int;
1889                         ciptr->def.type_int.min_value = qctrl.minimum;
1890                         ciptr->def.type_int.max_value = qctrl.maximum;
1891                         break;
1892                 case V4L2_CTRL_TYPE_BOOLEAN:
1893                         ciptr->type = pvr2_ctl_bool;
1894                         break;
1895                 case V4L2_CTRL_TYPE_MENU:
1896                         ciptr->type = pvr2_ctl_enum;
1897                         ciptr->def.type_enum.value_names =
1898                                 cx2341x_ctrl_get_menu(ciptr->v4l_id);
1899                         for (cnt1 = 0;
1900                              ciptr->def.type_enum.value_names[cnt1] != NULL;
1901                              cnt1++) { }
1902                         ciptr->def.type_enum.count = cnt1;
1903                         break;
1904                 }
1905                 cptr->info = ciptr;
1906         }
1907
1908         // Initialize video standard enum dynamic control
1909         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1910         if (cptr) {
1911                 memcpy(&hdw->std_info_enum,cptr->info,
1912                        sizeof(hdw->std_info_enum));
1913                 cptr->info = &hdw->std_info_enum;
1914
1915         }
1916         // Initialize control data regarding video standard masks
1917         valid_std_mask = pvr2_std_get_usable();
1918         for (idx = 0; idx < 32; idx++) {
1919                 if (!(valid_std_mask & (1 << idx))) continue;
1920                 cnt1 = pvr2_std_id_to_str(
1921                         hdw->std_mask_names[idx],
1922                         sizeof(hdw->std_mask_names[idx])-1,
1923                         1 << idx);
1924                 hdw->std_mask_names[idx][cnt1] = 0;
1925         }
1926         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1927         if (cptr) {
1928                 memcpy(&hdw->std_info_avail,cptr->info,
1929                        sizeof(hdw->std_info_avail));
1930                 cptr->info = &hdw->std_info_avail;
1931                 hdw->std_info_avail.def.type_bitmask.bit_names =
1932                         hdw->std_mask_ptrs;
1933                 hdw->std_info_avail.def.type_bitmask.valid_bits =
1934                         valid_std_mask;
1935         }
1936         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1937         if (cptr) {
1938                 memcpy(&hdw->std_info_cur,cptr->info,
1939                        sizeof(hdw->std_info_cur));
1940                 cptr->info = &hdw->std_info_cur;
1941                 hdw->std_info_cur.def.type_bitmask.bit_names =
1942                         hdw->std_mask_ptrs;
1943                 hdw->std_info_avail.def.type_bitmask.valid_bits =
1944                         valid_std_mask;
1945         }
1946
1947         hdw->eeprom_addr = -1;
1948         hdw->unit_number = -1;
1949         hdw->v4l_minor_number_video = -1;
1950         hdw->v4l_minor_number_vbi = -1;
1951         hdw->v4l_minor_number_radio = -1;
1952         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1953         if (!hdw->ctl_write_buffer) goto fail;
1954         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1955         if (!hdw->ctl_read_buffer) goto fail;
1956         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
1957         if (!hdw->ctl_write_urb) goto fail;
1958         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
1959         if (!hdw->ctl_read_urb) goto fail;
1960
1961         mutex_lock(&pvr2_unit_mtx); do {
1962                 for (idx = 0; idx < PVR_NUM; idx++) {
1963                         if (unit_pointers[idx]) continue;
1964                         hdw->unit_number = idx;
1965                         unit_pointers[idx] = hdw;
1966                         break;
1967                 }
1968         } while (0); mutex_unlock(&pvr2_unit_mtx);
1969
1970         cnt1 = 0;
1971         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
1972         cnt1 += cnt2;
1973         if (hdw->unit_number >= 0) {
1974                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
1975                                  ('a' + hdw->unit_number));
1976                 cnt1 += cnt2;
1977         }
1978         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
1979         hdw->name[cnt1] = 0;
1980
1981         hdw->workqueue = create_singlethread_workqueue(hdw->name);
1982         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
1983         INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
1984         INIT_WORK(&hdw->workinit,pvr2_hdw_worker_init);
1985
1986         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
1987                    hdw->unit_number,hdw->name);
1988
1989         hdw->tuner_type = -1;
1990         hdw->flag_ok = !0;
1991
1992         hdw->usb_intf = intf;
1993         hdw->usb_dev = interface_to_usbdev(intf);
1994
1995         scnprintf(hdw->bus_info,sizeof(hdw->bus_info),
1996                   "usb %s address %d",
1997                   hdw->usb_dev->dev.bus_id,
1998                   hdw->usb_dev->devnum);
1999
2000         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2001         usb_set_interface(hdw->usb_dev,ifnum,0);
2002
2003         mutex_init(&hdw->ctl_lock_mutex);
2004         mutex_init(&hdw->big_lock_mutex);
2005
2006         queue_work(hdw->workqueue,&hdw->workinit);
2007         return hdw;
2008  fail:
2009         if (hdw) {
2010                 del_timer_sync(&hdw->quiescent_timer);
2011                 del_timer_sync(&hdw->encoder_wait_timer);
2012                 if (hdw->workqueue) {
2013                         flush_workqueue(hdw->workqueue);
2014                         destroy_workqueue(hdw->workqueue);
2015                         hdw->workqueue = NULL;
2016                 }
2017                 usb_free_urb(hdw->ctl_read_urb);
2018                 usb_free_urb(hdw->ctl_write_urb);
2019                 kfree(hdw->ctl_read_buffer);
2020                 kfree(hdw->ctl_write_buffer);
2021                 kfree(hdw->controls);
2022                 kfree(hdw->mpeg_ctrl_info);
2023                 kfree(hdw->std_defs);
2024                 kfree(hdw->std_enum_names);
2025                 kfree(hdw);
2026         }
2027         return NULL;
2028 }
2029
2030
2031 /* Remove _all_ associations between this driver and the underlying USB
2032    layer. */
2033 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2034 {
2035         if (hdw->flag_disconnected) return;
2036         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2037         if (hdw->ctl_read_urb) {
2038                 usb_kill_urb(hdw->ctl_read_urb);
2039                 usb_free_urb(hdw->ctl_read_urb);
2040                 hdw->ctl_read_urb = NULL;
2041         }
2042         if (hdw->ctl_write_urb) {
2043                 usb_kill_urb(hdw->ctl_write_urb);
2044                 usb_free_urb(hdw->ctl_write_urb);
2045                 hdw->ctl_write_urb = NULL;
2046         }
2047         if (hdw->ctl_read_buffer) {
2048                 kfree(hdw->ctl_read_buffer);
2049                 hdw->ctl_read_buffer = NULL;
2050         }
2051         if (hdw->ctl_write_buffer) {
2052                 kfree(hdw->ctl_write_buffer);
2053                 hdw->ctl_write_buffer = NULL;
2054         }
2055         hdw->flag_disconnected = !0;
2056         hdw->usb_dev = NULL;
2057         hdw->usb_intf = NULL;
2058         pvr2_hdw_render_useless(hdw);
2059 }
2060
2061
2062 /* Destroy hardware interaction structure */
2063 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2064 {
2065         if (!hdw) return;
2066         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2067         del_timer_sync(&hdw->quiescent_timer);
2068         del_timer_sync(&hdw->encoder_wait_timer);
2069         if (hdw->workqueue) {
2070                 flush_workqueue(hdw->workqueue);
2071                 destroy_workqueue(hdw->workqueue);
2072                 hdw->workqueue = NULL;
2073         }
2074         if (hdw->fw_buffer) {
2075                 kfree(hdw->fw_buffer);
2076                 hdw->fw_buffer = NULL;
2077         }
2078         if (hdw->vid_stream) {
2079                 pvr2_stream_destroy(hdw->vid_stream);
2080                 hdw->vid_stream = NULL;
2081         }
2082         if (hdw->decoder_ctrl) {
2083                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2084         }
2085         pvr2_i2c_core_done(hdw);
2086         pvr2_hdw_remove_usb_stuff(hdw);
2087         mutex_lock(&pvr2_unit_mtx); do {
2088                 if ((hdw->unit_number >= 0) &&
2089                     (hdw->unit_number < PVR_NUM) &&
2090                     (unit_pointers[hdw->unit_number] == hdw)) {
2091                         unit_pointers[hdw->unit_number] = NULL;
2092                 }
2093         } while (0); mutex_unlock(&pvr2_unit_mtx);
2094         kfree(hdw->controls);
2095         kfree(hdw->mpeg_ctrl_info);
2096         kfree(hdw->std_defs);
2097         kfree(hdw->std_enum_names);
2098         kfree(hdw);
2099 }
2100
2101
2102 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2103 {
2104         return (hdw && hdw->flag_ok);
2105 }
2106
2107
2108 /* Called when hardware has been unplugged */
2109 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2110 {
2111         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2112         LOCK_TAKE(hdw->big_lock);
2113         LOCK_TAKE(hdw->ctl_lock);
2114         pvr2_hdw_remove_usb_stuff(hdw);
2115         LOCK_GIVE(hdw->ctl_lock);
2116         LOCK_GIVE(hdw->big_lock);
2117 }
2118
2119
2120 // Attempt to autoselect an appropriate value for std_enum_cur given
2121 // whatever is currently in std_mask_cur
2122 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2123 {
2124         unsigned int idx;
2125         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2126                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2127                         hdw->std_enum_cur = idx;
2128                         return;
2129                 }
2130         }
2131         hdw->std_enum_cur = 0;
2132 }
2133
2134
2135 // Calculate correct set of enumerated standards based on currently known
2136 // set of available standards bits.
2137 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2138 {
2139         struct v4l2_standard *newstd;
2140         unsigned int std_cnt;
2141         unsigned int idx;
2142
2143         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2144
2145         if (hdw->std_defs) {
2146                 kfree(hdw->std_defs);
2147                 hdw->std_defs = NULL;
2148         }
2149         hdw->std_enum_cnt = 0;
2150         if (hdw->std_enum_names) {
2151                 kfree(hdw->std_enum_names);
2152                 hdw->std_enum_names = NULL;
2153         }
2154
2155         if (!std_cnt) {
2156                 pvr2_trace(
2157                         PVR2_TRACE_ERROR_LEGS,
2158                         "WARNING: Failed to identify any viable standards");
2159         }
2160         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2161         hdw->std_enum_names[0] = "none";
2162         for (idx = 0; idx < std_cnt; idx++) {
2163                 hdw->std_enum_names[idx+1] =
2164                         newstd[idx].name;
2165         }
2166         // Set up the dynamic control for this standard
2167         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2168         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2169         hdw->std_defs = newstd;
2170         hdw->std_enum_cnt = std_cnt+1;
2171         hdw->std_enum_cur = 0;
2172         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2173 }
2174
2175
2176 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2177                                struct v4l2_standard *std,
2178                                unsigned int idx)
2179 {
2180         int ret = -EINVAL;
2181         if (!idx) return ret;
2182         LOCK_TAKE(hdw->big_lock); do {
2183                 if (idx >= hdw->std_enum_cnt) break;
2184                 idx--;
2185                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2186                 ret = 0;
2187         } while (0); LOCK_GIVE(hdw->big_lock);
2188         return ret;
2189 }
2190
2191
2192 /* Get the number of defined controls */
2193 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2194 {
2195         return hdw->control_cnt;
2196 }
2197
2198
2199 /* Retrieve a control handle given its index (0..count-1) */
2200 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2201                                              unsigned int idx)
2202 {
2203         if (idx >= hdw->control_cnt) return NULL;
2204         return hdw->controls + idx;
2205 }
2206
2207
2208 /* Retrieve a control handle given its index (0..count-1) */
2209 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2210                                           unsigned int ctl_id)
2211 {
2212         struct pvr2_ctrl *cptr;
2213         unsigned int idx;
2214         int i;
2215
2216         /* This could be made a lot more efficient, but for now... */
2217         for (idx = 0; idx < hdw->control_cnt; idx++) {
2218                 cptr = hdw->controls + idx;
2219                 i = cptr->info->internal_id;
2220                 if (i && (i == ctl_id)) return cptr;
2221         }
2222         return NULL;
2223 }
2224
2225
2226 /* Given a V4L ID, retrieve the control structure associated with it. */
2227 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2228 {
2229         struct pvr2_ctrl *cptr;
2230         unsigned int idx;
2231         int i;
2232
2233         /* This could be made a lot more efficient, but for now... */
2234         for (idx = 0; idx < hdw->control_cnt; idx++) {
2235                 cptr = hdw->controls + idx;
2236                 i = cptr->info->v4l_id;
2237                 if (i && (i == ctl_id)) return cptr;
2238         }
2239         return NULL;
2240 }
2241
2242
2243 /* Given a V4L ID for its immediate predecessor, retrieve the control
2244    structure associated with it. */
2245 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2246                                             unsigned int ctl_id)
2247 {
2248         struct pvr2_ctrl *cptr,*cp2;
2249         unsigned int idx;
2250         int i;
2251
2252         /* This could be made a lot more efficient, but for now... */
2253         cp2 = NULL;
2254         for (idx = 0; idx < hdw->control_cnt; idx++) {
2255                 cptr = hdw->controls + idx;
2256                 i = cptr->info->v4l_id;
2257                 if (!i) continue;
2258                 if (i <= ctl_id) continue;
2259                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2260                 cp2 = cptr;
2261         }
2262         return cp2;
2263         return NULL;
2264 }
2265
2266
2267 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2268 {
2269         switch (tp) {
2270         case pvr2_ctl_int: return "integer";
2271         case pvr2_ctl_enum: return "enum";
2272         case pvr2_ctl_bool: return "boolean";
2273         case pvr2_ctl_bitmask: return "bitmask";
2274         }
2275         return "";
2276 }
2277
2278
2279 /* Figure out if we need to commit control changes.  If so, mark internal
2280    state flags to indicate this fact and return true.  Otherwise do nothing
2281    else and return false. */
2282 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2283 {
2284         unsigned int idx;
2285         struct pvr2_ctrl *cptr;
2286         int value;
2287         int commit_flag = 0;
2288         char buf[100];
2289         unsigned int bcnt,ccnt;
2290
2291         for (idx = 0; idx < hdw->control_cnt; idx++) {
2292                 cptr = hdw->controls + idx;
2293                 if (cptr->info->is_dirty == 0) continue;
2294                 if (!cptr->info->is_dirty(cptr)) continue;
2295                 commit_flag = !0;
2296
2297                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2298                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2299                                  cptr->info->name);
2300                 value = 0;
2301                 cptr->info->get_value(cptr,&value);
2302                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2303                                                 buf+bcnt,
2304                                                 sizeof(buf)-bcnt,&ccnt);
2305                 bcnt += ccnt;
2306                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2307                                   get_ctrl_typename(cptr->info->type));
2308                 pvr2_trace(PVR2_TRACE_CTL,
2309                            "/*--TRACE_COMMIT--*/ %.*s",
2310                            bcnt,buf);
2311         }
2312
2313         if (!commit_flag) {
2314                 /* Nothing has changed */
2315                 return 0;
2316         }
2317
2318         hdw->state_pipeline_config = 0;
2319         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2320         pvr2_hdw_state_sched(hdw);
2321
2322         return !0;
2323 }
2324
2325
2326 /* Perform all operations needed to commit all control changes.  This must
2327    be performed in synchronization with the pipeline state and is thus
2328    expected to be called as part of the driver's worker thread.  Return
2329    true if commit successful, otherwise return false to indicate that
2330    commit isn't possible at this time. */
2331 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
2332 {
2333         unsigned int idx;
2334         struct pvr2_ctrl *cptr;
2335         int disruptive_change;
2336
2337         /* When video standard changes, reset the hres and vres values -
2338            but if the user has pending changes there, then let the changes
2339            take priority. */
2340         if (hdw->std_dirty) {
2341                 /* Rewrite the vertical resolution to be appropriate to the
2342                    video standard that has been selected. */
2343                 int nvres;
2344                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2345                         nvres = 480;
2346                 } else {
2347                         nvres = 576;
2348                 }
2349                 if (nvres != hdw->res_ver_val) {
2350                         hdw->res_ver_val = nvres;
2351                         hdw->res_ver_dirty = !0;
2352                 }
2353         }
2354
2355         /* If any of the below has changed, then we can't do the update
2356            while the pipeline is running.  Pipeline must be paused first
2357            and decoder -> encoder connection be made quiescent before we
2358            can proceed. */
2359         disruptive_change =
2360                 (hdw->std_dirty ||
2361                  hdw->enc_unsafe_stale ||
2362                  hdw->srate_dirty ||
2363                  hdw->res_ver_dirty ||
2364                  hdw->res_hor_dirty ||
2365                  hdw->input_dirty ||
2366                  (hdw->active_stream_type != hdw->desired_stream_type));
2367         if (disruptive_change && !hdw->state_pipeline_idle) {
2368                 /* Pipeline is not idle; we can't proceed.  Arrange to
2369                    cause pipeline to stop so that we can try this again
2370                    later.... */
2371                 hdw->state_pipeline_pause = !0;
2372                 return 0;
2373         }
2374
2375         if (hdw->srate_dirty) {
2376                 /* Write new sample rate into control structure since
2377                  * the master copy is stale.  We must track srate
2378                  * separate from the mpeg control structure because
2379                  * other logic also uses this value. */
2380                 struct v4l2_ext_controls cs;
2381                 struct v4l2_ext_control c1;
2382                 memset(&cs,0,sizeof(cs));
2383                 memset(&c1,0,sizeof(c1));
2384                 cs.controls = &c1;
2385                 cs.count = 1;
2386                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2387                 c1.value = hdw->srate_val;
2388                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
2389         }
2390
2391         /* Scan i2c core at this point - before we clear all the dirty
2392            bits.  Various parts of the i2c core will notice dirty bits as
2393            appropriate and arrange to broadcast or directly send updates to
2394            the client drivers in order to keep everything in sync */
2395         pvr2_i2c_core_check_stale(hdw);
2396
2397         for (idx = 0; idx < hdw->control_cnt; idx++) {
2398                 cptr = hdw->controls + idx;
2399                 if (!cptr->info->clear_dirty) continue;
2400                 cptr->info->clear_dirty(cptr);
2401         }
2402
2403         if (hdw->active_stream_type != hdw->desired_stream_type) {
2404                 /* Handle any side effects of stream config here */
2405                 hdw->active_stream_type = hdw->desired_stream_type;
2406         }
2407
2408         /* Now execute i2c core update */
2409         pvr2_i2c_core_sync(hdw);
2410
2411         if (hdw->state_encoder_run) {
2412                 /* If encoder isn't running, then this will get worked out
2413                    later when we start the encoder. */
2414                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
2415         }
2416
2417         hdw->state_pipeline_config = !0;
2418         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2419         return !0;
2420 }
2421
2422
2423 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2424 {
2425         int fl;
2426         LOCK_TAKE(hdw->big_lock);
2427         fl = pvr2_hdw_commit_setup(hdw);
2428         LOCK_GIVE(hdw->big_lock);
2429         if (!fl) return 0;
2430         return pvr2_hdw_wait(hdw,0);
2431 }
2432
2433
2434 static void pvr2_hdw_worker_i2c(struct work_struct *work)
2435 {
2436         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
2437         LOCK_TAKE(hdw->big_lock); do {
2438                 pvr2_i2c_core_sync(hdw);
2439         } while (0); LOCK_GIVE(hdw->big_lock);
2440 }
2441
2442
2443 static void pvr2_hdw_worker_poll(struct work_struct *work)
2444 {
2445         int fl = 0;
2446         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
2447         LOCK_TAKE(hdw->big_lock); do {
2448                 fl = pvr2_hdw_state_eval(hdw);
2449         } while (0); LOCK_GIVE(hdw->big_lock);
2450         if (fl && hdw->state_func) {
2451                 hdw->state_func(hdw->state_data);
2452         }
2453 }
2454
2455
2456 static void pvr2_hdw_worker_init(struct work_struct *work)
2457 {
2458         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workinit);
2459         LOCK_TAKE(hdw->big_lock); do {
2460                 pvr2_hdw_setup(hdw);
2461         } while (0); LOCK_GIVE(hdw->big_lock);
2462 }
2463
2464
2465 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
2466 {
2467         return wait_event_interruptible(
2468                 hdw->state_wait_data,
2469                 (hdw->state_stale == 0) &&
2470                 (!state || (hdw->master_state != state)));
2471 }
2472
2473
2474 void pvr2_hdw_set_state_callback(struct pvr2_hdw *hdw,
2475                                  void (*callback_func)(void *),
2476                                  void *callback_data)
2477 {
2478         LOCK_TAKE(hdw->big_lock); do {
2479                 hdw->state_data = callback_data;
2480                 hdw->state_func = callback_func;
2481         } while (0); LOCK_GIVE(hdw->big_lock);
2482 }
2483
2484
2485 /* Return name for this driver instance */
2486 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2487 {
2488         return hdw->name;
2489 }
2490
2491
2492 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
2493 {
2494         return hdw->hdw_desc->description;
2495 }
2496
2497
2498 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
2499 {
2500         return hdw->hdw_desc->shortname;
2501 }
2502
2503
2504 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2505 {
2506         int result;
2507         LOCK_TAKE(hdw->ctl_lock); do {
2508                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
2509                 result = pvr2_send_request(hdw,
2510                                            hdw->cmd_buffer,1,
2511                                            hdw->cmd_buffer,1);
2512                 if (result < 0) break;
2513                 result = (hdw->cmd_buffer[0] != 0);
2514         } while(0); LOCK_GIVE(hdw->ctl_lock);
2515         return result;
2516 }
2517
2518
2519 /* Execute poll of tuner status */
2520 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
2521 {
2522         LOCK_TAKE(hdw->big_lock); do {
2523                 pvr2_i2c_core_status_poll(hdw);
2524         } while (0); LOCK_GIVE(hdw->big_lock);
2525 }
2526
2527
2528 /* Return information about the tuner */
2529 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
2530 {
2531         LOCK_TAKE(hdw->big_lock); do {
2532                 if (hdw->tuner_signal_stale) {
2533                         pvr2_i2c_core_status_poll(hdw);
2534                 }
2535                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
2536         } while (0); LOCK_GIVE(hdw->big_lock);
2537         return 0;
2538 }
2539
2540
2541 /* Get handle to video output stream */
2542 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2543 {
2544         return hp->vid_stream;
2545 }
2546
2547
2548 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2549 {
2550         int nr = pvr2_hdw_get_unit_number(hdw);
2551         LOCK_TAKE(hdw->big_lock); do {
2552                 hdw->log_requested = !0;
2553                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
2554                 pvr2_i2c_core_check_stale(hdw);
2555                 hdw->log_requested = 0;
2556                 pvr2_i2c_core_sync(hdw);
2557                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
2558                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
2559                 pvr2_hdw_state_log_state(hdw);
2560                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
2561         } while (0); LOCK_GIVE(hdw->big_lock);
2562 }
2563
2564
2565 /* Grab EEPROM contents, needed for direct method. */
2566 #define EEPROM_SIZE 8192
2567 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
2568 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
2569 {
2570         struct i2c_msg msg[2];
2571         u8 *eeprom;
2572         u8 iadd[2];
2573         u8 addr;
2574         u16 eepromSize;
2575         unsigned int offs;
2576         int ret;
2577         int mode16 = 0;
2578         unsigned pcnt,tcnt;
2579         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
2580         if (!eeprom) {
2581                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2582                            "Failed to allocate memory"
2583                            " required to read eeprom");
2584                 return NULL;
2585         }
2586
2587         trace_eeprom("Value for eeprom addr from controller was 0x%x",
2588                      hdw->eeprom_addr);
2589         addr = hdw->eeprom_addr;
2590         /* Seems that if the high bit is set, then the *real* eeprom
2591            address is shifted right now bit position (noticed this in
2592            newer PVR USB2 hardware) */
2593         if (addr & 0x80) addr >>= 1;
2594
2595         /* FX2 documentation states that a 16bit-addressed eeprom is
2596            expected if the I2C address is an odd number (yeah, this is
2597            strange but it's what they do) */
2598         mode16 = (addr & 1);
2599         eepromSize = (mode16 ? EEPROM_SIZE : 256);
2600         trace_eeprom("Examining %d byte eeprom at location 0x%x"
2601                      " using %d bit addressing",eepromSize,addr,
2602                      mode16 ? 16 : 8);
2603
2604         msg[0].addr = addr;
2605         msg[0].flags = 0;
2606         msg[0].len = mode16 ? 2 : 1;
2607         msg[0].buf = iadd;
2608         msg[1].addr = addr;
2609         msg[1].flags = I2C_M_RD;
2610
2611         /* We have to do the actual eeprom data fetch ourselves, because
2612            (1) we're only fetching part of the eeprom, and (2) if we were
2613            getting the whole thing our I2C driver can't grab it in one
2614            pass - which is what tveeprom is otherwise going to attempt */
2615         memset(eeprom,0,EEPROM_SIZE);
2616         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
2617                 pcnt = 16;
2618                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
2619                 offs = tcnt + (eepromSize - EEPROM_SIZE);
2620                 if (mode16) {
2621                         iadd[0] = offs >> 8;
2622                         iadd[1] = offs;
2623                 } else {
2624                         iadd[0] = offs;
2625                 }
2626                 msg[1].len = pcnt;
2627                 msg[1].buf = eeprom+tcnt;
2628                 if ((ret = i2c_transfer(&hdw->i2c_adap,
2629                                         msg,ARRAY_SIZE(msg))) != 2) {
2630                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2631                                    "eeprom fetch set offs err=%d",ret);
2632                         kfree(eeprom);
2633                         return NULL;
2634                 }
2635         }
2636         return eeprom;
2637 }
2638
2639
2640 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
2641                                 int prom_flag,
2642                                 int enable_flag)
2643 {
2644         int ret;
2645         u16 address;
2646         unsigned int pipe;
2647         LOCK_TAKE(hdw->big_lock); do {
2648                 if ((hdw->fw_buffer == 0) == !enable_flag) break;
2649
2650                 if (!enable_flag) {
2651                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2652                                    "Cleaning up after CPU firmware fetch");
2653                         kfree(hdw->fw_buffer);
2654                         hdw->fw_buffer = NULL;
2655                         hdw->fw_size = 0;
2656                         if (hdw->fw_cpu_flag) {
2657                                 /* Now release the CPU.  It will disconnect
2658                                    and reconnect later. */
2659                                 pvr2_hdw_cpureset_assert(hdw,0);
2660                         }
2661                         break;
2662                 }
2663
2664                 hdw->fw_cpu_flag = (prom_flag == 0);
2665                 if (hdw->fw_cpu_flag) {
2666                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2667                                    "Preparing to suck out CPU firmware");
2668                         hdw->fw_size = 0x2000;
2669                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
2670                         if (!hdw->fw_buffer) {
2671                                 hdw->fw_size = 0;
2672                                 break;
2673                         }
2674
2675                         /* We have to hold the CPU during firmware upload. */
2676                         pvr2_hdw_cpureset_assert(hdw,1);
2677
2678                         /* download the firmware from address 0000-1fff in 2048
2679                            (=0x800) bytes chunk. */
2680
2681                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2682                                    "Grabbing CPU firmware");
2683                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2684                         for(address = 0; address < hdw->fw_size;
2685                             address += 0x800) {
2686                                 ret = usb_control_msg(hdw->usb_dev,pipe,
2687                                                       0xa0,0xc0,
2688                                                       address,0,
2689                                                       hdw->fw_buffer+address,
2690                                                       0x800,HZ);
2691                                 if (ret < 0) break;
2692                         }
2693
2694                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2695                                    "Done grabbing CPU firmware");
2696                 } else {
2697                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2698                                    "Sucking down EEPROM contents");
2699                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
2700                         if (!hdw->fw_buffer) {
2701                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2702                                            "EEPROM content suck failed.");
2703                                 break;
2704                         }
2705                         hdw->fw_size = EEPROM_SIZE;
2706                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2707                                    "Done sucking down EEPROM contents");
2708                 }
2709
2710         } while (0); LOCK_GIVE(hdw->big_lock);
2711 }
2712
2713
2714 /* Return true if we're in a mode for retrieval CPU firmware */
2715 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2716 {
2717         return hdw->fw_buffer != 0;
2718 }
2719
2720
2721 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2722                        char *buf,unsigned int cnt)
2723 {
2724         int ret = -EINVAL;
2725         LOCK_TAKE(hdw->big_lock); do {
2726                 if (!buf) break;
2727                 if (!cnt) break;
2728
2729                 if (!hdw->fw_buffer) {
2730                         ret = -EIO;
2731                         break;
2732                 }
2733
2734                 if (offs >= hdw->fw_size) {
2735                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2736                                    "Read firmware data offs=%d EOF",
2737                                    offs);
2738                         ret = 0;
2739                         break;
2740                 }
2741
2742                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2743
2744                 memcpy(buf,hdw->fw_buffer+offs,cnt);
2745
2746                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2747                            "Read firmware data offs=%d cnt=%d",
2748                            offs,cnt);
2749                 ret = cnt;
2750         } while (0); LOCK_GIVE(hdw->big_lock);
2751
2752         return ret;
2753 }
2754
2755
2756 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
2757                                   enum pvr2_v4l_type index)
2758 {
2759         switch (index) {
2760         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
2761         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
2762         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
2763         default: return -1;
2764         }
2765 }
2766
2767
2768 /* Store a v4l minor device number */
2769 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
2770                                      enum pvr2_v4l_type index,int v)
2771 {
2772         switch (index) {
2773         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
2774         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
2775         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
2776         default: break;
2777         }
2778 }
2779
2780
2781 static void pvr2_ctl_write_complete(struct urb *urb)
2782 {
2783         struct pvr2_hdw *hdw = urb->context;
2784         hdw->ctl_write_pend_flag = 0;
2785         if (hdw->ctl_read_pend_flag) return;
2786         complete(&hdw->ctl_done);
2787 }
2788
2789
2790 static void pvr2_ctl_read_complete(struct urb *urb)
2791 {
2792         struct pvr2_hdw *hdw = urb->context;
2793         hdw->ctl_read_pend_flag = 0;
2794         if (hdw->ctl_write_pend_flag) return;
2795         complete(&hdw->ctl_done);
2796 }
2797
2798
2799 static void pvr2_ctl_timeout(unsigned long data)
2800 {
2801         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2802         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2803                 hdw->ctl_timeout_flag = !0;
2804                 if (hdw->ctl_write_pend_flag)
2805                         usb_unlink_urb(hdw->ctl_write_urb);
2806                 if (hdw->ctl_read_pend_flag)
2807                         usb_unlink_urb(hdw->ctl_read_urb);
2808         }
2809 }
2810
2811
2812 /* Issue a command and get a response from the device.  This extended
2813    version includes a probe flag (which if set means that device errors
2814    should not be logged or treated as fatal) and a timeout in jiffies.
2815    This can be used to non-lethally probe the health of endpoint 1. */
2816 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2817                                 unsigned int timeout,int probe_fl,
2818                                 void *write_data,unsigned int write_len,
2819                                 void *read_data,unsigned int read_len)
2820 {
2821         unsigned int idx;
2822         int status = 0;
2823         struct timer_list timer;
2824         if (!hdw->ctl_lock_held) {
2825                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2826                            "Attempted to execute control transfer"
2827                            " without lock!!");
2828                 return -EDEADLK;
2829         }
2830         if (!hdw->flag_ok && !probe_fl) {
2831                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2832                            "Attempted to execute control transfer"
2833                            " when device not ok");
2834                 return -EIO;
2835         }
2836         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2837                 if (!probe_fl) {
2838                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2839                                    "Attempted to execute control transfer"
2840                                    " when USB is disconnected");
2841                 }
2842                 return -ENOTTY;
2843         }
2844
2845         /* Ensure that we have sane parameters */
2846         if (!write_data) write_len = 0;
2847         if (!read_data) read_len = 0;
2848         if (write_len > PVR2_CTL_BUFFSIZE) {
2849                 pvr2_trace(
2850                         PVR2_TRACE_ERROR_LEGS,
2851                         "Attempted to execute %d byte"
2852                         " control-write transfer (limit=%d)",
2853                         write_len,PVR2_CTL_BUFFSIZE);
2854                 return -EINVAL;
2855         }
2856         if (read_len > PVR2_CTL_BUFFSIZE) {
2857                 pvr2_trace(
2858                         PVR2_TRACE_ERROR_LEGS,
2859                         "Attempted to execute %d byte"
2860                         " control-read transfer (limit=%d)",
2861                         write_len,PVR2_CTL_BUFFSIZE);
2862                 return -EINVAL;
2863         }
2864         if ((!write_len) && (!read_len)) {
2865                 pvr2_trace(
2866                         PVR2_TRACE_ERROR_LEGS,
2867                         "Attempted to execute null control transfer?");
2868                 return -EINVAL;
2869         }
2870
2871
2872         hdw->cmd_debug_state = 1;
2873         if (write_len) {
2874                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2875         } else {
2876                 hdw->cmd_debug_code = 0;
2877         }
2878         hdw->cmd_debug_write_len = write_len;
2879         hdw->cmd_debug_read_len = read_len;
2880
2881         /* Initialize common stuff */
2882         init_completion(&hdw->ctl_done);
2883         hdw->ctl_timeout_flag = 0;
2884         hdw->ctl_write_pend_flag = 0;
2885         hdw->ctl_read_pend_flag = 0;
2886         init_timer(&timer);
2887         timer.expires = jiffies + timeout;
2888         timer.data = (unsigned long)hdw;
2889         timer.function = pvr2_ctl_timeout;
2890
2891         if (write_len) {
2892                 hdw->cmd_debug_state = 2;
2893                 /* Transfer write data to internal buffer */
2894                 for (idx = 0; idx < write_len; idx++) {
2895                         hdw->ctl_write_buffer[idx] =
2896                                 ((unsigned char *)write_data)[idx];
2897                 }
2898                 /* Initiate a write request */
2899                 usb_fill_bulk_urb(hdw->ctl_write_urb,
2900                                   hdw->usb_dev,
2901                                   usb_sndbulkpipe(hdw->usb_dev,
2902                                                   PVR2_CTL_WRITE_ENDPOINT),
2903                                   hdw->ctl_write_buffer,
2904                                   write_len,
2905                                   pvr2_ctl_write_complete,
2906                                   hdw);
2907                 hdw->ctl_write_urb->actual_length = 0;
2908                 hdw->ctl_write_pend_flag = !0;
2909                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2910                 if (status < 0) {
2911                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2912                                    "Failed to submit write-control"
2913                                    " URB status=%d",status);
2914                         hdw->ctl_write_pend_flag = 0;
2915                         goto done;
2916                 }
2917         }
2918
2919         if (read_len) {
2920                 hdw->cmd_debug_state = 3;
2921                 memset(hdw->ctl_read_buffer,0x43,read_len);
2922                 /* Initiate a read request */
2923                 usb_fill_bulk_urb(hdw->ctl_read_urb,
2924                                   hdw->usb_dev,
2925                                   usb_rcvbulkpipe(hdw->usb_dev,
2926                                                   PVR2_CTL_READ_ENDPOINT),
2927                                   hdw->ctl_read_buffer,
2928                                   read_len,
2929                                   pvr2_ctl_read_complete,
2930                                   hdw);
2931                 hdw->ctl_read_urb->actual_length = 0;
2932                 hdw->ctl_read_pend_flag = !0;
2933                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2934                 if (status < 0) {
2935                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2936                                    "Failed to submit read-control"
2937                                    " URB status=%d",status);
2938                         hdw->ctl_read_pend_flag = 0;
2939                         goto done;
2940                 }
2941         }
2942
2943         /* Start timer */
2944         add_timer(&timer);
2945
2946         /* Now wait for all I/O to complete */
2947         hdw->cmd_debug_state = 4;
2948         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2949                 wait_for_completion(&hdw->ctl_done);
2950         }
2951         hdw->cmd_debug_state = 5;
2952
2953         /* Stop timer */
2954         del_timer_sync(&timer);
2955
2956         hdw->cmd_debug_state = 6;
2957         status = 0;
2958
2959         if (hdw->ctl_timeout_flag) {
2960                 status = -ETIMEDOUT;
2961                 if (!probe_fl) {
2962                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2963                                    "Timed out control-write");
2964                 }
2965                 goto done;
2966         }
2967
2968         if (write_len) {
2969                 /* Validate results of write request */
2970                 if ((hdw->ctl_write_urb->status != 0) &&
2971                     (hdw->ctl_write_urb->status != -ENOENT) &&
2972                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2973                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
2974                         /* USB subsystem is reporting some kind of failure
2975                            on the write */
2976                         status = hdw->ctl_write_urb->status;
2977                         if (!probe_fl) {
2978                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2979                                            "control-write URB failure,"
2980                                            " status=%d",
2981                                            status);
2982                         }
2983                         goto done;
2984                 }
2985                 if (hdw->ctl_write_urb->actual_length < write_len) {
2986                         /* Failed to write enough data */
2987                         status = -EIO;
2988                         if (!probe_fl) {
2989                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2990                                            "control-write URB short,"
2991                                            " expected=%d got=%d",
2992                                            write_len,
2993                                            hdw->ctl_write_urb->actual_length);
2994                         }
2995                         goto done;
2996                 }
2997         }
2998         if (read_len) {
2999                 /* Validate results of read request */
3000                 if ((hdw->ctl_read_urb->status != 0) &&
3001                     (hdw->ctl_read_urb->status != -ENOENT) &&
3002                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3003                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3004                         /* USB subsystem is reporting some kind of failure
3005                            on the read */
3006                         status = hdw->ctl_read_urb->status;
3007                         if (!probe_fl) {
3008                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3009                                            "control-read URB failure,"
3010                                            " status=%d",
3011                                            status);
3012                         }
3013                         goto done;
3014                 }
3015                 if (hdw->ctl_read_urb->actual_length < read_len) {
3016                         /* Failed to read enough data */
3017                         status = -EIO;
3018                         if (!probe_fl) {
3019                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3020                                            "control-read URB short,"
3021                                            " expected=%d got=%d",
3022                                            read_len,
3023                                            hdw->ctl_read_urb->actual_length);
3024                         }
3025                         goto done;
3026                 }
3027                 /* Transfer retrieved data out from internal buffer */
3028                 for (idx = 0; idx < read_len; idx++) {
3029                         ((unsigned char *)read_data)[idx] =
3030                                 hdw->ctl_read_buffer[idx];
3031                 }
3032         }
3033
3034  done:
3035
3036         hdw->cmd_debug_state = 0;
3037         if ((status < 0) && (!probe_fl)) {
3038                 pvr2_hdw_render_useless(hdw);
3039         }
3040         return status;
3041 }
3042
3043
3044 int pvr2_send_request(struct pvr2_hdw *hdw,
3045                       void *write_data,unsigned int write_len,
3046                       void *read_data,unsigned int read_len)
3047 {
3048         return pvr2_send_request_ex(hdw,HZ*4,0,
3049                                     write_data,write_len,
3050                                     read_data,read_len);
3051 }
3052
3053 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3054 {
3055         int ret;
3056
3057         LOCK_TAKE(hdw->ctl_lock);
3058
3059         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3060         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3061         hdw->cmd_buffer[5] = 0;
3062         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3063         hdw->cmd_buffer[7] = reg & 0xff;
3064
3065
3066         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3067
3068         LOCK_GIVE(hdw->ctl_lock);
3069
3070         return ret;
3071 }
3072
3073
3074 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3075 {
3076         int ret = 0;
3077
3078         LOCK_TAKE(hdw->ctl_lock);
3079
3080         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3081         hdw->cmd_buffer[1] = 0;
3082         hdw->cmd_buffer[2] = 0;
3083         hdw->cmd_buffer[3] = 0;
3084         hdw->cmd_buffer[4] = 0;
3085         hdw->cmd_buffer[5] = 0;
3086         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3087         hdw->cmd_buffer[7] = reg & 0xff;
3088
3089         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3090         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3091
3092         LOCK_GIVE(hdw->ctl_lock);
3093
3094         return ret;
3095 }
3096
3097
3098 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3099 {
3100         if (!hdw->flag_ok) return;
3101         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3102                    "Device being rendered inoperable");
3103         if (hdw->vid_stream) {
3104                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3105         }
3106         hdw->flag_ok = 0;
3107         trace_stbit("flag_ok",hdw->flag_ok);
3108         pvr2_hdw_state_sched(hdw);
3109 }
3110
3111
3112 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3113 {
3114         int ret;
3115         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3116         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3117         if (ret == 1) {
3118                 ret = usb_reset_device(hdw->usb_dev);
3119                 usb_unlock_device(hdw->usb_dev);
3120         } else {
3121                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3122                            "Failed to lock USB device ret=%d",ret);
3123         }
3124         if (init_pause_msec) {
3125                 pvr2_trace(PVR2_TRACE_INFO,
3126                            "Waiting %u msec for hardware to settle",
3127                            init_pause_msec);
3128                 msleep(init_pause_msec);
3129         }
3130
3131 }
3132
3133
3134 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3135 {
3136         char da[1];
3137         unsigned int pipe;
3138         int ret;
3139
3140         if (!hdw->usb_dev) return;
3141
3142         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3143
3144         da[0] = val ? 0x01 : 0x00;
3145
3146         /* Write the CPUCS register on the 8051.  The lsb of the register
3147            is the reset bit; a 1 asserts reset while a 0 clears it. */
3148         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3149         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3150         if (ret < 0) {
3151                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3152                            "cpureset_assert(%d) error=%d",val,ret);
3153                 pvr2_hdw_render_useless(hdw);
3154         }
3155 }
3156
3157
3158 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3159 {
3160         int status;
3161         LOCK_TAKE(hdw->ctl_lock); do {
3162                 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
3163                 hdw->cmd_buffer[0] = FX2CMD_DEEP_RESET;
3164                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3165         } while (0); LOCK_GIVE(hdw->ctl_lock);
3166         return status;
3167 }
3168
3169
3170 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3171 {
3172         int status;
3173         LOCK_TAKE(hdw->ctl_lock); do {
3174                 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
3175                 hdw->cmd_buffer[0] = FX2CMD_POWER_ON;
3176                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3177         } while (0); LOCK_GIVE(hdw->ctl_lock);
3178         return status;
3179 }
3180
3181
3182 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3183 {
3184         if (!hdw->decoder_ctrl) {
3185                 pvr2_trace(PVR2_TRACE_INIT,
3186                            "Unable to reset decoder: nothing attached");
3187                 return -ENOTTY;
3188         }
3189
3190         if (!hdw->decoder_ctrl->force_reset) {
3191                 pvr2_trace(PVR2_TRACE_INIT,
3192                            "Unable to reset decoder: not implemented");
3193                 return -ENOTTY;
3194         }
3195
3196         pvr2_trace(PVR2_TRACE_INIT,
3197                    "Requesting decoder reset");
3198         hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3199         return 0;
3200 }
3201
3202
3203 /* Stop / start video stream transport */
3204 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
3205 {
3206         int status;
3207         LOCK_TAKE(hdw->ctl_lock); do {
3208                 hdw->cmd_buffer[0] =
3209                         (runFl ? FX2CMD_STREAMING_ON : FX2CMD_STREAMING_OFF);
3210                 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3211         } while (0); LOCK_GIVE(hdw->ctl_lock);
3212         return status;
3213 }
3214
3215
3216 /* Evaluate whether or not state_encoder_ok can change */
3217 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
3218 {
3219         if (hdw->state_encoder_ok) return 0;
3220         if (hdw->flag_tripped) return 0;
3221         if (hdw->state_encoder_run) return 0;
3222         if (hdw->state_encoder_config) return 0;
3223         if (hdw->state_decoder_run) return 0;
3224         if (hdw->state_usbstream_run) return 0;
3225         if (pvr2_upload_firmware2(hdw) < 0) {
3226                 hdw->flag_tripped = !0;
3227                 trace_stbit("flag_tripped",hdw->flag_tripped);
3228                 return !0;
3229         }
3230         hdw->state_encoder_ok = !0;
3231         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
3232         return !0;
3233 }
3234
3235
3236 /* Evaluate whether or not state_encoder_config can change */
3237 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
3238 {
3239         if (hdw->state_encoder_config) {
3240                 if (hdw->state_encoder_ok) {
3241                         if (hdw->state_pipeline_req &&
3242                             !hdw->state_pipeline_pause) return 0;
3243                 }
3244                 hdw->state_encoder_config = 0;
3245                 hdw->state_encoder_waitok = 0;
3246                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3247                 /* paranoia - solve race if timer just completed */
3248                 del_timer_sync(&hdw->encoder_wait_timer);
3249         } else {
3250                 if (!hdw->state_encoder_ok ||
3251                     !hdw->state_pipeline_idle ||
3252                     hdw->state_pipeline_pause ||
3253                     !hdw->state_pipeline_req ||
3254                     !hdw->state_pipeline_config) {
3255                         /* We must reset the enforced wait interval if
3256                            anything has happened that might have disturbed
3257                            the encoder.  This should be a rare case. */
3258                         if (timer_pending(&hdw->encoder_wait_timer)) {
3259                                 del_timer_sync(&hdw->encoder_wait_timer);
3260                         }
3261                         if (hdw->state_encoder_waitok) {
3262                                 /* Must clear the state - therefore we did
3263                                    something to a state bit and must also
3264                                    return true. */
3265                                 hdw->state_encoder_waitok = 0;
3266                                 trace_stbit("state_encoder_waitok",
3267                                             hdw->state_encoder_waitok);
3268                                 return !0;
3269                         }
3270                         return 0;
3271                 }
3272                 if (!hdw->state_encoder_waitok) {
3273                         if (!timer_pending(&hdw->encoder_wait_timer)) {
3274                                 /* waitok flag wasn't set and timer isn't
3275                                    running.  Check flag once more to avoid
3276                                    a race then start the timer.  This is
3277                                    the point when we measure out a minimal
3278                                    quiet interval before doing something to
3279                                    the encoder. */
3280                                 if (!hdw->state_encoder_waitok) {
3281                                         hdw->encoder_wait_timer.expires =
3282                                                 jiffies + (HZ*50/1000);
3283                                         add_timer(&hdw->encoder_wait_timer);
3284                                 }
3285                         }
3286                         /* We can't continue until we know we have been
3287                            quiet for the interval measured by this
3288                            timer. */
3289                         return 0;
3290                 }
3291                 pvr2_encoder_configure(hdw);
3292                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
3293         }
3294         trace_stbit("state_encoder_config",hdw->state_encoder_config);
3295         return !0;
3296 }
3297
3298
3299 /* Evaluate whether or not state_encoder_run can change */
3300 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
3301 {
3302         if (hdw->state_encoder_run) {
3303                 if (hdw->state_encoder_ok) {
3304                         if (hdw->state_decoder_run) return 0;
3305                         if (pvr2_encoder_stop(hdw) < 0) return !0;
3306                 }
3307                 hdw->state_encoder_run = 0;
3308         } else {
3309                 if (!hdw->state_encoder_ok) return 0;
3310                 if (!hdw->state_decoder_run) return 0;
3311                 if (pvr2_encoder_start(hdw) < 0) return !0;
3312                 hdw->state_encoder_run = !0;
3313         }
3314         trace_stbit("state_encoder_run",hdw->state_encoder_run);
3315         return !0;
3316 }
3317
3318
3319 /* Timeout function for quiescent timer. */
3320 static void pvr2_hdw_quiescent_timeout(unsigned long data)
3321 {
3322         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3323         hdw->state_decoder_quiescent = !0;
3324         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3325         hdw->state_stale = !0;
3326         queue_work(hdw->workqueue,&hdw->workpoll);
3327 }
3328
3329
3330 /* Timeout function for encoder wait timer. */
3331 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
3332 {
3333         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3334         hdw->state_encoder_waitok = !0;
3335         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3336         hdw->state_stale = !0;
3337         queue_work(hdw->workqueue,&hdw->workpoll);
3338 }
3339
3340
3341 /* Evaluate whether or not state_decoder_run can change */
3342 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
3343 {
3344         if (hdw->state_decoder_run) {
3345                 if (hdw->state_encoder_ok) {
3346                         if (hdw->state_pipeline_req &&
3347                             !hdw->state_pipeline_pause) return 0;
3348                 }
3349                 if (!hdw->flag_decoder_missed) {
3350                         pvr2_decoder_enable(hdw,0);
3351                 }
3352                 hdw->state_decoder_quiescent = 0;
3353                 hdw->state_decoder_run = 0;
3354                 /* paranoia - solve race if timer just completed */
3355                 del_timer_sync(&hdw->quiescent_timer);
3356         } else {
3357                 if (!hdw->state_decoder_quiescent) {
3358                         if (!timer_pending(&hdw->quiescent_timer)) {
3359                                 /* We don't do something about the
3360                                    quiescent timer until right here because
3361                                    we also want to catch cases where the
3362                                    decoder was already not running (like
3363                                    after initialization) as opposed to
3364                                    knowing that we had just stopped it.
3365                                    The second flag check is here to cover a
3366                                    race - the timer could have run and set
3367                                    this flag just after the previous check
3368                                    but before we did the pending check. */
3369                                 if (!hdw->state_decoder_quiescent) {
3370                                         hdw->quiescent_timer.expires =
3371                                                 jiffies + (HZ*50/1000);
3372                                         add_timer(&hdw->quiescent_timer);
3373                                 }
3374                         }
3375                         /* Don't allow decoder to start again until it has
3376                            been quiesced first.  This little detail should
3377                            hopefully further stabilize the encoder. */
3378                         return 0;
3379                 }
3380                 if (!hdw->state_pipeline_req ||
3381                     hdw->state_pipeline_pause ||
3382                     !hdw->state_pipeline_config ||
3383                     !hdw->state_encoder_config ||
3384                     !hdw->state_encoder_ok) return 0;
3385                 del_timer_sync(&hdw->quiescent_timer);
3386                 if (hdw->flag_decoder_missed) return 0;
3387                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
3388                 hdw->state_decoder_quiescent = 0;
3389                 hdw->state_decoder_run = !0;
3390         }
3391         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3392         trace_stbit("state_decoder_run",hdw->state_decoder_run);
3393         return !0;
3394 }
3395
3396
3397 /* Evaluate whether or not state_usbstream_run can change */
3398 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
3399 {
3400         if (hdw->state_usbstream_run) {
3401                 if (hdw->state_encoder_ok) {
3402                         if (hdw->state_encoder_run) return 0;
3403                 }
3404                 pvr2_hdw_cmd_usbstream(hdw,0);
3405                 hdw->state_usbstream_run = 0;
3406         } else {
3407                 if (!hdw->state_encoder_ok ||
3408                     !hdw->state_encoder_run ||
3409                     !hdw->state_pipeline_req ||
3410                     hdw->state_pipeline_pause) return 0;
3411                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
3412                 hdw->state_usbstream_run = !0;
3413         }
3414         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
3415         return !0;
3416 }
3417
3418
3419 /* Attempt to configure pipeline, if needed */
3420 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
3421 {
3422         if (hdw->state_pipeline_config ||
3423             hdw->state_pipeline_pause) return 0;
3424         pvr2_hdw_commit_execute(hdw);
3425         return !0;
3426 }
3427
3428
3429 /* Update pipeline idle and pipeline pause tracking states based on other
3430    inputs.  This must be called whenever the other relevant inputs have
3431    changed. */
3432 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
3433 {
3434         unsigned int st;
3435         int updatedFl = 0;
3436         /* Update pipeline state */
3437         st = !(hdw->state_encoder_run ||
3438                hdw->state_decoder_run ||
3439                hdw->state_usbstream_run ||
3440                (!hdw->state_decoder_quiescent));
3441         if (!st != !hdw->state_pipeline_idle) {
3442                 hdw->state_pipeline_idle = st;
3443                 updatedFl = !0;
3444         }
3445         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
3446                 hdw->state_pipeline_pause = 0;
3447                 updatedFl = !0;
3448         }
3449         return updatedFl;
3450 }
3451
3452
3453 typedef int (*state_eval_func)(struct pvr2_hdw *);
3454
3455 /* Set of functions to be run to evaluate various states in the driver. */
3456 const static state_eval_func eval_funcs[] = {
3457         state_eval_pipeline_config,
3458         state_eval_encoder_ok,
3459         state_eval_encoder_config,
3460         state_eval_decoder_run,
3461         state_eval_encoder_run,
3462         state_eval_usbstream_run,
3463 };
3464
3465
3466 /* Process various states and return true if we did anything interesting. */
3467 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
3468 {
3469         unsigned int i;
3470         int state_updated = 0;
3471         int check_flag;
3472
3473         if (!hdw->state_stale) return 0;
3474         if ((hdw->fw1_state != FW1_STATE_OK) ||
3475             !hdw->flag_ok) {
3476                 hdw->state_stale = 0;
3477                 return !0;
3478         }
3479         /* This loop is the heart of the entire driver.  It keeps trying to
3480            evaluate various bits of driver state until nothing changes for
3481            one full iteration.  Each "bit of state" tracks some global
3482            aspect of the driver, e.g. whether decoder should run, if
3483            pipeline is configured, usb streaming is on, etc.  We separately
3484            evaluate each of those questions based on other driver state to
3485            arrive at the correct running configuration. */
3486         do {
3487                 check_flag = 0;
3488                 state_update_pipeline_state(hdw);
3489                 /* Iterate over each bit of state */
3490                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
3491                         if ((*eval_funcs[i])(hdw)) {
3492                                 check_flag = !0;
3493                                 state_updated = !0;
3494                                 state_update_pipeline_state(hdw);
3495                         }
3496                 }
3497         } while (check_flag && hdw->flag_ok);
3498         hdw->state_stale = 0;
3499         trace_stbit("state_stale",hdw->state_stale);
3500         return state_updated;
3501 }
3502
3503
3504 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
3505                                              char *buf,unsigned int acnt)
3506 {
3507         switch (which) {
3508         case 0:
3509                 return scnprintf(
3510                         buf,acnt,
3511                         "driver:%s%s%s%s%s",
3512                         (hdw->flag_ok ? " <ok>" : " <fail>"),
3513                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
3514                         (hdw->flag_disconnected ? " <disconnected>" :
3515                          " <connected>"),
3516                         (hdw->flag_tripped ? " <tripped>" : ""),
3517                         (hdw->flag_decoder_missed ? " <no decoder>" : ""));
3518         case 1:
3519                 return scnprintf(
3520                         buf,acnt,
3521                         "pipeline:%s%s%s%s",
3522                         (hdw->state_pipeline_idle ? " <idle>" : ""),
3523                         (hdw->state_pipeline_config ?
3524                          " <configok>" : " <stale>"),
3525                         (hdw->state_pipeline_req ? " <req>" : ""),
3526                         (hdw->state_pipeline_pause ? " <pause>" : ""));
3527         case 2:
3528                 return scnprintf(
3529                         buf,acnt,
3530                         "worker:%s%s%s%s%s%s",
3531                         (hdw->state_decoder_run ?
3532                          " <decode:run>" :
3533                          (hdw->state_decoder_quiescent ?
3534                           "" : " <decode:stop>")),
3535                         (hdw->state_decoder_quiescent ?
3536                          " <decode:quiescent>" : ""),
3537                         (hdw->state_encoder_ok ?
3538                          "" : " <encode:init>"),
3539                         (hdw->state_encoder_run ?
3540                          " <encode:run>" : " <encode:stop>"),
3541                         (hdw->state_encoder_config ?
3542                          " <encode:configok>" :
3543                          (hdw->state_encoder_waitok ?
3544                           "" : " <encode:wait>")),
3545                         (hdw->state_usbstream_run ?
3546                          " <usb:run>" : " <usb:stop>"));
3547                 break;
3548         case 3:
3549                 return scnprintf(
3550                         buf,acnt,
3551                         "state: %s",
3552                         pvr2_get_state_name(hdw->master_state));
3553                 break;
3554         default: break;
3555         }
3556         return 0;
3557 }
3558
3559
3560 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
3561                                    char *buf,unsigned int acnt)
3562 {
3563         unsigned int bcnt,ccnt,idx;
3564         bcnt = 0;
3565         LOCK_TAKE(hdw->big_lock);
3566         for (idx = 0; ; idx++) {
3567                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
3568                 if (!ccnt) break;
3569                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
3570                 if (!acnt) break;
3571                 buf[0] = '\n'; ccnt = 1;
3572                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
3573         }
3574         LOCK_GIVE(hdw->big_lock);
3575         return bcnt;
3576 }
3577
3578
3579 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
3580 {
3581         char buf[128];
3582         unsigned int idx,ccnt;
3583
3584         for (idx = 0; ; idx++) {
3585                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
3586                 if (!ccnt) break;
3587                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
3588         }
3589 }
3590
3591
3592 /* Evaluate and update the driver's current state, taking various actions
3593    as appropriate for the update. */
3594 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
3595 {
3596         unsigned int st;
3597         int state_updated = 0;
3598         int callback_flag = 0;
3599
3600         pvr2_trace(PVR2_TRACE_STBITS,
3601                    "Drive state check START");
3602         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
3603                 pvr2_hdw_state_log_state(hdw);
3604         }
3605
3606         /* Process all state and get back over disposition */
3607         state_updated = pvr2_hdw_state_update(hdw);
3608
3609         /* Update master state based upon all other states. */
3610         if (!hdw->flag_ok) {
3611                 st = PVR2_STATE_DEAD;
3612         } else if (hdw->fw1_state != FW1_STATE_OK) {
3613                 st = PVR2_STATE_COLD;
3614         } else if (!hdw->state_encoder_ok) {
3615                 st = PVR2_STATE_WARM;
3616         } else if (hdw->flag_tripped || hdw->flag_decoder_missed) {
3617                 st = PVR2_STATE_ERROR;
3618         } else if (hdw->state_encoder_run &&
3619                    hdw->state_decoder_run &&
3620                    hdw->state_usbstream_run) {
3621                 st = PVR2_STATE_RUN;
3622         } else {
3623                 st = PVR2_STATE_READY;
3624         }
3625         if (hdw->master_state != st) {
3626                 pvr2_trace(PVR2_TRACE_STATE,
3627                            "Device state change from %s to %s",
3628                            pvr2_get_state_name(hdw->master_state),
3629                            pvr2_get_state_name(st));
3630                 hdw->master_state = st;
3631                 state_updated = !0;
3632                 callback_flag = !0;
3633         }
3634         if (state_updated) {
3635                 /* Trigger anyone waiting on any state changes here. */
3636                 wake_up(&hdw->state_wait_data);
3637         }
3638
3639         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
3640                 pvr2_hdw_state_log_state(hdw);
3641         }
3642         pvr2_trace(PVR2_TRACE_STBITS,
3643                    "Drive state check DONE callback=%d",callback_flag);
3644
3645         return callback_flag;
3646 }
3647
3648
3649 /* Cause kernel thread to check / update driver state */
3650 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
3651 {
3652         if (hdw->state_stale) return;
3653         hdw->state_stale = !0;
3654         trace_stbit("state_stale",hdw->state_stale);
3655         queue_work(hdw->workqueue,&hdw->workpoll);
3656 }
3657
3658
3659 void pvr2_hdw_get_debug_info_unlocked(const struct pvr2_hdw *hdw,
3660                                       struct pvr2_hdw_debug_info *ptr)
3661 {
3662         ptr->big_lock_held = hdw->big_lock_held;
3663         ptr->ctl_lock_held = hdw->ctl_lock_held;
3664         ptr->flag_disconnected = hdw->flag_disconnected;
3665         ptr->flag_init_ok = hdw->flag_init_ok;
3666         ptr->flag_ok = hdw->flag_ok;
3667         ptr->fw1_state = hdw->fw1_state;
3668         ptr->flag_decoder_missed = hdw->flag_decoder_missed;
3669         ptr->flag_tripped = hdw->flag_tripped;
3670         ptr->state_encoder_ok = hdw->state_encoder_ok;
3671         ptr->state_encoder_run = hdw->state_encoder_run;
3672         ptr->state_decoder_run = hdw->state_decoder_run;
3673         ptr->state_usbstream_run = hdw->state_usbstream_run;
3674         ptr->state_decoder_quiescent = hdw->state_decoder_quiescent;
3675         ptr->state_pipeline_config = hdw->state_pipeline_config;
3676         ptr->state_pipeline_req = hdw->state_pipeline_req;
3677         ptr->state_pipeline_pause = hdw->state_pipeline_pause;
3678         ptr->state_pipeline_idle = hdw->state_pipeline_idle;
3679         ptr->cmd_debug_state = hdw->cmd_debug_state;
3680         ptr->cmd_code = hdw->cmd_debug_code;
3681         ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
3682         ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
3683         ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
3684         ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
3685         ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
3686         ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
3687         ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
3688 }
3689
3690
3691 void pvr2_hdw_get_debug_info_locked(struct pvr2_hdw *hdw,
3692                                     struct pvr2_hdw_debug_info *ptr)
3693 {
3694         LOCK_TAKE(hdw->ctl_lock); do {
3695                 pvr2_hdw_get_debug_info_unlocked(hdw,ptr);
3696         } while(0); LOCK_GIVE(hdw->ctl_lock);
3697 }
3698
3699
3700 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
3701 {
3702         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
3703 }
3704
3705
3706 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
3707 {
3708         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
3709 }
3710
3711
3712 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
3713 {
3714         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
3715 }
3716
3717
3718 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
3719 {
3720         u32 cval,nval;
3721         int ret;
3722         if (~msk) {
3723                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
3724                 if (ret) return ret;
3725                 nval = (cval & ~msk) | (val & msk);
3726                 pvr2_trace(PVR2_TRACE_GPIO,
3727                            "GPIO direction changing 0x%x:0x%x"
3728                            " from 0x%x to 0x%x",
3729                            msk,val,cval,nval);
3730         } else {
3731                 nval = val;
3732                 pvr2_trace(PVR2_TRACE_GPIO,
3733                            "GPIO direction changing to 0x%x",nval);
3734         }
3735         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
3736 }
3737
3738
3739 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
3740 {
3741         u32 cval,nval;
3742         int ret;
3743         if (~msk) {
3744                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
3745                 if (ret) return ret;
3746                 nval = (cval & ~msk) | (val & msk);
3747                 pvr2_trace(PVR2_TRACE_GPIO,
3748                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
3749                            msk,val,cval,nval);
3750         } else {
3751                 nval = val;
3752                 pvr2_trace(PVR2_TRACE_GPIO,
3753                            "GPIO output changing to 0x%x",nval);
3754         }
3755         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
3756 }
3757
3758
3759 /* Find I2C address of eeprom */
3760 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
3761 {
3762         int result;
3763         LOCK_TAKE(hdw->ctl_lock); do {
3764                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
3765                 result = pvr2_send_request(hdw,
3766                                            hdw->cmd_buffer,1,
3767                                            hdw->cmd_buffer,1);
3768                 if (result < 0) break;
3769                 result = hdw->cmd_buffer[0];
3770         } while(0); LOCK_GIVE(hdw->ctl_lock);
3771         return result;
3772 }
3773
3774
3775 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
3776                              u32 match_type, u32 match_chip, u64 reg_id,
3777                              int setFl,u64 *val_ptr)
3778 {
3779 #ifdef CONFIG_VIDEO_ADV_DEBUG
3780         struct pvr2_i2c_client *cp;
3781         struct v4l2_register req;
3782         int stat = 0;
3783         int okFl = 0;
3784
3785         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
3786
3787         req.match_type = match_type;
3788         req.match_chip = match_chip;
3789         req.reg = reg_id;
3790         if (setFl) req.val = *val_ptr;
3791         mutex_lock(&hdw->i2c_list_lock); do {
3792                 list_for_each_entry(cp, &hdw->i2c_clients, list) {
3793                         if (!v4l2_chip_match_i2c_client(
3794                                     cp->client,
3795                                     req.match_type, req.match_chip)) {
3796                                 continue;
3797                         }
3798                         stat = pvr2_i2c_client_cmd(
3799                                 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
3800                                     VIDIOC_DBG_G_REGISTER),&req);
3801                         if (!setFl) *val_ptr = req.val;
3802                         okFl = !0;
3803                         break;
3804                 }
3805         } while (0); mutex_unlock(&hdw->i2c_list_lock);
3806         if (okFl) {
3807                 return stat;
3808         }
3809         return -EINVAL;
3810 #else
3811         return -ENOSYS;
3812 #endif
3813 }
3814
3815
3816 /*
3817   Stuff for Emacs to see, in order to encourage consistent editing style:
3818   *** Local Variables: ***
3819   *** mode: c ***
3820   *** fill-column: 75 ***
3821   *** tab-width: 8 ***
3822   *** c-basic-offset: 8 ***
3823   *** End: ***
3824   */