SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  *
  19  */
  20
  21 #include <linux/errno.h>
  22 #include <linux/string.h>
  23 #include <linux/slab.h>
  24 #include <linux/firmware.h>
  25 #include <linux/videodev2.h>
  26 #include <media/v4l2-common.h>
  27 #include "pvrusb2.h"
  28 #include "pvrusb2-std.h"
  29 #include "pvrusb2-util.h"
  30 #include "pvrusb2-hdw.h"
  31 #include "pvrusb2-i2c-core.h"
  32 #include "pvrusb2-i2c-track.h"
  33 #include "pvrusb2-tuner.h"
  34 #include "pvrusb2-eeprom.h"
  35 #include "pvrusb2-hdw-internal.h"
  36 #include "pvrusb2-encoder.h"
  37 #include "pvrusb2-debug.h"
  38 #include "pvrusb2-fx2-cmd.h"
  39 #include "pvrusb2-wm8775.h"
  40 #include "pvrusb2-video-v4l.h"
  41
  42 #define TV_MIN_FREQ     55250000L
  43 #define TV_MAX_FREQ    850000000L
  44
  45 /* This defines a minimum interval that the decoder must remain quiet
  46    before we are allowed to start it running. */
  47 #define TIME_MSEC_DECODER_WAIT 50
  48
  49 /* This defines a minimum interval that the encoder must remain quiet
  50    before we are allowed to configure it.  I had this originally set to
  51    50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
  52    things work better when it's set to 100msec. */
  53 #define TIME_MSEC_ENCODER_WAIT 100
  54
  55 /* This defines the minimum interval that the encoder must successfully run
  56    before we consider that the encoder has run at least once since its
  57    firmware has been loaded.  This measurement is in important for cases
  58    where we can't do something until we know that the encoder has been run
  59    at least once. */
  60 #define TIME_MSEC_ENCODER_OK 250
  61
  62 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  63 static DEFINE_MUTEX(pvr2_unit_mtx);
  64
  65 static int ctlchg;
  66 static int procreload;
  67 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  68 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  69 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  70 static int init_pause_msec;
  71
  72 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  73 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  74 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  75 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  76 module_param(procreload, int, S_IRUGO|S_IWUSR);
  77 MODULE_PARM_DESC(procreload,
  78                  "Attempt init failure recovery with firmware reload");
  79 module_param_array(tuner,    int, NULL, 0444);
  80 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  81 module_param_array(video_std,    int, NULL, 0444);
  82 MODULE_PARM_DESC(video_std,"specify initial video standard");
  83 module_param_array(tolerance,    int, NULL, 0444);
  84 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  85
  86 /* US Broadcast channel 7 (175.25 MHz) */
  87 static int default_tv_freq    = 175250000L;
  88 /* 104.3 MHz, a usable FM station for my area */
  89 static int default_radio_freq = 104300000L;
  90
  91 module_param_named(tv_freq, default_tv_freq, int, 0444);
  92 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  93 module_param_named(radio_freq, default_radio_freq, int, 0444);
  94 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  95
  96 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  97 #define PVR2_CTL_READ_ENDPOINT   0x81
  98
  99 #define PVR2_GPIO_IN 0x9008
 100 #define PVR2_GPIO_OUT 0x900c
 101 #define PVR2_GPIO_DIR 0x9020
 102
 103 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 104
 105 #define PVR2_FIRMWARE_ENDPOINT   0x02
 106
 107 /* size of a firmware chunk */
 108 #define FIRMWARE_CHUNK_SIZE 0x2000
 109
 110 typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
 111                                         struct v4l2_subdev *);
 112
 113 static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
 114         [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_update,
 115         [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
 116 };
 117
 118 static const char *module_names[] = {
 119         [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 120         [PVR2_CLIENT_ID_CX25840] = "cx25840",
 121         [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 122         [PVR2_CLIENT_ID_TUNER] = "tuner",
 123         [PVR2_CLIENT_ID_CS53132A] = "cs53132a",
 124         [PVR2_CLIENT_ID_WM8775] = "wm8775",
 125 };
 126
 127
 128 static const unsigned char *module_i2c_addresses[] = {
 129         [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 130 };
 131
 132
 133 /* Define the list of additional controls we'll dynamically construct based
 134    on query of the cx2341x module. */
 135 struct pvr2_mpeg_ids {
 136         const char *strid;
 137         int id;
 138 };
 139 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 140         {
 141                 .strid = "audio_layer",
 142                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 143         },{
 144                 .strid = "audio_bitrate",
 145                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 146         },{
 147                 /* Already using audio_mode elsewhere :-( */
 148                 .strid = "mpeg_audio_mode",
 149                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 150         },{
 151                 .strid = "mpeg_audio_mode_extension",
 152                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 153         },{
 154                 .strid = "audio_emphasis",
 155                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 156         },{
 157                 .strid = "audio_crc",
 158                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 159         },{
 160                 .strid = "video_aspect",
 161                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 162         },{
 163                 .strid = "video_b_frames",
 164                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 165         },{
 166                 .strid = "video_gop_size",
 167                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 168         },{
 169                 .strid = "video_gop_closure",
 170                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 171         },{
 172                 .strid = "video_bitrate_mode",
 173                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 174         },{
 175                 .strid = "video_bitrate",
 176                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 177         },{
 178                 .strid = "video_bitrate_peak",
 179                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 180         },{
 181                 .strid = "video_temporal_decimation",
 182                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 183         },{
 184                 .strid = "stream_type",
 185                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 186         },{
 187                 .strid = "video_spatial_filter_mode",
 188                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 189         },{
 190                 .strid = "video_spatial_filter",
 191                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 192         },{
 193                 .strid = "video_luma_spatial_filter_type",
 194                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 195         },{
 196                 .strid = "video_chroma_spatial_filter_type",
 197                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 198         },{
 199                 .strid = "video_temporal_filter_mode",
 200                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 201         },{
 202                 .strid = "video_temporal_filter",
 203                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 204         },{
 205                 .strid = "video_median_filter_type",
 206                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 207         },{
 208                 .strid = "video_luma_median_filter_top",
 209                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 210         },{
 211                 .strid = "video_luma_median_filter_bottom",
 212                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 213         },{
 214                 .strid = "video_chroma_median_filter_top",
 215                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 216         },{
 217                 .strid = "video_chroma_median_filter_bottom",
 218                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 219         }
 220 };
 221 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 222
 223
 224 static const char *control_values_srate[] = {
 225         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 226         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 227         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 228 };
 229
 230
 231
 232 static const char *control_values_input[] = {
 233         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 234         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 235         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 236         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 237         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 238 };
 239
 240
 241 static const char *control_values_audiomode[] = {
 242         [V4L2_TUNER_MODE_MONO]   = "Mono",
 243         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 244         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 245         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 246         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 247 };
 248
 249
 250 static const char *control_values_hsm[] = {
 251         [PVR2_CVAL_HSM_FAIL] = "Fail",
 252         [PVR2_CVAL_HSM_HIGH] = "High",
 253         [PVR2_CVAL_HSM_FULL] = "Full",
 254 };
 255
 256
 257 static const char *pvr2_state_names[] = {
 258         [PVR2_STATE_NONE] =    "none",
 259         [PVR2_STATE_DEAD] =    "dead",
 260         [PVR2_STATE_COLD] =    "cold",
 261         [PVR2_STATE_WARM] =    "warm",
 262         [PVR2_STATE_ERROR] =   "error",
 263         [PVR2_STATE_READY] =   "ready",
 264         [PVR2_STATE_RUN] =     "run",
 265 };
 266
 267
 268 struct pvr2_fx2cmd_descdef {
 269         unsigned char id;
 270         unsigned char *desc;
 271 };
 272
 273 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 274         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 275         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 276         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 277         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 278         {FX2CMD_REG_WRITE, "write encoder register"},
 279         {FX2CMD_REG_READ, "read encoder register"},
 280         {FX2CMD_MEMSEL, "encoder memsel"},
 281         {FX2CMD_I2C_WRITE, "i2c write"},
 282         {FX2CMD_I2C_READ, "i2c read"},
 283         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 284         {FX2CMD_STREAMING_ON, "stream on"},
 285         {FX2CMD_STREAMING_OFF, "stream off"},
 286         {FX2CMD_FWPOST1, "fwpost1"},
 287         {FX2CMD_POWER_OFF, "power off"},
 288         {FX2CMD_POWER_ON, "power on"},
 289         {FX2CMD_DEEP_RESET, "deep reset"},
 290         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 291         {FX2CMD_GET_IR_CODE, "get IR code"},
 292         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 293         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 294         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 295         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 296         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 297         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 298         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 299 };
 300
 301
 302 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 303 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 304 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 305 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 306 static void pvr2_hdw_worker_i2c(struct work_struct *work);
 307 static void pvr2_hdw_worker_poll(struct work_struct *work);
 308 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 309 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 310 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 311 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 312 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 313 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 314 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 315 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 316 static void pvr2_hdw_quiescent_timeout(unsigned long);
 317 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 318 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 319 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 320 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 321                                 unsigned int timeout,int probe_fl,
 322                                 void *write_data,unsigned int write_len,
 323                                 void *read_data,unsigned int read_len);
 324 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 325
 326
 327 static void trace_stbit(const char *name,int val)
 328 {
 329         pvr2_trace(PVR2_TRACE_STBITS,
 330                    "State bit %s <-- %s",
 331                    name,(val ? "true" : "false"));
 332 }
 333
 334 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 335 {
 336         struct pvr2_hdw *hdw = cptr->hdw;
 337         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 338                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 339         } else {
 340                 *vp = 0;
 341         }
 342         return 0;
 343 }
 344
 345 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 346 {
 347         struct pvr2_hdw *hdw = cptr->hdw;
 348         unsigned int slotId = hdw->freqProgSlot;
 349         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 350                 hdw->freqTable[slotId-1] = v;
 351                 /* Handle side effects correctly - if we're tuned to this
 352                    slot, then forgot the slot id relation since the stored
 353                    frequency has been changed. */
 354                 if (hdw->freqSelector) {
 355                         if (hdw->freqSlotRadio == slotId) {
 356                                 hdw->freqSlotRadio = 0;
 357                         }
 358                 } else {
 359                         if (hdw->freqSlotTelevision == slotId) {
 360                                 hdw->freqSlotTelevision = 0;
 361                         }
 362                 }
 363         }
 364         return 0;
 365 }
 366
 367 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 368 {
 369         *vp = cptr->hdw->freqProgSlot;
 370         return 0;
 371 }
 372
 373 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 374 {
 375         struct pvr2_hdw *hdw = cptr->hdw;
 376         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 377                 hdw->freqProgSlot = v;
 378         }
 379         return 0;
 380 }
 381
 382 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 383 {
 384         struct pvr2_hdw *hdw = cptr->hdw;
 385         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 386         return 0;
 387 }
 388
 389 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 390 {
 391         unsigned freq = 0;
 392         struct pvr2_hdw *hdw = cptr->hdw;
 393         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 394         if (slotId > 0) {
 395                 freq = hdw->freqTable[slotId-1];
 396                 if (!freq) return 0;
 397                 pvr2_hdw_set_cur_freq(hdw,freq);
 398         }
 399         if (hdw->freqSelector) {
 400                 hdw->freqSlotRadio = slotId;
 401         } else {
 402                 hdw->freqSlotTelevision = slotId;
 403         }
 404         return 0;
 405 }
 406
 407 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 408 {
 409         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 410         return 0;
 411 }
 412
 413 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 414 {
 415         return cptr->hdw->freqDirty != 0;
 416 }
 417
 418 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 419 {
 420         cptr->hdw->freqDirty = 0;
 421 }
 422
 423 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 424 {
 425         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 426         return 0;
 427 }
 428
 429 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 430 {
 431         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 432         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 433         if (stat != 0) {
 434                 return stat;
 435         }
 436         *left = cap->bounds.left;
 437         return 0;
 438 }
 439
 440 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 441 {
 442         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 443         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 444         if (stat != 0) {
 445                 return stat;
 446         }
 447         *left = cap->bounds.left;
 448         if (cap->bounds.width > cptr->hdw->cropw_val) {
 449                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 450         }
 451         return 0;
 452 }
 453
 454 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 455 {
 456         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 457         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 458         if (stat != 0) {
 459                 return stat;
 460         }
 461         *top = cap->bounds.top;
 462         return 0;
 463 }
 464
 465 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 466 {
 467         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 468         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 469         if (stat != 0) {
 470                 return stat;
 471         }
 472         *top = cap->bounds.top;
 473         if (cap->bounds.height > cptr->hdw->croph_val) {
 474                 *top += cap->bounds.height - cptr->hdw->croph_val;
 475         }
 476         return 0;
 477 }
 478
 479 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
 480 {
 481         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 482         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 483         if (stat != 0) {
 484                 return stat;
 485         }
 486         *val = 0;
 487         if (cap->bounds.width > cptr->hdw->cropl_val) {
 488                 *val = cap->bounds.width - cptr->hdw->cropl_val;
 489         }
 490         return 0;
 491 }
 492
 493 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
 494 {
 495         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 496         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 497         if (stat != 0) {
 498                 return stat;
 499         }
 500         *val = 0;
 501         if (cap->bounds.height > cptr->hdw->cropt_val) {
 502                 *val = cap->bounds.height - cptr->hdw->cropt_val;
 503         }
 504         return 0;
 505 }
 506
 507 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 508 {
 509         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 510         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 511         if (stat != 0) {
 512                 return stat;
 513         }
 514         *val = cap->bounds.left;
 515         return 0;
 516 }
 517
 518 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 519 {
 520         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 521         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 522         if (stat != 0) {
 523                 return stat;
 524         }
 525         *val = cap->bounds.top;
 526         return 0;
 527 }
 528
 529 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 530 {
 531         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 532         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 533         if (stat != 0) {
 534                 return stat;
 535         }
 536         *val = cap->bounds.width;
 537         return 0;
 538 }
 539
 540 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 541 {
 542         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 543         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 544         if (stat != 0) {
 545                 return stat;
 546         }
 547         *val = cap->bounds.height;
 548         return 0;
 549 }
 550
 551 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 552 {
 553         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 554         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 555         if (stat != 0) {
 556                 return stat;
 557         }
 558         *val = cap->defrect.left;
 559         return 0;
 560 }
 561
 562 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 563 {
 564         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 565         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 566         if (stat != 0) {
 567                 return stat;
 568         }
 569         *val = cap->defrect.top;
 570         return 0;
 571 }
 572
 573 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 574 {
 575         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 576         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 577         if (stat != 0) {
 578                 return stat;
 579         }
 580         *val = cap->defrect.width;
 581         return 0;
 582 }
 583
 584 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 585 {
 586         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 587         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 588         if (stat != 0) {
 589                 return stat;
 590         }
 591         *val = cap->defrect.height;
 592         return 0;
 593 }
 594
 595 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 596 {
 597         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 598         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 599         if (stat != 0) {
 600                 return stat;
 601         }
 602         *val = cap->pixelaspect.numerator;
 603         return 0;
 604 }
 605
 606 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 607 {
 608         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 609         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 610         if (stat != 0) {
 611                 return stat;
 612         }
 613         *val = cap->pixelaspect.denominator;
 614         return 0;
 615 }
 616
 617 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 618 {
 619         /* Actual maximum depends on the video standard in effect. */
 620         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 621                 *vp = 480;
 622         } else {
 623                 *vp = 576;
 624         }
 625         return 0;
 626 }
 627
 628 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 629 {
 630         /* Actual minimum depends on device digitizer type. */
 631         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 632                 *vp = 75;
 633         } else {
 634                 *vp = 17;
 635         }
 636         return 0;
 637 }
 638
 639 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 640 {
 641         *vp = cptr->hdw->input_val;
 642         return 0;
 643 }
 644
 645 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 646 {
 647         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 648 }
 649
 650 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 651 {
 652         return pvr2_hdw_set_input(cptr->hdw,v);
 653 }
 654
 655 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 656 {
 657         return cptr->hdw->input_dirty != 0;
 658 }
 659
 660 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 661 {
 662         cptr->hdw->input_dirty = 0;
 663 }
 664
 665
 666 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 667 {
 668         unsigned long fv;
 669         struct pvr2_hdw *hdw = cptr->hdw;
 670         if (hdw->tuner_signal_stale) {
 671                 pvr2_hdw_status_poll(hdw);
 672         }
 673         fv = hdw->tuner_signal_info.rangehigh;
 674         if (!fv) {
 675                 /* Safety fallback */
 676                 *vp = TV_MAX_FREQ;
 677                 return 0;
 678         }
 679         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 680                 fv = (fv * 125) / 2;
 681         } else {
 682                 fv = fv * 62500;
 683         }
 684         *vp = fv;
 685         return 0;
 686 }
 687
 688 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 689 {
 690         unsigned long fv;
 691         struct pvr2_hdw *hdw = cptr->hdw;
 692         if (hdw->tuner_signal_stale) {
 693                 pvr2_hdw_status_poll(hdw);
 694         }
 695         fv = hdw->tuner_signal_info.rangelow;
 696         if (!fv) {
 697                 /* Safety fallback */
 698                 *vp = TV_MIN_FREQ;
 699                 return 0;
 700         }
 701         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 702                 fv = (fv * 125) / 2;
 703         } else {
 704                 fv = fv * 62500;
 705         }
 706         *vp = fv;
 707         return 0;
 708 }
 709
 710 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 711 {
 712         return cptr->hdw->enc_stale != 0;
 713 }
 714
 715 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 716 {
 717         cptr->hdw->enc_stale = 0;
 718         cptr->hdw->enc_unsafe_stale = 0;
 719 }
 720
 721 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 722 {
 723         int ret;
 724         struct v4l2_ext_controls cs;
 725         struct v4l2_ext_control c1;
 726         memset(&cs,0,sizeof(cs));
 727         memset(&c1,0,sizeof(c1));
 728         cs.controls = &c1;
 729         cs.count = 1;
 730         c1.id = cptr->info->v4l_id;
 731         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 732                                 VIDIOC_G_EXT_CTRLS);
 733         if (ret) return ret;
 734         *vp = c1.value;
 735         return 0;
 736 }
 737
 738 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 739 {
 740         int ret;
 741         struct pvr2_hdw *hdw = cptr->hdw;
 742         struct v4l2_ext_controls cs;
 743         struct v4l2_ext_control c1;
 744         memset(&cs,0,sizeof(cs));
 745         memset(&c1,0,sizeof(c1));
 746         cs.controls = &c1;
 747         cs.count = 1;
 748         c1.id = cptr->info->v4l_id;
 749         c1.value = v;
 750         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 751                                 hdw->state_encoder_run, &cs,
 752                                 VIDIOC_S_EXT_CTRLS);
 753         if (ret == -EBUSY) {
 754                 /* Oops.  cx2341x is telling us it's not safe to change
 755                    this control while we're capturing.  Make a note of this
 756                    fact so that the pipeline will be stopped the next time
 757                    controls are committed.  Then go on ahead and store this
 758                    change anyway. */
 759                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 760                                         0, &cs,
 761                                         VIDIOC_S_EXT_CTRLS);
 762                 if (!ret) hdw->enc_unsafe_stale = !0;
 763         }
 764         if (ret) return ret;
 765         hdw->enc_stale = !0;
 766         return 0;
 767 }
 768
 769 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 770 {
 771         struct v4l2_queryctrl qctrl;
 772         struct pvr2_ctl_info *info;
 773         qctrl.id = cptr->info->v4l_id;
 774         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 775         /* Strip out the const so we can adjust a function pointer.  It's
 776            OK to do this here because we know this is a dynamically created
 777            control, so the underlying storage for the info pointer is (a)
 778            private to us, and (b) not in read-only storage.  Either we do
 779            this or we significantly complicate the underlying control
 780            implementation. */
 781         info = (struct pvr2_ctl_info *)(cptr->info);
 782         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 783                 if (info->set_value) {
 784                         info->set_value = NULL;
 785                 }
 786         } else {
 787                 if (!(info->set_value)) {
 788                         info->set_value = ctrl_cx2341x_set;
 789                 }
 790         }
 791         return qctrl.flags;
 792 }
 793
 794 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 795 {
 796         *vp = cptr->hdw->state_pipeline_req;
 797         return 0;
 798 }
 799
 800 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 801 {
 802         *vp = cptr->hdw->master_state;
 803         return 0;
 804 }
 805
 806 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 807 {
 808         int result = pvr2_hdw_is_hsm(cptr->hdw);
 809         *vp = PVR2_CVAL_HSM_FULL;
 810         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 811         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 812         return 0;
 813 }
 814
 815 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 816 {
 817         *vp = cptr->hdw->std_mask_avail;
 818         return 0;
 819 }
 820
 821 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 822 {
 823         struct pvr2_hdw *hdw = cptr->hdw;
 824         v4l2_std_id ns;
 825         ns = hdw->std_mask_avail;
 826         ns = (ns & ~m) | (v & m);
 827         if (ns == hdw->std_mask_avail) return 0;
 828         hdw->std_mask_avail = ns;
 829         pvr2_hdw_internal_set_std_avail(hdw);
 830         pvr2_hdw_internal_find_stdenum(hdw);
 831         return 0;
 832 }
 833
 834 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 835                                char *bufPtr,unsigned int bufSize,
 836                                unsigned int *len)
 837 {
 838         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 839         return 0;
 840 }
 841
 842 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 843                                const char *bufPtr,unsigned int bufSize,
 844                                int *mskp,int *valp)
 845 {
 846         int ret;
 847         v4l2_std_id id;
 848         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 849         if (ret < 0) return ret;
 850         if (mskp) *mskp = id;
 851         if (valp) *valp = id;
 852         return 0;
 853 }
 854
 855 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 856 {
 857         *vp = cptr->hdw->std_mask_cur;
 858         return 0;
 859 }
 860
 861 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 862 {
 863         struct pvr2_hdw *hdw = cptr->hdw;
 864         v4l2_std_id ns;
 865         ns = hdw->std_mask_cur;
 866         ns = (ns & ~m) | (v & m);
 867         if (ns == hdw->std_mask_cur) return 0;
 868         hdw->std_mask_cur = ns;
 869         hdw->std_dirty = !0;
 870         pvr2_hdw_internal_find_stdenum(hdw);
 871         return 0;
 872 }
 873
 874 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 875 {
 876         return cptr->hdw->std_dirty != 0;
 877 }
 878
 879 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 880 {
 881         cptr->hdw->std_dirty = 0;
 882 }
 883
 884 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 885 {
 886         struct pvr2_hdw *hdw = cptr->hdw;
 887         pvr2_hdw_status_poll(hdw);
 888         *vp = hdw->tuner_signal_info.signal;
 889         return 0;
 890 }
 891
 892 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 893 {
 894         int val = 0;
 895         unsigned int subchan;
 896         struct pvr2_hdw *hdw = cptr->hdw;
 897         pvr2_hdw_status_poll(hdw);
 898         subchan = hdw->tuner_signal_info.rxsubchans;
 899         if (subchan & V4L2_TUNER_SUB_MONO) {
 900                 val |= (1 << V4L2_TUNER_MODE_MONO);
 901         }
 902         if (subchan & V4L2_TUNER_SUB_STEREO) {
 903                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 904         }
 905         if (subchan & V4L2_TUNER_SUB_LANG1) {
 906                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 907         }
 908         if (subchan & V4L2_TUNER_SUB_LANG2) {
 909                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 910         }
 911         *vp = val;
 912         return 0;
 913 }
 914
 915
 916 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 917 {
 918         struct pvr2_hdw *hdw = cptr->hdw;
 919         if (v < 0) return -EINVAL;
 920         if (v > hdw->std_enum_cnt) return -EINVAL;
 921         hdw->std_enum_cur = v;
 922         if (!v) return 0;
 923         v--;
 924         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 925         hdw->std_mask_cur = hdw->std_defs[v].id;
 926         hdw->std_dirty = !0;
 927         return 0;
 928 }
 929
 930
 931 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 932 {
 933         *vp = cptr->hdw->std_enum_cur;
 934         return 0;
 935 }
 936
 937
 938 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 939 {
 940         return cptr->hdw->std_dirty != 0;
 941 }
 942
 943
 944 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 945 {
 946         cptr->hdw->std_dirty = 0;
 947 }
 948
 949
 950 #define DEFINT(vmin,vmax) \
 951         .type = pvr2_ctl_int, \
 952         .def.type_int.min_value = vmin, \
 953         .def.type_int.max_value = vmax
 954
 955 #define DEFENUM(tab) \
 956         .type = pvr2_ctl_enum, \
 957         .def.type_enum.count = ARRAY_SIZE(tab), \
 958         .def.type_enum.value_names = tab
 959
 960 #define DEFBOOL \
 961         .type = pvr2_ctl_bool
 962
 963 #define DEFMASK(msk,tab) \
 964         .type = pvr2_ctl_bitmask, \
 965         .def.type_bitmask.valid_bits = msk, \
 966         .def.type_bitmask.bit_names = tab
 967
 968 #define DEFREF(vname) \
 969         .set_value = ctrl_set_##vname, \
 970         .get_value = ctrl_get_##vname, \
 971         .is_dirty = ctrl_isdirty_##vname, \
 972         .clear_dirty = ctrl_cleardirty_##vname
 973
 974
 975 #define VCREATE_FUNCS(vname) \
 976 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 977 {*vp = cptr->hdw->vname##_val; return 0;} \
 978 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 979 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 980 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 981 {return cptr->hdw->vname##_dirty != 0;} \
 982 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 983 {cptr->hdw->vname##_dirty = 0;}
 984
 985 VCREATE_FUNCS(brightness)
 986 VCREATE_FUNCS(contrast)
 987 VCREATE_FUNCS(saturation)
 988 VCREATE_FUNCS(hue)
 989 VCREATE_FUNCS(volume)
 990 VCREATE_FUNCS(balance)
 991 VCREATE_FUNCS(bass)
 992 VCREATE_FUNCS(treble)
 993 VCREATE_FUNCS(mute)
 994 VCREATE_FUNCS(cropl)
 995 VCREATE_FUNCS(cropt)
 996 VCREATE_FUNCS(cropw)
 997 VCREATE_FUNCS(croph)
 998 VCREATE_FUNCS(audiomode)
 999 VCREATE_FUNCS(res_hor)
1000 VCREATE_FUNCS(res_ver)
1001 VCREATE_FUNCS(srate)
1002
1003 /* Table definition of all controls which can be manipulated */
1004 static const struct pvr2_ctl_info control_defs[] = {
1005         {
1006                 .v4l_id = V4L2_CID_BRIGHTNESS,
1007                 .desc = "Brightness",
1008                 .name = "brightness",
1009                 .default_value = 128,
1010                 DEFREF(brightness),
1011                 DEFINT(0,255),
1012         },{
1013                 .v4l_id = V4L2_CID_CONTRAST,
1014                 .desc = "Contrast",
1015                 .name = "contrast",
1016                 .default_value = 68,
1017                 DEFREF(contrast),
1018                 DEFINT(0,127),
1019         },{
1020                 .v4l_id = V4L2_CID_SATURATION,
1021                 .desc = "Saturation",
1022                 .name = "saturation",
1023                 .default_value = 64,
1024                 DEFREF(saturation),
1025                 DEFINT(0,127),
1026         },{
1027                 .v4l_id = V4L2_CID_HUE,
1028                 .desc = "Hue",
1029                 .name = "hue",
1030                 .default_value = 0,
1031                 DEFREF(hue),
1032                 DEFINT(-128,127),
1033         },{
1034                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1035                 .desc = "Volume",
1036                 .name = "volume",
1037                 .default_value = 62000,
1038                 DEFREF(volume),
1039                 DEFINT(0,65535),
1040         },{
1041                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1042                 .desc = "Balance",
1043                 .name = "balance",
1044                 .default_value = 0,
1045                 DEFREF(balance),
1046                 DEFINT(-32768,32767),
1047         },{
1048                 .v4l_id = V4L2_CID_AUDIO_BASS,
1049                 .desc = "Bass",
1050                 .name = "bass",
1051                 .default_value = 0,
1052                 DEFREF(bass),
1053                 DEFINT(-32768,32767),
1054         },{
1055                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1056                 .desc = "Treble",
1057                 .name = "treble",
1058                 .default_value = 0,
1059                 DEFREF(treble),
1060                 DEFINT(-32768,32767),
1061         },{
1062                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1063                 .desc = "Mute",
1064                 .name = "mute",
1065                 .default_value = 0,
1066                 DEFREF(mute),
1067                 DEFBOOL,
1068         }, {
1069                 .desc = "Capture crop left margin",
1070                 .name = "crop_left",
1071                 .internal_id = PVR2_CID_CROPL,
1072                 .default_value = 0,
1073                 DEFREF(cropl),
1074                 DEFINT(-129, 340),
1075                 .get_min_value = ctrl_cropl_min_get,
1076                 .get_max_value = ctrl_cropl_max_get,
1077                 .get_def_value = ctrl_get_cropcapdl,
1078         }, {
1079                 .desc = "Capture crop top margin",
1080                 .name = "crop_top",
1081                 .internal_id = PVR2_CID_CROPT,
1082                 .default_value = 0,
1083                 DEFREF(cropt),
1084                 DEFINT(-35, 544),
1085                 .get_min_value = ctrl_cropt_min_get,
1086                 .get_max_value = ctrl_cropt_max_get,
1087                 .get_def_value = ctrl_get_cropcapdt,
1088         }, {
1089                 .desc = "Capture crop width",
1090                 .name = "crop_width",
1091                 .internal_id = PVR2_CID_CROPW,
1092                 .default_value = 720,
1093                 DEFREF(cropw),
1094                 .get_max_value = ctrl_cropw_max_get,
1095                 .get_def_value = ctrl_get_cropcapdw,
1096         }, {
1097                 .desc = "Capture crop height",
1098                 .name = "crop_height",
1099                 .internal_id = PVR2_CID_CROPH,
1100                 .default_value = 480,
1101                 DEFREF(croph),
1102                 .get_max_value = ctrl_croph_max_get,
1103                 .get_def_value = ctrl_get_cropcapdh,
1104         }, {
1105                 .desc = "Capture capability pixel aspect numerator",
1106                 .name = "cropcap_pixel_numerator",
1107                 .internal_id = PVR2_CID_CROPCAPPAN,
1108                 .get_value = ctrl_get_cropcappan,
1109         }, {
1110                 .desc = "Capture capability pixel aspect denominator",
1111                 .name = "cropcap_pixel_denominator",
1112                 .internal_id = PVR2_CID_CROPCAPPAD,
1113                 .get_value = ctrl_get_cropcappad,
1114         }, {
1115                 .desc = "Capture capability bounds top",
1116                 .name = "cropcap_bounds_top",
1117                 .internal_id = PVR2_CID_CROPCAPBT,
1118                 .get_value = ctrl_get_cropcapbt,
1119         }, {
1120                 .desc = "Capture capability bounds left",
1121                 .name = "cropcap_bounds_left",
1122                 .internal_id = PVR2_CID_CROPCAPBL,
1123                 .get_value = ctrl_get_cropcapbl,
1124         }, {
1125                 .desc = "Capture capability bounds width",
1126                 .name = "cropcap_bounds_width",
1127                 .internal_id = PVR2_CID_CROPCAPBW,
1128                 .get_value = ctrl_get_cropcapbw,
1129         }, {
1130                 .desc = "Capture capability bounds height",
1131                 .name = "cropcap_bounds_height",
1132                 .internal_id = PVR2_CID_CROPCAPBH,
1133                 .get_value = ctrl_get_cropcapbh,
1134         },{
1135                 .desc = "Video Source",
1136                 .name = "input",
1137                 .internal_id = PVR2_CID_INPUT,
1138                 .default_value = PVR2_CVAL_INPUT_TV,
1139                 .check_value = ctrl_check_input,
1140                 DEFREF(input),
1141                 DEFENUM(control_values_input),
1142         },{
1143                 .desc = "Audio Mode",
1144                 .name = "audio_mode",
1145                 .internal_id = PVR2_CID_AUDIOMODE,
1146                 .default_value = V4L2_TUNER_MODE_STEREO,
1147                 DEFREF(audiomode),
1148                 DEFENUM(control_values_audiomode),
1149         },{
1150                 .desc = "Horizontal capture resolution",
1151                 .name = "resolution_hor",
1152                 .internal_id = PVR2_CID_HRES,
1153                 .default_value = 720,
1154                 DEFREF(res_hor),
1155                 DEFINT(19,720),
1156         },{
1157                 .desc = "Vertical capture resolution",
1158                 .name = "resolution_ver",
1159                 .internal_id = PVR2_CID_VRES,
1160                 .default_value = 480,
1161                 DEFREF(res_ver),
1162                 DEFINT(17,576),
1163                 /* Hook in check for video standard and adjust maximum
1164                    depending on the standard. */
1165                 .get_max_value = ctrl_vres_max_get,
1166                 .get_min_value = ctrl_vres_min_get,
1167         },{
1168                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1169                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1170                 .desc = "Audio Sampling Frequency",
1171                 .name = "srate",
1172                 DEFREF(srate),
1173                 DEFENUM(control_values_srate),
1174         },{
1175                 .desc = "Tuner Frequency (Hz)",
1176                 .name = "frequency",
1177                 .internal_id = PVR2_CID_FREQUENCY,
1178                 .default_value = 0,
1179                 .set_value = ctrl_freq_set,
1180                 .get_value = ctrl_freq_get,
1181                 .is_dirty = ctrl_freq_is_dirty,
1182                 .clear_dirty = ctrl_freq_clear_dirty,
1183                 DEFINT(0,0),
1184                 /* Hook in check for input value (tv/radio) and adjust
1185                    max/min values accordingly */
1186                 .get_max_value = ctrl_freq_max_get,
1187                 .get_min_value = ctrl_freq_min_get,
1188         },{
1189                 .desc = "Channel",
1190                 .name = "channel",
1191                 .set_value = ctrl_channel_set,
1192                 .get_value = ctrl_channel_get,
1193                 DEFINT(0,FREQTABLE_SIZE),
1194         },{
1195                 .desc = "Channel Program Frequency",
1196                 .name = "freq_table_value",
1197                 .set_value = ctrl_channelfreq_set,
1198                 .get_value = ctrl_channelfreq_get,
1199                 DEFINT(0,0),
1200                 /* Hook in check for input value (tv/radio) and adjust
1201                    max/min values accordingly */
1202                 .get_max_value = ctrl_freq_max_get,
1203                 .get_min_value = ctrl_freq_min_get,
1204         },{
1205                 .desc = "Channel Program ID",
1206                 .name = "freq_table_channel",
1207                 .set_value = ctrl_channelprog_set,
1208                 .get_value = ctrl_channelprog_get,
1209                 DEFINT(0,FREQTABLE_SIZE),
1210         },{
1211                 .desc = "Streaming Enabled",
1212                 .name = "streaming_enabled",
1213                 .get_value = ctrl_streamingenabled_get,
1214                 DEFBOOL,
1215         },{
1216                 .desc = "USB Speed",
1217                 .name = "usb_speed",
1218                 .get_value = ctrl_hsm_get,
1219                 DEFENUM(control_values_hsm),
1220         },{
1221                 .desc = "Master State",
1222                 .name = "master_state",
1223                 .get_value = ctrl_masterstate_get,
1224                 DEFENUM(pvr2_state_names),
1225         },{
1226                 .desc = "Signal Present",
1227                 .name = "signal_present",
1228                 .get_value = ctrl_signal_get,
1229                 DEFINT(0,65535),
1230         },{
1231                 .desc = "Audio Modes Present",
1232                 .name = "audio_modes_present",
1233                 .get_value = ctrl_audio_modes_present_get,
1234                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1235                    v4l.  Nothing outside of this module cares about this,
1236                    but I reuse it in order to also reuse the
1237                    control_values_audiomode string table. */
1238                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1239                          (1 << V4L2_TUNER_MODE_STEREO)|
1240                          (1 << V4L2_TUNER_MODE_LANG1)|
1241                          (1 << V4L2_TUNER_MODE_LANG2)),
1242                         control_values_audiomode),
1243         },{
1244                 .desc = "Video Standards Available Mask",
1245                 .name = "video_standard_mask_available",
1246                 .internal_id = PVR2_CID_STDAVAIL,
1247                 .skip_init = !0,
1248                 .get_value = ctrl_stdavail_get,
1249                 .set_value = ctrl_stdavail_set,
1250                 .val_to_sym = ctrl_std_val_to_sym,
1251                 .sym_to_val = ctrl_std_sym_to_val,
1252                 .type = pvr2_ctl_bitmask,
1253         },{
1254                 .desc = "Video Standards In Use Mask",
1255                 .name = "video_standard_mask_active",
1256                 .internal_id = PVR2_CID_STDCUR,
1257                 .skip_init = !0,
1258                 .get_value = ctrl_stdcur_get,
1259                 .set_value = ctrl_stdcur_set,
1260                 .is_dirty = ctrl_stdcur_is_dirty,
1261                 .clear_dirty = ctrl_stdcur_clear_dirty,
1262                 .val_to_sym = ctrl_std_val_to_sym,
1263                 .sym_to_val = ctrl_std_sym_to_val,
1264                 .type = pvr2_ctl_bitmask,
1265         },{
1266                 .desc = "Video Standard Name",
1267                 .name = "video_standard",
1268                 .internal_id = PVR2_CID_STDENUM,
1269                 .skip_init = !0,
1270                 .get_value = ctrl_stdenumcur_get,
1271                 .set_value = ctrl_stdenumcur_set,
1272                 .is_dirty = ctrl_stdenumcur_is_dirty,
1273                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1274                 .type = pvr2_ctl_enum,
1275         }
1276 };
1277
1278 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1279
1280
1281 const char *pvr2_config_get_name(enum pvr2_config cfg)
1282 {
1283         switch (cfg) {
1284         case pvr2_config_empty: return "empty";
1285         case pvr2_config_mpeg: return "mpeg";
1286         case pvr2_config_vbi: return "vbi";
1287         case pvr2_config_pcm: return "pcm";
1288         case pvr2_config_rawvideo: return "raw video";
1289         }
1290         return "<unknown>";
1291 }
1292
1293
1294 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1295 {
1296         return hdw->usb_dev;
1297 }
1298
1299
1300 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1301 {
1302         return hdw->serial_number;
1303 }
1304
1305
1306 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1307 {
1308         return hdw->bus_info;
1309 }
1310
1311
1312 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1313 {
1314         return hdw->identifier;
1315 }
1316
1317
1318 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1319 {
1320         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1321 }
1322
1323 /* Set the currently tuned frequency and account for all possible
1324    driver-core side effects of this action. */
1325 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1326 {
1327         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1328                 if (hdw->freqSelector) {
1329                         /* Swing over to radio frequency selection */
1330                         hdw->freqSelector = 0;
1331                         hdw->freqDirty = !0;
1332                 }
1333                 if (hdw->freqValRadio != val) {
1334                         hdw->freqValRadio = val;
1335                         hdw->freqSlotRadio = 0;
1336                         hdw->freqDirty = !0;
1337                 }
1338         } else {
1339                 if (!(hdw->freqSelector)) {
1340                         /* Swing over to television frequency selection */
1341                         hdw->freqSelector = 1;
1342                         hdw->freqDirty = !0;
1343                 }
1344                 if (hdw->freqValTelevision != val) {
1345                         hdw->freqValTelevision = val;
1346                         hdw->freqSlotTelevision = 0;
1347                         hdw->freqDirty = !0;
1348                 }
1349         }
1350 }
1351
1352 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1353 {
1354         return hdw->unit_number;
1355 }
1356
1357
1358 /* Attempt to locate one of the given set of files.  Messages are logged
1359    appropriate to what has been found.  The return value will be 0 or
1360    greater on success (it will be the index of the file name found) and
1361    fw_entry will be filled in.  Otherwise a negative error is returned on
1362    failure.  If the return value is -ENOENT then no viable firmware file
1363    could be located. */
1364 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1365                                 const struct firmware **fw_entry,
1366                                 const char *fwtypename,
1367                                 unsigned int fwcount,
1368                                 const char *fwnames[])
1369 {
1370         unsigned int idx;
1371         int ret = -EINVAL;
1372         for (idx = 0; idx < fwcount; idx++) {
1373                 ret = request_firmware(fw_entry,
1374                                        fwnames[idx],
1375                                        &hdw->usb_dev->dev);
1376                 if (!ret) {
1377                         trace_firmware("Located %s firmware: %s;"
1378                                        " uploading...",
1379                                        fwtypename,
1380                                        fwnames[idx]);
1381                         return idx;
1382                 }
1383                 if (ret == -ENOENT) continue;
1384                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1385                            "request_firmware fatal error with code=%d",ret);
1386                 return ret;
1387         }
1388         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1389                    "***WARNING***"
1390                    " Device %s firmware"
1391                    " seems to be missing.",
1392                    fwtypename);
1393         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1394                    "Did you install the pvrusb2 firmware files"
1395                    " in their proper location?");
1396         if (fwcount == 1) {
1397                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1398                            "request_firmware unable to locate %s file %s",
1399                            fwtypename,fwnames[0]);
1400         } else {
1401                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1402                            "request_firmware unable to locate"
1403                            " one of the following %s files:",
1404                            fwtypename);
1405                 for (idx = 0; idx < fwcount; idx++) {
1406                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1407                                    "request_firmware: Failed to find %s",
1408                                    fwnames[idx]);
1409                 }
1410         }
1411         return ret;
1412 }
1413
1414
1415 /*
1416  * pvr2_upload_firmware1().
1417  *
1418  * Send the 8051 firmware to the device.  After the upload, arrange for
1419  * device to re-enumerate.
1420  *
1421  * NOTE : the pointer to the firmware data given by request_firmware()
1422  * is not suitable for an usb transaction.
1423  *
1424  */
1425 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1426 {
1427         const struct firmware *fw_entry = NULL;
1428         void  *fw_ptr;
1429         unsigned int pipe;
1430         int ret;
1431         u16 address;
1432
1433         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1434                 hdw->fw1_state = FW1_STATE_OK;
1435                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1436                            "Connected device type defines"
1437                            " no firmware to upload; ignoring firmware");
1438                 return -ENOTTY;
1439         }
1440
1441         hdw->fw1_state = FW1_STATE_FAILED; // default result
1442
1443         trace_firmware("pvr2_upload_firmware1");
1444
1445         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1446                                    hdw->hdw_desc->fx2_firmware.cnt,
1447                                    hdw->hdw_desc->fx2_firmware.lst);
1448         if (ret < 0) {
1449                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1450                 return ret;
1451         }
1452
1453         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1454         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1455
1456         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1457
1458         if (fw_entry->size != 0x2000){
1459                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1460                 release_firmware(fw_entry);
1461                 return -ENOMEM;
1462         }
1463
1464         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1465         if (fw_ptr == NULL){
1466                 release_firmware(fw_entry);
1467                 return -ENOMEM;
1468         }
1469
1470         /* We have to hold the CPU during firmware upload. */
1471         pvr2_hdw_cpureset_assert(hdw,1);
1472
1473         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1474            chunk. */
1475
1476         ret = 0;
1477         for(address = 0; address < fw_entry->size; address += 0x800) {
1478                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1479                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1480                                        0, fw_ptr, 0x800, HZ);
1481         }
1482
1483         trace_firmware("Upload done, releasing device's CPU");
1484
1485         /* Now release the CPU.  It will disconnect and reconnect later. */
1486         pvr2_hdw_cpureset_assert(hdw,0);
1487
1488         kfree(fw_ptr);
1489         release_firmware(fw_entry);
1490
1491         trace_firmware("Upload done (%d bytes sent)",ret);
1492
1493         /* We should have written 8192 bytes */
1494         if (ret == 8192) {
1495                 hdw->fw1_state = FW1_STATE_RELOAD;
1496                 return 0;
1497         }
1498
1499         return -EIO;
1500 }
1501
1502
1503 /*
1504  * pvr2_upload_firmware2()
1505  *
1506  * This uploads encoder firmware on endpoint 2.
1507  *
1508  */
1509
1510 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1511 {
1512         const struct firmware *fw_entry = NULL;
1513         void  *fw_ptr;
1514         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1515         int actual_length;
1516         int ret = 0;
1517         int fwidx;
1518         static const char *fw_files[] = {
1519                 CX2341X_FIRM_ENC_FILENAME,
1520         };
1521
1522         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1523                 return 0;
1524         }
1525
1526         trace_firmware("pvr2_upload_firmware2");
1527
1528         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1529                                    ARRAY_SIZE(fw_files), fw_files);
1530         if (ret < 0) return ret;
1531         fwidx = ret;
1532         ret = 0;
1533         /* Since we're about to completely reinitialize the encoder,
1534            invalidate our cached copy of its configuration state.  Next
1535            time we configure the encoder, then we'll fully configure it. */
1536         hdw->enc_cur_valid = 0;
1537
1538         /* Encoder is about to be reset so note that as far as we're
1539            concerned now, the encoder has never been run. */
1540         del_timer_sync(&hdw->encoder_run_timer);
1541         if (hdw->state_encoder_runok) {
1542                 hdw->state_encoder_runok = 0;
1543                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1544         }
1545
1546         /* First prepare firmware loading */
1547         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1548         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1549         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1550         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1551         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1552         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1553         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1554         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1555         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1556         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1557         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1558         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1559         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1560         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1561         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1562         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1563         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1564         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1565
1566         if (ret) {
1567                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1568                            "firmware2 upload prep failed, ret=%d",ret);
1569                 release_firmware(fw_entry);
1570                 goto done;
1571         }
1572
1573         /* Now send firmware */
1574
1575         fw_len = fw_entry->size;
1576
1577         if (fw_len % sizeof(u32)) {
1578                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1579                            "size of %s firmware"
1580                            " must be a multiple of %zu bytes",
1581                            fw_files[fwidx],sizeof(u32));
1582                 release_firmware(fw_entry);
1583                 ret = -EINVAL;
1584                 goto done;
1585         }
1586
1587         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1588         if (fw_ptr == NULL){
1589                 release_firmware(fw_entry);
1590                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1591                            "failed to allocate memory for firmware2 upload");
1592                 ret = -ENOMEM;
1593                 goto done;
1594         }
1595
1596         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1597
1598         fw_done = 0;
1599         for (fw_done = 0; fw_done < fw_len;) {
1600                 bcnt = fw_len - fw_done;
1601                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1602                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1603                 /* Usbsnoop log shows that we must swap bytes... */
1604                 /* Some background info: The data being swapped here is a
1605                    firmware image destined for the mpeg encoder chip that
1606                    lives at the other end of a USB endpoint.  The encoder
1607                    chip always talks in 32 bit chunks and its storage is
1608                    organized into 32 bit words.  However from the file
1609                    system to the encoder chip everything is purely a byte
1610                    stream.  The firmware file's contents are always 32 bit
1611                    swapped from what the encoder expects.  Thus the need
1612                    always exists to swap the bytes regardless of the endian
1613                    type of the host processor and therefore swab32() makes
1614                    the most sense. */
1615                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1616                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1617
1618                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1619                                     &actual_length, HZ);
1620                 ret |= (actual_length != bcnt);
1621                 if (ret) break;
1622                 fw_done += bcnt;
1623         }
1624
1625         trace_firmware("upload of %s : %i / %i ",
1626                        fw_files[fwidx],fw_done,fw_len);
1627
1628         kfree(fw_ptr);
1629         release_firmware(fw_entry);
1630
1631         if (ret) {
1632                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1633                            "firmware2 upload transfer failure");
1634                 goto done;
1635         }
1636
1637         /* Finish upload */
1638
1639         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1640         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1641         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1642
1643         if (ret) {
1644                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1645                            "firmware2 upload post-proc failure");
1646         }
1647
1648  done:
1649         if (hdw->hdw_desc->signal_routing_scheme ==
1650             PVR2_ROUTING_SCHEME_GOTVIEW) {
1651                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1652                    hardware. */
1653                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1654         }
1655         return ret;
1656 }
1657
1658
1659 static const char *pvr2_get_state_name(unsigned int st)
1660 {
1661         if (st < ARRAY_SIZE(pvr2_state_names)) {
1662                 return pvr2_state_names[st];
1663         }
1664         return "???";
1665 }
1666
1667 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1668 {
1669         if (hdw->decoder_ctrl) {
1670                 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt, enablefl);
1671                 return 0;
1672         }
1673         /* Even though we really only care about the video decoder chip at
1674            this point, we'll broadcast stream on/off to all sub-devices
1675            anyway, just in case somebody else wants to hear the
1676            command... */
1677         v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1678         if (hdw->decoder_client_id) {
1679                 /* We get here if the encoder has been noticed.  Otherwise
1680                    we'll issue a warning to the user (which should
1681                    normally never happen). */
1682                 return 0;
1683         }
1684         if (!hdw->flag_decoder_missed) {
1685                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1686                            "WARNING: No decoder present");
1687                 hdw->flag_decoder_missed = !0;
1688                 trace_stbit("flag_decoder_missed",
1689                             hdw->flag_decoder_missed);
1690         }
1691         return -EIO;
1692 }
1693
1694
1695 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1696 {
1697         if (hdw->decoder_ctrl == ptr) return;
1698         hdw->decoder_ctrl = ptr;
1699         if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1700                 hdw->flag_decoder_missed = 0;
1701                 trace_stbit("flag_decoder_missed",
1702                             hdw->flag_decoder_missed);
1703                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1704                            "Decoder has appeared");
1705                 pvr2_hdw_state_sched(hdw);
1706         }
1707 }
1708
1709
1710 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1711 {
1712         return hdw->master_state;
1713 }
1714
1715
1716 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1717 {
1718         if (!hdw->flag_tripped) return 0;
1719         hdw->flag_tripped = 0;
1720         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1721                    "Clearing driver error statuss");
1722         return !0;
1723 }
1724
1725
1726 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1727 {
1728         int fl;
1729         LOCK_TAKE(hdw->big_lock); do {
1730                 fl = pvr2_hdw_untrip_unlocked(hdw);
1731         } while (0); LOCK_GIVE(hdw->big_lock);
1732         if (fl) pvr2_hdw_state_sched(hdw);
1733         return 0;
1734 }
1735
1736
1737
1738
1739 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1740 {
1741         return hdw->state_pipeline_req != 0;
1742 }
1743
1744
1745 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1746 {
1747         int ret,st;
1748         LOCK_TAKE(hdw->big_lock); do {
1749                 pvr2_hdw_untrip_unlocked(hdw);
1750                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1751                         hdw->state_pipeline_req = enable_flag != 0;
1752                         pvr2_trace(PVR2_TRACE_START_STOP,
1753                                    "/*--TRACE_STREAM--*/ %s",
1754                                    enable_flag ? "enable" : "disable");
1755                 }
1756                 pvr2_hdw_state_sched(hdw);
1757         } while (0); LOCK_GIVE(hdw->big_lock);
1758         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1759         if (enable_flag) {
1760                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1761                         if (st != PVR2_STATE_READY) return -EIO;
1762                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1763                 }
1764         }
1765         return 0;
1766 }
1767
1768
1769 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1770 {
1771         int fl;
1772         LOCK_TAKE(hdw->big_lock);
1773         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1774                 hdw->desired_stream_type = config;
1775                 hdw->state_pipeline_config = 0;
1776                 trace_stbit("state_pipeline_config",
1777                             hdw->state_pipeline_config);
1778                 pvr2_hdw_state_sched(hdw);
1779         }
1780         LOCK_GIVE(hdw->big_lock);
1781         if (fl) return 0;
1782         return pvr2_hdw_wait(hdw,0);
1783 }
1784
1785
1786 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1787 {
1788         int unit_number = hdw->unit_number;
1789         int tp = -1;
1790         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1791                 tp = tuner[unit_number];
1792         }
1793         if (tp < 0) return -EINVAL;
1794         hdw->tuner_type = tp;
1795         hdw->tuner_updated = !0;
1796         return 0;
1797 }
1798
1799
1800 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1801 {
1802         int unit_number = hdw->unit_number;
1803         int tp = 0;
1804         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1805                 tp = video_std[unit_number];
1806                 if (tp) return tp;
1807         }
1808         return 0;
1809 }
1810
1811
1812 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1813 {
1814         int unit_number = hdw->unit_number;
1815         int tp = 0;
1816         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1817                 tp = tolerance[unit_number];
1818         }
1819         return tp;
1820 }
1821
1822
1823 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1824 {
1825         /* Try a harmless request to fetch the eeprom's address over
1826            endpoint 1.  See what happens.  Only the full FX2 image can
1827            respond to this.  If this probe fails then likely the FX2
1828            firmware needs be loaded. */
1829         int result;
1830         LOCK_TAKE(hdw->ctl_lock); do {
1831                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1832                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1833                                            hdw->cmd_buffer,1,
1834                                            hdw->cmd_buffer,1);
1835                 if (result < 0) break;
1836         } while(0); LOCK_GIVE(hdw->ctl_lock);
1837         if (result) {
1838                 pvr2_trace(PVR2_TRACE_INIT,
1839                            "Probe of device endpoint 1 result status %d",
1840                            result);
1841         } else {
1842                 pvr2_trace(PVR2_TRACE_INIT,
1843                            "Probe of device endpoint 1 succeeded");
1844         }
1845         return result == 0;
1846 }
1847
1848 struct pvr2_std_hack {
1849         v4l2_std_id pat;  /* Pattern to match */
1850         v4l2_std_id msk;  /* Which bits we care about */
1851         v4l2_std_id std;  /* What additional standards or default to set */
1852 };
1853
1854 /* This data structure labels specific combinations of standards from
1855    tveeprom that we'll try to recognize.  If we recognize one, then assume
1856    a specified default standard to use.  This is here because tveeprom only
1857    tells us about available standards not the intended default standard (if
1858    any) for the device in question.  We guess the default based on what has
1859    been reported as available.  Note that this is only for guessing a
1860    default - which can always be overridden explicitly - and if the user
1861    has otherwise named a default then that default will always be used in
1862    place of this table. */
1863 static const struct pvr2_std_hack std_eeprom_maps[] = {
1864         {       /* PAL(B/G) */
1865                 .pat = V4L2_STD_B|V4L2_STD_GH,
1866                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1867         },
1868         {       /* NTSC(M) */
1869                 .pat = V4L2_STD_MN,
1870                 .std = V4L2_STD_NTSC_M,
1871         },
1872         {       /* PAL(I) */
1873                 .pat = V4L2_STD_PAL_I,
1874                 .std = V4L2_STD_PAL_I,
1875         },
1876         {       /* SECAM(L/L') */
1877                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1878                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1879         },
1880         {       /* PAL(D/D1/K) */
1881                 .pat = V4L2_STD_DK,
1882                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1883         },
1884 };
1885
1886 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1887 {
1888         char buf[40];
1889         unsigned int bcnt;
1890         v4l2_std_id std1,std2,std3;
1891
1892         std1 = get_default_standard(hdw);
1893         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1894
1895         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1896         pvr2_trace(PVR2_TRACE_STD,
1897                    "Supported video standard(s) reported available"
1898                    " in hardware: %.*s",
1899                    bcnt,buf);
1900
1901         hdw->std_mask_avail = hdw->std_mask_eeprom;
1902
1903         std2 = (std1|std3) & ~hdw->std_mask_avail;
1904         if (std2) {
1905                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1906                 pvr2_trace(PVR2_TRACE_STD,
1907                            "Expanding supported video standards"
1908                            " to include: %.*s",
1909                            bcnt,buf);
1910                 hdw->std_mask_avail |= std2;
1911         }
1912
1913         pvr2_hdw_internal_set_std_avail(hdw);
1914
1915         if (std1) {
1916                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1917                 pvr2_trace(PVR2_TRACE_STD,
1918                            "Initial video standard forced to %.*s",
1919                            bcnt,buf);
1920                 hdw->std_mask_cur = std1;
1921                 hdw->std_dirty = !0;
1922                 pvr2_hdw_internal_find_stdenum(hdw);
1923                 return;
1924         }
1925         if (std3) {
1926                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1927                 pvr2_trace(PVR2_TRACE_STD,
1928                            "Initial video standard"
1929                            " (determined by device type): %.*s",bcnt,buf);
1930                 hdw->std_mask_cur = std3;
1931                 hdw->std_dirty = !0;
1932                 pvr2_hdw_internal_find_stdenum(hdw);
1933                 return;
1934         }
1935
1936         {
1937                 unsigned int idx;
1938                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1939                         if (std_eeprom_maps[idx].msk ?
1940                             ((std_eeprom_maps[idx].pat ^
1941                              hdw->std_mask_eeprom) &
1942                              std_eeprom_maps[idx].msk) :
1943                             (std_eeprom_maps[idx].pat !=
1944                              hdw->std_mask_eeprom)) continue;
1945                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1946                                                   std_eeprom_maps[idx].std);
1947                         pvr2_trace(PVR2_TRACE_STD,
1948                                    "Initial video standard guessed as %.*s",
1949                                    bcnt,buf);
1950                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1951                         hdw->std_dirty = !0;
1952                         pvr2_hdw_internal_find_stdenum(hdw);
1953                         return;
1954                 }
1955         }
1956
1957         if (hdw->std_enum_cnt > 1) {
1958                 // Autoselect the first listed standard
1959                 hdw->std_enum_cur = 1;
1960                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1961                 hdw->std_dirty = !0;
1962                 pvr2_trace(PVR2_TRACE_STD,
1963                            "Initial video standard auto-selected to %s",
1964                            hdw->std_defs[hdw->std_enum_cur-1].name);
1965                 return;
1966         }
1967
1968         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1969                    "Unable to select a viable initial video standard");
1970 }
1971
1972
1973 static unsigned int pvr2_copy_i2c_addr_list(
1974         unsigned short *dst, const unsigned char *src,
1975         unsigned int dst_max)
1976 {
1977         unsigned int cnt;
1978         if (!src) return 0;
1979         while (src[cnt] && (cnt + 1) < dst_max) {
1980                 dst[cnt] = src[cnt];
1981                 cnt++;
1982         }
1983         dst[cnt] = I2C_CLIENT_END;
1984         return cnt;
1985 }
1986
1987
1988 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1989                                 const struct pvr2_device_client_desc *cd)
1990 {
1991         const char *fname;
1992         unsigned char mid;
1993         struct v4l2_subdev *sd;
1994         unsigned int i2ccnt;
1995         const unsigned char *p;
1996         /* Arbitrary count - max # i2c addresses we will probe */
1997         unsigned short i2caddr[25];
1998
1999         mid = cd->module_id;
2000         fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2001         if (!fname) {
2002                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2003                            "Module ID %u for device %s has no name",
2004                            mid,
2005                            hdw->hdw_desc->description);
2006                 return -EINVAL;
2007         }
2008
2009         i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2010                                          ARRAY_SIZE(i2caddr));
2011         if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2012                          module_i2c_addresses[mid] : NULL) != NULL)) {
2013                 /* Second chance: Try default i2c address list */
2014                 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2015                                                  ARRAY_SIZE(i2caddr));
2016         }
2017
2018         if (!i2ccnt) {
2019                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2020                            "Module ID %u (%s) for device %s:"
2021                            " No i2c addresses",
2022                            mid, fname, hdw->hdw_desc->description);
2023                 return -EINVAL;
2024         }
2025
2026         /* Note how the 2nd and 3rd arguments are the same for both
2027          * v4l2_i2c_new_subdev() and v4l2_i2c_new_probed_subdev().  Why?
2028          * Well the 2nd argument is the module name to load, while the 3rd
2029          * argument is documented in the framework as being the "chipid" -
2030          * and every other place where I can find examples of this, the
2031          * "chipid" appears to just be the module name again.  So here we
2032          * just do the same thing. */
2033         if (i2ccnt == 1) {
2034                 sd = v4l2_i2c_new_subdev(&hdw->i2c_adap,
2035                                          fname, fname,
2036                                          i2caddr[0]);
2037         } else {
2038                 sd = v4l2_i2c_new_probed_subdev(&hdw->i2c_adap,
2039                                                 fname, fname,
2040                                                 i2caddr);
2041         }
2042
2043         if (!sd) {
2044                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2045                            "Module ID %u (%s) for device %s failed to load",
2046                            mid, fname, hdw->hdw_desc->description);
2047                 return -EIO;
2048         }
2049
2050         /* Tag this sub-device instance with the module ID we know about.
2051            In other places we'll use that tag to determine if the instance
2052            requires special handling. */
2053         sd->grp_id = mid;
2054
2055         /* If we have both old and new i2c layers enabled, make sure that
2056            old layer isn't also tracking this module.  This is a debugging
2057            aid, in normal situations there's no reason for both mechanisms
2058            to be enabled. */
2059         pvr2_i2c_untrack_subdev(hdw, sd);
2060         pvr2_trace(PVR2_TRACE_INIT, "Attached sub-driver %s", fname);
2061
2062
2063         /* client-specific setup... */
2064         switch (mid) {
2065         case PVR2_CLIENT_ID_CX25840:
2066                 hdw->decoder_client_id = mid;
2067                 {
2068                         /*
2069                           Mike Isely <isely@pobox.com> 19-Nov-2006 - This
2070                           bit of nuttiness for cx25840 causes that module
2071                           to correctly set up its video scaling.  This is
2072                           really a problem in the cx25840 module itself,
2073                           but we work around it here.  The problem has not
2074                           been seen in ivtv because there VBI is supported
2075                           and set up.  We don't do VBI here (at least not
2076                           yet) and thus we never attempted to even set it
2077                           up.
2078                         */
2079                         struct v4l2_format fmt;
2080                         memset(&fmt, 0, sizeof(fmt));
2081                         fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2082                         v4l2_device_call_all(&hdw->v4l2_dev, mid,
2083                                              video, s_fmt, &fmt);
2084                 }
2085                 break;
2086         case PVR2_CLIENT_ID_SAA7115:
2087                 hdw->decoder_client_id = mid;
2088                 break;
2089         default: break;
2090         }
2091
2092         return 0;
2093 }
2094
2095
2096 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2097 {
2098         unsigned int idx;
2099         const struct pvr2_string_table *cm;
2100         const struct pvr2_device_client_table *ct;
2101         int okFl = !0;
2102
2103         cm = &hdw->hdw_desc->client_modules;
2104         for (idx = 0; idx < cm->cnt; idx++) {
2105                 request_module(cm->lst[idx]);
2106         }
2107
2108         ct = &hdw->hdw_desc->client_table;
2109         for (idx = 0; idx < ct->cnt; idx++) {
2110                 if (!pvr2_hdw_load_subdev(hdw, &ct->lst[idx])) okFl = 0;
2111         }
2112         if (!okFl) pvr2_hdw_render_useless(hdw);
2113 }
2114
2115
2116 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2117 {
2118         int ret;
2119         unsigned int idx;
2120         struct pvr2_ctrl *cptr;
2121         int reloadFl = 0;
2122         if (hdw->hdw_desc->fx2_firmware.cnt) {
2123                 if (!reloadFl) {
2124                         reloadFl =
2125                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2126                                  == 0);
2127                         if (reloadFl) {
2128                                 pvr2_trace(PVR2_TRACE_INIT,
2129                                            "USB endpoint config looks strange"
2130                                            "; possibly firmware needs to be"
2131                                            " loaded");
2132                         }
2133                 }
2134                 if (!reloadFl) {
2135                         reloadFl = !pvr2_hdw_check_firmware(hdw);
2136                         if (reloadFl) {
2137                                 pvr2_trace(PVR2_TRACE_INIT,
2138                                            "Check for FX2 firmware failed"
2139                                            "; possibly firmware needs to be"
2140                                            " loaded");
2141                         }
2142                 }
2143                 if (reloadFl) {
2144                         if (pvr2_upload_firmware1(hdw) != 0) {
2145                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2146                                            "Failure uploading firmware1");
2147                         }
2148                         return;
2149                 }
2150         }
2151         hdw->fw1_state = FW1_STATE_OK;
2152
2153         if (!pvr2_hdw_dev_ok(hdw)) return;
2154
2155         if (!hdw->hdw_desc->flag_no_powerup) {
2156                 pvr2_hdw_cmd_powerup(hdw);
2157                 if (!pvr2_hdw_dev_ok(hdw)) return;
2158         }
2159
2160         /* Take the IR chip out of reset, if appropriate */
2161         if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
2162                 pvr2_issue_simple_cmd(hdw,
2163                                       FX2CMD_HCW_ZILOG_RESET |
2164                                       (1 << 8) |
2165                                       ((0) << 16));
2166         }
2167
2168         // This step MUST happen after the earlier powerup step.
2169         pvr2_i2c_track_init(hdw);
2170         pvr2_i2c_core_init(hdw);
2171         if (!pvr2_hdw_dev_ok(hdw)) return;
2172
2173         pvr2_hdw_load_modules(hdw);
2174         if (!pvr2_hdw_dev_ok(hdw)) return;
2175
2176         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2177                 cptr = hdw->controls + idx;
2178                 if (cptr->info->skip_init) continue;
2179                 if (!cptr->info->set_value) continue;
2180                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2181         }
2182
2183         /* Set up special default values for the television and radio
2184            frequencies here.  It's not really important what these defaults
2185            are, but I set them to something usable in the Chicago area just
2186            to make driver testing a little easier. */
2187
2188         hdw->freqValTelevision = default_tv_freq;
2189         hdw->freqValRadio = default_radio_freq;
2190
2191         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2192         // thread-safe against the normal pvr2_send_request() mechanism.
2193         // (We should make it thread safe).
2194
2195         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2196                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2197                 if (!pvr2_hdw_dev_ok(hdw)) return;
2198                 if (ret < 0) {
2199                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2200                                    "Unable to determine location of eeprom,"
2201                                    " skipping");
2202                 } else {
2203                         hdw->eeprom_addr = ret;
2204                         pvr2_eeprom_analyze(hdw);
2205                         if (!pvr2_hdw_dev_ok(hdw)) return;
2206                 }
2207         } else {
2208                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2209                 hdw->tuner_updated = !0;
2210                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2211         }
2212
2213         if (hdw->serial_number) {
2214                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2215                                 "sn-%lu", hdw->serial_number);
2216         } else if (hdw->unit_number >= 0) {
2217                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2218                                 "unit-%c",
2219                                 hdw->unit_number + 'a');
2220         } else {
2221                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2222                                 "unit-??");
2223         }
2224         hdw->identifier[idx] = 0;
2225
2226         pvr2_hdw_setup_std(hdw);
2227
2228         if (!get_default_tuner_type(hdw)) {
2229                 pvr2_trace(PVR2_TRACE_INIT,
2230                            "pvr2_hdw_setup: Tuner type overridden to %d",
2231                            hdw->tuner_type);
2232         }
2233
2234         pvr2_i2c_core_check_stale(hdw);
2235         hdw->tuner_updated = 0;
2236
2237         if (!pvr2_hdw_dev_ok(hdw)) return;
2238
2239         if (hdw->hdw_desc->signal_routing_scheme ==
2240             PVR2_ROUTING_SCHEME_GOTVIEW) {
2241                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2242                    hardware. */
2243                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2244         }
2245
2246         pvr2_hdw_commit_setup(hdw);
2247
2248         hdw->vid_stream = pvr2_stream_create();
2249         if (!pvr2_hdw_dev_ok(hdw)) return;
2250         pvr2_trace(PVR2_TRACE_INIT,
2251                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2252         if (hdw->vid_stream) {
2253                 idx = get_default_error_tolerance(hdw);
2254                 if (idx) {
2255                         pvr2_trace(PVR2_TRACE_INIT,
2256                                    "pvr2_hdw_setup: video stream %p"
2257                                    " setting tolerance %u",
2258                                    hdw->vid_stream,idx);
2259                 }
2260                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2261                                   PVR2_VID_ENDPOINT,idx);
2262         }
2263
2264         if (!pvr2_hdw_dev_ok(hdw)) return;
2265
2266         hdw->flag_init_ok = !0;
2267
2268         pvr2_hdw_state_sched(hdw);
2269 }
2270
2271
2272 /* Set up the structure and attempt to put the device into a usable state.
2273    This can be a time-consuming operation, which is why it is not done
2274    internally as part of the create() step. */
2275 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2276 {
2277         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2278         do {
2279                 pvr2_hdw_setup_low(hdw);
2280                 pvr2_trace(PVR2_TRACE_INIT,
2281                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2282                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2283                 if (pvr2_hdw_dev_ok(hdw)) {
2284                         if (hdw->flag_init_ok) {
2285                                 pvr2_trace(
2286                                         PVR2_TRACE_INFO,
2287                                         "Device initialization"
2288                                         " completed successfully.");
2289                                 break;
2290                         }
2291                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2292                                 pvr2_trace(
2293                                         PVR2_TRACE_INFO,
2294                                         "Device microcontroller firmware"
2295                                         " (re)loaded; it should now reset"
2296                                         " and reconnect.");
2297                                 break;
2298                         }
2299                         pvr2_trace(
2300                                 PVR2_TRACE_ERROR_LEGS,
2301                                 "Device initialization was not successful.");
2302                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2303                                 pvr2_trace(
2304                                         PVR2_TRACE_ERROR_LEGS,
2305                                         "Giving up since device"
2306                                         " microcontroller firmware"
2307                                         " appears to be missing.");
2308                                 break;
2309                         }
2310                 }
2311                 if (procreload) {
2312                         pvr2_trace(
2313                                 PVR2_TRACE_ERROR_LEGS,
2314                                 "Attempting pvrusb2 recovery by reloading"
2315                                 " primary firmware.");
2316                         pvr2_trace(
2317                                 PVR2_TRACE_ERROR_LEGS,
2318                                 "If this works, device should disconnect"
2319                                 " and reconnect in a sane state.");
2320                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2321                         pvr2_upload_firmware1(hdw);
2322                 } else {
2323                         pvr2_trace(
2324                                 PVR2_TRACE_ERROR_LEGS,
2325                                 "***WARNING*** pvrusb2 device hardware"
2326                                 " appears to be jammed"
2327                                 " and I can't clear it.");
2328                         pvr2_trace(
2329                                 PVR2_TRACE_ERROR_LEGS,
2330                                 "You might need to power cycle"
2331                                 " the pvrusb2 device"
2332                                 " in order to recover.");
2333                 }
2334         } while (0);
2335         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2336 }
2337
2338
2339 /* Perform second stage initialization.  Set callback pointer first so that
2340    we can avoid a possible initialization race (if the kernel thread runs
2341    before the callback has been set). */
2342 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2343                         void (*callback_func)(void *),
2344                         void *callback_data)
2345 {
2346         LOCK_TAKE(hdw->big_lock); do {
2347                 if (hdw->flag_disconnected) {
2348                         /* Handle a race here: If we're already
2349                            disconnected by this point, then give up.  If we
2350                            get past this then we'll remain connected for
2351                            the duration of initialization since the entire
2352                            initialization sequence is now protected by the
2353                            big_lock. */
2354                         break;
2355                 }
2356                 hdw->state_data = callback_data;
2357                 hdw->state_func = callback_func;
2358                 pvr2_hdw_setup(hdw);
2359         } while (0); LOCK_GIVE(hdw->big_lock);
2360         return hdw->flag_init_ok;
2361 }
2362
2363
2364 /* Create, set up, and return a structure for interacting with the
2365    underlying hardware.  */
2366 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2367                                  const struct usb_device_id *devid)
2368 {
2369         unsigned int idx,cnt1,cnt2,m;
2370         struct pvr2_hdw *hdw = NULL;
2371         int valid_std_mask;
2372         struct pvr2_ctrl *cptr;
2373         struct usb_device *usb_dev;
2374         const struct pvr2_device_desc *hdw_desc;
2375         __u8 ifnum;
2376         struct v4l2_queryctrl qctrl;
2377         struct pvr2_ctl_info *ciptr;
2378
2379         usb_dev = interface_to_usbdev(intf);
2380
2381         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2382
2383         if (hdw_desc == NULL) {
2384                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2385                            " No device description pointer,"
2386                            " unable to continue.");
2387                 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2388                            " please contact Mike Isely <isely@pobox.com>"
2389                            " to get it included in the driver\n");
2390                 goto fail;
2391         }
2392
2393         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2394         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2395                    hdw,hdw_desc->description);
2396         if (!hdw) goto fail;
2397
2398         init_timer(&hdw->quiescent_timer);
2399         hdw->quiescent_timer.data = (unsigned long)hdw;
2400         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2401
2402         init_timer(&hdw->encoder_wait_timer);
2403         hdw->encoder_wait_timer.data = (unsigned long)hdw;
2404         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2405
2406         init_timer(&hdw->encoder_run_timer);
2407         hdw->encoder_run_timer.data = (unsigned long)hdw;
2408         hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2409
2410         hdw->master_state = PVR2_STATE_DEAD;
2411
2412         init_waitqueue_head(&hdw->state_wait_data);
2413
2414         hdw->tuner_signal_stale = !0;
2415         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2416
2417         /* Calculate which inputs are OK */
2418         m = 0;
2419         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2420         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2421                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2422         }
2423         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2424         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2425         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2426         hdw->input_avail_mask = m;
2427         hdw->input_allowed_mask = hdw->input_avail_mask;
2428
2429         /* If not a hybrid device, pathway_state never changes.  So
2430            initialize it here to what it should forever be. */
2431         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2432                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2433         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2434                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2435         }
2436
2437         hdw->control_cnt = CTRLDEF_COUNT;
2438         hdw->control_cnt += MPEGDEF_COUNT;
2439         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2440                                 GFP_KERNEL);
2441         if (!hdw->controls) goto fail;
2442         hdw->hdw_desc = hdw_desc;
2443         for (idx = 0; idx < hdw->control_cnt; idx++) {
2444                 cptr = hdw->controls + idx;
2445                 cptr->hdw = hdw;
2446         }
2447         for (idx = 0; idx < 32; idx++) {
2448                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2449         }
2450         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2451                 cptr = hdw->controls + idx;
2452                 cptr->info = control_defs+idx;
2453         }
2454
2455         /* Ensure that default input choice is a valid one. */
2456         m = hdw->input_avail_mask;
2457         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2458                 if (!((1 << idx) & m)) continue;
2459                 hdw->input_val = idx;
2460                 break;
2461         }
2462
2463         /* Define and configure additional controls from cx2341x module. */
2464         hdw->mpeg_ctrl_info = kzalloc(
2465                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2466         if (!hdw->mpeg_ctrl_info) goto fail;
2467         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2468                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2469                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2470                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2471                 ciptr->name = mpeg_ids[idx].strid;
2472                 ciptr->v4l_id = mpeg_ids[idx].id;
2473                 ciptr->skip_init = !0;
2474                 ciptr->get_value = ctrl_cx2341x_get;
2475                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2476                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2477                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2478                 qctrl.id = ciptr->v4l_id;
2479                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2480                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2481                         ciptr->set_value = ctrl_cx2341x_set;
2482                 }
2483                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2484                         PVR2_CTLD_INFO_DESC_SIZE);
2485                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2486                 ciptr->default_value = qctrl.default_value;
2487                 switch (qctrl.type) {
2488                 default:
2489                 case V4L2_CTRL_TYPE_INTEGER:
2490                         ciptr->type = pvr2_ctl_int;
2491                         ciptr->def.type_int.min_value = qctrl.minimum;
2492                         ciptr->def.type_int.max_value = qctrl.maximum;
2493                         break;
2494                 case V4L2_CTRL_TYPE_BOOLEAN:
2495                         ciptr->type = pvr2_ctl_bool;
2496                         break;
2497                 case V4L2_CTRL_TYPE_MENU:
2498                         ciptr->type = pvr2_ctl_enum;
2499                         ciptr->def.type_enum.value_names =
2500                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2501                                                                 ciptr->v4l_id);
2502                         for (cnt1 = 0;
2503                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2504                              cnt1++) { }
2505                         ciptr->def.type_enum.count = cnt1;
2506                         break;
2507                 }
2508                 cptr->info = ciptr;
2509         }
2510
2511         // Initialize video standard enum dynamic control
2512         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2513         if (cptr) {
2514                 memcpy(&hdw->std_info_enum,cptr->info,
2515                        sizeof(hdw->std_info_enum));
2516                 cptr->info = &hdw->std_info_enum;
2517
2518         }
2519         // Initialize control data regarding video standard masks
2520         valid_std_mask = pvr2_std_get_usable();
2521         for (idx = 0; idx < 32; idx++) {
2522                 if (!(valid_std_mask & (1 << idx))) continue;
2523                 cnt1 = pvr2_std_id_to_str(
2524                         hdw->std_mask_names[idx],
2525                         sizeof(hdw->std_mask_names[idx])-1,
2526                         1 << idx);
2527                 hdw->std_mask_names[idx][cnt1] = 0;
2528         }
2529         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2530         if (cptr) {
2531                 memcpy(&hdw->std_info_avail,cptr->info,
2532                        sizeof(hdw->std_info_avail));
2533                 cptr->info = &hdw->std_info_avail;
2534                 hdw->std_info_avail.def.type_bitmask.bit_names =
2535                         hdw->std_mask_ptrs;
2536                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2537                         valid_std_mask;
2538         }
2539         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2540         if (cptr) {
2541                 memcpy(&hdw->std_info_cur,cptr->info,
2542                        sizeof(hdw->std_info_cur));
2543                 cptr->info = &hdw->std_info_cur;
2544                 hdw->std_info_cur.def.type_bitmask.bit_names =
2545                         hdw->std_mask_ptrs;
2546                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2547                         valid_std_mask;
2548         }
2549
2550         hdw->cropcap_stale = !0;
2551         hdw->eeprom_addr = -1;
2552         hdw->unit_number = -1;
2553         hdw->v4l_minor_number_video = -1;
2554         hdw->v4l_minor_number_vbi = -1;
2555         hdw->v4l_minor_number_radio = -1;
2556         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2557         if (!hdw->ctl_write_buffer) goto fail;
2558         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2559         if (!hdw->ctl_read_buffer) goto fail;
2560         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2561         if (!hdw->ctl_write_urb) goto fail;
2562         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2563         if (!hdw->ctl_read_urb) goto fail;
2564
2565         if (v4l2_device_register(&usb_dev->dev, &hdw->v4l2_dev) != 0) {
2566                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2567                            "Error registering with v4l core, giving up");
2568                 goto fail;
2569         }
2570         mutex_lock(&pvr2_unit_mtx); do {
2571                 for (idx = 0; idx < PVR_NUM; idx++) {
2572                         if (unit_pointers[idx]) continue;
2573                         hdw->unit_number = idx;
2574                         unit_pointers[idx] = hdw;
2575                         break;
2576                 }
2577         } while (0); mutex_unlock(&pvr2_unit_mtx);
2578
2579         cnt1 = 0;
2580         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2581         cnt1 += cnt2;
2582         if (hdw->unit_number >= 0) {
2583                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2584                                  ('a' + hdw->unit_number));
2585                 cnt1 += cnt2;
2586         }
2587         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2588         hdw->name[cnt1] = 0;
2589
2590         hdw->workqueue = create_singlethread_workqueue(hdw->name);
2591         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2592         INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2593
2594         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2595                    hdw->unit_number,hdw->name);
2596
2597         hdw->tuner_type = -1;
2598         hdw->flag_ok = !0;
2599
2600         hdw->usb_intf = intf;
2601         hdw->usb_dev = usb_dev;
2602
2603         usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2604
2605         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2606         usb_set_interface(hdw->usb_dev,ifnum,0);
2607
2608         mutex_init(&hdw->ctl_lock_mutex);
2609         mutex_init(&hdw->big_lock_mutex);
2610
2611         return hdw;
2612  fail:
2613         if (hdw) {
2614                 del_timer_sync(&hdw->quiescent_timer);
2615                 del_timer_sync(&hdw->encoder_run_timer);
2616                 del_timer_sync(&hdw->encoder_wait_timer);
2617                 if (hdw->workqueue) {
2618                         flush_workqueue(hdw->workqueue);
2619                         destroy_workqueue(hdw->workqueue);
2620                         hdw->workqueue = NULL;
2621                 }
2622                 usb_free_urb(hdw->ctl_read_urb);
2623                 usb_free_urb(hdw->ctl_write_urb);
2624                 kfree(hdw->ctl_read_buffer);
2625                 kfree(hdw->ctl_write_buffer);
2626                 kfree(hdw->controls);
2627                 kfree(hdw->mpeg_ctrl_info);
2628                 kfree(hdw->std_defs);
2629                 kfree(hdw->std_enum_names);
2630                 kfree(hdw);
2631         }
2632         return NULL;
2633 }
2634
2635
2636 /* Remove _all_ associations between this driver and the underlying USB
2637    layer. */
2638 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2639 {
2640         if (hdw->flag_disconnected) return;
2641         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2642         if (hdw->ctl_read_urb) {
2643                 usb_kill_urb(hdw->ctl_read_urb);
2644                 usb_free_urb(hdw->ctl_read_urb);
2645                 hdw->ctl_read_urb = NULL;
2646         }
2647         if (hdw->ctl_write_urb) {
2648                 usb_kill_urb(hdw->ctl_write_urb);
2649                 usb_free_urb(hdw->ctl_write_urb);
2650                 hdw->ctl_write_urb = NULL;
2651         }
2652         if (hdw->ctl_read_buffer) {
2653                 kfree(hdw->ctl_read_buffer);
2654                 hdw->ctl_read_buffer = NULL;
2655         }
2656         if (hdw->ctl_write_buffer) {
2657                 kfree(hdw->ctl_write_buffer);
2658                 hdw->ctl_write_buffer = NULL;
2659         }
2660         hdw->flag_disconnected = !0;
2661         /* If we don't do this, then there will be a dangling struct device
2662            reference to our disappearing device persisting inside the V4L
2663            core... */
2664         if (hdw->v4l2_dev.dev) {
2665                 dev_set_drvdata(hdw->v4l2_dev.dev, NULL);
2666                 hdw->v4l2_dev.dev = NULL;
2667         }
2668         hdw->usb_dev = NULL;
2669         hdw->usb_intf = NULL;
2670         pvr2_hdw_render_useless(hdw);
2671 }
2672
2673
2674 /* Destroy hardware interaction structure */
2675 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2676 {
2677         if (!hdw) return;
2678         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2679         if (hdw->workqueue) {
2680                 flush_workqueue(hdw->workqueue);
2681                 destroy_workqueue(hdw->workqueue);
2682                 hdw->workqueue = NULL;
2683         }
2684         del_timer_sync(&hdw->quiescent_timer);
2685         del_timer_sync(&hdw->encoder_run_timer);
2686         del_timer_sync(&hdw->encoder_wait_timer);
2687         if (hdw->fw_buffer) {
2688                 kfree(hdw->fw_buffer);
2689                 hdw->fw_buffer = NULL;
2690         }
2691         if (hdw->vid_stream) {
2692                 pvr2_stream_destroy(hdw->vid_stream);
2693                 hdw->vid_stream = NULL;
2694         }
2695         if (hdw->decoder_ctrl) {
2696                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2697         }
2698         pvr2_i2c_core_done(hdw);
2699         pvr2_i2c_track_done(hdw);
2700         v4l2_device_unregister(&hdw->v4l2_dev);
2701         pvr2_hdw_remove_usb_stuff(hdw);
2702         mutex_lock(&pvr2_unit_mtx); do {
2703                 if ((hdw->unit_number >= 0) &&
2704                     (hdw->unit_number < PVR_NUM) &&
2705                     (unit_pointers[hdw->unit_number] == hdw)) {
2706                         unit_pointers[hdw->unit_number] = NULL;
2707                 }
2708         } while (0); mutex_unlock(&pvr2_unit_mtx);
2709         kfree(hdw->controls);
2710         kfree(hdw->mpeg_ctrl_info);
2711         kfree(hdw->std_defs);
2712         kfree(hdw->std_enum_names);
2713         kfree(hdw);
2714 }
2715
2716
2717 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2718 {
2719         return (hdw && hdw->flag_ok);
2720 }
2721
2722
2723 /* Called when hardware has been unplugged */
2724 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2725 {
2726         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2727         LOCK_TAKE(hdw->big_lock);
2728         LOCK_TAKE(hdw->ctl_lock);
2729         pvr2_hdw_remove_usb_stuff(hdw);
2730         LOCK_GIVE(hdw->ctl_lock);
2731         LOCK_GIVE(hdw->big_lock);
2732 }
2733
2734
2735 // Attempt to autoselect an appropriate value for std_enum_cur given
2736 // whatever is currently in std_mask_cur
2737 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2738 {
2739         unsigned int idx;
2740         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2741                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2742                         hdw->std_enum_cur = idx;
2743                         return;
2744                 }
2745         }
2746         hdw->std_enum_cur = 0;
2747 }
2748
2749
2750 // Calculate correct set of enumerated standards based on currently known
2751 // set of available standards bits.
2752 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2753 {
2754         struct v4l2_standard *newstd;
2755         unsigned int std_cnt;
2756         unsigned int idx;
2757
2758         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2759
2760         if (hdw->std_defs) {
2761                 kfree(hdw->std_defs);
2762                 hdw->std_defs = NULL;
2763         }
2764         hdw->std_enum_cnt = 0;
2765         if (hdw->std_enum_names) {
2766                 kfree(hdw->std_enum_names);
2767                 hdw->std_enum_names = NULL;
2768         }
2769
2770         if (!std_cnt) {
2771                 pvr2_trace(
2772                         PVR2_TRACE_ERROR_LEGS,
2773                         "WARNING: Failed to identify any viable standards");
2774         }
2775         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2776         hdw->std_enum_names[0] = "none";
2777         for (idx = 0; idx < std_cnt; idx++) {
2778                 hdw->std_enum_names[idx+1] =
2779                         newstd[idx].name;
2780         }
2781         // Set up the dynamic control for this standard
2782         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2783         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2784         hdw->std_defs = newstd;
2785         hdw->std_enum_cnt = std_cnt+1;
2786         hdw->std_enum_cur = 0;
2787         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2788 }
2789
2790
2791 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2792                                struct v4l2_standard *std,
2793                                unsigned int idx)
2794 {
2795         int ret = -EINVAL;
2796         if (!idx) return ret;
2797         LOCK_TAKE(hdw->big_lock); do {
2798                 if (idx >= hdw->std_enum_cnt) break;
2799                 idx--;
2800                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2801                 ret = 0;
2802         } while (0); LOCK_GIVE(hdw->big_lock);
2803         return ret;
2804 }
2805
2806
2807 /* Get the number of defined controls */
2808 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2809 {
2810         return hdw->control_cnt;
2811 }
2812
2813
2814 /* Retrieve a control handle given its index (0..count-1) */
2815 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2816                                              unsigned int idx)
2817 {
2818         if (idx >= hdw->control_cnt) return NULL;
2819         return hdw->controls + idx;
2820 }
2821
2822
2823 /* Retrieve a control handle given its index (0..count-1) */
2824 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2825                                           unsigned int ctl_id)
2826 {
2827         struct pvr2_ctrl *cptr;
2828         unsigned int idx;
2829         int i;
2830
2831         /* This could be made a lot more efficient, but for now... */
2832         for (idx = 0; idx < hdw->control_cnt; idx++) {
2833                 cptr = hdw->controls + idx;
2834                 i = cptr->info->internal_id;
2835                 if (i && (i == ctl_id)) return cptr;
2836         }
2837         return NULL;
2838 }
2839
2840
2841 /* Given a V4L ID, retrieve the control structure associated with it. */
2842 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2843 {
2844         struct pvr2_ctrl *cptr;
2845         unsigned int idx;
2846         int i;
2847
2848         /* This could be made a lot more efficient, but for now... */
2849         for (idx = 0; idx < hdw->control_cnt; idx++) {
2850                 cptr = hdw->controls + idx;
2851                 i = cptr->info->v4l_id;
2852                 if (i && (i == ctl_id)) return cptr;
2853         }
2854         return NULL;
2855 }
2856
2857
2858 /* Given a V4L ID for its immediate predecessor, retrieve the control
2859    structure associated with it. */
2860 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2861                                             unsigned int ctl_id)
2862 {
2863         struct pvr2_ctrl *cptr,*cp2;
2864         unsigned int idx;
2865         int i;
2866
2867         /* This could be made a lot more efficient, but for now... */
2868         cp2 = NULL;
2869         for (idx = 0; idx < hdw->control_cnt; idx++) {
2870                 cptr = hdw->controls + idx;
2871                 i = cptr->info->v4l_id;
2872                 if (!i) continue;
2873                 if (i <= ctl_id) continue;
2874                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2875                 cp2 = cptr;
2876         }
2877         return cp2;
2878         return NULL;
2879 }
2880
2881
2882 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2883 {
2884         switch (tp) {
2885         case pvr2_ctl_int: return "integer";
2886         case pvr2_ctl_enum: return "enum";
2887         case pvr2_ctl_bool: return "boolean";
2888         case pvr2_ctl_bitmask: return "bitmask";
2889         }
2890         return "";
2891 }
2892
2893
2894 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2895                                     const char *name, int val)
2896 {
2897         struct v4l2_control ctrl;
2898         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2899         memset(&ctrl, 0, sizeof(ctrl));
2900         ctrl.id = id;
2901         ctrl.value = val;
2902         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2903 }
2904
2905 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2906         if ((hdw)->lab##_dirty) { \
2907                 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2908         }
2909
2910 /* Execute whatever commands are required to update the state of all the
2911    sub-devices so that they match our current control values. */
2912 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2913 {
2914         struct v4l2_subdev *sd;
2915         unsigned int id;
2916         pvr2_subdev_update_func fp;
2917
2918         if (hdw->input_dirty || hdw->std_dirty) {
2919                 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_standard");
2920                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2921                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2922                                              tuner, s_radio);
2923                 } else {
2924                         v4l2_std_id vs;
2925                         vs = hdw->std_mask_cur;
2926                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2927                                              tuner, s_std, vs);
2928                 }
2929                 hdw->tuner_signal_stale = !0;
2930                 hdw->cropcap_stale = !0;
2931         }
2932
2933         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2934         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2935         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2936         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2937         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2938         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2939         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2940         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2941         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2942
2943         if (hdw->input_dirty || hdw->audiomode_dirty) {
2944                 struct v4l2_tuner vt;
2945                 memset(&vt, 0, sizeof(vt));
2946                 vt.audmode = hdw->audiomode_val;
2947                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2948         }
2949
2950         if (hdw->freqDirty) {
2951                 unsigned long fv;
2952                 struct v4l2_frequency freq;
2953                 fv = pvr2_hdw_get_cur_freq(hdw);
2954                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2955                 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2956                 memset(&freq, 0, sizeof(freq));
2957                 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2958                         /* ((fv * 1000) / 62500) */
2959                         freq.frequency = (fv * 2) / 125;
2960                 } else {
2961                         freq.frequency = fv / 62500;
2962                 }
2963                 /* tuner-core currently doesn't seem to care about this, but
2964                    let's set it anyway for completeness. */
2965                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2966                         freq.type = V4L2_TUNER_RADIO;
2967                 } else {
2968                         freq.type = V4L2_TUNER_ANALOG_TV;
2969                 }
2970                 freq.tuner = 0;
2971                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2972                                      s_frequency, &freq);
2973         }
2974
2975         if (hdw->res_hor_dirty || hdw->res_ver_dirty) {
2976                 struct v4l2_format fmt;
2977                 memset(&fmt, 0, sizeof(fmt));
2978                 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2979                 fmt.fmt.pix.width = hdw->res_hor_val;
2980                 fmt.fmt.pix.height = hdw->res_ver_val;
2981                 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_size(%dx%d)",
2982                            fmt.fmt.pix.width, fmt.fmt.pix.height);
2983                 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
2984         }
2985
2986         if (hdw->srate_dirty) {
2987                 u32 val;
2988                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
2989                            hdw->srate_val);
2990                 switch (hdw->srate_val) {
2991                 default:
2992                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
2993                         val = 48000;
2994                         break;
2995                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
2996                         val = 44100;
2997                         break;
2998                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
2999                         val = 32000;
3000                         break;
3001                 }
3002                 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3003                                      audio, s_clock_freq, val);
3004         }
3005
3006         /* Unable to set crop parameters; there is apparently no equivalent
3007            for VIDIOC_S_CROP */
3008
3009         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3010                 id = sd->grp_id;
3011                 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3012                 fp = pvr2_module_update_functions[id];
3013                 if (!fp) continue;
3014                 (*fp)(hdw, sd);
3015         }
3016
3017         if (hdw->tuner_signal_stale && hdw->cropcap_stale) {
3018                 pvr2_hdw_status_poll(hdw);
3019         }
3020 }
3021
3022
3023 /* Figure out if we need to commit control changes.  If so, mark internal
3024    state flags to indicate this fact and return true.  Otherwise do nothing
3025    else and return false. */
3026 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
3027 {
3028         unsigned int idx;
3029         struct pvr2_ctrl *cptr;
3030         int value;
3031         int commit_flag = 0;
3032         char buf[100];
3033         unsigned int bcnt,ccnt;
3034
3035         for (idx = 0; idx < hdw->control_cnt; idx++) {
3036                 cptr = hdw->controls + idx;
3037                 if (!cptr->info->is_dirty) continue;
3038                 if (!cptr->info->is_dirty(cptr)) continue;
3039                 commit_flag = !0;
3040
3041                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
3042                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3043                                  cptr->info->name);
3044                 value = 0;
3045                 cptr->info->get_value(cptr,&value);
3046                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3047                                                 buf+bcnt,
3048                                                 sizeof(buf)-bcnt,&ccnt);
3049                 bcnt += ccnt;
3050                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3051                                   get_ctrl_typename(cptr->info->type));
3052                 pvr2_trace(PVR2_TRACE_CTL,
3053                            "/*--TRACE_COMMIT--*/ %.*s",
3054                            bcnt,buf);
3055         }
3056
3057         if (!commit_flag) {
3058                 /* Nothing has changed */
3059                 return 0;
3060         }
3061
3062         hdw->state_pipeline_config = 0;
3063         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3064         pvr2_hdw_state_sched(hdw);
3065
3066         return !0;
3067 }
3068
3069
3070 /* Perform all operations needed to commit all control changes.  This must
3071    be performed in synchronization with the pipeline state and is thus
3072    expected to be called as part of the driver's worker thread.  Return
3073    true if commit successful, otherwise return false to indicate that
3074    commit isn't possible at this time. */
3075 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3076 {
3077         unsigned int idx;
3078         struct pvr2_ctrl *cptr;
3079         int disruptive_change;
3080
3081         /* Handle some required side effects when the video standard is
3082            changed.... */
3083         if (hdw->std_dirty) {
3084                 int nvres;
3085                 int gop_size;
3086                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3087                         nvres = 480;
3088                         gop_size = 15;
3089                 } else {
3090                         nvres = 576;
3091                         gop_size = 12;
3092                 }
3093                 /* Rewrite the vertical resolution to be appropriate to the
3094                    video standard that has been selected. */
3095                 if (nvres != hdw->res_ver_val) {
3096                         hdw->res_ver_val = nvres;
3097                         hdw->res_ver_dirty = !0;
3098                 }
3099                 /* Rewrite the GOP size to be appropriate to the video
3100                    standard that has been selected. */
3101                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3102                         struct v4l2_ext_controls cs;
3103                         struct v4l2_ext_control c1;
3104                         memset(&cs, 0, sizeof(cs));
3105                         memset(&c1, 0, sizeof(c1));
3106                         cs.controls = &c1;
3107                         cs.count = 1;
3108                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3109                         c1.value = gop_size;
3110                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3111                                           VIDIOC_S_EXT_CTRLS);
3112                 }
3113         }
3114
3115         if (hdw->input_dirty && hdw->state_pathway_ok &&
3116             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3117               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3118              hdw->pathway_state)) {
3119                 /* Change of mode being asked for... */
3120                 hdw->state_pathway_ok = 0;
3121                 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3122         }
3123         if (!hdw->state_pathway_ok) {
3124                 /* Can't commit anything until pathway is ok. */
3125                 return 0;
3126         }
3127         /* The broadcast decoder can only scale down, so if
3128          * res_*_dirty && crop window < output format ==> enlarge crop.
3129          *
3130          * The mpeg encoder receives fields of res_hor_val dots and
3131          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3132          */
3133         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3134                 hdw->cropw_val = hdw->res_hor_val;
3135                 hdw->cropw_dirty = !0;
3136         } else if (hdw->cropw_dirty) {
3137                 hdw->res_hor_dirty = !0;           /* must rescale */
3138                 hdw->res_hor_val = min(720, hdw->cropw_val);
3139         }
3140         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3141                 hdw->croph_val = hdw->res_ver_val;
3142                 hdw->croph_dirty = !0;
3143         } else if (hdw->croph_dirty) {
3144                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3145                 hdw->res_ver_dirty = !0;
3146                 hdw->res_ver_val = min(nvres, hdw->croph_val);
3147         }
3148
3149         /* If any of the below has changed, then we can't do the update
3150            while the pipeline is running.  Pipeline must be paused first
3151            and decoder -> encoder connection be made quiescent before we
3152            can proceed. */
3153         disruptive_change =
3154                 (hdw->std_dirty ||
3155                  hdw->enc_unsafe_stale ||
3156                  hdw->srate_dirty ||
3157                  hdw->res_ver_dirty ||
3158                  hdw->res_hor_dirty ||
3159                  hdw->cropw_dirty ||
3160                  hdw->croph_dirty ||
3161                  hdw->input_dirty ||
3162                  (hdw->active_stream_type != hdw->desired_stream_type));
3163         if (disruptive_change && !hdw->state_pipeline_idle) {
3164                 /* Pipeline is not idle; we can't proceed.  Arrange to
3165                    cause pipeline to stop so that we can try this again
3166                    later.... */
3167                 hdw->state_pipeline_pause = !0;
3168                 return 0;
3169         }
3170
3171         if (hdw->srate_dirty) {
3172                 /* Write new sample rate into control structure since
3173                  * the master copy is stale.  We must track srate
3174                  * separate from the mpeg control structure because
3175                  * other logic also uses this value. */
3176                 struct v4l2_ext_controls cs;
3177                 struct v4l2_ext_control c1;
3178                 memset(&cs,0,sizeof(cs));
3179                 memset(&c1,0,sizeof(c1));
3180                 cs.controls = &c1;
3181                 cs.count = 1;
3182                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3183                 c1.value = hdw->srate_val;
3184                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3185         }
3186
3187         /* Scan i2c core at this point - before we clear all the dirty
3188            bits.  Various parts of the i2c core will notice dirty bits as
3189            appropriate and arrange to broadcast or directly send updates to
3190            the client drivers in order to keep everything in sync */
3191         pvr2_i2c_core_check_stale(hdw);
3192
3193         if (hdw->active_stream_type != hdw->desired_stream_type) {
3194                 /* Handle any side effects of stream config here */
3195                 hdw->active_stream_type = hdw->desired_stream_type;
3196         }
3197
3198         if (hdw->hdw_desc->signal_routing_scheme ==
3199             PVR2_ROUTING_SCHEME_GOTVIEW) {
3200                 u32 b;
3201                 /* Handle GOTVIEW audio switching */
3202                 pvr2_hdw_gpio_get_out(hdw,&b);
3203                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3204                         /* Set GPIO 11 */
3205                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3206                 } else {
3207                         /* Clear GPIO 11 */
3208                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3209                 }
3210         }
3211
3212         for (idx = 0; idx < hdw->control_cnt; idx++) {
3213                 cptr = hdw->controls + idx;
3214                 if (!cptr->info->clear_dirty) continue;
3215                 cptr->info->clear_dirty(cptr);
3216         }
3217
3218         /* Check and update state for all sub-devices. */
3219         pvr2_subdev_update(hdw);
3220
3221         /* Now execute i2c core update */
3222         pvr2_i2c_core_sync(hdw);
3223
3224         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3225             hdw->state_encoder_run) {
3226                 /* If encoder isn't running or it can't be touched, then
3227                    this will get worked out later when we start the
3228                    encoder. */
3229                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3230         }
3231
3232         hdw->state_pipeline_config = !0;
3233         /* Hardware state may have changed in a way to cause the cropping
3234            capabilities to have changed.  So mark it stale, which will
3235            cause a later re-fetch. */
3236         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3237         return !0;
3238 }
3239
3240
3241 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3242 {
3243         int fl;
3244         LOCK_TAKE(hdw->big_lock);
3245         fl = pvr2_hdw_commit_setup(hdw);
3246         LOCK_GIVE(hdw->big_lock);
3247         if (!fl) return 0;
3248         return pvr2_hdw_wait(hdw,0);
3249 }
3250
3251
3252 static void pvr2_hdw_worker_i2c(struct work_struct *work)
3253 {
3254         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
3255         LOCK_TAKE(hdw->big_lock); do {
3256                 pvr2_i2c_core_sync(hdw);
3257         } while (0); LOCK_GIVE(hdw->big_lock);
3258 }
3259
3260
3261 static void pvr2_hdw_worker_poll(struct work_struct *work)
3262 {
3263         int fl = 0;
3264         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3265         LOCK_TAKE(hdw->big_lock); do {
3266                 fl = pvr2_hdw_state_eval(hdw);
3267         } while (0); LOCK_GIVE(hdw->big_lock);
3268         if (fl && hdw->state_func) {
3269                 hdw->state_func(hdw->state_data);
3270         }
3271 }
3272
3273
3274 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3275 {
3276         return wait_event_interruptible(
3277                 hdw->state_wait_data,
3278                 (hdw->state_stale == 0) &&
3279                 (!state || (hdw->master_state != state)));
3280 }
3281
3282
3283 /* Return name for this driver instance */
3284 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3285 {
3286         return hdw->name;
3287 }
3288
3289
3290 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3291 {
3292         return hdw->hdw_desc->description;
3293 }
3294
3295
3296 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3297 {
3298         return hdw->hdw_desc->shortname;
3299 }
3300
3301
3302 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3303 {
3304         int result;
3305         LOCK_TAKE(hdw->ctl_lock); do {
3306                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3307                 result = pvr2_send_request(hdw,
3308                                            hdw->cmd_buffer,1,
3309                                            hdw->cmd_buffer,1);
3310                 if (result < 0) break;
3311                 result = (hdw->cmd_buffer[0] != 0);
3312         } while(0); LOCK_GIVE(hdw->ctl_lock);
3313         return result;
3314 }
3315
3316
3317 /* Execute poll of tuner status */
3318 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3319 {
3320         LOCK_TAKE(hdw->big_lock); do {
3321                 pvr2_hdw_status_poll(hdw);
3322         } while (0); LOCK_GIVE(hdw->big_lock);
3323 }
3324
3325
3326 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3327 {
3328         if (!hdw->cropcap_stale) {
3329                 return 0;
3330         }
3331         pvr2_hdw_status_poll(hdw);
3332         if (hdw->cropcap_stale) {
3333                 return -EIO;
3334         }
3335         return 0;
3336 }
3337
3338
3339 /* Return information about cropping capabilities */
3340 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3341 {
3342         int stat = 0;
3343         LOCK_TAKE(hdw->big_lock);
3344         stat = pvr2_hdw_check_cropcap(hdw);
3345         if (!stat) {
3346                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3347         }
3348         LOCK_GIVE(hdw->big_lock);
3349         return stat;
3350 }
3351
3352
3353 /* Return information about the tuner */
3354 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3355 {
3356         LOCK_TAKE(hdw->big_lock); do {
3357                 if (hdw->tuner_signal_stale) {
3358                         pvr2_hdw_status_poll(hdw);
3359                 }
3360                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3361         } while (0); LOCK_GIVE(hdw->big_lock);
3362         return 0;
3363 }
3364
3365
3366 /* Get handle to video output stream */
3367 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3368 {
3369         return hp->vid_stream;
3370 }
3371
3372
3373 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3374 {
3375         int nr = pvr2_hdw_get_unit_number(hdw);
3376         LOCK_TAKE(hdw->big_lock); do {
3377                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3378                 hdw->log_requested = !0;
3379                 pvr2_i2c_core_check_stale(hdw);
3380                 pvr2_i2c_core_sync(hdw);
3381                 hdw->log_requested = 0;
3382                 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3383                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3384                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3385                 pvr2_hdw_state_log_state(hdw);
3386                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3387         } while (0); LOCK_GIVE(hdw->big_lock);
3388 }
3389
3390
3391 /* Grab EEPROM contents, needed for direct method. */
3392 #define EEPROM_SIZE 8192
3393 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3394 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3395 {
3396         struct i2c_msg msg[2];
3397         u8 *eeprom;
3398         u8 iadd[2];
3399         u8 addr;
3400         u16 eepromSize;
3401         unsigned int offs;
3402         int ret;
3403         int mode16 = 0;
3404         unsigned pcnt,tcnt;
3405         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3406         if (!eeprom) {
3407                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3408                            "Failed to allocate memory"
3409                            " required to read eeprom");
3410                 return NULL;
3411         }
3412
3413         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3414                      hdw->eeprom_addr);
3415         addr = hdw->eeprom_addr;
3416         /* Seems that if the high bit is set, then the *real* eeprom
3417            address is shifted right now bit position (noticed this in
3418            newer PVR USB2 hardware) */
3419         if (addr & 0x80) addr >>= 1;
3420
3421         /* FX2 documentation states that a 16bit-addressed eeprom is
3422            expected if the I2C address is an odd number (yeah, this is
3423            strange but it's what they do) */
3424         mode16 = (addr & 1);
3425         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3426         trace_eeprom("Examining %d byte eeprom at location 0x%x"
3427                      " using %d bit addressing",eepromSize,addr,
3428                      mode16 ? 16 : 8);
3429
3430         msg[0].addr = addr;
3431         msg[0].flags = 0;
3432         msg[0].len = mode16 ? 2 : 1;
3433         msg[0].buf = iadd;
3434         msg[1].addr = addr;
3435         msg[1].flags = I2C_M_RD;
3436
3437         /* We have to do the actual eeprom data fetch ourselves, because
3438            (1) we're only fetching part of the eeprom, and (2) if we were
3439            getting the whole thing our I2C driver can't grab it in one
3440            pass - which is what tveeprom is otherwise going to attempt */
3441         memset(eeprom,0,EEPROM_SIZE);
3442         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3443                 pcnt = 16;
3444                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3445                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3446                 if (mode16) {
3447                         iadd[0] = offs >> 8;
3448                         iadd[1] = offs;
3449                 } else {
3450                         iadd[0] = offs;
3451                 }
3452                 msg[1].len = pcnt;
3453                 msg[1].buf = eeprom+tcnt;
3454                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3455                                         msg,ARRAY_SIZE(msg))) != 2) {
3456                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3457                                    "eeprom fetch set offs err=%d",ret);
3458                         kfree(eeprom);
3459                         return NULL;
3460                 }
3461         }
3462         return eeprom;
3463 }
3464
3465
3466 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3467                                 int prom_flag,
3468                                 int enable_flag)
3469 {
3470         int ret;
3471         u16 address;
3472         unsigned int pipe;
3473         LOCK_TAKE(hdw->big_lock); do {
3474                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3475
3476                 if (!enable_flag) {
3477                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3478                                    "Cleaning up after CPU firmware fetch");
3479                         kfree(hdw->fw_buffer);
3480                         hdw->fw_buffer = NULL;
3481                         hdw->fw_size = 0;
3482                         if (hdw->fw_cpu_flag) {
3483                                 /* Now release the CPU.  It will disconnect
3484                                    and reconnect later. */
3485                                 pvr2_hdw_cpureset_assert(hdw,0);
3486                         }
3487                         break;
3488                 }
3489
3490                 hdw->fw_cpu_flag = (prom_flag == 0);
3491                 if (hdw->fw_cpu_flag) {
3492                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3493                                    "Preparing to suck out CPU firmware");
3494                         hdw->fw_size = 0x2000;
3495                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3496                         if (!hdw->fw_buffer) {
3497                                 hdw->fw_size = 0;
3498                                 break;
3499                         }
3500
3501                         /* We have to hold the CPU during firmware upload. */
3502                         pvr2_hdw_cpureset_assert(hdw,1);
3503
3504                         /* download the firmware from address 0000-1fff in 2048
3505                            (=0x800) bytes chunk. */
3506
3507                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3508                                    "Grabbing CPU firmware");
3509                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3510                         for(address = 0; address < hdw->fw_size;
3511                             address += 0x800) {
3512                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3513                                                       0xa0,0xc0,
3514                                                       address,0,
3515                                                       hdw->fw_buffer+address,
3516                                                       0x800,HZ);
3517                                 if (ret < 0) break;
3518                         }
3519
3520                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3521                                    "Done grabbing CPU firmware");
3522                 } else {
3523                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3524                                    "Sucking down EEPROM contents");
3525                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3526                         if (!hdw->fw_buffer) {
3527                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3528                                            "EEPROM content suck failed.");
3529                                 break;
3530                         }
3531                         hdw->fw_size = EEPROM_SIZE;
3532                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3533                                    "Done sucking down EEPROM contents");
3534                 }
3535
3536         } while (0); LOCK_GIVE(hdw->big_lock);
3537 }
3538
3539
3540 /* Return true if we're in a mode for retrieval CPU firmware */
3541 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3542 {
3543         return hdw->fw_buffer != NULL;
3544 }
3545
3546
3547 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3548                        char *buf,unsigned int cnt)
3549 {
3550         int ret = -EINVAL;
3551         LOCK_TAKE(hdw->big_lock); do {
3552                 if (!buf) break;
3553                 if (!cnt) break;
3554
3555                 if (!hdw->fw_buffer) {
3556                         ret = -EIO;
3557                         break;
3558                 }
3559
3560                 if (offs >= hdw->fw_size) {
3561                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3562                                    "Read firmware data offs=%d EOF",
3563                                    offs);
3564                         ret = 0;
3565                         break;
3566                 }
3567
3568                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3569
3570                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3571
3572                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3573                            "Read firmware data offs=%d cnt=%d",
3574                            offs,cnt);
3575                 ret = cnt;
3576         } while (0); LOCK_GIVE(hdw->big_lock);
3577
3578         return ret;
3579 }
3580
3581
3582 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3583                                   enum pvr2_v4l_type index)
3584 {
3585         switch (index) {
3586         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3587         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3588         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3589         default: return -1;
3590         }
3591 }
3592
3593
3594 /* Store a v4l minor device number */
3595 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3596                                      enum pvr2_v4l_type index,int v)
3597 {
3598         switch (index) {
3599         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3600         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3601         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
3602         default: break;
3603         }
3604 }
3605
3606
3607 static void pvr2_ctl_write_complete(struct urb *urb)
3608 {
3609         struct pvr2_hdw *hdw = urb->context;
3610         hdw->ctl_write_pend_flag = 0;
3611         if (hdw->ctl_read_pend_flag) return;
3612         complete(&hdw->ctl_done);
3613 }
3614
3615
3616 static void pvr2_ctl_read_complete(struct urb *urb)
3617 {
3618         struct pvr2_hdw *hdw = urb->context;
3619         hdw->ctl_read_pend_flag = 0;
3620         if (hdw->ctl_write_pend_flag) return;
3621         complete(&hdw->ctl_done);
3622 }
3623
3624
3625 static void pvr2_ctl_timeout(unsigned long data)
3626 {
3627         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3628         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3629                 hdw->ctl_timeout_flag = !0;
3630                 if (hdw->ctl_write_pend_flag)
3631                         usb_unlink_urb(hdw->ctl_write_urb);
3632                 if (hdw->ctl_read_pend_flag)
3633                         usb_unlink_urb(hdw->ctl_read_urb);
3634         }
3635 }
3636
3637
3638 /* Issue a command and get a response from the device.  This extended
3639    version includes a probe flag (which if set means that device errors
3640    should not be logged or treated as fatal) and a timeout in jiffies.
3641    This can be used to non-lethally probe the health of endpoint 1. */
3642 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3643                                 unsigned int timeout,int probe_fl,
3644                                 void *write_data,unsigned int write_len,
3645                                 void *read_data,unsigned int read_len)
3646 {
3647         unsigned int idx;
3648         int status = 0;
3649         struct timer_list timer;
3650         if (!hdw->ctl_lock_held) {
3651                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3652                            "Attempted to execute control transfer"
3653                            " without lock!!");
3654                 return -EDEADLK;
3655         }
3656         if (!hdw->flag_ok && !probe_fl) {
3657                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3658                            "Attempted to execute control transfer"
3659                            " when device not ok");
3660                 return -EIO;
3661         }
3662         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3663                 if (!probe_fl) {
3664                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3665                                    "Attempted to execute control transfer"
3666                                    " when USB is disconnected");
3667                 }
3668                 return -ENOTTY;
3669         }
3670
3671         /* Ensure that we have sane parameters */
3672         if (!write_data) write_len = 0;
3673         if (!read_data) read_len = 0;
3674         if (write_len > PVR2_CTL_BUFFSIZE) {
3675                 pvr2_trace(
3676                         PVR2_TRACE_ERROR_LEGS,
3677                         "Attempted to execute %d byte"
3678                         " control-write transfer (limit=%d)",
3679                         write_len,PVR2_CTL_BUFFSIZE);
3680                 return -EINVAL;
3681         }
3682         if (read_len > PVR2_CTL_BUFFSIZE) {
3683                 pvr2_trace(
3684                         PVR2_TRACE_ERROR_LEGS,
3685                         "Attempted to execute %d byte"
3686                         " control-read transfer (limit=%d)",
3687                         write_len,PVR2_CTL_BUFFSIZE);
3688                 return -EINVAL;
3689         }
3690         if ((!write_len) && (!read_len)) {
3691                 pvr2_trace(
3692                         PVR2_TRACE_ERROR_LEGS,
3693                         "Attempted to execute null control transfer?");
3694                 return -EINVAL;
3695         }
3696
3697
3698         hdw->cmd_debug_state = 1;
3699         if (write_len) {
3700                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3701         } else {
3702                 hdw->cmd_debug_code = 0;
3703         }
3704         hdw->cmd_debug_write_len = write_len;
3705         hdw->cmd_debug_read_len = read_len;
3706
3707         /* Initialize common stuff */
3708         init_completion(&hdw->ctl_done);
3709         hdw->ctl_timeout_flag = 0;
3710         hdw->ctl_write_pend_flag = 0;
3711         hdw->ctl_read_pend_flag = 0;
3712         init_timer(&timer);
3713         timer.expires = jiffies + timeout;
3714         timer.data = (unsigned long)hdw;
3715         timer.function = pvr2_ctl_timeout;
3716
3717         if (write_len) {
3718                 hdw->cmd_debug_state = 2;
3719                 /* Transfer write data to internal buffer */
3720                 for (idx = 0; idx < write_len; idx++) {
3721                         hdw->ctl_write_buffer[idx] =
3722                                 ((unsigned char *)write_data)[idx];
3723                 }
3724                 /* Initiate a write request */
3725                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3726                                   hdw->usb_dev,
3727                                   usb_sndbulkpipe(hdw->usb_dev,
3728                                                   PVR2_CTL_WRITE_ENDPOINT),
3729                                   hdw->ctl_write_buffer,
3730                                   write_len,
3731                                   pvr2_ctl_write_complete,
3732                                   hdw);
3733                 hdw->ctl_write_urb->actual_length = 0;
3734                 hdw->ctl_write_pend_flag = !0;
3735                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3736                 if (status < 0) {
3737                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3738                                    "Failed to submit write-control"
3739                                    " URB status=%d",status);
3740                         hdw->ctl_write_pend_flag = 0;
3741                         goto done;
3742                 }
3743         }
3744
3745         if (read_len) {
3746                 hdw->cmd_debug_state = 3;
3747                 memset(hdw->ctl_read_buffer,0x43,read_len);
3748                 /* Initiate a read request */
3749                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3750                                   hdw->usb_dev,
3751                                   usb_rcvbulkpipe(hdw->usb_dev,
3752                                                   PVR2_CTL_READ_ENDPOINT),
3753                                   hdw->ctl_read_buffer,
3754                                   read_len,
3755                                   pvr2_ctl_read_complete,
3756                                   hdw);
3757                 hdw->ctl_read_urb->actual_length = 0;
3758                 hdw->ctl_read_pend_flag = !0;
3759                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3760                 if (status < 0) {
3761                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3762                                    "Failed to submit read-control"
3763                                    " URB status=%d",status);
3764                         hdw->ctl_read_pend_flag = 0;
3765                         goto done;
3766                 }
3767         }
3768
3769         /* Start timer */
3770         add_timer(&timer);
3771
3772         /* Now wait for all I/O to complete */
3773         hdw->cmd_debug_state = 4;
3774         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3775                 wait_for_completion(&hdw->ctl_done);
3776         }
3777         hdw->cmd_debug_state = 5;
3778
3779         /* Stop timer */
3780         del_timer_sync(&timer);
3781
3782         hdw->cmd_debug_state = 6;
3783         status = 0;
3784
3785         if (hdw->ctl_timeout_flag) {
3786                 status = -ETIMEDOUT;
3787                 if (!probe_fl) {
3788                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3789                                    "Timed out control-write");
3790                 }
3791                 goto done;
3792         }
3793
3794         if (write_len) {
3795                 /* Validate results of write request */
3796                 if ((hdw->ctl_write_urb->status != 0) &&
3797                     (hdw->ctl_write_urb->status != -ENOENT) &&
3798                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3799                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3800                         /* USB subsystem is reporting some kind of failure
3801                            on the write */
3802                         status = hdw->ctl_write_urb->status;
3803                         if (!probe_fl) {
3804                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3805                                            "control-write URB failure,"
3806                                            " status=%d",
3807                                            status);
3808                         }
3809                         goto done;
3810                 }
3811                 if (hdw->ctl_write_urb->actual_length < write_len) {
3812                         /* Failed to write enough data */
3813                         status = -EIO;
3814                         if (!probe_fl) {
3815                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3816                                            "control-write URB short,"
3817                                            " expected=%d got=%d",
3818                                            write_len,
3819                                            hdw->ctl_write_urb->actual_length);
3820                         }
3821                         goto done;
3822                 }
3823         }
3824         if (read_len) {
3825                 /* Validate results of read request */
3826                 if ((hdw->ctl_read_urb->status != 0) &&
3827                     (hdw->ctl_read_urb->status != -ENOENT) &&
3828                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3829                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3830                         /* USB subsystem is reporting some kind of failure
3831                            on the read */
3832                         status = hdw->ctl_read_urb->status;
3833                         if (!probe_fl) {
3834                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3835                                            "control-read URB failure,"
3836                                            " status=%d",
3837                                            status);
3838                         }
3839                         goto done;
3840                 }
3841                 if (hdw->ctl_read_urb->actual_length < read_len) {
3842                         /* Failed to read enough data */
3843                         status = -EIO;
3844                         if (!probe_fl) {
3845                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3846                                            "control-read URB short,"
3847                                            " expected=%d got=%d",
3848                                            read_len,
3849                                            hdw->ctl_read_urb->actual_length);
3850                         }
3851                         goto done;
3852                 }
3853                 /* Transfer retrieved data out from internal buffer */
3854                 for (idx = 0; idx < read_len; idx++) {
3855                         ((unsigned char *)read_data)[idx] =
3856                                 hdw->ctl_read_buffer[idx];
3857                 }
3858         }
3859
3860  done:
3861
3862         hdw->cmd_debug_state = 0;
3863         if ((status < 0) && (!probe_fl)) {
3864                 pvr2_hdw_render_useless(hdw);
3865         }
3866         return status;
3867 }
3868
3869
3870 int pvr2_send_request(struct pvr2_hdw *hdw,
3871                       void *write_data,unsigned int write_len,
3872                       void *read_data,unsigned int read_len)
3873 {
3874         return pvr2_send_request_ex(hdw,HZ*4,0,
3875                                     write_data,write_len,
3876                                     read_data,read_len);
3877 }
3878
3879
3880 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3881 {
3882         int ret;
3883         unsigned int cnt = 1;
3884         unsigned int args = 0;
3885         LOCK_TAKE(hdw->ctl_lock);
3886         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3887         args = (cmdcode >> 8) & 0xffu;
3888         args = (args > 2) ? 2 : args;
3889         if (args) {
3890                 cnt += args;
3891                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3892                 if (args > 1) {
3893                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3894                 }
3895         }
3896         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3897                 unsigned int idx;
3898                 unsigned int ccnt,bcnt;
3899                 char tbuf[50];
3900                 cmdcode &= 0xffu;
3901                 bcnt = 0;
3902                 ccnt = scnprintf(tbuf+bcnt,
3903                                  sizeof(tbuf)-bcnt,
3904                                  "Sending FX2 command 0x%x",cmdcode);
3905                 bcnt += ccnt;
3906                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3907                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3908                                 ccnt = scnprintf(tbuf+bcnt,
3909                                                  sizeof(tbuf)-bcnt,
3910                                                  " \"%s\"",
3911                                                  pvr2_fx2cmd_desc[idx].desc);
3912                                 bcnt += ccnt;
3913                                 break;
3914                         }
3915                 }
3916                 if (args) {
3917                         ccnt = scnprintf(tbuf+bcnt,
3918                                          sizeof(tbuf)-bcnt,
3919                                          " (%u",hdw->cmd_buffer[1]);
3920                         bcnt += ccnt;
3921                         if (args > 1) {
3922                                 ccnt = scnprintf(tbuf+bcnt,
3923                                                  sizeof(tbuf)-bcnt,
3924                                                  ",%u",hdw->cmd_buffer[2]);
3925                                 bcnt += ccnt;
3926                         }
3927                         ccnt = scnprintf(tbuf+bcnt,
3928                                          sizeof(tbuf)-bcnt,
3929                                          ")");
3930                         bcnt += ccnt;
3931                 }
3932                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3933         }
3934         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3935         LOCK_GIVE(hdw->ctl_lock);
3936         return ret;
3937 }
3938
3939
3940 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3941 {
3942         int ret;
3943
3944         LOCK_TAKE(hdw->ctl_lock);
3945
3946         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3947         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3948         hdw->cmd_buffer[5] = 0;
3949         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3950         hdw->cmd_buffer[7] = reg & 0xff;
3951
3952
3953         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3954
3955         LOCK_GIVE(hdw->ctl_lock);
3956
3957         return ret;
3958 }
3959
3960
3961 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3962 {
3963         int ret = 0;
3964
3965         LOCK_TAKE(hdw->ctl_lock);
3966
3967         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3968         hdw->cmd_buffer[1] = 0;
3969         hdw->cmd_buffer[2] = 0;
3970         hdw->cmd_buffer[3] = 0;
3971         hdw->cmd_buffer[4] = 0;
3972         hdw->cmd_buffer[5] = 0;
3973         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3974         hdw->cmd_buffer[7] = reg & 0xff;
3975
3976         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3977         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3978
3979         LOCK_GIVE(hdw->ctl_lock);
3980
3981         return ret;
3982 }
3983
3984
3985 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3986 {
3987         if (!hdw->flag_ok) return;
3988         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3989                    "Device being rendered inoperable");
3990         if (hdw->vid_stream) {
3991                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3992         }
3993         hdw->flag_ok = 0;
3994         trace_stbit("flag_ok",hdw->flag_ok);
3995         pvr2_hdw_state_sched(hdw);
3996 }
3997
3998
3999 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4000 {
4001         int ret;
4002         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
4003         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
4004         if (ret == 0) {
4005                 ret = usb_reset_device(hdw->usb_dev);
4006                 usb_unlock_device(hdw->usb_dev);
4007         } else {
4008                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4009                            "Failed to lock USB device ret=%d",ret);
4010         }
4011         if (init_pause_msec) {
4012                 pvr2_trace(PVR2_TRACE_INFO,
4013                            "Waiting %u msec for hardware to settle",
4014                            init_pause_msec);
4015                 msleep(init_pause_msec);
4016         }
4017
4018 }
4019
4020
4021 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4022 {
4023         char da[1];
4024         unsigned int pipe;
4025         int ret;
4026
4027         if (!hdw->usb_dev) return;
4028
4029         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4030
4031         da[0] = val ? 0x01 : 0x00;
4032
4033         /* Write the CPUCS register on the 8051.  The lsb of the register
4034            is the reset bit; a 1 asserts reset while a 0 clears it. */
4035         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4036         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4037         if (ret < 0) {
4038                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4039                            "cpureset_assert(%d) error=%d",val,ret);
4040                 pvr2_hdw_render_useless(hdw);
4041         }
4042 }
4043
4044
4045 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4046 {
4047         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
4048 }
4049
4050
4051 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4052 {
4053         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4054 }
4055
4056
4057 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4058 {
4059         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
4060 }
4061
4062
4063 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4064 {
4065         pvr2_trace(PVR2_TRACE_INIT,
4066                    "Requesting decoder reset");
4067         if (hdw->decoder_ctrl) {
4068                 if (!hdw->decoder_ctrl->force_reset) {
4069                         pvr2_trace(PVR2_TRACE_INIT,
4070                                    "Unable to reset decoder: not implemented");
4071                         return -ENOTTY;
4072                 }
4073                 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
4074                 return 0;
4075         } else {
4076         }
4077         if (hdw->decoder_client_id) {
4078                 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4079                                      core, reset, 0);
4080                 return 0;
4081         }
4082         pvr2_trace(PVR2_TRACE_INIT,
4083                    "Unable to reset decoder: nothing attached");
4084         return -ENOTTY;
4085 }
4086
4087
4088 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4089 {
4090         hdw->flag_ok = !0;
4091         return pvr2_issue_simple_cmd(hdw,
4092                                      FX2CMD_HCW_DEMOD_RESETIN |
4093                                      (1 << 8) |
4094                                      ((onoff ? 1 : 0) << 16));
4095 }
4096
4097
4098 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4099 {
4100         hdw->flag_ok = !0;
4101         return pvr2_issue_simple_cmd(hdw,(onoff ?
4102                                           FX2CMD_ONAIR_DTV_POWER_ON :
4103                                           FX2CMD_ONAIR_DTV_POWER_OFF));
4104 }
4105
4106
4107 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4108                                                 int onoff)
4109 {
4110         return pvr2_issue_simple_cmd(hdw,(onoff ?
4111                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
4112                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
4113 }
4114
4115
4116 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4117 {
4118         int cmode;
4119         /* Compare digital/analog desired setting with current setting.  If
4120            they don't match, fix it... */
4121         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4122         if (cmode == hdw->pathway_state) {
4123                 /* They match; nothing to do */
4124                 return;
4125         }
4126
4127         switch (hdw->hdw_desc->digital_control_scheme) {
4128         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4129                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4130                 if (cmode == PVR2_PATHWAY_ANALOG) {
4131                         /* If moving to analog mode, also force the decoder
4132                            to reset.  If no decoder is attached, then it's
4133                            ok to ignore this because if/when the decoder
4134                            attaches, it will reset itself at that time. */
4135                         pvr2_hdw_cmd_decoder_reset(hdw);
4136                 }
4137                 break;
4138         case PVR2_DIGITAL_SCHEME_ONAIR:
4139                 /* Supposedly we should always have the power on whether in
4140                    digital or analog mode.  But for now do what appears to
4141                    work... */
4142                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4143                 break;
4144         default: break;
4145         }
4146
4147         pvr2_hdw_untrip_unlocked(hdw);
4148         hdw->pathway_state = cmode;
4149 }
4150
4151
4152 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4153 {
4154         /* change some GPIO data
4155          *
4156          * note: bit d7 of dir appears to control the LED,
4157          * so we shut it off here.
4158          *
4159          */
4160         if (onoff) {
4161                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4162         } else {
4163                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4164         }
4165         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4166 }
4167
4168
4169 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4170
4171 static led_method_func led_methods[] = {
4172         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4173 };
4174
4175
4176 /* Toggle LED */
4177 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4178 {
4179         unsigned int scheme_id;
4180         led_method_func fp;
4181
4182         if ((!onoff) == (!hdw->led_on)) return;
4183
4184         hdw->led_on = onoff != 0;
4185
4186         scheme_id = hdw->hdw_desc->led_scheme;
4187         if (scheme_id < ARRAY_SIZE(led_methods)) {
4188                 fp = led_methods[scheme_id];
4189         } else {
4190                 fp = NULL;
4191         }
4192
4193         if (fp) (*fp)(hdw,onoff);
4194 }
4195
4196
4197 /* Stop / start video stream transport */
4198 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4199 {
4200         int ret;
4201
4202         /* If we're in analog mode, then just issue the usual analog
4203            command. */
4204         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4205                 return pvr2_issue_simple_cmd(hdw,
4206                                              (runFl ?
4207                                               FX2CMD_STREAMING_ON :
4208                                               FX2CMD_STREAMING_OFF));
4209                 /*Note: Not reached */
4210         }
4211
4212         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4213                 /* Whoops, we don't know what mode we're in... */
4214                 return -EINVAL;
4215         }
4216
4217         /* To get here we have to be in digital mode.  The mechanism here
4218            is unfortunately different for different vendors.  So we switch
4219            on the device's digital scheme attribute in order to figure out
4220            what to do. */
4221         switch (hdw->hdw_desc->digital_control_scheme) {
4222         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4223                 return pvr2_issue_simple_cmd(hdw,
4224                                              (runFl ?
4225                                               FX2CMD_HCW_DTV_STREAMING_ON :
4226                                               FX2CMD_HCW_DTV_STREAMING_OFF));
4227         case PVR2_DIGITAL_SCHEME_ONAIR:
4228                 ret = pvr2_issue_simple_cmd(hdw,
4229                                             (runFl ?
4230                                              FX2CMD_STREAMING_ON :
4231                                              FX2CMD_STREAMING_OFF));
4232                 if (ret) return ret;
4233                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4234         default:
4235                 return -EINVAL;
4236         }
4237 }
4238
4239
4240 /* Evaluate whether or not state_pathway_ok can change */
4241 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4242 {
4243         if (hdw->state_pathway_ok) {
4244                 /* Nothing to do if pathway is already ok */
4245                 return 0;
4246         }
4247         if (!hdw->state_pipeline_idle) {
4248                 /* Not allowed to change anything if pipeline is not idle */
4249                 return 0;
4250         }
4251         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4252         hdw->state_pathway_ok = !0;
4253         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4254         return !0;
4255 }
4256
4257
4258 /* Evaluate whether or not state_encoder_ok can change */
4259 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4260 {
4261         if (hdw->state_encoder_ok) return 0;
4262         if (hdw->flag_tripped) return 0;
4263         if (hdw->state_encoder_run) return 0;
4264         if (hdw->state_encoder_config) return 0;
4265         if (hdw->state_decoder_run) return 0;
4266         if (hdw->state_usbstream_run) return 0;
4267         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4268                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4269         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4270                 return 0;
4271         }
4272
4273         if (pvr2_upload_firmware2(hdw) < 0) {
4274                 hdw->flag_tripped = !0;
4275                 trace_stbit("flag_tripped",hdw->flag_tripped);
4276                 return !0;
4277         }
4278         hdw->state_encoder_ok = !0;
4279         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4280         return !0;
4281 }
4282
4283
4284 /* Evaluate whether or not state_encoder_config can change */
4285 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4286 {
4287         if (hdw->state_encoder_config) {
4288                 if (hdw->state_encoder_ok) {
4289                         if (hdw->state_pipeline_req &&
4290                             !hdw->state_pipeline_pause) return 0;
4291                 }
4292                 hdw->state_encoder_config = 0;
4293                 hdw->state_encoder_waitok = 0;
4294                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4295                 /* paranoia - solve race if timer just completed */
4296                 del_timer_sync(&hdw->encoder_wait_timer);
4297         } else {
4298                 if (!hdw->state_pathway_ok ||
4299                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4300                     !hdw->state_encoder_ok ||
4301                     !hdw->state_pipeline_idle ||
4302                     hdw->state_pipeline_pause ||
4303                     !hdw->state_pipeline_req ||
4304                     !hdw->state_pipeline_config) {
4305                         /* We must reset the enforced wait interval if
4306                            anything has happened that might have disturbed
4307                            the encoder.  This should be a rare case. */
4308                         if (timer_pending(&hdw->encoder_wait_timer)) {
4309                                 del_timer_sync(&hdw->encoder_wait_timer);
4310                         }
4311                         if (hdw->state_encoder_waitok) {
4312                                 /* Must clear the state - therefore we did
4313                                    something to a state bit and must also
4314                                    return true. */
4315                                 hdw->state_encoder_waitok = 0;
4316                                 trace_stbit("state_encoder_waitok",
4317                                             hdw->state_encoder_waitok);
4318                                 return !0;
4319                         }
4320                         return 0;
4321                 }
4322                 if (!hdw->state_encoder_waitok) {
4323                         if (!timer_pending(&hdw->encoder_wait_timer)) {
4324                                 /* waitok flag wasn't set and timer isn't
4325                                    running.  Check flag once more to avoid
4326                                    a race then start the timer.  This is
4327                                    the point when we measure out a minimal
4328                                    quiet interval before doing something to
4329                                    the encoder. */
4330                                 if (!hdw->state_encoder_waitok) {
4331                                         hdw->encoder_wait_timer.expires =
4332                                                 jiffies +
4333                                                 (HZ * TIME_MSEC_ENCODER_WAIT
4334                                                  / 1000);
4335                                         add_timer(&hdw->encoder_wait_timer);
4336                                 }
4337                         }
4338                         /* We can't continue until we know we have been
4339                            quiet for the interval measured by this
4340                            timer. */
4341                         return 0;
4342                 }
4343                 pvr2_encoder_configure(hdw);
4344                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4345         }
4346         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4347         return !0;
4348 }
4349
4350
4351 /* Return true if the encoder should not be running. */
4352 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4353 {
4354         if (!hdw->state_encoder_ok) {
4355                 /* Encoder isn't healthy at the moment, so stop it. */
4356                 return !0;
4357         }
4358         if (!hdw->state_pathway_ok) {
4359                 /* Mode is not understood at the moment (i.e. it wants to
4360                    change), so encoder must be stopped. */
4361                 return !0;
4362         }
4363
4364         switch (hdw->pathway_state) {
4365         case PVR2_PATHWAY_ANALOG:
4366                 if (!hdw->state_decoder_run) {
4367                         /* We're in analog mode and the decoder is not
4368                            running; thus the encoder should be stopped as
4369                            well. */
4370                         return !0;
4371                 }
4372                 break;
4373         case PVR2_PATHWAY_DIGITAL:
4374                 if (hdw->state_encoder_runok) {
4375                         /* This is a funny case.  We're in digital mode so
4376                            really the encoder should be stopped.  However
4377                            if it really is running, only kill it after
4378                            runok has been set.  This gives a chance for the
4379                            onair quirk to function (encoder must run
4380                            briefly first, at least once, before onair
4381                            digital streaming can work). */
4382                         return !0;
4383                 }
4384                 break;
4385         default:
4386                 /* Unknown mode; so encoder should be stopped. */
4387                 return !0;
4388         }
4389
4390         /* If we get here, we haven't found a reason to stop the
4391            encoder. */
4392         return 0;
4393 }
4394
4395
4396 /* Return true if the encoder should be running. */
4397 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4398 {
4399         if (!hdw->state_encoder_ok) {
4400                 /* Don't run the encoder if it isn't healthy... */
4401                 return 0;
4402         }
4403         if (!hdw->state_pathway_ok) {
4404                 /* Don't run the encoder if we don't (yet) know what mode
4405                    we need to be in... */
4406                 return 0;
4407         }
4408
4409         switch (hdw->pathway_state) {
4410         case PVR2_PATHWAY_ANALOG:
4411                 if (hdw->state_decoder_run) {
4412                         /* In analog mode, if the decoder is running, then
4413                            run the encoder. */
4414                         return !0;
4415                 }
4416                 break;
4417         case PVR2_PATHWAY_DIGITAL:
4418                 if ((hdw->hdw_desc->digital_control_scheme ==
4419                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4420                     !hdw->state_encoder_runok) {
4421                         /* This is a quirk.  OnAir hardware won't stream
4422                            digital until the encoder has been run at least
4423                            once, for a minimal period of time (empiricially
4424                            measured to be 1/4 second).  So if we're on
4425                            OnAir hardware and the encoder has never been
4426                            run at all, then start the encoder.  Normal
4427                            state machine logic in the driver will
4428                            automatically handle the remaining bits. */
4429                         return !0;
4430                 }
4431                 break;
4432         default:
4433                 /* For completeness (unknown mode; encoder won't run ever) */
4434                 break;
4435         }
4436         /* If we get here, then we haven't found any reason to run the
4437            encoder, so don't run it. */
4438         return 0;
4439 }
4440
4441
4442 /* Evaluate whether or not state_encoder_run can change */
4443 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4444 {
4445         if (hdw->state_encoder_run) {
4446                 if (!state_check_disable_encoder_run(hdw)) return 0;
4447                 if (hdw->state_encoder_ok) {
4448                         del_timer_sync(&hdw->encoder_run_timer);
4449                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4450                 }
4451                 hdw->state_encoder_run = 0;
4452         } else {
4453                 if (!state_check_enable_encoder_run(hdw)) return 0;
4454                 if (pvr2_encoder_start(hdw) < 0) return !0;
4455                 hdw->state_encoder_run = !0;
4456                 if (!hdw->state_encoder_runok) {
4457                         hdw->encoder_run_timer.expires =
4458                                 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4459                         add_timer(&hdw->encoder_run_timer);
4460                 }
4461         }
4462         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4463         return !0;
4464 }
4465
4466
4467 /* Timeout function for quiescent timer. */
4468 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4469 {
4470         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4471         hdw->state_decoder_quiescent = !0;
4472         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4473         hdw->state_stale = !0;
4474         queue_work(hdw->workqueue,&hdw->workpoll);
4475 }
4476
4477
4478 /* Timeout function for encoder wait timer. */
4479 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4480 {
4481         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4482         hdw->state_encoder_waitok = !0;
4483         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4484         hdw->state_stale = !0;
4485         queue_work(hdw->workqueue,&hdw->workpoll);
4486 }
4487
4488
4489 /* Timeout function for encoder run timer. */
4490 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4491 {
4492         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4493         if (!hdw->state_encoder_runok) {
4494                 hdw->state_encoder_runok = !0;
4495                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4496                 hdw->state_stale = !0;
4497                 queue_work(hdw->workqueue,&hdw->workpoll);
4498         }
4499 }
4500
4501
4502 /* Evaluate whether or not state_decoder_run can change */
4503 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4504 {
4505         if (hdw->state_decoder_run) {
4506                 if (hdw->state_encoder_ok) {
4507                         if (hdw->state_pipeline_req &&
4508                             !hdw->state_pipeline_pause &&
4509                             hdw->state_pathway_ok) return 0;
4510                 }
4511                 if (!hdw->flag_decoder_missed) {
4512                         pvr2_decoder_enable(hdw,0);
4513                 }
4514                 hdw->state_decoder_quiescent = 0;
4515                 hdw->state_decoder_run = 0;
4516                 /* paranoia - solve race if timer just completed */
4517                 del_timer_sync(&hdw->quiescent_timer);
4518         } else {
4519                 if (!hdw->state_decoder_quiescent) {
4520                         if (!timer_pending(&hdw->quiescent_timer)) {
4521                                 /* We don't do something about the
4522                                    quiescent timer until right here because
4523                                    we also want to catch cases where the
4524                                    decoder was already not running (like
4525                                    after initialization) as opposed to
4526                                    knowing that we had just stopped it.
4527                                    The second flag check is here to cover a
4528                                    race - the timer could have run and set
4529                                    this flag just after the previous check
4530                                    but before we did the pending check. */
4531                                 if (!hdw->state_decoder_quiescent) {
4532                                         hdw->quiescent_timer.expires =
4533                                                 jiffies +
4534                                                 (HZ * TIME_MSEC_DECODER_WAIT
4535                                                  / 1000);
4536                                         add_timer(&hdw->quiescent_timer);
4537                                 }
4538                         }
4539                         /* Don't allow decoder to start again until it has
4540                            been quiesced first.  This little detail should
4541                            hopefully further stabilize the encoder. */
4542                         return 0;
4543                 }
4544                 if (!hdw->state_pathway_ok ||
4545                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4546                     !hdw->state_pipeline_req ||
4547                     hdw->state_pipeline_pause ||
4548                     !hdw->state_pipeline_config ||
4549                     !hdw->state_encoder_config ||
4550                     !hdw->state_encoder_ok) return 0;
4551                 del_timer_sync(&hdw->quiescent_timer);
4552                 if (hdw->flag_decoder_missed) return 0;
4553                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4554                 hdw->state_decoder_quiescent = 0;
4555                 hdw->state_decoder_run = !0;
4556         }
4557         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4558         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4559         return !0;
4560 }
4561
4562
4563 /* Evaluate whether or not state_usbstream_run can change */
4564 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4565 {
4566         if (hdw->state_usbstream_run) {
4567                 int fl = !0;
4568                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4569                         fl = (hdw->state_encoder_ok &&
4570                               hdw->state_encoder_run);
4571                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4572                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4573                         fl = hdw->state_encoder_ok;
4574                 }
4575                 if (fl &&
4576                     hdw->state_pipeline_req &&
4577                     !hdw->state_pipeline_pause &&
4578                     hdw->state_pathway_ok) {
4579                         return 0;
4580                 }
4581                 pvr2_hdw_cmd_usbstream(hdw,0);
4582                 hdw->state_usbstream_run = 0;
4583         } else {
4584                 if (!hdw->state_pipeline_req ||
4585                     hdw->state_pipeline_pause ||
4586                     !hdw->state_pathway_ok) return 0;
4587                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4588                         if (!hdw->state_encoder_ok ||
4589                             !hdw->state_encoder_run) return 0;
4590                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4591                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4592                         if (!hdw->state_encoder_ok) return 0;
4593                         if (hdw->state_encoder_run) return 0;
4594                         if (hdw->hdw_desc->digital_control_scheme ==
4595                             PVR2_DIGITAL_SCHEME_ONAIR) {
4596                                 /* OnAir digital receivers won't stream
4597                                    unless the analog encoder has run first.
4598                                    Why?  I have no idea.  But don't even
4599                                    try until we know the analog side is
4600                                    known to have run. */
4601                                 if (!hdw->state_encoder_runok) return 0;
4602                         }
4603                 }
4604                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4605                 hdw->state_usbstream_run = !0;
4606         }
4607         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4608         return !0;
4609 }
4610
4611
4612 /* Attempt to configure pipeline, if needed */
4613 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4614 {
4615         if (hdw->state_pipeline_config ||
4616             hdw->state_pipeline_pause) return 0;
4617         pvr2_hdw_commit_execute(hdw);
4618         return !0;
4619 }
4620
4621
4622 /* Update pipeline idle and pipeline pause tracking states based on other
4623    inputs.  This must be called whenever the other relevant inputs have
4624    changed. */
4625 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4626 {
4627         unsigned int st;
4628         int updatedFl = 0;
4629         /* Update pipeline state */
4630         st = !(hdw->state_encoder_run ||
4631                hdw->state_decoder_run ||
4632                hdw->state_usbstream_run ||
4633                (!hdw->state_decoder_quiescent));
4634         if (!st != !hdw->state_pipeline_idle) {
4635                 hdw->state_pipeline_idle = st;
4636                 updatedFl = !0;
4637         }
4638         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4639                 hdw->state_pipeline_pause = 0;
4640                 updatedFl = !0;
4641         }
4642         return updatedFl;
4643 }
4644
4645
4646 typedef int (*state_eval_func)(struct pvr2_hdw *);
4647
4648 /* Set of functions to be run to evaluate various states in the driver. */
4649 static const state_eval_func eval_funcs[] = {
4650         state_eval_pathway_ok,
4651         state_eval_pipeline_config,
4652         state_eval_encoder_ok,
4653         state_eval_encoder_config,
4654         state_eval_decoder_run,
4655         state_eval_encoder_run,
4656         state_eval_usbstream_run,
4657 };
4658
4659
4660 /* Process various states and return true if we did anything interesting. */
4661 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4662 {
4663         unsigned int i;
4664         int state_updated = 0;
4665         int check_flag;
4666
4667         if (!hdw->state_stale) return 0;
4668         if ((hdw->fw1_state != FW1_STATE_OK) ||
4669             !hdw->flag_ok) {
4670                 hdw->state_stale = 0;
4671                 return !0;
4672         }
4673         /* This loop is the heart of the entire driver.  It keeps trying to
4674            evaluate various bits of driver state until nothing changes for
4675            one full iteration.  Each "bit of state" tracks some global
4676            aspect of the driver, e.g. whether decoder should run, if
4677            pipeline is configured, usb streaming is on, etc.  We separately
4678            evaluate each of those questions based on other driver state to
4679            arrive at the correct running configuration. */
4680         do {
4681                 check_flag = 0;
4682                 state_update_pipeline_state(hdw);
4683                 /* Iterate over each bit of state */
4684                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4685                         if ((*eval_funcs[i])(hdw)) {
4686                                 check_flag = !0;
4687                                 state_updated = !0;
4688                                 state_update_pipeline_state(hdw);
4689                         }
4690                 }
4691         } while (check_flag && hdw->flag_ok);
4692         hdw->state_stale = 0;
4693         trace_stbit("state_stale",hdw->state_stale);
4694         return state_updated;
4695 }
4696
4697
4698 static unsigned int print_input_mask(unsigned int msk,
4699                                      char *buf,unsigned int acnt)
4700 {
4701         unsigned int idx,ccnt;
4702         unsigned int tcnt = 0;
4703         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4704                 if (!((1 << idx) & msk)) continue;
4705                 ccnt = scnprintf(buf+tcnt,
4706                                  acnt-tcnt,
4707                                  "%s%s",
4708                                  (tcnt ? ", " : ""),
4709                                  control_values_input[idx]);
4710                 tcnt += ccnt;
4711         }
4712         return tcnt;
4713 }
4714
4715
4716 static const char *pvr2_pathway_state_name(int id)
4717 {
4718         switch (id) {
4719         case PVR2_PATHWAY_ANALOG: return "analog";
4720         case PVR2_PATHWAY_DIGITAL: return "digital";
4721         default: return "unknown";
4722         }
4723 }
4724
4725
4726 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4727                                              char *buf,unsigned int acnt)
4728 {
4729         switch (which) {
4730         case 0:
4731                 return scnprintf(
4732                         buf,acnt,
4733                         "driver:%s%s%s%s%s <mode=%s>",
4734                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4735                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4736                         (hdw->flag_disconnected ? " <disconnected>" :
4737                          " <connected>"),
4738                         (hdw->flag_tripped ? " <tripped>" : ""),
4739                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4740                         pvr2_pathway_state_name(hdw->pathway_state));
4741
4742         case 1:
4743                 return scnprintf(
4744                         buf,acnt,
4745                         "pipeline:%s%s%s%s",
4746                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4747                         (hdw->state_pipeline_config ?
4748                          " <configok>" : " <stale>"),
4749                         (hdw->state_pipeline_req ? " <req>" : ""),
4750                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4751         case 2:
4752                 return scnprintf(
4753                         buf,acnt,
4754                         "worker:%s%s%s%s%s%s%s",
4755                         (hdw->state_decoder_run ?
4756                          " <decode:run>" :
4757                          (hdw->state_decoder_quiescent ?
4758                           "" : " <decode:stop>")),
4759                         (hdw->state_decoder_quiescent ?
4760                          " <decode:quiescent>" : ""),
4761                         (hdw->state_encoder_ok ?
4762                          "" : " <encode:init>"),
4763                         (hdw->state_encoder_run ?
4764                          (hdw->state_encoder_runok ?
4765                           " <encode:run>" :
4766                           " <encode:firstrun>") :
4767                          (hdw->state_encoder_runok ?
4768                           " <encode:stop>" :
4769                           " <encode:virgin>")),
4770                         (hdw->state_encoder_config ?
4771                          " <encode:configok>" :
4772                          (hdw->state_encoder_waitok ?
4773                           "" : " <encode:waitok>")),
4774                         (hdw->state_usbstream_run ?
4775                          " <usb:run>" : " <usb:stop>"),
4776                         (hdw->state_pathway_ok ?
4777                          " <pathway:ok>" : ""));
4778         case 3:
4779                 return scnprintf(
4780                         buf,acnt,
4781                         "state: %s",
4782                         pvr2_get_state_name(hdw->master_state));
4783         case 4: {
4784                 unsigned int tcnt = 0;
4785                 unsigned int ccnt;
4786
4787                 ccnt = scnprintf(buf,
4788                                  acnt,
4789                                  "Hardware supported inputs: ");
4790                 tcnt += ccnt;
4791                 tcnt += print_input_mask(hdw->input_avail_mask,
4792                                          buf+tcnt,
4793                                          acnt-tcnt);
4794                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4795                         ccnt = scnprintf(buf+tcnt,
4796                                          acnt-tcnt,
4797                                          "; allowed inputs: ");
4798                         tcnt += ccnt;
4799                         tcnt += print_input_mask(hdw->input_allowed_mask,
4800                                                  buf+tcnt,
4801                                                  acnt-tcnt);
4802                 }
4803                 return tcnt;
4804         }
4805         case 5: {
4806                 struct pvr2_stream_stats stats;
4807                 if (!hdw->vid_stream) break;
4808                 pvr2_stream_get_stats(hdw->vid_stream,
4809                                       &stats,
4810                                       0);
4811                 return scnprintf(
4812                         buf,acnt,
4813                         "Bytes streamed=%u"
4814                         " URBs: queued=%u idle=%u ready=%u"
4815                         " processed=%u failed=%u",
4816                         stats.bytes_processed,
4817                         stats.buffers_in_queue,
4818                         stats.buffers_in_idle,
4819                         stats.buffers_in_ready,
4820                         stats.buffers_processed,
4821                         stats.buffers_failed);
4822         }
4823         case 6: {
4824                 struct v4l2_subdev *sd;
4825                 unsigned int tcnt = 0;
4826                 unsigned int ccnt;
4827                 const char *p;
4828                 unsigned int id;
4829                 ccnt = scnprintf(buf,
4830                                  acnt,
4831                                  "Associted v4l2_subdev drivers:");
4832                 tcnt += ccnt;
4833                 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4834                         id = sd->grp_id;
4835                         p = NULL;
4836                         if (id < ARRAY_SIZE(module_names)) {
4837                                 p = module_names[id];
4838                         }
4839                         if (!p) p = "(unknown)";
4840                         ccnt = scnprintf(buf + tcnt,
4841                                          acnt - tcnt,
4842                                          " %s (%u)", p, id);
4843                 }
4844                 return tcnt;
4845         }
4846         default: break;
4847         }
4848         return 0;
4849 }
4850
4851
4852 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4853                                    char *buf,unsigned int acnt)
4854 {
4855         unsigned int bcnt,ccnt,idx;
4856         bcnt = 0;
4857         LOCK_TAKE(hdw->big_lock);
4858         for (idx = 0; ; idx++) {
4859                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4860                 if (!ccnt) break;
4861                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4862                 if (!acnt) break;
4863                 buf[0] = '\n'; ccnt = 1;
4864                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4865         }
4866         LOCK_GIVE(hdw->big_lock);
4867         return bcnt;
4868 }
4869
4870
4871 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4872 {
4873         char buf[128];
4874         unsigned int idx,ccnt;
4875
4876         for (idx = 0; ; idx++) {
4877                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4878                 if (!ccnt) break;
4879                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4880         }
4881 }
4882
4883
4884 /* Evaluate and update the driver's current state, taking various actions
4885    as appropriate for the update. */
4886 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4887 {
4888         unsigned int st;
4889         int state_updated = 0;
4890         int callback_flag = 0;
4891         int analog_mode;
4892
4893         pvr2_trace(PVR2_TRACE_STBITS,
4894                    "Drive state check START");
4895         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4896                 pvr2_hdw_state_log_state(hdw);
4897         }
4898
4899         /* Process all state and get back over disposition */
4900         state_updated = pvr2_hdw_state_update(hdw);
4901
4902         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4903
4904         /* Update master state based upon all other states. */
4905         if (!hdw->flag_ok) {
4906                 st = PVR2_STATE_DEAD;
4907         } else if (hdw->fw1_state != FW1_STATE_OK) {
4908                 st = PVR2_STATE_COLD;
4909         } else if ((analog_mode ||
4910                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4911                    !hdw->state_encoder_ok) {
4912                 st = PVR2_STATE_WARM;
4913         } else if (hdw->flag_tripped ||
4914                    (analog_mode && hdw->flag_decoder_missed)) {
4915                 st = PVR2_STATE_ERROR;
4916         } else if (hdw->state_usbstream_run &&
4917                    (!analog_mode ||
4918                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4919                 st = PVR2_STATE_RUN;
4920         } else {
4921                 st = PVR2_STATE_READY;
4922         }
4923         if (hdw->master_state != st) {
4924                 pvr2_trace(PVR2_TRACE_STATE,
4925                            "Device state change from %s to %s",
4926                            pvr2_get_state_name(hdw->master_state),
4927                            pvr2_get_state_name(st));
4928                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4929                 hdw->master_state = st;
4930                 state_updated = !0;
4931                 callback_flag = !0;
4932         }
4933         if (state_updated) {
4934                 /* Trigger anyone waiting on any state changes here. */
4935                 wake_up(&hdw->state_wait_data);
4936         }
4937
4938         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4939                 pvr2_hdw_state_log_state(hdw);
4940         }
4941         pvr2_trace(PVR2_TRACE_STBITS,
4942                    "Drive state check DONE callback=%d",callback_flag);
4943
4944         return callback_flag;
4945 }
4946
4947
4948 /* Cause kernel thread to check / update driver state */
4949 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4950 {
4951         if (hdw->state_stale) return;
4952         hdw->state_stale = !0;
4953         trace_stbit("state_stale",hdw->state_stale);
4954         queue_work(hdw->workqueue,&hdw->workpoll);
4955 }
4956
4957
4958 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4959 {
4960         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4961 }
4962
4963
4964 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4965 {
4966         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4967 }
4968
4969
4970 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4971 {
4972         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4973 }
4974
4975
4976 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4977 {
4978         u32 cval,nval;
4979         int ret;
4980         if (~msk) {
4981                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4982                 if (ret) return ret;
4983                 nval = (cval & ~msk) | (val & msk);
4984                 pvr2_trace(PVR2_TRACE_GPIO,
4985                            "GPIO direction changing 0x%x:0x%x"
4986                            " from 0x%x to 0x%x",
4987                            msk,val,cval,nval);
4988         } else {
4989                 nval = val;
4990                 pvr2_trace(PVR2_TRACE_GPIO,
4991                            "GPIO direction changing to 0x%x",nval);
4992         }
4993         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4994 }
4995
4996
4997 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4998 {
4999         u32 cval,nval;
5000         int ret;
5001         if (~msk) {
5002                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5003                 if (ret) return ret;
5004                 nval = (cval & ~msk) | (val & msk);
5005                 pvr2_trace(PVR2_TRACE_GPIO,
5006                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5007                            msk,val,cval,nval);
5008         } else {
5009                 nval = val;
5010                 pvr2_trace(PVR2_TRACE_GPIO,
5011                            "GPIO output changing to 0x%x",nval);
5012         }
5013         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5014 }
5015
5016
5017 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5018 {
5019         struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5020         memset(vtp, 0, sizeof(*vtp));
5021         hdw->tuner_signal_stale = 0;
5022         pvr2_i2c_core_status_poll(hdw);
5023         /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5024            using v4l2-subdev - therefore we can't support that AT ALL right
5025            now.  (Of course, no sub-drivers seem to implement it either.
5026            But now it's a a chicken and egg problem...) */
5027         v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5028                              &hdw->tuner_signal_info);
5029         pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
5030                    " type=%u strength=%u audio=0x%x cap=0x%x"
5031                    " low=%u hi=%u",
5032                    vtp->type,
5033                    vtp->signal, vtp->rxsubchans, vtp->capability,
5034                    vtp->rangelow, vtp->rangehigh);
5035
5036         /* We have to do this to avoid getting into constant polling if
5037            there's nobody to answer a poll of cropcap info. */
5038         hdw->cropcap_stale = 0;
5039 }
5040
5041
5042 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5043 {
5044         return hdw->input_avail_mask;
5045 }
5046
5047
5048 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5049 {
5050         return hdw->input_allowed_mask;
5051 }
5052
5053
5054 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5055 {
5056         if (hdw->input_val != v) {
5057                 hdw->input_val = v;
5058                 hdw->input_dirty = !0;
5059         }
5060
5061         /* Handle side effects - if we switch to a mode that needs the RF
5062            tuner, then select the right frequency choice as well and mark
5063            it dirty. */
5064         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5065                 hdw->freqSelector = 0;
5066                 hdw->freqDirty = !0;
5067         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5068                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5069                 hdw->freqSelector = 1;
5070                 hdw->freqDirty = !0;
5071         }
5072         return 0;
5073 }
5074
5075
5076 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5077                                unsigned int change_mask,
5078                                unsigned int change_val)
5079 {
5080         int ret = 0;
5081         unsigned int nv,m,idx;
5082         LOCK_TAKE(hdw->big_lock);
5083         do {
5084                 nv = hdw->input_allowed_mask & ~change_mask;
5085                 nv |= (change_val & change_mask);
5086                 nv &= hdw->input_avail_mask;
5087                 if (!nv) {
5088                         /* No legal modes left; return error instead. */
5089                         ret = -EPERM;
5090                         break;
5091                 }
5092                 hdw->input_allowed_mask = nv;
5093                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5094                         /* Current mode is still in the allowed mask, so
5095                            we're done. */
5096                         break;
5097                 }
5098                 /* Select and switch to a mode that is still in the allowed
5099                    mask */
5100                 if (!hdw->input_allowed_mask) {
5101                         /* Nothing legal; give up */
5102                         break;
5103                 }
5104                 m = hdw->input_allowed_mask;
5105                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5106                         if (!((1 << idx) & m)) continue;
5107                         pvr2_hdw_set_input(hdw,idx);
5108                         break;
5109                 }
5110         } while (0);
5111         LOCK_GIVE(hdw->big_lock);
5112         return ret;
5113 }
5114
5115
5116 /* Find I2C address of eeprom */
5117 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5118 {
5119         int result;
5120         LOCK_TAKE(hdw->ctl_lock); do {
5121                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5122                 result = pvr2_send_request(hdw,
5123                                            hdw->cmd_buffer,1,
5124                                            hdw->cmd_buffer,1);
5125                 if (result < 0) break;
5126                 result = hdw->cmd_buffer[0];
5127         } while(0); LOCK_GIVE(hdw->ctl_lock);
5128         return result;
5129 }
5130
5131
5132 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
5133                              struct v4l2_dbg_match *match, u64 reg_id,
5134                              int setFl, u64 *val_ptr)
5135 {
5136 #ifdef CONFIG_VIDEO_ADV_DEBUG
5137         struct pvr2_i2c_client *cp;
5138         struct v4l2_dbg_register req;
5139         int stat = 0;
5140         int okFl = 0;
5141
5142         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5143
5144         req.match = *match;
5145         req.reg = reg_id;
5146         if (setFl) req.val = *val_ptr;
5147         /* It would be nice to know if a sub-device answered the request */
5148         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5149         if (!setFl) *val_ptr = req.val;
5150         if (!okFl) mutex_lock(&hdw->i2c_list_lock); do {
5151                 list_for_each_entry(cp, &hdw->i2c_clients, list) {
5152                         if (!v4l2_chip_match_i2c_client(
5153                                     cp->client,
5154                                     &req.match)) {
5155                                 continue;
5156                         }
5157                         stat = pvr2_i2c_client_cmd(
5158                                 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
5159                                     VIDIOC_DBG_G_REGISTER),&req);
5160                         if (!setFl) *val_ptr = req.val;
5161                         okFl = !0;
5162                         break;
5163                 }
5164         } while (0); mutex_unlock(&hdw->i2c_list_lock);
5165         if (okFl) {
5166                 return stat;
5167         }
5168         return -EINVAL;
5169 #else
5170         return -ENOSYS;
5171 #endif
5172 }
5173
5174
5175 /*
5176   Stuff for Emacs to see, in order to encourage consistent editing style:
5177   *** Local Variables: ***
5178   *** mode: c ***
5179   *** fill-column: 75 ***
5180   *** tab-width: 8 ***
5181   *** c-basic-offset: 8 ***
5182   *** End: ***
5183   */