4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/errno.h>
22 #include <linux/string.h>
23 #include <linux/slab.h>
24 #include <linux/firmware.h>
25 #include <linux/videodev2.h>
26 #include <media/v4l2-common.h>
28 #include "pvrusb2-std.h"
29 #include "pvrusb2-util.h"
30 #include "pvrusb2-hdw.h"
31 #include "pvrusb2-i2c-core.h"
32 #include "pvrusb2-i2c-track.h"
33 #include "pvrusb2-tuner.h"
34 #include "pvrusb2-eeprom.h"
35 #include "pvrusb2-hdw-internal.h"
36 #include "pvrusb2-encoder.h"
37 #include "pvrusb2-debug.h"
38 #include "pvrusb2-fx2-cmd.h"
40 #define TV_MIN_FREQ 55250000L
41 #define TV_MAX_FREQ 850000000L
43 /* This defines a minimum interval that the decoder must remain quiet
44 before we are allowed to start it running. */
45 #define TIME_MSEC_DECODER_WAIT 50
47 /* This defines a minimum interval that the encoder must remain quiet
48 before we are allowed to configure it. I had this originally set to
49 50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
50 things work better when it's set to 100msec. */
51 #define TIME_MSEC_ENCODER_WAIT 100
53 /* This defines the minimum interval that the encoder must successfully run
54 before we consider that the encoder has run at least once since its
55 firmware has been loaded. This measurement is in important for cases
56 where we can't do something until we know that the encoder has been run
58 #define TIME_MSEC_ENCODER_OK 250
60 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
61 static DEFINE_MUTEX(pvr2_unit_mtx);
64 static int procreload;
65 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
66 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
67 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
68 static int init_pause_msec;
70 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
71 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
72 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
73 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
74 module_param(procreload, int, S_IRUGO|S_IWUSR);
75 MODULE_PARM_DESC(procreload,
76 "Attempt init failure recovery with firmware reload");
77 module_param_array(tuner, int, NULL, 0444);
78 MODULE_PARM_DESC(tuner,"specify installed tuner type");
79 module_param_array(video_std, int, NULL, 0444);
80 MODULE_PARM_DESC(video_std,"specify initial video standard");
81 module_param_array(tolerance, int, NULL, 0444);
82 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
84 /* US Broadcast channel 7 (175.25 MHz) */
85 static int default_tv_freq = 175250000L;
86 /* 104.3 MHz, a usable FM station for my area */
87 static int default_radio_freq = 104300000L;
89 module_param_named(tv_freq, default_tv_freq, int, 0444);
90 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
91 module_param_named(radio_freq, default_radio_freq, int, 0444);
92 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
94 #define PVR2_CTL_WRITE_ENDPOINT 0x01
95 #define PVR2_CTL_READ_ENDPOINT 0x81
97 #define PVR2_GPIO_IN 0x9008
98 #define PVR2_GPIO_OUT 0x900c
99 #define PVR2_GPIO_DIR 0x9020
101 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
103 #define PVR2_FIRMWARE_ENDPOINT 0x02
105 /* size of a firmware chunk */
106 #define FIRMWARE_CHUNK_SIZE 0x2000
108 static const char *module_names[] = {
109 [PVR2_CLIENT_ID_MSP3400] = "msp3400",
110 [PVR2_CLIENT_ID_CX25840] = "cx25840",
111 [PVR2_CLIENT_ID_SAA7115] = "saa7115",
112 [PVR2_CLIENT_ID_TUNER] = "tuner",
113 [PVR2_CLIENT_ID_CS53132A] = "cs53132a",
117 static const unsigned char *module_i2c_addresses[] = {
118 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
122 /* Define the list of additional controls we'll dynamically construct based
123 on query of the cx2341x module. */
124 struct pvr2_mpeg_ids {
128 static const struct pvr2_mpeg_ids mpeg_ids[] = {
130 .strid = "audio_layer",
131 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
133 .strid = "audio_bitrate",
134 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
136 /* Already using audio_mode elsewhere :-( */
137 .strid = "mpeg_audio_mode",
138 .id = V4L2_CID_MPEG_AUDIO_MODE,
140 .strid = "mpeg_audio_mode_extension",
141 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
143 .strid = "audio_emphasis",
144 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
146 .strid = "audio_crc",
147 .id = V4L2_CID_MPEG_AUDIO_CRC,
149 .strid = "video_aspect",
150 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
152 .strid = "video_b_frames",
153 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
155 .strid = "video_gop_size",
156 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
158 .strid = "video_gop_closure",
159 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
161 .strid = "video_bitrate_mode",
162 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
164 .strid = "video_bitrate",
165 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
167 .strid = "video_bitrate_peak",
168 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
170 .strid = "video_temporal_decimation",
171 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
173 .strid = "stream_type",
174 .id = V4L2_CID_MPEG_STREAM_TYPE,
176 .strid = "video_spatial_filter_mode",
177 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
179 .strid = "video_spatial_filter",
180 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
182 .strid = "video_luma_spatial_filter_type",
183 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
185 .strid = "video_chroma_spatial_filter_type",
186 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
188 .strid = "video_temporal_filter_mode",
189 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
191 .strid = "video_temporal_filter",
192 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
194 .strid = "video_median_filter_type",
195 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
197 .strid = "video_luma_median_filter_top",
198 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
200 .strid = "video_luma_median_filter_bottom",
201 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
203 .strid = "video_chroma_median_filter_top",
204 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
206 .strid = "video_chroma_median_filter_bottom",
207 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
210 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
213 static const char *control_values_srate[] = {
214 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
215 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
216 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
221 static const char *control_values_input[] = {
222 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
223 [PVR2_CVAL_INPUT_DTV] = "dtv",
224 [PVR2_CVAL_INPUT_RADIO] = "radio",
225 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
226 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
230 static const char *control_values_audiomode[] = {
231 [V4L2_TUNER_MODE_MONO] = "Mono",
232 [V4L2_TUNER_MODE_STEREO] = "Stereo",
233 [V4L2_TUNER_MODE_LANG1] = "Lang1",
234 [V4L2_TUNER_MODE_LANG2] = "Lang2",
235 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
239 static const char *control_values_hsm[] = {
240 [PVR2_CVAL_HSM_FAIL] = "Fail",
241 [PVR2_CVAL_HSM_HIGH] = "High",
242 [PVR2_CVAL_HSM_FULL] = "Full",
246 static const char *pvr2_state_names[] = {
247 [PVR2_STATE_NONE] = "none",
248 [PVR2_STATE_DEAD] = "dead",
249 [PVR2_STATE_COLD] = "cold",
250 [PVR2_STATE_WARM] = "warm",
251 [PVR2_STATE_ERROR] = "error",
252 [PVR2_STATE_READY] = "ready",
253 [PVR2_STATE_RUN] = "run",
257 struct pvr2_fx2cmd_descdef {
262 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
263 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
264 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
265 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
266 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
267 {FX2CMD_REG_WRITE, "write encoder register"},
268 {FX2CMD_REG_READ, "read encoder register"},
269 {FX2CMD_MEMSEL, "encoder memsel"},
270 {FX2CMD_I2C_WRITE, "i2c write"},
271 {FX2CMD_I2C_READ, "i2c read"},
272 {FX2CMD_GET_USB_SPEED, "get USB speed"},
273 {FX2CMD_STREAMING_ON, "stream on"},
274 {FX2CMD_STREAMING_OFF, "stream off"},
275 {FX2CMD_FWPOST1, "fwpost1"},
276 {FX2CMD_POWER_OFF, "power off"},
277 {FX2CMD_POWER_ON, "power on"},
278 {FX2CMD_DEEP_RESET, "deep reset"},
279 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
280 {FX2CMD_GET_IR_CODE, "get IR code"},
281 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
282 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
283 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
284 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
285 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
286 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
287 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
291 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
292 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
293 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
294 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
295 static void pvr2_hdw_worker_i2c(struct work_struct *work);
296 static void pvr2_hdw_worker_poll(struct work_struct *work);
297 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
298 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
299 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
300 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
301 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
302 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
303 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
304 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
305 static void pvr2_hdw_quiescent_timeout(unsigned long);
306 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
307 static void pvr2_hdw_encoder_run_timeout(unsigned long);
308 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
309 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
310 unsigned int timeout,int probe_fl,
311 void *write_data,unsigned int write_len,
312 void *read_data,unsigned int read_len);
313 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
316 static void trace_stbit(const char *name,int val)
318 pvr2_trace(PVR2_TRACE_STBITS,
319 "State bit %s <-- %s",
320 name,(val ? "true" : "false"));
323 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
325 struct pvr2_hdw *hdw = cptr->hdw;
326 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
327 *vp = hdw->freqTable[hdw->freqProgSlot-1];
334 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
336 struct pvr2_hdw *hdw = cptr->hdw;
337 unsigned int slotId = hdw->freqProgSlot;
338 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
339 hdw->freqTable[slotId-1] = v;
340 /* Handle side effects correctly - if we're tuned to this
341 slot, then forgot the slot id relation since the stored
342 frequency has been changed. */
343 if (hdw->freqSelector) {
344 if (hdw->freqSlotRadio == slotId) {
345 hdw->freqSlotRadio = 0;
348 if (hdw->freqSlotTelevision == slotId) {
349 hdw->freqSlotTelevision = 0;
356 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
358 *vp = cptr->hdw->freqProgSlot;
362 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
364 struct pvr2_hdw *hdw = cptr->hdw;
365 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
366 hdw->freqProgSlot = v;
371 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
373 struct pvr2_hdw *hdw = cptr->hdw;
374 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
378 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
381 struct pvr2_hdw *hdw = cptr->hdw;
382 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
384 freq = hdw->freqTable[slotId-1];
386 pvr2_hdw_set_cur_freq(hdw,freq);
388 if (hdw->freqSelector) {
389 hdw->freqSlotRadio = slotId;
391 hdw->freqSlotTelevision = slotId;
396 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
398 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
402 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
404 return cptr->hdw->freqDirty != 0;
407 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
409 cptr->hdw->freqDirty = 0;
412 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
414 pvr2_hdw_set_cur_freq(cptr->hdw,v);
418 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
420 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
421 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
425 *left = cap->bounds.left;
429 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
431 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
432 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
436 *left = cap->bounds.left;
437 if (cap->bounds.width > cptr->hdw->cropw_val) {
438 *left += cap->bounds.width - cptr->hdw->cropw_val;
443 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
445 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
446 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
450 *top = cap->bounds.top;
454 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
456 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
457 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
461 *top = cap->bounds.top;
462 if (cap->bounds.height > cptr->hdw->croph_val) {
463 *top += cap->bounds.height - cptr->hdw->croph_val;
468 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
470 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
471 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
476 if (cap->bounds.width > cptr->hdw->cropl_val) {
477 *val = cap->bounds.width - cptr->hdw->cropl_val;
482 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
484 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
485 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
490 if (cap->bounds.height > cptr->hdw->cropt_val) {
491 *val = cap->bounds.height - cptr->hdw->cropt_val;
496 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
498 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
499 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
503 *val = cap->bounds.left;
507 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
509 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
510 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
514 *val = cap->bounds.top;
518 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
520 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
521 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
525 *val = cap->bounds.width;
529 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
531 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
532 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
536 *val = cap->bounds.height;
540 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
542 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
543 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
547 *val = cap->defrect.left;
551 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
553 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
554 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
558 *val = cap->defrect.top;
562 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
564 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
565 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
569 *val = cap->defrect.width;
573 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
575 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
576 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
580 *val = cap->defrect.height;
584 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
586 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
587 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
591 *val = cap->pixelaspect.numerator;
595 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
597 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
598 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
602 *val = cap->pixelaspect.denominator;
606 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
608 /* Actual maximum depends on the video standard in effect. */
609 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
617 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
619 /* Actual minimum depends on device digitizer type. */
620 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
628 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
630 *vp = cptr->hdw->input_val;
634 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
636 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
639 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
641 return pvr2_hdw_set_input(cptr->hdw,v);
644 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
646 return cptr->hdw->input_dirty != 0;
649 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
651 cptr->hdw->input_dirty = 0;
655 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
658 struct pvr2_hdw *hdw = cptr->hdw;
659 if (hdw->tuner_signal_stale) {
660 pvr2_hdw_status_poll(hdw);
662 fv = hdw->tuner_signal_info.rangehigh;
664 /* Safety fallback */
668 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
677 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
680 struct pvr2_hdw *hdw = cptr->hdw;
681 if (hdw->tuner_signal_stale) {
682 pvr2_hdw_status_poll(hdw);
684 fv = hdw->tuner_signal_info.rangelow;
686 /* Safety fallback */
690 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
699 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
701 return cptr->hdw->enc_stale != 0;
704 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
706 cptr->hdw->enc_stale = 0;
707 cptr->hdw->enc_unsafe_stale = 0;
710 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
713 struct v4l2_ext_controls cs;
714 struct v4l2_ext_control c1;
715 memset(&cs,0,sizeof(cs));
716 memset(&c1,0,sizeof(c1));
719 c1.id = cptr->info->v4l_id;
720 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
727 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
730 struct pvr2_hdw *hdw = cptr->hdw;
731 struct v4l2_ext_controls cs;
732 struct v4l2_ext_control c1;
733 memset(&cs,0,sizeof(cs));
734 memset(&c1,0,sizeof(c1));
737 c1.id = cptr->info->v4l_id;
739 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
740 hdw->state_encoder_run, &cs,
743 /* Oops. cx2341x is telling us it's not safe to change
744 this control while we're capturing. Make a note of this
745 fact so that the pipeline will be stopped the next time
746 controls are committed. Then go on ahead and store this
748 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
751 if (!ret) hdw->enc_unsafe_stale = !0;
758 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
760 struct v4l2_queryctrl qctrl;
761 struct pvr2_ctl_info *info;
762 qctrl.id = cptr->info->v4l_id;
763 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
764 /* Strip out the const so we can adjust a function pointer. It's
765 OK to do this here because we know this is a dynamically created
766 control, so the underlying storage for the info pointer is (a)
767 private to us, and (b) not in read-only storage. Either we do
768 this or we significantly complicate the underlying control
770 info = (struct pvr2_ctl_info *)(cptr->info);
771 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
772 if (info->set_value) {
773 info->set_value = NULL;
776 if (!(info->set_value)) {
777 info->set_value = ctrl_cx2341x_set;
783 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
785 *vp = cptr->hdw->state_pipeline_req;
789 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
791 *vp = cptr->hdw->master_state;
795 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
797 int result = pvr2_hdw_is_hsm(cptr->hdw);
798 *vp = PVR2_CVAL_HSM_FULL;
799 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
800 if (result) *vp = PVR2_CVAL_HSM_HIGH;
804 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
806 *vp = cptr->hdw->std_mask_avail;
810 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
812 struct pvr2_hdw *hdw = cptr->hdw;
814 ns = hdw->std_mask_avail;
815 ns = (ns & ~m) | (v & m);
816 if (ns == hdw->std_mask_avail) return 0;
817 hdw->std_mask_avail = ns;
818 pvr2_hdw_internal_set_std_avail(hdw);
819 pvr2_hdw_internal_find_stdenum(hdw);
823 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
824 char *bufPtr,unsigned int bufSize,
827 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
831 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
832 const char *bufPtr,unsigned int bufSize,
837 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
838 if (ret < 0) return ret;
839 if (mskp) *mskp = id;
840 if (valp) *valp = id;
844 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
846 *vp = cptr->hdw->std_mask_cur;
850 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
852 struct pvr2_hdw *hdw = cptr->hdw;
854 ns = hdw->std_mask_cur;
855 ns = (ns & ~m) | (v & m);
856 if (ns == hdw->std_mask_cur) return 0;
857 hdw->std_mask_cur = ns;
859 pvr2_hdw_internal_find_stdenum(hdw);
863 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
865 return cptr->hdw->std_dirty != 0;
868 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
870 cptr->hdw->std_dirty = 0;
873 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
875 struct pvr2_hdw *hdw = cptr->hdw;
876 pvr2_hdw_status_poll(hdw);
877 *vp = hdw->tuner_signal_info.signal;
881 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
884 unsigned int subchan;
885 struct pvr2_hdw *hdw = cptr->hdw;
886 pvr2_hdw_status_poll(hdw);
887 subchan = hdw->tuner_signal_info.rxsubchans;
888 if (subchan & V4L2_TUNER_SUB_MONO) {
889 val |= (1 << V4L2_TUNER_MODE_MONO);
891 if (subchan & V4L2_TUNER_SUB_STEREO) {
892 val |= (1 << V4L2_TUNER_MODE_STEREO);
894 if (subchan & V4L2_TUNER_SUB_LANG1) {
895 val |= (1 << V4L2_TUNER_MODE_LANG1);
897 if (subchan & V4L2_TUNER_SUB_LANG2) {
898 val |= (1 << V4L2_TUNER_MODE_LANG2);
905 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
907 struct pvr2_hdw *hdw = cptr->hdw;
908 if (v < 0) return -EINVAL;
909 if (v > hdw->std_enum_cnt) return -EINVAL;
910 hdw->std_enum_cur = v;
913 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
914 hdw->std_mask_cur = hdw->std_defs[v].id;
920 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
922 *vp = cptr->hdw->std_enum_cur;
927 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
929 return cptr->hdw->std_dirty != 0;
933 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
935 cptr->hdw->std_dirty = 0;
939 #define DEFINT(vmin,vmax) \
940 .type = pvr2_ctl_int, \
941 .def.type_int.min_value = vmin, \
942 .def.type_int.max_value = vmax
944 #define DEFENUM(tab) \
945 .type = pvr2_ctl_enum, \
946 .def.type_enum.count = ARRAY_SIZE(tab), \
947 .def.type_enum.value_names = tab
950 .type = pvr2_ctl_bool
952 #define DEFMASK(msk,tab) \
953 .type = pvr2_ctl_bitmask, \
954 .def.type_bitmask.valid_bits = msk, \
955 .def.type_bitmask.bit_names = tab
957 #define DEFREF(vname) \
958 .set_value = ctrl_set_##vname, \
959 .get_value = ctrl_get_##vname, \
960 .is_dirty = ctrl_isdirty_##vname, \
961 .clear_dirty = ctrl_cleardirty_##vname
964 #define VCREATE_FUNCS(vname) \
965 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
966 {*vp = cptr->hdw->vname##_val; return 0;} \
967 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
968 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
969 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
970 {return cptr->hdw->vname##_dirty != 0;} \
971 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
972 {cptr->hdw->vname##_dirty = 0;}
974 VCREATE_FUNCS(brightness)
975 VCREATE_FUNCS(contrast)
976 VCREATE_FUNCS(saturation)
978 VCREATE_FUNCS(volume)
979 VCREATE_FUNCS(balance)
981 VCREATE_FUNCS(treble)
987 VCREATE_FUNCS(audiomode)
988 VCREATE_FUNCS(res_hor)
989 VCREATE_FUNCS(res_ver)
992 /* Table definition of all controls which can be manipulated */
993 static const struct pvr2_ctl_info control_defs[] = {
995 .v4l_id = V4L2_CID_BRIGHTNESS,
996 .desc = "Brightness",
997 .name = "brightness",
998 .default_value = 128,
1002 .v4l_id = V4L2_CID_CONTRAST,
1005 .default_value = 68,
1009 .v4l_id = V4L2_CID_SATURATION,
1010 .desc = "Saturation",
1011 .name = "saturation",
1012 .default_value = 64,
1016 .v4l_id = V4L2_CID_HUE,
1023 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1026 .default_value = 62000,
1030 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1035 DEFINT(-32768,32767),
1037 .v4l_id = V4L2_CID_AUDIO_BASS,
1042 DEFINT(-32768,32767),
1044 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1049 DEFINT(-32768,32767),
1051 .v4l_id = V4L2_CID_AUDIO_MUTE,
1058 .desc = "Capture crop left margin",
1059 .name = "crop_left",
1060 .internal_id = PVR2_CID_CROPL,
1064 .get_min_value = ctrl_cropl_min_get,
1065 .get_max_value = ctrl_cropl_max_get,
1066 .get_def_value = ctrl_get_cropcapdl,
1068 .desc = "Capture crop top margin",
1070 .internal_id = PVR2_CID_CROPT,
1074 .get_min_value = ctrl_cropt_min_get,
1075 .get_max_value = ctrl_cropt_max_get,
1076 .get_def_value = ctrl_get_cropcapdt,
1078 .desc = "Capture crop width",
1079 .name = "crop_width",
1080 .internal_id = PVR2_CID_CROPW,
1081 .default_value = 720,
1083 .get_max_value = ctrl_cropw_max_get,
1084 .get_def_value = ctrl_get_cropcapdw,
1086 .desc = "Capture crop height",
1087 .name = "crop_height",
1088 .internal_id = PVR2_CID_CROPH,
1089 .default_value = 480,
1091 .get_max_value = ctrl_croph_max_get,
1092 .get_def_value = ctrl_get_cropcapdh,
1094 .desc = "Capture capability pixel aspect numerator",
1095 .name = "cropcap_pixel_numerator",
1096 .internal_id = PVR2_CID_CROPCAPPAN,
1097 .get_value = ctrl_get_cropcappan,
1099 .desc = "Capture capability pixel aspect denominator",
1100 .name = "cropcap_pixel_denominator",
1101 .internal_id = PVR2_CID_CROPCAPPAD,
1102 .get_value = ctrl_get_cropcappad,
1104 .desc = "Capture capability bounds top",
1105 .name = "cropcap_bounds_top",
1106 .internal_id = PVR2_CID_CROPCAPBT,
1107 .get_value = ctrl_get_cropcapbt,
1109 .desc = "Capture capability bounds left",
1110 .name = "cropcap_bounds_left",
1111 .internal_id = PVR2_CID_CROPCAPBL,
1112 .get_value = ctrl_get_cropcapbl,
1114 .desc = "Capture capability bounds width",
1115 .name = "cropcap_bounds_width",
1116 .internal_id = PVR2_CID_CROPCAPBW,
1117 .get_value = ctrl_get_cropcapbw,
1119 .desc = "Capture capability bounds height",
1120 .name = "cropcap_bounds_height",
1121 .internal_id = PVR2_CID_CROPCAPBH,
1122 .get_value = ctrl_get_cropcapbh,
1124 .desc = "Video Source",
1126 .internal_id = PVR2_CID_INPUT,
1127 .default_value = PVR2_CVAL_INPUT_TV,
1128 .check_value = ctrl_check_input,
1130 DEFENUM(control_values_input),
1132 .desc = "Audio Mode",
1133 .name = "audio_mode",
1134 .internal_id = PVR2_CID_AUDIOMODE,
1135 .default_value = V4L2_TUNER_MODE_STEREO,
1137 DEFENUM(control_values_audiomode),
1139 .desc = "Horizontal capture resolution",
1140 .name = "resolution_hor",
1141 .internal_id = PVR2_CID_HRES,
1142 .default_value = 720,
1146 .desc = "Vertical capture resolution",
1147 .name = "resolution_ver",
1148 .internal_id = PVR2_CID_VRES,
1149 .default_value = 480,
1152 /* Hook in check for video standard and adjust maximum
1153 depending on the standard. */
1154 .get_max_value = ctrl_vres_max_get,
1155 .get_min_value = ctrl_vres_min_get,
1157 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1158 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1159 .desc = "Audio Sampling Frequency",
1162 DEFENUM(control_values_srate),
1164 .desc = "Tuner Frequency (Hz)",
1165 .name = "frequency",
1166 .internal_id = PVR2_CID_FREQUENCY,
1168 .set_value = ctrl_freq_set,
1169 .get_value = ctrl_freq_get,
1170 .is_dirty = ctrl_freq_is_dirty,
1171 .clear_dirty = ctrl_freq_clear_dirty,
1173 /* Hook in check for input value (tv/radio) and adjust
1174 max/min values accordingly */
1175 .get_max_value = ctrl_freq_max_get,
1176 .get_min_value = ctrl_freq_min_get,
1180 .set_value = ctrl_channel_set,
1181 .get_value = ctrl_channel_get,
1182 DEFINT(0,FREQTABLE_SIZE),
1184 .desc = "Channel Program Frequency",
1185 .name = "freq_table_value",
1186 .set_value = ctrl_channelfreq_set,
1187 .get_value = ctrl_channelfreq_get,
1189 /* Hook in check for input value (tv/radio) and adjust
1190 max/min values accordingly */
1191 .get_max_value = ctrl_freq_max_get,
1192 .get_min_value = ctrl_freq_min_get,
1194 .desc = "Channel Program ID",
1195 .name = "freq_table_channel",
1196 .set_value = ctrl_channelprog_set,
1197 .get_value = ctrl_channelprog_get,
1198 DEFINT(0,FREQTABLE_SIZE),
1200 .desc = "Streaming Enabled",
1201 .name = "streaming_enabled",
1202 .get_value = ctrl_streamingenabled_get,
1205 .desc = "USB Speed",
1206 .name = "usb_speed",
1207 .get_value = ctrl_hsm_get,
1208 DEFENUM(control_values_hsm),
1210 .desc = "Master State",
1211 .name = "master_state",
1212 .get_value = ctrl_masterstate_get,
1213 DEFENUM(pvr2_state_names),
1215 .desc = "Signal Present",
1216 .name = "signal_present",
1217 .get_value = ctrl_signal_get,
1220 .desc = "Audio Modes Present",
1221 .name = "audio_modes_present",
1222 .get_value = ctrl_audio_modes_present_get,
1223 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1224 v4l. Nothing outside of this module cares about this,
1225 but I reuse it in order to also reuse the
1226 control_values_audiomode string table. */
1227 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1228 (1 << V4L2_TUNER_MODE_STEREO)|
1229 (1 << V4L2_TUNER_MODE_LANG1)|
1230 (1 << V4L2_TUNER_MODE_LANG2)),
1231 control_values_audiomode),
1233 .desc = "Video Standards Available Mask",
1234 .name = "video_standard_mask_available",
1235 .internal_id = PVR2_CID_STDAVAIL,
1237 .get_value = ctrl_stdavail_get,
1238 .set_value = ctrl_stdavail_set,
1239 .val_to_sym = ctrl_std_val_to_sym,
1240 .sym_to_val = ctrl_std_sym_to_val,
1241 .type = pvr2_ctl_bitmask,
1243 .desc = "Video Standards In Use Mask",
1244 .name = "video_standard_mask_active",
1245 .internal_id = PVR2_CID_STDCUR,
1247 .get_value = ctrl_stdcur_get,
1248 .set_value = ctrl_stdcur_set,
1249 .is_dirty = ctrl_stdcur_is_dirty,
1250 .clear_dirty = ctrl_stdcur_clear_dirty,
1251 .val_to_sym = ctrl_std_val_to_sym,
1252 .sym_to_val = ctrl_std_sym_to_val,
1253 .type = pvr2_ctl_bitmask,
1255 .desc = "Video Standard Name",
1256 .name = "video_standard",
1257 .internal_id = PVR2_CID_STDENUM,
1259 .get_value = ctrl_stdenumcur_get,
1260 .set_value = ctrl_stdenumcur_set,
1261 .is_dirty = ctrl_stdenumcur_is_dirty,
1262 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1263 .type = pvr2_ctl_enum,
1267 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1270 const char *pvr2_config_get_name(enum pvr2_config cfg)
1273 case pvr2_config_empty: return "empty";
1274 case pvr2_config_mpeg: return "mpeg";
1275 case pvr2_config_vbi: return "vbi";
1276 case pvr2_config_pcm: return "pcm";
1277 case pvr2_config_rawvideo: return "raw video";
1283 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1285 return hdw->usb_dev;
1289 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1291 return hdw->serial_number;
1295 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1297 return hdw->bus_info;
1301 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1303 return hdw->identifier;
1307 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1309 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1312 /* Set the currently tuned frequency and account for all possible
1313 driver-core side effects of this action. */
1314 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1316 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1317 if (hdw->freqSelector) {
1318 /* Swing over to radio frequency selection */
1319 hdw->freqSelector = 0;
1320 hdw->freqDirty = !0;
1322 if (hdw->freqValRadio != val) {
1323 hdw->freqValRadio = val;
1324 hdw->freqSlotRadio = 0;
1325 hdw->freqDirty = !0;
1328 if (!(hdw->freqSelector)) {
1329 /* Swing over to television frequency selection */
1330 hdw->freqSelector = 1;
1331 hdw->freqDirty = !0;
1333 if (hdw->freqValTelevision != val) {
1334 hdw->freqValTelevision = val;
1335 hdw->freqSlotTelevision = 0;
1336 hdw->freqDirty = !0;
1341 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1343 return hdw->unit_number;
1347 /* Attempt to locate one of the given set of files. Messages are logged
1348 appropriate to what has been found. The return value will be 0 or
1349 greater on success (it will be the index of the file name found) and
1350 fw_entry will be filled in. Otherwise a negative error is returned on
1351 failure. If the return value is -ENOENT then no viable firmware file
1352 could be located. */
1353 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1354 const struct firmware **fw_entry,
1355 const char *fwtypename,
1356 unsigned int fwcount,
1357 const char *fwnames[])
1361 for (idx = 0; idx < fwcount; idx++) {
1362 ret = request_firmware(fw_entry,
1364 &hdw->usb_dev->dev);
1366 trace_firmware("Located %s firmware: %s;"
1372 if (ret == -ENOENT) continue;
1373 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1374 "request_firmware fatal error with code=%d",ret);
1377 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1379 " Device %s firmware"
1380 " seems to be missing.",
1382 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1383 "Did you install the pvrusb2 firmware files"
1384 " in their proper location?");
1386 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1387 "request_firmware unable to locate %s file %s",
1388 fwtypename,fwnames[0]);
1390 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1391 "request_firmware unable to locate"
1392 " one of the following %s files:",
1394 for (idx = 0; idx < fwcount; idx++) {
1395 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1396 "request_firmware: Failed to find %s",
1405 * pvr2_upload_firmware1().
1407 * Send the 8051 firmware to the device. After the upload, arrange for
1408 * device to re-enumerate.
1410 * NOTE : the pointer to the firmware data given by request_firmware()
1411 * is not suitable for an usb transaction.
1414 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1416 const struct firmware *fw_entry = NULL;
1422 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1423 hdw->fw1_state = FW1_STATE_OK;
1424 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1425 "Connected device type defines"
1426 " no firmware to upload; ignoring firmware");
1430 hdw->fw1_state = FW1_STATE_FAILED; // default result
1432 trace_firmware("pvr2_upload_firmware1");
1434 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1435 hdw->hdw_desc->fx2_firmware.cnt,
1436 hdw->hdw_desc->fx2_firmware.lst);
1438 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1442 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1443 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1445 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1447 if (fw_entry->size != 0x2000){
1448 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1449 release_firmware(fw_entry);
1453 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1454 if (fw_ptr == NULL){
1455 release_firmware(fw_entry);
1459 /* We have to hold the CPU during firmware upload. */
1460 pvr2_hdw_cpureset_assert(hdw,1);
1462 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1466 for(address = 0; address < fw_entry->size; address += 0x800) {
1467 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1468 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1469 0, fw_ptr, 0x800, HZ);
1472 trace_firmware("Upload done, releasing device's CPU");
1474 /* Now release the CPU. It will disconnect and reconnect later. */
1475 pvr2_hdw_cpureset_assert(hdw,0);
1478 release_firmware(fw_entry);
1480 trace_firmware("Upload done (%d bytes sent)",ret);
1482 /* We should have written 8192 bytes */
1484 hdw->fw1_state = FW1_STATE_RELOAD;
1493 * pvr2_upload_firmware2()
1495 * This uploads encoder firmware on endpoint 2.
1499 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1501 const struct firmware *fw_entry = NULL;
1503 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1507 static const char *fw_files[] = {
1508 CX2341X_FIRM_ENC_FILENAME,
1511 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1515 trace_firmware("pvr2_upload_firmware2");
1517 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1518 ARRAY_SIZE(fw_files), fw_files);
1519 if (ret < 0) return ret;
1522 /* Since we're about to completely reinitialize the encoder,
1523 invalidate our cached copy of its configuration state. Next
1524 time we configure the encoder, then we'll fully configure it. */
1525 hdw->enc_cur_valid = 0;
1527 /* Encoder is about to be reset so note that as far as we're
1528 concerned now, the encoder has never been run. */
1529 del_timer_sync(&hdw->encoder_run_timer);
1530 if (hdw->state_encoder_runok) {
1531 hdw->state_encoder_runok = 0;
1532 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1535 /* First prepare firmware loading */
1536 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1537 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1538 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1539 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1540 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1541 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1542 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1543 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1544 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1545 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1546 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1547 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1548 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1549 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1550 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1551 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1552 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1553 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1556 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1557 "firmware2 upload prep failed, ret=%d",ret);
1558 release_firmware(fw_entry);
1562 /* Now send firmware */
1564 fw_len = fw_entry->size;
1566 if (fw_len % sizeof(u32)) {
1567 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1568 "size of %s firmware"
1569 " must be a multiple of %zu bytes",
1570 fw_files[fwidx],sizeof(u32));
1571 release_firmware(fw_entry);
1576 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1577 if (fw_ptr == NULL){
1578 release_firmware(fw_entry);
1579 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1580 "failed to allocate memory for firmware2 upload");
1585 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1588 for (fw_done = 0; fw_done < fw_len;) {
1589 bcnt = fw_len - fw_done;
1590 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1591 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1592 /* Usbsnoop log shows that we must swap bytes... */
1593 /* Some background info: The data being swapped here is a
1594 firmware image destined for the mpeg encoder chip that
1595 lives at the other end of a USB endpoint. The encoder
1596 chip always talks in 32 bit chunks and its storage is
1597 organized into 32 bit words. However from the file
1598 system to the encoder chip everything is purely a byte
1599 stream. The firmware file's contents are always 32 bit
1600 swapped from what the encoder expects. Thus the need
1601 always exists to swap the bytes regardless of the endian
1602 type of the host processor and therefore swab32() makes
1604 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1605 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1607 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1608 &actual_length, HZ);
1609 ret |= (actual_length != bcnt);
1614 trace_firmware("upload of %s : %i / %i ",
1615 fw_files[fwidx],fw_done,fw_len);
1618 release_firmware(fw_entry);
1621 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1622 "firmware2 upload transfer failure");
1628 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1629 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1630 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1633 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1634 "firmware2 upload post-proc failure");
1638 if (hdw->hdw_desc->signal_routing_scheme ==
1639 PVR2_ROUTING_SCHEME_GOTVIEW) {
1640 /* Ensure that GPIO 11 is set to output for GOTVIEW
1642 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1648 static const char *pvr2_get_state_name(unsigned int st)
1650 if (st < ARRAY_SIZE(pvr2_state_names)) {
1651 return pvr2_state_names[st];
1656 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1658 if (!hdw->decoder_ctrl) {
1659 if (!hdw->flag_decoder_missed) {
1660 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1661 "WARNING: No decoder present");
1662 hdw->flag_decoder_missed = !0;
1663 trace_stbit("flag_decoder_missed",
1664 hdw->flag_decoder_missed);
1668 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1673 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1675 if (hdw->decoder_ctrl == ptr) return;
1676 hdw->decoder_ctrl = ptr;
1677 if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1678 hdw->flag_decoder_missed = 0;
1679 trace_stbit("flag_decoder_missed",
1680 hdw->flag_decoder_missed);
1681 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1682 "Decoder has appeared");
1683 pvr2_hdw_state_sched(hdw);
1688 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1690 return hdw->master_state;
1694 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1696 if (!hdw->flag_tripped) return 0;
1697 hdw->flag_tripped = 0;
1698 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1699 "Clearing driver error statuss");
1704 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1707 LOCK_TAKE(hdw->big_lock); do {
1708 fl = pvr2_hdw_untrip_unlocked(hdw);
1709 } while (0); LOCK_GIVE(hdw->big_lock);
1710 if (fl) pvr2_hdw_state_sched(hdw);
1717 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1719 return hdw->state_pipeline_req != 0;
1723 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1726 LOCK_TAKE(hdw->big_lock); do {
1727 pvr2_hdw_untrip_unlocked(hdw);
1728 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1729 hdw->state_pipeline_req = enable_flag != 0;
1730 pvr2_trace(PVR2_TRACE_START_STOP,
1731 "/*--TRACE_STREAM--*/ %s",
1732 enable_flag ? "enable" : "disable");
1734 pvr2_hdw_state_sched(hdw);
1735 } while (0); LOCK_GIVE(hdw->big_lock);
1736 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1738 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1739 if (st != PVR2_STATE_READY) return -EIO;
1740 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1747 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1750 LOCK_TAKE(hdw->big_lock);
1751 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1752 hdw->desired_stream_type = config;
1753 hdw->state_pipeline_config = 0;
1754 trace_stbit("state_pipeline_config",
1755 hdw->state_pipeline_config);
1756 pvr2_hdw_state_sched(hdw);
1758 LOCK_GIVE(hdw->big_lock);
1760 return pvr2_hdw_wait(hdw,0);
1764 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1766 int unit_number = hdw->unit_number;
1768 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1769 tp = tuner[unit_number];
1771 if (tp < 0) return -EINVAL;
1772 hdw->tuner_type = tp;
1773 hdw->tuner_updated = !0;
1778 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1780 int unit_number = hdw->unit_number;
1782 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1783 tp = video_std[unit_number];
1790 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1792 int unit_number = hdw->unit_number;
1794 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1795 tp = tolerance[unit_number];
1801 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1803 /* Try a harmless request to fetch the eeprom's address over
1804 endpoint 1. See what happens. Only the full FX2 image can
1805 respond to this. If this probe fails then likely the FX2
1806 firmware needs be loaded. */
1808 LOCK_TAKE(hdw->ctl_lock); do {
1809 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1810 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1813 if (result < 0) break;
1814 } while(0); LOCK_GIVE(hdw->ctl_lock);
1816 pvr2_trace(PVR2_TRACE_INIT,
1817 "Probe of device endpoint 1 result status %d",
1820 pvr2_trace(PVR2_TRACE_INIT,
1821 "Probe of device endpoint 1 succeeded");
1826 struct pvr2_std_hack {
1827 v4l2_std_id pat; /* Pattern to match */
1828 v4l2_std_id msk; /* Which bits we care about */
1829 v4l2_std_id std; /* What additional standards or default to set */
1832 /* This data structure labels specific combinations of standards from
1833 tveeprom that we'll try to recognize. If we recognize one, then assume
1834 a specified default standard to use. This is here because tveeprom only
1835 tells us about available standards not the intended default standard (if
1836 any) for the device in question. We guess the default based on what has
1837 been reported as available. Note that this is only for guessing a
1838 default - which can always be overridden explicitly - and if the user
1839 has otherwise named a default then that default will always be used in
1840 place of this table. */
1841 static const struct pvr2_std_hack std_eeprom_maps[] = {
1843 .pat = V4L2_STD_B|V4L2_STD_GH,
1844 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1848 .std = V4L2_STD_NTSC_M,
1851 .pat = V4L2_STD_PAL_I,
1852 .std = V4L2_STD_PAL_I,
1855 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1856 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1860 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1864 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1868 v4l2_std_id std1,std2,std3;
1870 std1 = get_default_standard(hdw);
1871 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1873 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1874 pvr2_trace(PVR2_TRACE_STD,
1875 "Supported video standard(s) reported available"
1876 " in hardware: %.*s",
1879 hdw->std_mask_avail = hdw->std_mask_eeprom;
1881 std2 = (std1|std3) & ~hdw->std_mask_avail;
1883 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1884 pvr2_trace(PVR2_TRACE_STD,
1885 "Expanding supported video standards"
1886 " to include: %.*s",
1888 hdw->std_mask_avail |= std2;
1891 pvr2_hdw_internal_set_std_avail(hdw);
1894 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1895 pvr2_trace(PVR2_TRACE_STD,
1896 "Initial video standard forced to %.*s",
1898 hdw->std_mask_cur = std1;
1899 hdw->std_dirty = !0;
1900 pvr2_hdw_internal_find_stdenum(hdw);
1904 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1905 pvr2_trace(PVR2_TRACE_STD,
1906 "Initial video standard"
1907 " (determined by device type): %.*s",bcnt,buf);
1908 hdw->std_mask_cur = std3;
1909 hdw->std_dirty = !0;
1910 pvr2_hdw_internal_find_stdenum(hdw);
1916 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1917 if (std_eeprom_maps[idx].msk ?
1918 ((std_eeprom_maps[idx].pat ^
1919 hdw->std_mask_eeprom) &
1920 std_eeprom_maps[idx].msk) :
1921 (std_eeprom_maps[idx].pat !=
1922 hdw->std_mask_eeprom)) continue;
1923 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1924 std_eeprom_maps[idx].std);
1925 pvr2_trace(PVR2_TRACE_STD,
1926 "Initial video standard guessed as %.*s",
1928 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1929 hdw->std_dirty = !0;
1930 pvr2_hdw_internal_find_stdenum(hdw);
1935 if (hdw->std_enum_cnt > 1) {
1936 // Autoselect the first listed standard
1937 hdw->std_enum_cur = 1;
1938 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1939 hdw->std_dirty = !0;
1940 pvr2_trace(PVR2_TRACE_STD,
1941 "Initial video standard auto-selected to %s",
1942 hdw->std_defs[hdw->std_enum_cur-1].name);
1946 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1947 "Unable to select a viable initial video standard");
1951 static unsigned int pvr2_copy_i2c_addr_list(
1952 unsigned short *dst, const unsigned char *src,
1953 unsigned int dst_max)
1957 while (src[cnt] && (cnt + 1) < dst_max) {
1958 dst[cnt] = src[cnt];
1961 dst[cnt] = I2C_CLIENT_END;
1966 static void pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1967 const struct pvr2_device_client_desc *cd)
1971 struct v4l2_subdev *sd;
1972 unsigned int i2ccnt;
1973 const unsigned char *p;
1974 /* Arbitrary count - max # i2c addresses we will probe */
1975 unsigned short i2caddr[25];
1977 mid = cd->module_id;
1978 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
1980 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1981 "Module ID %u for device %s is unknown"
1982 " (this is probably a bad thing...)",
1984 hdw->hdw_desc->description);
1988 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
1989 ARRAY_SIZE(i2caddr));
1990 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
1991 module_i2c_addresses[mid] : NULL) != NULL)) {
1992 /* Second chance: Try default i2c address list */
1993 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
1994 ARRAY_SIZE(i2caddr));
1998 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1999 "Module ID %u for device %s:"
2001 " (this is probably a bad thing...)",
2002 mid, hdw->hdw_desc->description);
2006 /* Note how the 2nd and 3rd arguments are the same for both
2007 * v4l2_i2c_new_subdev() and v4l2_i2c_new_probed_subdev(). Why?
2008 * Well the 2nd argument is the module name to load, while the 3rd
2009 * argument is documented in the framework as being the "chipid" -
2010 * and every other place where I can find examples of this, the
2011 * "chipid" appears to just be the module name again. So here we
2012 * just do the same thing. */
2014 sd = v4l2_i2c_new_subdev(&hdw->i2c_adap,
2018 sd = v4l2_i2c_new_probed_subdev(&hdw->i2c_adap,
2024 /* Based on module ID, we should remember subdev pointers
2025 so that we can send certain custom commands where
2032 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2035 const struct pvr2_string_table *cm;
2036 const struct pvr2_device_client_table *ct;
2038 cm = &hdw->hdw_desc->client_modules;
2039 for (idx = 0; idx < cm->cnt; idx++) {
2040 request_module(cm->lst[idx]);
2043 ct = &hdw->hdw_desc->client_table;
2044 for (idx = 0; idx < ct->cnt; idx++) {
2045 pvr2_hdw_load_subdev(hdw,&ct->lst[idx]);
2050 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2054 struct pvr2_ctrl *cptr;
2056 if (hdw->hdw_desc->fx2_firmware.cnt) {
2059 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2062 pvr2_trace(PVR2_TRACE_INIT,
2063 "USB endpoint config looks strange"
2064 "; possibly firmware needs to be"
2069 reloadFl = !pvr2_hdw_check_firmware(hdw);
2071 pvr2_trace(PVR2_TRACE_INIT,
2072 "Check for FX2 firmware failed"
2073 "; possibly firmware needs to be"
2078 if (pvr2_upload_firmware1(hdw) != 0) {
2079 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2080 "Failure uploading firmware1");
2085 hdw->fw1_state = FW1_STATE_OK;
2087 if (!pvr2_hdw_dev_ok(hdw)) return;
2089 if (!hdw->hdw_desc->flag_no_powerup) {
2090 pvr2_hdw_cmd_powerup(hdw);
2091 if (!pvr2_hdw_dev_ok(hdw)) return;
2094 /* Take the IR chip out of reset, if appropriate */
2095 if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
2096 pvr2_issue_simple_cmd(hdw,
2097 FX2CMD_HCW_ZILOG_RESET |
2102 // This step MUST happen after the earlier powerup step.
2103 pvr2_i2c_track_init(hdw);
2104 pvr2_i2c_core_init(hdw);
2105 if (!pvr2_hdw_dev_ok(hdw)) return;
2107 pvr2_hdw_load_modules(hdw);
2109 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2110 cptr = hdw->controls + idx;
2111 if (cptr->info->skip_init) continue;
2112 if (!cptr->info->set_value) continue;
2113 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2116 /* Set up special default values for the television and radio
2117 frequencies here. It's not really important what these defaults
2118 are, but I set them to something usable in the Chicago area just
2119 to make driver testing a little easier. */
2121 hdw->freqValTelevision = default_tv_freq;
2122 hdw->freqValRadio = default_radio_freq;
2124 // Do not use pvr2_reset_ctl_endpoints() here. It is not
2125 // thread-safe against the normal pvr2_send_request() mechanism.
2126 // (We should make it thread safe).
2128 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2129 ret = pvr2_hdw_get_eeprom_addr(hdw);
2130 if (!pvr2_hdw_dev_ok(hdw)) return;
2132 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2133 "Unable to determine location of eeprom,"
2136 hdw->eeprom_addr = ret;
2137 pvr2_eeprom_analyze(hdw);
2138 if (!pvr2_hdw_dev_ok(hdw)) return;
2141 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2142 hdw->tuner_updated = !0;
2143 hdw->std_mask_eeprom = V4L2_STD_ALL;
2146 if (hdw->serial_number) {
2147 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2148 "sn-%lu", hdw->serial_number);
2149 } else if (hdw->unit_number >= 0) {
2150 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2152 hdw->unit_number + 'a');
2154 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2157 hdw->identifier[idx] = 0;
2159 pvr2_hdw_setup_std(hdw);
2161 if (!get_default_tuner_type(hdw)) {
2162 pvr2_trace(PVR2_TRACE_INIT,
2163 "pvr2_hdw_setup: Tuner type overridden to %d",
2167 pvr2_i2c_core_check_stale(hdw);
2168 hdw->tuner_updated = 0;
2170 if (!pvr2_hdw_dev_ok(hdw)) return;
2172 if (hdw->hdw_desc->signal_routing_scheme ==
2173 PVR2_ROUTING_SCHEME_GOTVIEW) {
2174 /* Ensure that GPIO 11 is set to output for GOTVIEW
2176 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2179 pvr2_hdw_commit_setup(hdw);
2181 hdw->vid_stream = pvr2_stream_create();
2182 if (!pvr2_hdw_dev_ok(hdw)) return;
2183 pvr2_trace(PVR2_TRACE_INIT,
2184 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2185 if (hdw->vid_stream) {
2186 idx = get_default_error_tolerance(hdw);
2188 pvr2_trace(PVR2_TRACE_INIT,
2189 "pvr2_hdw_setup: video stream %p"
2190 " setting tolerance %u",
2191 hdw->vid_stream,idx);
2193 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2194 PVR2_VID_ENDPOINT,idx);
2197 if (!pvr2_hdw_dev_ok(hdw)) return;
2199 hdw->flag_init_ok = !0;
2201 pvr2_hdw_state_sched(hdw);
2205 /* Set up the structure and attempt to put the device into a usable state.
2206 This can be a time-consuming operation, which is why it is not done
2207 internally as part of the create() step. */
2208 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2210 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2212 pvr2_hdw_setup_low(hdw);
2213 pvr2_trace(PVR2_TRACE_INIT,
2214 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2215 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2216 if (pvr2_hdw_dev_ok(hdw)) {
2217 if (hdw->flag_init_ok) {
2220 "Device initialization"
2221 " completed successfully.");
2224 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2227 "Device microcontroller firmware"
2228 " (re)loaded; it should now reset"
2233 PVR2_TRACE_ERROR_LEGS,
2234 "Device initialization was not successful.");
2235 if (hdw->fw1_state == FW1_STATE_MISSING) {
2237 PVR2_TRACE_ERROR_LEGS,
2238 "Giving up since device"
2239 " microcontroller firmware"
2240 " appears to be missing.");
2246 PVR2_TRACE_ERROR_LEGS,
2247 "Attempting pvrusb2 recovery by reloading"
2248 " primary firmware.");
2250 PVR2_TRACE_ERROR_LEGS,
2251 "If this works, device should disconnect"
2252 " and reconnect in a sane state.");
2253 hdw->fw1_state = FW1_STATE_UNKNOWN;
2254 pvr2_upload_firmware1(hdw);
2257 PVR2_TRACE_ERROR_LEGS,
2258 "***WARNING*** pvrusb2 device hardware"
2259 " appears to be jammed"
2260 " and I can't clear it.");
2262 PVR2_TRACE_ERROR_LEGS,
2263 "You might need to power cycle"
2264 " the pvrusb2 device"
2265 " in order to recover.");
2268 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2272 /* Perform second stage initialization. Set callback pointer first so that
2273 we can avoid a possible initialization race (if the kernel thread runs
2274 before the callback has been set). */
2275 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2276 void (*callback_func)(void *),
2277 void *callback_data)
2279 LOCK_TAKE(hdw->big_lock); do {
2280 if (hdw->flag_disconnected) {
2281 /* Handle a race here: If we're already
2282 disconnected by this point, then give up. If we
2283 get past this then we'll remain connected for
2284 the duration of initialization since the entire
2285 initialization sequence is now protected by the
2289 hdw->state_data = callback_data;
2290 hdw->state_func = callback_func;
2291 pvr2_hdw_setup(hdw);
2292 } while (0); LOCK_GIVE(hdw->big_lock);
2293 return hdw->flag_init_ok;
2297 /* Create, set up, and return a structure for interacting with the
2298 underlying hardware. */
2299 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2300 const struct usb_device_id *devid)
2302 unsigned int idx,cnt1,cnt2,m;
2303 struct pvr2_hdw *hdw = NULL;
2305 struct pvr2_ctrl *cptr;
2306 struct usb_device *usb_dev;
2307 const struct pvr2_device_desc *hdw_desc;
2309 struct v4l2_queryctrl qctrl;
2310 struct pvr2_ctl_info *ciptr;
2312 usb_dev = interface_to_usbdev(intf);
2314 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2316 if (hdw_desc == NULL) {
2317 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2318 " No device description pointer,"
2319 " unable to continue.");
2320 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2321 " please contact Mike Isely <isely@pobox.com>"
2322 " to get it included in the driver\n");
2326 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2327 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2328 hdw,hdw_desc->description);
2329 if (!hdw) goto fail;
2331 init_timer(&hdw->quiescent_timer);
2332 hdw->quiescent_timer.data = (unsigned long)hdw;
2333 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2335 init_timer(&hdw->encoder_wait_timer);
2336 hdw->encoder_wait_timer.data = (unsigned long)hdw;
2337 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2339 init_timer(&hdw->encoder_run_timer);
2340 hdw->encoder_run_timer.data = (unsigned long)hdw;
2341 hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2343 hdw->master_state = PVR2_STATE_DEAD;
2345 init_waitqueue_head(&hdw->state_wait_data);
2347 hdw->tuner_signal_stale = !0;
2348 cx2341x_fill_defaults(&hdw->enc_ctl_state);
2350 /* Calculate which inputs are OK */
2352 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2353 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2354 m |= 1 << PVR2_CVAL_INPUT_DTV;
2356 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2357 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2358 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2359 hdw->input_avail_mask = m;
2360 hdw->input_allowed_mask = hdw->input_avail_mask;
2362 /* If not a hybrid device, pathway_state never changes. So
2363 initialize it here to what it should forever be. */
2364 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2365 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2366 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2367 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2370 hdw->control_cnt = CTRLDEF_COUNT;
2371 hdw->control_cnt += MPEGDEF_COUNT;
2372 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2374 if (!hdw->controls) goto fail;
2375 hdw->hdw_desc = hdw_desc;
2376 for (idx = 0; idx < hdw->control_cnt; idx++) {
2377 cptr = hdw->controls + idx;
2380 for (idx = 0; idx < 32; idx++) {
2381 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2383 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2384 cptr = hdw->controls + idx;
2385 cptr->info = control_defs+idx;
2388 /* Ensure that default input choice is a valid one. */
2389 m = hdw->input_avail_mask;
2390 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2391 if (!((1 << idx) & m)) continue;
2392 hdw->input_val = idx;
2396 /* Define and configure additional controls from cx2341x module. */
2397 hdw->mpeg_ctrl_info = kzalloc(
2398 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2399 if (!hdw->mpeg_ctrl_info) goto fail;
2400 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2401 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2402 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2403 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2404 ciptr->name = mpeg_ids[idx].strid;
2405 ciptr->v4l_id = mpeg_ids[idx].id;
2406 ciptr->skip_init = !0;
2407 ciptr->get_value = ctrl_cx2341x_get;
2408 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2409 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2410 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2411 qctrl.id = ciptr->v4l_id;
2412 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2413 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2414 ciptr->set_value = ctrl_cx2341x_set;
2416 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2417 PVR2_CTLD_INFO_DESC_SIZE);
2418 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2419 ciptr->default_value = qctrl.default_value;
2420 switch (qctrl.type) {
2422 case V4L2_CTRL_TYPE_INTEGER:
2423 ciptr->type = pvr2_ctl_int;
2424 ciptr->def.type_int.min_value = qctrl.minimum;
2425 ciptr->def.type_int.max_value = qctrl.maximum;
2427 case V4L2_CTRL_TYPE_BOOLEAN:
2428 ciptr->type = pvr2_ctl_bool;
2430 case V4L2_CTRL_TYPE_MENU:
2431 ciptr->type = pvr2_ctl_enum;
2432 ciptr->def.type_enum.value_names =
2433 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2436 ciptr->def.type_enum.value_names[cnt1] != NULL;
2438 ciptr->def.type_enum.count = cnt1;
2444 // Initialize video standard enum dynamic control
2445 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2447 memcpy(&hdw->std_info_enum,cptr->info,
2448 sizeof(hdw->std_info_enum));
2449 cptr->info = &hdw->std_info_enum;
2452 // Initialize control data regarding video standard masks
2453 valid_std_mask = pvr2_std_get_usable();
2454 for (idx = 0; idx < 32; idx++) {
2455 if (!(valid_std_mask & (1 << idx))) continue;
2456 cnt1 = pvr2_std_id_to_str(
2457 hdw->std_mask_names[idx],
2458 sizeof(hdw->std_mask_names[idx])-1,
2460 hdw->std_mask_names[idx][cnt1] = 0;
2462 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2464 memcpy(&hdw->std_info_avail,cptr->info,
2465 sizeof(hdw->std_info_avail));
2466 cptr->info = &hdw->std_info_avail;
2467 hdw->std_info_avail.def.type_bitmask.bit_names =
2469 hdw->std_info_avail.def.type_bitmask.valid_bits =
2472 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2474 memcpy(&hdw->std_info_cur,cptr->info,
2475 sizeof(hdw->std_info_cur));
2476 cptr->info = &hdw->std_info_cur;
2477 hdw->std_info_cur.def.type_bitmask.bit_names =
2479 hdw->std_info_avail.def.type_bitmask.valid_bits =
2483 hdw->cropcap_stale = !0;
2484 hdw->eeprom_addr = -1;
2485 hdw->unit_number = -1;
2486 hdw->v4l_minor_number_video = -1;
2487 hdw->v4l_minor_number_vbi = -1;
2488 hdw->v4l_minor_number_radio = -1;
2489 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2490 if (!hdw->ctl_write_buffer) goto fail;
2491 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2492 if (!hdw->ctl_read_buffer) goto fail;
2493 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2494 if (!hdw->ctl_write_urb) goto fail;
2495 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2496 if (!hdw->ctl_read_urb) goto fail;
2498 if (v4l2_device_register(&usb_dev->dev, &hdw->v4l2_dev) != 0) {
2499 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2500 "Error registering with v4l core, giving up");
2503 mutex_lock(&pvr2_unit_mtx); do {
2504 for (idx = 0; idx < PVR_NUM; idx++) {
2505 if (unit_pointers[idx]) continue;
2506 hdw->unit_number = idx;
2507 unit_pointers[idx] = hdw;
2510 } while (0); mutex_unlock(&pvr2_unit_mtx);
2513 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2515 if (hdw->unit_number >= 0) {
2516 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2517 ('a' + hdw->unit_number));
2520 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2521 hdw->name[cnt1] = 0;
2523 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2524 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2525 INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2527 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2528 hdw->unit_number,hdw->name);
2530 hdw->tuner_type = -1;
2533 hdw->usb_intf = intf;
2534 hdw->usb_dev = usb_dev;
2536 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2538 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2539 usb_set_interface(hdw->usb_dev,ifnum,0);
2541 mutex_init(&hdw->ctl_lock_mutex);
2542 mutex_init(&hdw->big_lock_mutex);
2547 del_timer_sync(&hdw->quiescent_timer);
2548 del_timer_sync(&hdw->encoder_run_timer);
2549 del_timer_sync(&hdw->encoder_wait_timer);
2550 if (hdw->workqueue) {
2551 flush_workqueue(hdw->workqueue);
2552 destroy_workqueue(hdw->workqueue);
2553 hdw->workqueue = NULL;
2555 usb_free_urb(hdw->ctl_read_urb);
2556 usb_free_urb(hdw->ctl_write_urb);
2557 kfree(hdw->ctl_read_buffer);
2558 kfree(hdw->ctl_write_buffer);
2559 kfree(hdw->controls);
2560 kfree(hdw->mpeg_ctrl_info);
2561 kfree(hdw->std_defs);
2562 kfree(hdw->std_enum_names);
2569 /* Remove _all_ associations between this driver and the underlying USB
2571 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2573 if (hdw->flag_disconnected) return;
2574 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2575 if (hdw->ctl_read_urb) {
2576 usb_kill_urb(hdw->ctl_read_urb);
2577 usb_free_urb(hdw->ctl_read_urb);
2578 hdw->ctl_read_urb = NULL;
2580 if (hdw->ctl_write_urb) {
2581 usb_kill_urb(hdw->ctl_write_urb);
2582 usb_free_urb(hdw->ctl_write_urb);
2583 hdw->ctl_write_urb = NULL;
2585 if (hdw->ctl_read_buffer) {
2586 kfree(hdw->ctl_read_buffer);
2587 hdw->ctl_read_buffer = NULL;
2589 if (hdw->ctl_write_buffer) {
2590 kfree(hdw->ctl_write_buffer);
2591 hdw->ctl_write_buffer = NULL;
2593 hdw->flag_disconnected = !0;
2594 /* If we don't do this, then there will be a dangling struct device
2595 reference to our disappearing device persisting inside the V4L
2597 if (hdw->v4l2_dev.dev) {
2598 dev_set_drvdata(hdw->v4l2_dev.dev, NULL);
2599 hdw->v4l2_dev.dev = NULL;
2601 hdw->usb_dev = NULL;
2602 hdw->usb_intf = NULL;
2603 pvr2_hdw_render_useless(hdw);
2607 /* Destroy hardware interaction structure */
2608 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2611 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2612 if (hdw->workqueue) {
2613 flush_workqueue(hdw->workqueue);
2614 destroy_workqueue(hdw->workqueue);
2615 hdw->workqueue = NULL;
2617 del_timer_sync(&hdw->quiescent_timer);
2618 del_timer_sync(&hdw->encoder_run_timer);
2619 del_timer_sync(&hdw->encoder_wait_timer);
2620 if (hdw->fw_buffer) {
2621 kfree(hdw->fw_buffer);
2622 hdw->fw_buffer = NULL;
2624 if (hdw->vid_stream) {
2625 pvr2_stream_destroy(hdw->vid_stream);
2626 hdw->vid_stream = NULL;
2628 if (hdw->decoder_ctrl) {
2629 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2631 pvr2_i2c_core_done(hdw);
2632 pvr2_i2c_track_done(hdw);
2633 v4l2_device_unregister(&hdw->v4l2_dev);
2634 pvr2_hdw_remove_usb_stuff(hdw);
2635 mutex_lock(&pvr2_unit_mtx); do {
2636 if ((hdw->unit_number >= 0) &&
2637 (hdw->unit_number < PVR_NUM) &&
2638 (unit_pointers[hdw->unit_number] == hdw)) {
2639 unit_pointers[hdw->unit_number] = NULL;
2641 } while (0); mutex_unlock(&pvr2_unit_mtx);
2642 kfree(hdw->controls);
2643 kfree(hdw->mpeg_ctrl_info);
2644 kfree(hdw->std_defs);
2645 kfree(hdw->std_enum_names);
2650 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2652 return (hdw && hdw->flag_ok);
2656 /* Called when hardware has been unplugged */
2657 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2659 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2660 LOCK_TAKE(hdw->big_lock);
2661 LOCK_TAKE(hdw->ctl_lock);
2662 pvr2_hdw_remove_usb_stuff(hdw);
2663 LOCK_GIVE(hdw->ctl_lock);
2664 LOCK_GIVE(hdw->big_lock);
2668 // Attempt to autoselect an appropriate value for std_enum_cur given
2669 // whatever is currently in std_mask_cur
2670 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2673 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2674 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2675 hdw->std_enum_cur = idx;
2679 hdw->std_enum_cur = 0;
2683 // Calculate correct set of enumerated standards based on currently known
2684 // set of available standards bits.
2685 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2687 struct v4l2_standard *newstd;
2688 unsigned int std_cnt;
2691 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2693 if (hdw->std_defs) {
2694 kfree(hdw->std_defs);
2695 hdw->std_defs = NULL;
2697 hdw->std_enum_cnt = 0;
2698 if (hdw->std_enum_names) {
2699 kfree(hdw->std_enum_names);
2700 hdw->std_enum_names = NULL;
2705 PVR2_TRACE_ERROR_LEGS,
2706 "WARNING: Failed to identify any viable standards");
2708 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2709 hdw->std_enum_names[0] = "none";
2710 for (idx = 0; idx < std_cnt; idx++) {
2711 hdw->std_enum_names[idx+1] =
2714 // Set up the dynamic control for this standard
2715 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2716 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2717 hdw->std_defs = newstd;
2718 hdw->std_enum_cnt = std_cnt+1;
2719 hdw->std_enum_cur = 0;
2720 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2724 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2725 struct v4l2_standard *std,
2729 if (!idx) return ret;
2730 LOCK_TAKE(hdw->big_lock); do {
2731 if (idx >= hdw->std_enum_cnt) break;
2733 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2735 } while (0); LOCK_GIVE(hdw->big_lock);
2740 /* Get the number of defined controls */
2741 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2743 return hdw->control_cnt;
2747 /* Retrieve a control handle given its index (0..count-1) */
2748 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2751 if (idx >= hdw->control_cnt) return NULL;
2752 return hdw->controls + idx;
2756 /* Retrieve a control handle given its index (0..count-1) */
2757 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2758 unsigned int ctl_id)
2760 struct pvr2_ctrl *cptr;
2764 /* This could be made a lot more efficient, but for now... */
2765 for (idx = 0; idx < hdw->control_cnt; idx++) {
2766 cptr = hdw->controls + idx;
2767 i = cptr->info->internal_id;
2768 if (i && (i == ctl_id)) return cptr;
2774 /* Given a V4L ID, retrieve the control structure associated with it. */
2775 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2777 struct pvr2_ctrl *cptr;
2781 /* This could be made a lot more efficient, but for now... */
2782 for (idx = 0; idx < hdw->control_cnt; idx++) {
2783 cptr = hdw->controls + idx;
2784 i = cptr->info->v4l_id;
2785 if (i && (i == ctl_id)) return cptr;
2791 /* Given a V4L ID for its immediate predecessor, retrieve the control
2792 structure associated with it. */
2793 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2794 unsigned int ctl_id)
2796 struct pvr2_ctrl *cptr,*cp2;
2800 /* This could be made a lot more efficient, but for now... */
2802 for (idx = 0; idx < hdw->control_cnt; idx++) {
2803 cptr = hdw->controls + idx;
2804 i = cptr->info->v4l_id;
2806 if (i <= ctl_id) continue;
2807 if (cp2 && (cp2->info->v4l_id < i)) continue;
2815 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2818 case pvr2_ctl_int: return "integer";
2819 case pvr2_ctl_enum: return "enum";
2820 case pvr2_ctl_bool: return "boolean";
2821 case pvr2_ctl_bitmask: return "bitmask";
2827 /* Figure out if we need to commit control changes. If so, mark internal
2828 state flags to indicate this fact and return true. Otherwise do nothing
2829 else and return false. */
2830 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2833 struct pvr2_ctrl *cptr;
2835 int commit_flag = 0;
2837 unsigned int bcnt,ccnt;
2839 for (idx = 0; idx < hdw->control_cnt; idx++) {
2840 cptr = hdw->controls + idx;
2841 if (!cptr->info->is_dirty) continue;
2842 if (!cptr->info->is_dirty(cptr)) continue;
2845 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2846 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2849 cptr->info->get_value(cptr,&value);
2850 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2852 sizeof(buf)-bcnt,&ccnt);
2854 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2855 get_ctrl_typename(cptr->info->type));
2856 pvr2_trace(PVR2_TRACE_CTL,
2857 "/*--TRACE_COMMIT--*/ %.*s",
2862 /* Nothing has changed */
2866 hdw->state_pipeline_config = 0;
2867 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2868 pvr2_hdw_state_sched(hdw);
2874 /* Perform all operations needed to commit all control changes. This must
2875 be performed in synchronization with the pipeline state and is thus
2876 expected to be called as part of the driver's worker thread. Return
2877 true if commit successful, otherwise return false to indicate that
2878 commit isn't possible at this time. */
2879 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
2882 struct pvr2_ctrl *cptr;
2883 int disruptive_change;
2885 /* Handle some required side effects when the video standard is
2887 if (hdw->std_dirty) {
2890 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2897 /* Rewrite the vertical resolution to be appropriate to the
2898 video standard that has been selected. */
2899 if (nvres != hdw->res_ver_val) {
2900 hdw->res_ver_val = nvres;
2901 hdw->res_ver_dirty = !0;
2903 /* Rewrite the GOP size to be appropriate to the video
2904 standard that has been selected. */
2905 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
2906 struct v4l2_ext_controls cs;
2907 struct v4l2_ext_control c1;
2908 memset(&cs, 0, sizeof(cs));
2909 memset(&c1, 0, sizeof(c1));
2912 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
2913 c1.value = gop_size;
2914 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
2915 VIDIOC_S_EXT_CTRLS);
2919 if (hdw->input_dirty && hdw->state_pathway_ok &&
2920 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
2921 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
2922 hdw->pathway_state)) {
2923 /* Change of mode being asked for... */
2924 hdw->state_pathway_ok = 0;
2925 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
2927 if (!hdw->state_pathway_ok) {
2928 /* Can't commit anything until pathway is ok. */
2931 /* The broadcast decoder can only scale down, so if
2932 * res_*_dirty && crop window < output format ==> enlarge crop.
2934 * The mpeg encoder receives fields of res_hor_val dots and
2935 * res_ver_val halflines. Limits: hor<=720, ver<=576.
2937 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
2938 hdw->cropw_val = hdw->res_hor_val;
2939 hdw->cropw_dirty = !0;
2940 } else if (hdw->cropw_dirty) {
2941 hdw->res_hor_dirty = !0; /* must rescale */
2942 hdw->res_hor_val = min(720, hdw->cropw_val);
2944 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
2945 hdw->croph_val = hdw->res_ver_val;
2946 hdw->croph_dirty = !0;
2947 } else if (hdw->croph_dirty) {
2948 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
2949 hdw->res_ver_dirty = !0;
2950 hdw->res_ver_val = min(nvres, hdw->croph_val);
2953 /* If any of the below has changed, then we can't do the update
2954 while the pipeline is running. Pipeline must be paused first
2955 and decoder -> encoder connection be made quiescent before we
2959 hdw->enc_unsafe_stale ||
2961 hdw->res_ver_dirty ||
2962 hdw->res_hor_dirty ||
2966 (hdw->active_stream_type != hdw->desired_stream_type));
2967 if (disruptive_change && !hdw->state_pipeline_idle) {
2968 /* Pipeline is not idle; we can't proceed. Arrange to
2969 cause pipeline to stop so that we can try this again
2971 hdw->state_pipeline_pause = !0;
2975 if (hdw->srate_dirty) {
2976 /* Write new sample rate into control structure since
2977 * the master copy is stale. We must track srate
2978 * separate from the mpeg control structure because
2979 * other logic also uses this value. */
2980 struct v4l2_ext_controls cs;
2981 struct v4l2_ext_control c1;
2982 memset(&cs,0,sizeof(cs));
2983 memset(&c1,0,sizeof(c1));
2986 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2987 c1.value = hdw->srate_val;
2988 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
2991 /* Scan i2c core at this point - before we clear all the dirty
2992 bits. Various parts of the i2c core will notice dirty bits as
2993 appropriate and arrange to broadcast or directly send updates to
2994 the client drivers in order to keep everything in sync */
2995 pvr2_i2c_core_check_stale(hdw);
2997 for (idx = 0; idx < hdw->control_cnt; idx++) {
2998 cptr = hdw->controls + idx;
2999 if (!cptr->info->clear_dirty) continue;
3000 cptr->info->clear_dirty(cptr);
3003 if (hdw->active_stream_type != hdw->desired_stream_type) {
3004 /* Handle any side effects of stream config here */
3005 hdw->active_stream_type = hdw->desired_stream_type;
3008 if (hdw->hdw_desc->signal_routing_scheme ==
3009 PVR2_ROUTING_SCHEME_GOTVIEW) {
3011 /* Handle GOTVIEW audio switching */
3012 pvr2_hdw_gpio_get_out(hdw,&b);
3013 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3015 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3018 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3022 /* Now execute i2c core update */
3023 pvr2_i2c_core_sync(hdw);
3025 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3026 hdw->state_encoder_run) {
3027 /* If encoder isn't running or it can't be touched, then
3028 this will get worked out later when we start the
3030 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3033 hdw->state_pipeline_config = !0;
3034 /* Hardware state may have changed in a way to cause the cropping
3035 capabilities to have changed. So mark it stale, which will
3036 cause a later re-fetch. */
3037 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3042 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3045 LOCK_TAKE(hdw->big_lock);
3046 fl = pvr2_hdw_commit_setup(hdw);
3047 LOCK_GIVE(hdw->big_lock);
3049 return pvr2_hdw_wait(hdw,0);
3053 static void pvr2_hdw_worker_i2c(struct work_struct *work)
3055 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
3056 LOCK_TAKE(hdw->big_lock); do {
3057 pvr2_i2c_core_sync(hdw);
3058 } while (0); LOCK_GIVE(hdw->big_lock);
3062 static void pvr2_hdw_worker_poll(struct work_struct *work)
3065 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3066 LOCK_TAKE(hdw->big_lock); do {
3067 fl = pvr2_hdw_state_eval(hdw);
3068 } while (0); LOCK_GIVE(hdw->big_lock);
3069 if (fl && hdw->state_func) {
3070 hdw->state_func(hdw->state_data);
3075 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3077 return wait_event_interruptible(
3078 hdw->state_wait_data,
3079 (hdw->state_stale == 0) &&
3080 (!state || (hdw->master_state != state)));
3084 /* Return name for this driver instance */
3085 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3091 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3093 return hdw->hdw_desc->description;
3097 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3099 return hdw->hdw_desc->shortname;
3103 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3106 LOCK_TAKE(hdw->ctl_lock); do {
3107 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3108 result = pvr2_send_request(hdw,
3111 if (result < 0) break;
3112 result = (hdw->cmd_buffer[0] != 0);
3113 } while(0); LOCK_GIVE(hdw->ctl_lock);
3118 /* Execute poll of tuner status */
3119 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3121 LOCK_TAKE(hdw->big_lock); do {
3122 pvr2_hdw_status_poll(hdw);
3123 } while (0); LOCK_GIVE(hdw->big_lock);
3127 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3129 if (!hdw->cropcap_stale) {
3132 pvr2_hdw_status_poll(hdw);
3133 if (hdw->cropcap_stale) {
3140 /* Return information about cropping capabilities */
3141 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3144 LOCK_TAKE(hdw->big_lock);
3145 stat = pvr2_hdw_check_cropcap(hdw);
3147 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3149 LOCK_GIVE(hdw->big_lock);
3154 /* Return information about the tuner */
3155 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3157 LOCK_TAKE(hdw->big_lock); do {
3158 if (hdw->tuner_signal_stale) {
3159 pvr2_hdw_status_poll(hdw);
3161 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3162 } while (0); LOCK_GIVE(hdw->big_lock);
3167 /* Get handle to video output stream */
3168 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3170 return hp->vid_stream;
3174 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3176 int nr = pvr2_hdw_get_unit_number(hdw);
3177 LOCK_TAKE(hdw->big_lock); do {
3178 hdw->log_requested = !0;
3179 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
3180 pvr2_i2c_core_check_stale(hdw);
3181 pvr2_i2c_core_sync(hdw);
3182 hdw->log_requested = 0;
3183 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3184 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3185 pvr2_hdw_state_log_state(hdw);
3186 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
3187 } while (0); LOCK_GIVE(hdw->big_lock);
3191 /* Grab EEPROM contents, needed for direct method. */
3192 #define EEPROM_SIZE 8192
3193 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3194 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3196 struct i2c_msg msg[2];
3205 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3207 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3208 "Failed to allocate memory"
3209 " required to read eeprom");
3213 trace_eeprom("Value for eeprom addr from controller was 0x%x",
3215 addr = hdw->eeprom_addr;
3216 /* Seems that if the high bit is set, then the *real* eeprom
3217 address is shifted right now bit position (noticed this in
3218 newer PVR USB2 hardware) */
3219 if (addr & 0x80) addr >>= 1;
3221 /* FX2 documentation states that a 16bit-addressed eeprom is
3222 expected if the I2C address is an odd number (yeah, this is
3223 strange but it's what they do) */
3224 mode16 = (addr & 1);
3225 eepromSize = (mode16 ? EEPROM_SIZE : 256);
3226 trace_eeprom("Examining %d byte eeprom at location 0x%x"
3227 " using %d bit addressing",eepromSize,addr,
3232 msg[0].len = mode16 ? 2 : 1;
3235 msg[1].flags = I2C_M_RD;
3237 /* We have to do the actual eeprom data fetch ourselves, because
3238 (1) we're only fetching part of the eeprom, and (2) if we were
3239 getting the whole thing our I2C driver can't grab it in one
3240 pass - which is what tveeprom is otherwise going to attempt */
3241 memset(eeprom,0,EEPROM_SIZE);
3242 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3244 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3245 offs = tcnt + (eepromSize - EEPROM_SIZE);
3247 iadd[0] = offs >> 8;
3253 msg[1].buf = eeprom+tcnt;
3254 if ((ret = i2c_transfer(&hdw->i2c_adap,
3255 msg,ARRAY_SIZE(msg))) != 2) {
3256 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3257 "eeprom fetch set offs err=%d",ret);
3266 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3273 LOCK_TAKE(hdw->big_lock); do {
3274 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3277 pvr2_trace(PVR2_TRACE_FIRMWARE,
3278 "Cleaning up after CPU firmware fetch");
3279 kfree(hdw->fw_buffer);
3280 hdw->fw_buffer = NULL;
3282 if (hdw->fw_cpu_flag) {
3283 /* Now release the CPU. It will disconnect
3284 and reconnect later. */
3285 pvr2_hdw_cpureset_assert(hdw,0);
3290 hdw->fw_cpu_flag = (prom_flag == 0);
3291 if (hdw->fw_cpu_flag) {
3292 pvr2_trace(PVR2_TRACE_FIRMWARE,
3293 "Preparing to suck out CPU firmware");
3294 hdw->fw_size = 0x2000;
3295 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3296 if (!hdw->fw_buffer) {
3301 /* We have to hold the CPU during firmware upload. */
3302 pvr2_hdw_cpureset_assert(hdw,1);
3304 /* download the firmware from address 0000-1fff in 2048
3305 (=0x800) bytes chunk. */
3307 pvr2_trace(PVR2_TRACE_FIRMWARE,
3308 "Grabbing CPU firmware");
3309 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3310 for(address = 0; address < hdw->fw_size;
3312 ret = usb_control_msg(hdw->usb_dev,pipe,
3315 hdw->fw_buffer+address,
3320 pvr2_trace(PVR2_TRACE_FIRMWARE,
3321 "Done grabbing CPU firmware");
3323 pvr2_trace(PVR2_TRACE_FIRMWARE,
3324 "Sucking down EEPROM contents");
3325 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3326 if (!hdw->fw_buffer) {
3327 pvr2_trace(PVR2_TRACE_FIRMWARE,
3328 "EEPROM content suck failed.");
3331 hdw->fw_size = EEPROM_SIZE;
3332 pvr2_trace(PVR2_TRACE_FIRMWARE,
3333 "Done sucking down EEPROM contents");
3336 } while (0); LOCK_GIVE(hdw->big_lock);
3340 /* Return true if we're in a mode for retrieval CPU firmware */
3341 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3343 return hdw->fw_buffer != NULL;
3347 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3348 char *buf,unsigned int cnt)
3351 LOCK_TAKE(hdw->big_lock); do {
3355 if (!hdw->fw_buffer) {
3360 if (offs >= hdw->fw_size) {
3361 pvr2_trace(PVR2_TRACE_FIRMWARE,
3362 "Read firmware data offs=%d EOF",
3368 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3370 memcpy(buf,hdw->fw_buffer+offs,cnt);
3372 pvr2_trace(PVR2_TRACE_FIRMWARE,
3373 "Read firmware data offs=%d cnt=%d",
3376 } while (0); LOCK_GIVE(hdw->big_lock);
3382 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3383 enum pvr2_v4l_type index)
3386 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3387 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3388 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3394 /* Store a v4l minor device number */
3395 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3396 enum pvr2_v4l_type index,int v)
3399 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3400 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3401 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
3407 static void pvr2_ctl_write_complete(struct urb *urb)
3409 struct pvr2_hdw *hdw = urb->context;
3410 hdw->ctl_write_pend_flag = 0;
3411 if (hdw->ctl_read_pend_flag) return;
3412 complete(&hdw->ctl_done);
3416 static void pvr2_ctl_read_complete(struct urb *urb)
3418 struct pvr2_hdw *hdw = urb->context;
3419 hdw->ctl_read_pend_flag = 0;
3420 if (hdw->ctl_write_pend_flag) return;
3421 complete(&hdw->ctl_done);
3425 static void pvr2_ctl_timeout(unsigned long data)
3427 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3428 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3429 hdw->ctl_timeout_flag = !0;
3430 if (hdw->ctl_write_pend_flag)
3431 usb_unlink_urb(hdw->ctl_write_urb);
3432 if (hdw->ctl_read_pend_flag)
3433 usb_unlink_urb(hdw->ctl_read_urb);
3438 /* Issue a command and get a response from the device. This extended
3439 version includes a probe flag (which if set means that device errors
3440 should not be logged or treated as fatal) and a timeout in jiffies.
3441 This can be used to non-lethally probe the health of endpoint 1. */
3442 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3443 unsigned int timeout,int probe_fl,
3444 void *write_data,unsigned int write_len,
3445 void *read_data,unsigned int read_len)
3449 struct timer_list timer;
3450 if (!hdw->ctl_lock_held) {
3451 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3452 "Attempted to execute control transfer"
3456 if (!hdw->flag_ok && !probe_fl) {
3457 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3458 "Attempted to execute control transfer"
3459 " when device not ok");
3462 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3464 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3465 "Attempted to execute control transfer"
3466 " when USB is disconnected");
3471 /* Ensure that we have sane parameters */
3472 if (!write_data) write_len = 0;
3473 if (!read_data) read_len = 0;
3474 if (write_len > PVR2_CTL_BUFFSIZE) {
3476 PVR2_TRACE_ERROR_LEGS,
3477 "Attempted to execute %d byte"
3478 " control-write transfer (limit=%d)",
3479 write_len,PVR2_CTL_BUFFSIZE);
3482 if (read_len > PVR2_CTL_BUFFSIZE) {
3484 PVR2_TRACE_ERROR_LEGS,
3485 "Attempted to execute %d byte"
3486 " control-read transfer (limit=%d)",
3487 write_len,PVR2_CTL_BUFFSIZE);
3490 if ((!write_len) && (!read_len)) {
3492 PVR2_TRACE_ERROR_LEGS,
3493 "Attempted to execute null control transfer?");
3498 hdw->cmd_debug_state = 1;
3500 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3502 hdw->cmd_debug_code = 0;
3504 hdw->cmd_debug_write_len = write_len;
3505 hdw->cmd_debug_read_len = read_len;
3507 /* Initialize common stuff */
3508 init_completion(&hdw->ctl_done);
3509 hdw->ctl_timeout_flag = 0;
3510 hdw->ctl_write_pend_flag = 0;
3511 hdw->ctl_read_pend_flag = 0;
3513 timer.expires = jiffies + timeout;
3514 timer.data = (unsigned long)hdw;
3515 timer.function = pvr2_ctl_timeout;
3518 hdw->cmd_debug_state = 2;
3519 /* Transfer write data to internal buffer */
3520 for (idx = 0; idx < write_len; idx++) {
3521 hdw->ctl_write_buffer[idx] =
3522 ((unsigned char *)write_data)[idx];
3524 /* Initiate a write request */
3525 usb_fill_bulk_urb(hdw->ctl_write_urb,
3527 usb_sndbulkpipe(hdw->usb_dev,
3528 PVR2_CTL_WRITE_ENDPOINT),
3529 hdw->ctl_write_buffer,
3531 pvr2_ctl_write_complete,
3533 hdw->ctl_write_urb->actual_length = 0;
3534 hdw->ctl_write_pend_flag = !0;
3535 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3537 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3538 "Failed to submit write-control"
3539 " URB status=%d",status);
3540 hdw->ctl_write_pend_flag = 0;
3546 hdw->cmd_debug_state = 3;
3547 memset(hdw->ctl_read_buffer,0x43,read_len);
3548 /* Initiate a read request */
3549 usb_fill_bulk_urb(hdw->ctl_read_urb,
3551 usb_rcvbulkpipe(hdw->usb_dev,
3552 PVR2_CTL_READ_ENDPOINT),
3553 hdw->ctl_read_buffer,
3555 pvr2_ctl_read_complete,
3557 hdw->ctl_read_urb->actual_length = 0;
3558 hdw->ctl_read_pend_flag = !0;
3559 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3561 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3562 "Failed to submit read-control"
3563 " URB status=%d",status);
3564 hdw->ctl_read_pend_flag = 0;
3572 /* Now wait for all I/O to complete */
3573 hdw->cmd_debug_state = 4;
3574 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3575 wait_for_completion(&hdw->ctl_done);
3577 hdw->cmd_debug_state = 5;
3580 del_timer_sync(&timer);
3582 hdw->cmd_debug_state = 6;
3585 if (hdw->ctl_timeout_flag) {
3586 status = -ETIMEDOUT;
3588 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3589 "Timed out control-write");
3595 /* Validate results of write request */
3596 if ((hdw->ctl_write_urb->status != 0) &&
3597 (hdw->ctl_write_urb->status != -ENOENT) &&
3598 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3599 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3600 /* USB subsystem is reporting some kind of failure
3602 status = hdw->ctl_write_urb->status;
3604 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3605 "control-write URB failure,"
3611 if (hdw->ctl_write_urb->actual_length < write_len) {
3612 /* Failed to write enough data */
3615 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3616 "control-write URB short,"
3617 " expected=%d got=%d",
3619 hdw->ctl_write_urb->actual_length);
3625 /* Validate results of read request */
3626 if ((hdw->ctl_read_urb->status != 0) &&
3627 (hdw->ctl_read_urb->status != -ENOENT) &&
3628 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3629 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3630 /* USB subsystem is reporting some kind of failure
3632 status = hdw->ctl_read_urb->status;
3634 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3635 "control-read URB failure,"
3641 if (hdw->ctl_read_urb->actual_length < read_len) {
3642 /* Failed to read enough data */
3645 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3646 "control-read URB short,"
3647 " expected=%d got=%d",
3649 hdw->ctl_read_urb->actual_length);
3653 /* Transfer retrieved data out from internal buffer */
3654 for (idx = 0; idx < read_len; idx++) {
3655 ((unsigned char *)read_data)[idx] =
3656 hdw->ctl_read_buffer[idx];
3662 hdw->cmd_debug_state = 0;
3663 if ((status < 0) && (!probe_fl)) {
3664 pvr2_hdw_render_useless(hdw);
3670 int pvr2_send_request(struct pvr2_hdw *hdw,
3671 void *write_data,unsigned int write_len,
3672 void *read_data,unsigned int read_len)
3674 return pvr2_send_request_ex(hdw,HZ*4,0,
3675 write_data,write_len,
3676 read_data,read_len);
3680 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3683 unsigned int cnt = 1;
3684 unsigned int args = 0;
3685 LOCK_TAKE(hdw->ctl_lock);
3686 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3687 args = (cmdcode >> 8) & 0xffu;
3688 args = (args > 2) ? 2 : args;
3691 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3693 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3696 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3698 unsigned int ccnt,bcnt;
3702 ccnt = scnprintf(tbuf+bcnt,
3704 "Sending FX2 command 0x%x",cmdcode);
3706 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3707 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3708 ccnt = scnprintf(tbuf+bcnt,
3711 pvr2_fx2cmd_desc[idx].desc);
3717 ccnt = scnprintf(tbuf+bcnt,
3719 " (%u",hdw->cmd_buffer[1]);
3722 ccnt = scnprintf(tbuf+bcnt,
3724 ",%u",hdw->cmd_buffer[2]);
3727 ccnt = scnprintf(tbuf+bcnt,
3732 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3734 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3735 LOCK_GIVE(hdw->ctl_lock);
3740 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3744 LOCK_TAKE(hdw->ctl_lock);
3746 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
3747 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3748 hdw->cmd_buffer[5] = 0;
3749 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3750 hdw->cmd_buffer[7] = reg & 0xff;
3753 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3755 LOCK_GIVE(hdw->ctl_lock);
3761 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3765 LOCK_TAKE(hdw->ctl_lock);
3767 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
3768 hdw->cmd_buffer[1] = 0;
3769 hdw->cmd_buffer[2] = 0;
3770 hdw->cmd_buffer[3] = 0;
3771 hdw->cmd_buffer[4] = 0;
3772 hdw->cmd_buffer[5] = 0;
3773 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3774 hdw->cmd_buffer[7] = reg & 0xff;
3776 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3777 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3779 LOCK_GIVE(hdw->ctl_lock);
3785 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3787 if (!hdw->flag_ok) return;
3788 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3789 "Device being rendered inoperable");
3790 if (hdw->vid_stream) {
3791 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3794 trace_stbit("flag_ok",hdw->flag_ok);
3795 pvr2_hdw_state_sched(hdw);
3799 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3802 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3803 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3805 ret = usb_reset_device(hdw->usb_dev);
3806 usb_unlock_device(hdw->usb_dev);
3808 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3809 "Failed to lock USB device ret=%d",ret);
3811 if (init_pause_msec) {
3812 pvr2_trace(PVR2_TRACE_INFO,
3813 "Waiting %u msec for hardware to settle",
3815 msleep(init_pause_msec);
3821 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3827 if (!hdw->usb_dev) return;
3829 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3831 da[0] = val ? 0x01 : 0x00;
3833 /* Write the CPUCS register on the 8051. The lsb of the register
3834 is the reset bit; a 1 asserts reset while a 0 clears it. */
3835 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3836 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3838 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3839 "cpureset_assert(%d) error=%d",val,ret);
3840 pvr2_hdw_render_useless(hdw);
3845 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3847 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
3851 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3853 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
3857 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
3859 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
3863 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3865 if (!hdw->decoder_ctrl) {
3866 pvr2_trace(PVR2_TRACE_INIT,
3867 "Unable to reset decoder: nothing attached");
3871 if (!hdw->decoder_ctrl->force_reset) {
3872 pvr2_trace(PVR2_TRACE_INIT,
3873 "Unable to reset decoder: not implemented");
3877 pvr2_trace(PVR2_TRACE_INIT,
3878 "Requesting decoder reset");
3879 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3884 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
3887 return pvr2_issue_simple_cmd(hdw,
3888 FX2CMD_HCW_DEMOD_RESETIN |
3890 ((onoff ? 1 : 0) << 16));
3894 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
3897 return pvr2_issue_simple_cmd(hdw,(onoff ?
3898 FX2CMD_ONAIR_DTV_POWER_ON :
3899 FX2CMD_ONAIR_DTV_POWER_OFF));
3903 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
3906 return pvr2_issue_simple_cmd(hdw,(onoff ?
3907 FX2CMD_ONAIR_DTV_STREAMING_ON :
3908 FX2CMD_ONAIR_DTV_STREAMING_OFF));
3912 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
3915 /* Compare digital/analog desired setting with current setting. If
3916 they don't match, fix it... */
3917 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
3918 if (cmode == hdw->pathway_state) {
3919 /* They match; nothing to do */
3923 switch (hdw->hdw_desc->digital_control_scheme) {
3924 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3925 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
3926 if (cmode == PVR2_PATHWAY_ANALOG) {
3927 /* If moving to analog mode, also force the decoder
3928 to reset. If no decoder is attached, then it's
3929 ok to ignore this because if/when the decoder
3930 attaches, it will reset itself at that time. */
3931 pvr2_hdw_cmd_decoder_reset(hdw);
3934 case PVR2_DIGITAL_SCHEME_ONAIR:
3935 /* Supposedly we should always have the power on whether in
3936 digital or analog mode. But for now do what appears to
3938 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
3943 pvr2_hdw_untrip_unlocked(hdw);
3944 hdw->pathway_state = cmode;
3948 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
3950 /* change some GPIO data
3952 * note: bit d7 of dir appears to control the LED,
3953 * so we shut it off here.
3957 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
3959 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
3961 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
3965 typedef void (*led_method_func)(struct pvr2_hdw *,int);
3967 static led_method_func led_methods[] = {
3968 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
3973 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
3975 unsigned int scheme_id;
3978 if ((!onoff) == (!hdw->led_on)) return;
3980 hdw->led_on = onoff != 0;
3982 scheme_id = hdw->hdw_desc->led_scheme;
3983 if (scheme_id < ARRAY_SIZE(led_methods)) {
3984 fp = led_methods[scheme_id];
3989 if (fp) (*fp)(hdw,onoff);
3993 /* Stop / start video stream transport */
3994 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
3998 /* If we're in analog mode, then just issue the usual analog
4000 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4001 return pvr2_issue_simple_cmd(hdw,
4003 FX2CMD_STREAMING_ON :
4004 FX2CMD_STREAMING_OFF));
4005 /*Note: Not reached */
4008 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4009 /* Whoops, we don't know what mode we're in... */
4013 /* To get here we have to be in digital mode. The mechanism here
4014 is unfortunately different for different vendors. So we switch
4015 on the device's digital scheme attribute in order to figure out
4017 switch (hdw->hdw_desc->digital_control_scheme) {
4018 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4019 return pvr2_issue_simple_cmd(hdw,
4021 FX2CMD_HCW_DTV_STREAMING_ON :
4022 FX2CMD_HCW_DTV_STREAMING_OFF));
4023 case PVR2_DIGITAL_SCHEME_ONAIR:
4024 ret = pvr2_issue_simple_cmd(hdw,
4026 FX2CMD_STREAMING_ON :
4027 FX2CMD_STREAMING_OFF));
4028 if (ret) return ret;
4029 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4036 /* Evaluate whether or not state_pathway_ok can change */
4037 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4039 if (hdw->state_pathway_ok) {
4040 /* Nothing to do if pathway is already ok */
4043 if (!hdw->state_pipeline_idle) {
4044 /* Not allowed to change anything if pipeline is not idle */
4047 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4048 hdw->state_pathway_ok = !0;
4049 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4054 /* Evaluate whether or not state_encoder_ok can change */
4055 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4057 if (hdw->state_encoder_ok) return 0;
4058 if (hdw->flag_tripped) return 0;
4059 if (hdw->state_encoder_run) return 0;
4060 if (hdw->state_encoder_config) return 0;
4061 if (hdw->state_decoder_run) return 0;
4062 if (hdw->state_usbstream_run) return 0;
4063 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4064 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4065 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4069 if (pvr2_upload_firmware2(hdw) < 0) {
4070 hdw->flag_tripped = !0;
4071 trace_stbit("flag_tripped",hdw->flag_tripped);
4074 hdw->state_encoder_ok = !0;
4075 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4080 /* Evaluate whether or not state_encoder_config can change */
4081 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4083 if (hdw->state_encoder_config) {
4084 if (hdw->state_encoder_ok) {
4085 if (hdw->state_pipeline_req &&
4086 !hdw->state_pipeline_pause) return 0;
4088 hdw->state_encoder_config = 0;
4089 hdw->state_encoder_waitok = 0;
4090 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4091 /* paranoia - solve race if timer just completed */
4092 del_timer_sync(&hdw->encoder_wait_timer);
4094 if (!hdw->state_pathway_ok ||
4095 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4096 !hdw->state_encoder_ok ||
4097 !hdw->state_pipeline_idle ||
4098 hdw->state_pipeline_pause ||
4099 !hdw->state_pipeline_req ||
4100 !hdw->state_pipeline_config) {
4101 /* We must reset the enforced wait interval if
4102 anything has happened that might have disturbed
4103 the encoder. This should be a rare case. */
4104 if (timer_pending(&hdw->encoder_wait_timer)) {
4105 del_timer_sync(&hdw->encoder_wait_timer);
4107 if (hdw->state_encoder_waitok) {
4108 /* Must clear the state - therefore we did
4109 something to a state bit and must also
4111 hdw->state_encoder_waitok = 0;
4112 trace_stbit("state_encoder_waitok",
4113 hdw->state_encoder_waitok);
4118 if (!hdw->state_encoder_waitok) {
4119 if (!timer_pending(&hdw->encoder_wait_timer)) {
4120 /* waitok flag wasn't set and timer isn't
4121 running. Check flag once more to avoid
4122 a race then start the timer. This is
4123 the point when we measure out a minimal
4124 quiet interval before doing something to
4126 if (!hdw->state_encoder_waitok) {
4127 hdw->encoder_wait_timer.expires =
4129 (HZ * TIME_MSEC_ENCODER_WAIT
4131 add_timer(&hdw->encoder_wait_timer);
4134 /* We can't continue until we know we have been
4135 quiet for the interval measured by this
4139 pvr2_encoder_configure(hdw);
4140 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4142 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4147 /* Return true if the encoder should not be running. */
4148 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4150 if (!hdw->state_encoder_ok) {
4151 /* Encoder isn't healthy at the moment, so stop it. */
4154 if (!hdw->state_pathway_ok) {
4155 /* Mode is not understood at the moment (i.e. it wants to
4156 change), so encoder must be stopped. */
4160 switch (hdw->pathway_state) {
4161 case PVR2_PATHWAY_ANALOG:
4162 if (!hdw->state_decoder_run) {
4163 /* We're in analog mode and the decoder is not
4164 running; thus the encoder should be stopped as
4169 case PVR2_PATHWAY_DIGITAL:
4170 if (hdw->state_encoder_runok) {
4171 /* This is a funny case. We're in digital mode so
4172 really the encoder should be stopped. However
4173 if it really is running, only kill it after
4174 runok has been set. This gives a chance for the
4175 onair quirk to function (encoder must run
4176 briefly first, at least once, before onair
4177 digital streaming can work). */
4182 /* Unknown mode; so encoder should be stopped. */
4186 /* If we get here, we haven't found a reason to stop the
4192 /* Return true if the encoder should be running. */
4193 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4195 if (!hdw->state_encoder_ok) {
4196 /* Don't run the encoder if it isn't healthy... */
4199 if (!hdw->state_pathway_ok) {
4200 /* Don't run the encoder if we don't (yet) know what mode
4201 we need to be in... */
4205 switch (hdw->pathway_state) {
4206 case PVR2_PATHWAY_ANALOG:
4207 if (hdw->state_decoder_run) {
4208 /* In analog mode, if the decoder is running, then
4213 case PVR2_PATHWAY_DIGITAL:
4214 if ((hdw->hdw_desc->digital_control_scheme ==
4215 PVR2_DIGITAL_SCHEME_ONAIR) &&
4216 !hdw->state_encoder_runok) {
4217 /* This is a quirk. OnAir hardware won't stream
4218 digital until the encoder has been run at least
4219 once, for a minimal period of time (empiricially
4220 measured to be 1/4 second). So if we're on
4221 OnAir hardware and the encoder has never been
4222 run at all, then start the encoder. Normal
4223 state machine logic in the driver will
4224 automatically handle the remaining bits. */
4229 /* For completeness (unknown mode; encoder won't run ever) */
4232 /* If we get here, then we haven't found any reason to run the
4233 encoder, so don't run it. */
4238 /* Evaluate whether or not state_encoder_run can change */
4239 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4241 if (hdw->state_encoder_run) {
4242 if (!state_check_disable_encoder_run(hdw)) return 0;
4243 if (hdw->state_encoder_ok) {
4244 del_timer_sync(&hdw->encoder_run_timer);
4245 if (pvr2_encoder_stop(hdw) < 0) return !0;
4247 hdw->state_encoder_run = 0;
4249 if (!state_check_enable_encoder_run(hdw)) return 0;
4250 if (pvr2_encoder_start(hdw) < 0) return !0;
4251 hdw->state_encoder_run = !0;
4252 if (!hdw->state_encoder_runok) {
4253 hdw->encoder_run_timer.expires =
4254 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4255 add_timer(&hdw->encoder_run_timer);
4258 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4263 /* Timeout function for quiescent timer. */
4264 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4266 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4267 hdw->state_decoder_quiescent = !0;
4268 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4269 hdw->state_stale = !0;
4270 queue_work(hdw->workqueue,&hdw->workpoll);
4274 /* Timeout function for encoder wait timer. */
4275 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4277 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4278 hdw->state_encoder_waitok = !0;
4279 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4280 hdw->state_stale = !0;
4281 queue_work(hdw->workqueue,&hdw->workpoll);
4285 /* Timeout function for encoder run timer. */
4286 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4288 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4289 if (!hdw->state_encoder_runok) {
4290 hdw->state_encoder_runok = !0;
4291 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4292 hdw->state_stale = !0;
4293 queue_work(hdw->workqueue,&hdw->workpoll);
4298 /* Evaluate whether or not state_decoder_run can change */
4299 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4301 if (hdw->state_decoder_run) {
4302 if (hdw->state_encoder_ok) {
4303 if (hdw->state_pipeline_req &&
4304 !hdw->state_pipeline_pause &&
4305 hdw->state_pathway_ok) return 0;
4307 if (!hdw->flag_decoder_missed) {
4308 pvr2_decoder_enable(hdw,0);
4310 hdw->state_decoder_quiescent = 0;
4311 hdw->state_decoder_run = 0;
4312 /* paranoia - solve race if timer just completed */
4313 del_timer_sync(&hdw->quiescent_timer);
4315 if (!hdw->state_decoder_quiescent) {
4316 if (!timer_pending(&hdw->quiescent_timer)) {
4317 /* We don't do something about the
4318 quiescent timer until right here because
4319 we also want to catch cases where the
4320 decoder was already not running (like
4321 after initialization) as opposed to
4322 knowing that we had just stopped it.
4323 The second flag check is here to cover a
4324 race - the timer could have run and set
4325 this flag just after the previous check
4326 but before we did the pending check. */
4327 if (!hdw->state_decoder_quiescent) {
4328 hdw->quiescent_timer.expires =
4330 (HZ * TIME_MSEC_DECODER_WAIT
4332 add_timer(&hdw->quiescent_timer);
4335 /* Don't allow decoder to start again until it has
4336 been quiesced first. This little detail should
4337 hopefully further stabilize the encoder. */
4340 if (!hdw->state_pathway_ok ||
4341 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4342 !hdw->state_pipeline_req ||
4343 hdw->state_pipeline_pause ||
4344 !hdw->state_pipeline_config ||
4345 !hdw->state_encoder_config ||
4346 !hdw->state_encoder_ok) return 0;
4347 del_timer_sync(&hdw->quiescent_timer);
4348 if (hdw->flag_decoder_missed) return 0;
4349 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4350 hdw->state_decoder_quiescent = 0;
4351 hdw->state_decoder_run = !0;
4353 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4354 trace_stbit("state_decoder_run",hdw->state_decoder_run);
4359 /* Evaluate whether or not state_usbstream_run can change */
4360 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4362 if (hdw->state_usbstream_run) {
4364 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4365 fl = (hdw->state_encoder_ok &&
4366 hdw->state_encoder_run);
4367 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4368 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4369 fl = hdw->state_encoder_ok;
4372 hdw->state_pipeline_req &&
4373 !hdw->state_pipeline_pause &&
4374 hdw->state_pathway_ok) {
4377 pvr2_hdw_cmd_usbstream(hdw,0);
4378 hdw->state_usbstream_run = 0;
4380 if (!hdw->state_pipeline_req ||
4381 hdw->state_pipeline_pause ||
4382 !hdw->state_pathway_ok) return 0;
4383 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4384 if (!hdw->state_encoder_ok ||
4385 !hdw->state_encoder_run) return 0;
4386 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4387 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4388 if (!hdw->state_encoder_ok) return 0;
4389 if (hdw->state_encoder_run) return 0;
4390 if (hdw->hdw_desc->digital_control_scheme ==
4391 PVR2_DIGITAL_SCHEME_ONAIR) {
4392 /* OnAir digital receivers won't stream
4393 unless the analog encoder has run first.
4394 Why? I have no idea. But don't even
4395 try until we know the analog side is
4396 known to have run. */
4397 if (!hdw->state_encoder_runok) return 0;
4400 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4401 hdw->state_usbstream_run = !0;
4403 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4408 /* Attempt to configure pipeline, if needed */
4409 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4411 if (hdw->state_pipeline_config ||
4412 hdw->state_pipeline_pause) return 0;
4413 pvr2_hdw_commit_execute(hdw);
4418 /* Update pipeline idle and pipeline pause tracking states based on other
4419 inputs. This must be called whenever the other relevant inputs have
4421 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4425 /* Update pipeline state */
4426 st = !(hdw->state_encoder_run ||
4427 hdw->state_decoder_run ||
4428 hdw->state_usbstream_run ||
4429 (!hdw->state_decoder_quiescent));
4430 if (!st != !hdw->state_pipeline_idle) {
4431 hdw->state_pipeline_idle = st;
4434 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4435 hdw->state_pipeline_pause = 0;
4442 typedef int (*state_eval_func)(struct pvr2_hdw *);
4444 /* Set of functions to be run to evaluate various states in the driver. */
4445 static const state_eval_func eval_funcs[] = {
4446 state_eval_pathway_ok,
4447 state_eval_pipeline_config,
4448 state_eval_encoder_ok,
4449 state_eval_encoder_config,
4450 state_eval_decoder_run,
4451 state_eval_encoder_run,
4452 state_eval_usbstream_run,
4456 /* Process various states and return true if we did anything interesting. */
4457 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4460 int state_updated = 0;
4463 if (!hdw->state_stale) return 0;
4464 if ((hdw->fw1_state != FW1_STATE_OK) ||
4466 hdw->state_stale = 0;
4469 /* This loop is the heart of the entire driver. It keeps trying to
4470 evaluate various bits of driver state until nothing changes for
4471 one full iteration. Each "bit of state" tracks some global
4472 aspect of the driver, e.g. whether decoder should run, if
4473 pipeline is configured, usb streaming is on, etc. We separately
4474 evaluate each of those questions based on other driver state to
4475 arrive at the correct running configuration. */
4478 state_update_pipeline_state(hdw);
4479 /* Iterate over each bit of state */
4480 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4481 if ((*eval_funcs[i])(hdw)) {
4484 state_update_pipeline_state(hdw);
4487 } while (check_flag && hdw->flag_ok);
4488 hdw->state_stale = 0;
4489 trace_stbit("state_stale",hdw->state_stale);
4490 return state_updated;
4494 static unsigned int print_input_mask(unsigned int msk,
4495 char *buf,unsigned int acnt)
4497 unsigned int idx,ccnt;
4498 unsigned int tcnt = 0;
4499 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4500 if (!((1 << idx) & msk)) continue;
4501 ccnt = scnprintf(buf+tcnt,
4505 control_values_input[idx]);
4512 static const char *pvr2_pathway_state_name(int id)
4515 case PVR2_PATHWAY_ANALOG: return "analog";
4516 case PVR2_PATHWAY_DIGITAL: return "digital";
4517 default: return "unknown";
4522 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4523 char *buf,unsigned int acnt)
4529 "driver:%s%s%s%s%s <mode=%s>",
4530 (hdw->flag_ok ? " <ok>" : " <fail>"),
4531 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4532 (hdw->flag_disconnected ? " <disconnected>" :
4534 (hdw->flag_tripped ? " <tripped>" : ""),
4535 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4536 pvr2_pathway_state_name(hdw->pathway_state));
4541 "pipeline:%s%s%s%s",
4542 (hdw->state_pipeline_idle ? " <idle>" : ""),
4543 (hdw->state_pipeline_config ?
4544 " <configok>" : " <stale>"),
4545 (hdw->state_pipeline_req ? " <req>" : ""),
4546 (hdw->state_pipeline_pause ? " <pause>" : ""));
4550 "worker:%s%s%s%s%s%s%s",
4551 (hdw->state_decoder_run ?
4553 (hdw->state_decoder_quiescent ?
4554 "" : " <decode:stop>")),
4555 (hdw->state_decoder_quiescent ?
4556 " <decode:quiescent>" : ""),
4557 (hdw->state_encoder_ok ?
4558 "" : " <encode:init>"),
4559 (hdw->state_encoder_run ?
4560 (hdw->state_encoder_runok ?
4562 " <encode:firstrun>") :
4563 (hdw->state_encoder_runok ?
4565 " <encode:virgin>")),
4566 (hdw->state_encoder_config ?
4567 " <encode:configok>" :
4568 (hdw->state_encoder_waitok ?
4569 "" : " <encode:waitok>")),
4570 (hdw->state_usbstream_run ?
4571 " <usb:run>" : " <usb:stop>"),
4572 (hdw->state_pathway_ok ?
4573 " <pathway:ok>" : ""));
4578 pvr2_get_state_name(hdw->master_state));
4580 unsigned int tcnt = 0;
4583 ccnt = scnprintf(buf,
4585 "Hardware supported inputs: ");
4587 tcnt += print_input_mask(hdw->input_avail_mask,
4590 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4591 ccnt = scnprintf(buf+tcnt,
4593 "; allowed inputs: ");
4595 tcnt += print_input_mask(hdw->input_allowed_mask,
4602 struct pvr2_stream_stats stats;
4603 if (!hdw->vid_stream) break;
4604 pvr2_stream_get_stats(hdw->vid_stream,
4610 " URBs: queued=%u idle=%u ready=%u"
4611 " processed=%u failed=%u",
4612 stats.bytes_processed,
4613 stats.buffers_in_queue,
4614 stats.buffers_in_idle,
4615 stats.buffers_in_ready,
4616 stats.buffers_processed,
4617 stats.buffers_failed);
4625 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4626 char *buf,unsigned int acnt)
4628 unsigned int bcnt,ccnt,idx;
4630 LOCK_TAKE(hdw->big_lock);
4631 for (idx = 0; ; idx++) {
4632 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4634 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4636 buf[0] = '\n'; ccnt = 1;
4637 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4639 LOCK_GIVE(hdw->big_lock);
4644 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4647 unsigned int idx,ccnt;
4649 for (idx = 0; ; idx++) {
4650 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4652 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4657 /* Evaluate and update the driver's current state, taking various actions
4658 as appropriate for the update. */
4659 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4662 int state_updated = 0;
4663 int callback_flag = 0;
4666 pvr2_trace(PVR2_TRACE_STBITS,
4667 "Drive state check START");
4668 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4669 pvr2_hdw_state_log_state(hdw);
4672 /* Process all state and get back over disposition */
4673 state_updated = pvr2_hdw_state_update(hdw);
4675 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4677 /* Update master state based upon all other states. */
4678 if (!hdw->flag_ok) {
4679 st = PVR2_STATE_DEAD;
4680 } else if (hdw->fw1_state != FW1_STATE_OK) {
4681 st = PVR2_STATE_COLD;
4682 } else if ((analog_mode ||
4683 hdw->hdw_desc->flag_digital_requires_cx23416) &&
4684 !hdw->state_encoder_ok) {
4685 st = PVR2_STATE_WARM;
4686 } else if (hdw->flag_tripped ||
4687 (analog_mode && hdw->flag_decoder_missed)) {
4688 st = PVR2_STATE_ERROR;
4689 } else if (hdw->state_usbstream_run &&
4691 (hdw->state_encoder_run && hdw->state_decoder_run))) {
4692 st = PVR2_STATE_RUN;
4694 st = PVR2_STATE_READY;
4696 if (hdw->master_state != st) {
4697 pvr2_trace(PVR2_TRACE_STATE,
4698 "Device state change from %s to %s",
4699 pvr2_get_state_name(hdw->master_state),
4700 pvr2_get_state_name(st));
4701 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4702 hdw->master_state = st;
4706 if (state_updated) {
4707 /* Trigger anyone waiting on any state changes here. */
4708 wake_up(&hdw->state_wait_data);
4711 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4712 pvr2_hdw_state_log_state(hdw);
4714 pvr2_trace(PVR2_TRACE_STBITS,
4715 "Drive state check DONE callback=%d",callback_flag);
4717 return callback_flag;
4721 /* Cause kernel thread to check / update driver state */
4722 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4724 if (hdw->state_stale) return;
4725 hdw->state_stale = !0;
4726 trace_stbit("state_stale",hdw->state_stale);
4727 queue_work(hdw->workqueue,&hdw->workpoll);
4731 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4733 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4737 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4739 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4743 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4745 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4749 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4754 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4755 if (ret) return ret;
4756 nval = (cval & ~msk) | (val & msk);
4757 pvr2_trace(PVR2_TRACE_GPIO,
4758 "GPIO direction changing 0x%x:0x%x"
4759 " from 0x%x to 0x%x",
4763 pvr2_trace(PVR2_TRACE_GPIO,
4764 "GPIO direction changing to 0x%x",nval);
4766 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4770 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4775 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
4776 if (ret) return ret;
4777 nval = (cval & ~msk) | (val & msk);
4778 pvr2_trace(PVR2_TRACE_GPIO,
4779 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
4783 pvr2_trace(PVR2_TRACE_GPIO,
4784 "GPIO output changing to 0x%x",nval);
4786 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
4790 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
4792 pvr2_i2c_core_status_poll(hdw);
4796 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
4798 return hdw->input_avail_mask;
4802 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
4804 return hdw->input_allowed_mask;
4808 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
4810 if (hdw->input_val != v) {
4812 hdw->input_dirty = !0;
4815 /* Handle side effects - if we switch to a mode that needs the RF
4816 tuner, then select the right frequency choice as well and mark
4818 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
4819 hdw->freqSelector = 0;
4820 hdw->freqDirty = !0;
4821 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
4822 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
4823 hdw->freqSelector = 1;
4824 hdw->freqDirty = !0;
4830 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
4831 unsigned int change_mask,
4832 unsigned int change_val)
4835 unsigned int nv,m,idx;
4836 LOCK_TAKE(hdw->big_lock);
4838 nv = hdw->input_allowed_mask & ~change_mask;
4839 nv |= (change_val & change_mask);
4840 nv &= hdw->input_avail_mask;
4842 /* No legal modes left; return error instead. */
4846 hdw->input_allowed_mask = nv;
4847 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
4848 /* Current mode is still in the allowed mask, so
4852 /* Select and switch to a mode that is still in the allowed
4854 if (!hdw->input_allowed_mask) {
4855 /* Nothing legal; give up */
4858 m = hdw->input_allowed_mask;
4859 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
4860 if (!((1 << idx) & m)) continue;
4861 pvr2_hdw_set_input(hdw,idx);
4865 LOCK_GIVE(hdw->big_lock);
4870 /* Find I2C address of eeprom */
4871 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
4874 LOCK_TAKE(hdw->ctl_lock); do {
4875 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
4876 result = pvr2_send_request(hdw,
4879 if (result < 0) break;
4880 result = hdw->cmd_buffer[0];
4881 } while(0); LOCK_GIVE(hdw->ctl_lock);
4886 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
4887 struct v4l2_dbg_match *match, u64 reg_id,
4888 int setFl, u64 *val_ptr)
4890 #ifdef CONFIG_VIDEO_ADV_DEBUG
4891 struct pvr2_i2c_client *cp;
4892 struct v4l2_dbg_register req;
4896 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
4900 if (setFl) req.val = *val_ptr;
4901 mutex_lock(&hdw->i2c_list_lock); do {
4902 list_for_each_entry(cp, &hdw->i2c_clients, list) {
4903 if (!v4l2_chip_match_i2c_client(
4908 stat = pvr2_i2c_client_cmd(
4909 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
4910 VIDIOC_DBG_G_REGISTER),&req);
4911 if (!setFl) *val_ptr = req.val;
4915 } while (0); mutex_unlock(&hdw->i2c_list_lock);
4927 Stuff for Emacs to see, in order to encourage consistent editing style:
4928 *** Local Variables: ***
4930 *** fill-column: 75 ***
4931 *** tab-width: 8 ***
4932 *** c-basic-offset: 8 ***