SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  *
  19  */
  20
  21 #include <linux/errno.h>
  22 #include <linux/string.h>
  23 #include <linux/slab.h>
  24 #include <linux/firmware.h>
  25 #include <linux/videodev2.h>
  26 #include <media/v4l2-common.h>
  27 #include "pvrusb2.h"
  28 #include "pvrusb2-std.h"
  29 #include "pvrusb2-util.h"
  30 #include "pvrusb2-hdw.h"
  31 #include "pvrusb2-i2c-core.h"
  32 #include "pvrusb2-i2c-track.h"
  33 #include "pvrusb2-tuner.h"
  34 #include "pvrusb2-eeprom.h"
  35 #include "pvrusb2-hdw-internal.h"
  36 #include "pvrusb2-encoder.h"
  37 #include "pvrusb2-debug.h"
  38 #include "pvrusb2-fx2-cmd.h"
  39
  40 #define TV_MIN_FREQ     55250000L
  41 #define TV_MAX_FREQ    850000000L
  42
  43 /* This defines a minimum interval that the decoder must remain quiet
  44    before we are allowed to start it running. */
  45 #define TIME_MSEC_DECODER_WAIT 50
  46
  47 /* This defines a minimum interval that the encoder must remain quiet
  48    before we are allowed to configure it.  I had this originally set to
  49    50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
  50    things work better when it's set to 100msec. */
  51 #define TIME_MSEC_ENCODER_WAIT 100
  52
  53 /* This defines the minimum interval that the encoder must successfully run
  54    before we consider that the encoder has run at least once since its
  55    firmware has been loaded.  This measurement is in important for cases
  56    where we can't do something until we know that the encoder has been run
  57    at least once. */
  58 #define TIME_MSEC_ENCODER_OK 250
  59
  60 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  61 static DEFINE_MUTEX(pvr2_unit_mtx);
  62
  63 static int ctlchg;
  64 static int procreload;
  65 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  66 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  67 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  68 static int init_pause_msec;
  69
  70 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  71 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  72 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  73 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  74 module_param(procreload, int, S_IRUGO|S_IWUSR);
  75 MODULE_PARM_DESC(procreload,
  76                  "Attempt init failure recovery with firmware reload");
  77 module_param_array(tuner,    int, NULL, 0444);
  78 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  79 module_param_array(video_std,    int, NULL, 0444);
  80 MODULE_PARM_DESC(video_std,"specify initial video standard");
  81 module_param_array(tolerance,    int, NULL, 0444);
  82 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  83
  84 /* US Broadcast channel 7 (175.25 MHz) */
  85 static int default_tv_freq    = 175250000L;
  86 /* 104.3 MHz, a usable FM station for my area */
  87 static int default_radio_freq = 104300000L;
  88
  89 module_param_named(tv_freq, default_tv_freq, int, 0444);
  90 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  91 module_param_named(radio_freq, default_radio_freq, int, 0444);
  92 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  93
  94 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  95 #define PVR2_CTL_READ_ENDPOINT   0x81
  96
  97 #define PVR2_GPIO_IN 0x9008
  98 #define PVR2_GPIO_OUT 0x900c
  99 #define PVR2_GPIO_DIR 0x9020
 100
 101 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 102
 103 #define PVR2_FIRMWARE_ENDPOINT   0x02
 104
 105 /* size of a firmware chunk */
 106 #define FIRMWARE_CHUNK_SIZE 0x2000
 107
 108 /* Define the list of additional controls we'll dynamically construct based
 109    on query of the cx2341x module. */
 110 struct pvr2_mpeg_ids {
 111         const char *strid;
 112         int id;
 113 };
 114 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 115         {
 116                 .strid = "audio_layer",
 117                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 118         },{
 119                 .strid = "audio_bitrate",
 120                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 121         },{
 122                 /* Already using audio_mode elsewhere :-( */
 123                 .strid = "mpeg_audio_mode",
 124                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 125         },{
 126                 .strid = "mpeg_audio_mode_extension",
 127                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 128         },{
 129                 .strid = "audio_emphasis",
 130                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 131         },{
 132                 .strid = "audio_crc",
 133                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 134         },{
 135                 .strid = "video_aspect",
 136                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 137         },{
 138                 .strid = "video_b_frames",
 139                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 140         },{
 141                 .strid = "video_gop_size",
 142                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 143         },{
 144                 .strid = "video_gop_closure",
 145                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 146         },{
 147                 .strid = "video_bitrate_mode",
 148                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 149         },{
 150                 .strid = "video_bitrate",
 151                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 152         },{
 153                 .strid = "video_bitrate_peak",
 154                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 155         },{
 156                 .strid = "video_temporal_decimation",
 157                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 158         },{
 159                 .strid = "stream_type",
 160                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 161         },{
 162                 .strid = "video_spatial_filter_mode",
 163                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 164         },{
 165                 .strid = "video_spatial_filter",
 166                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 167         },{
 168                 .strid = "video_luma_spatial_filter_type",
 169                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 170         },{
 171                 .strid = "video_chroma_spatial_filter_type",
 172                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 173         },{
 174                 .strid = "video_temporal_filter_mode",
 175                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 176         },{
 177                 .strid = "video_temporal_filter",
 178                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 179         },{
 180                 .strid = "video_median_filter_type",
 181                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 182         },{
 183                 .strid = "video_luma_median_filter_top",
 184                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 185         },{
 186                 .strid = "video_luma_median_filter_bottom",
 187                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 188         },{
 189                 .strid = "video_chroma_median_filter_top",
 190                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 191         },{
 192                 .strid = "video_chroma_median_filter_bottom",
 193                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 194         }
 195 };
 196 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 197
 198
 199 static const char *control_values_srate[] = {
 200         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 201         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 202         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 203 };
 204
 205
 206
 207 static const char *control_values_input[] = {
 208         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 209         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 210         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 211         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 212         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 213 };
 214
 215
 216 static const char *control_values_audiomode[] = {
 217         [V4L2_TUNER_MODE_MONO]   = "Mono",
 218         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 219         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 220         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 221         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 222 };
 223
 224
 225 static const char *control_values_hsm[] = {
 226         [PVR2_CVAL_HSM_FAIL] = "Fail",
 227         [PVR2_CVAL_HSM_HIGH] = "High",
 228         [PVR2_CVAL_HSM_FULL] = "Full",
 229 };
 230
 231
 232 static const char *pvr2_state_names[] = {
 233         [PVR2_STATE_NONE] =    "none",
 234         [PVR2_STATE_DEAD] =    "dead",
 235         [PVR2_STATE_COLD] =    "cold",
 236         [PVR2_STATE_WARM] =    "warm",
 237         [PVR2_STATE_ERROR] =   "error",
 238         [PVR2_STATE_READY] =   "ready",
 239         [PVR2_STATE_RUN] =     "run",
 240 };
 241
 242
 243 struct pvr2_fx2cmd_descdef {
 244         unsigned char id;
 245         unsigned char *desc;
 246 };
 247
 248 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 249         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 250         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 251         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 252         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 253         {FX2CMD_REG_WRITE, "write encoder register"},
 254         {FX2CMD_REG_READ, "read encoder register"},
 255         {FX2CMD_MEMSEL, "encoder memsel"},
 256         {FX2CMD_I2C_WRITE, "i2c write"},
 257         {FX2CMD_I2C_READ, "i2c read"},
 258         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 259         {FX2CMD_STREAMING_ON, "stream on"},
 260         {FX2CMD_STREAMING_OFF, "stream off"},
 261         {FX2CMD_FWPOST1, "fwpost1"},
 262         {FX2CMD_POWER_OFF, "power off"},
 263         {FX2CMD_POWER_ON, "power on"},
 264         {FX2CMD_DEEP_RESET, "deep reset"},
 265         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 266         {FX2CMD_GET_IR_CODE, "get IR code"},
 267         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 268         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 269         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 270         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 271         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 272         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 273         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 274 };
 275
 276
 277 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 278 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 279 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 280 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 281 static void pvr2_hdw_worker_i2c(struct work_struct *work);
 282 static void pvr2_hdw_worker_poll(struct work_struct *work);
 283 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 284 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 285 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 286 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 287 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 288 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 289 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 290 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 291 static void pvr2_hdw_quiescent_timeout(unsigned long);
 292 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 293 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 294 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 295 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 296                                 unsigned int timeout,int probe_fl,
 297                                 void *write_data,unsigned int write_len,
 298                                 void *read_data,unsigned int read_len);
 299 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 300
 301
 302 static void trace_stbit(const char *name,int val)
 303 {
 304         pvr2_trace(PVR2_TRACE_STBITS,
 305                    "State bit %s <-- %s",
 306                    name,(val ? "true" : "false"));
 307 }
 308
 309 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 310 {
 311         struct pvr2_hdw *hdw = cptr->hdw;
 312         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 313                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 314         } else {
 315                 *vp = 0;
 316         }
 317         return 0;
 318 }
 319
 320 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 321 {
 322         struct pvr2_hdw *hdw = cptr->hdw;
 323         unsigned int slotId = hdw->freqProgSlot;
 324         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 325                 hdw->freqTable[slotId-1] = v;
 326                 /* Handle side effects correctly - if we're tuned to this
 327                    slot, then forgot the slot id relation since the stored
 328                    frequency has been changed. */
 329                 if (hdw->freqSelector) {
 330                         if (hdw->freqSlotRadio == slotId) {
 331                                 hdw->freqSlotRadio = 0;
 332                         }
 333                 } else {
 334                         if (hdw->freqSlotTelevision == slotId) {
 335                                 hdw->freqSlotTelevision = 0;
 336                         }
 337                 }
 338         }
 339         return 0;
 340 }
 341
 342 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 343 {
 344         *vp = cptr->hdw->freqProgSlot;
 345         return 0;
 346 }
 347
 348 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 349 {
 350         struct pvr2_hdw *hdw = cptr->hdw;
 351         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 352                 hdw->freqProgSlot = v;
 353         }
 354         return 0;
 355 }
 356
 357 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 358 {
 359         struct pvr2_hdw *hdw = cptr->hdw;
 360         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 361         return 0;
 362 }
 363
 364 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 365 {
 366         unsigned freq = 0;
 367         struct pvr2_hdw *hdw = cptr->hdw;
 368         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 369         if (slotId > 0) {
 370                 freq = hdw->freqTable[slotId-1];
 371                 if (!freq) return 0;
 372                 pvr2_hdw_set_cur_freq(hdw,freq);
 373         }
 374         if (hdw->freqSelector) {
 375                 hdw->freqSlotRadio = slotId;
 376         } else {
 377                 hdw->freqSlotTelevision = slotId;
 378         }
 379         return 0;
 380 }
 381
 382 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 383 {
 384         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 385         return 0;
 386 }
 387
 388 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 389 {
 390         return cptr->hdw->freqDirty != 0;
 391 }
 392
 393 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 394 {
 395         cptr->hdw->freqDirty = 0;
 396 }
 397
 398 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 399 {
 400         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 401         return 0;
 402 }
 403
 404 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 405 {
 406         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 407         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 408         if (stat != 0) {
 409                 return stat;
 410         }
 411         *left = cap->bounds.left;
 412         return 0;
 413 }
 414
 415 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 416 {
 417         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 418         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 419         if (stat != 0) {
 420                 return stat;
 421         }
 422         *left = cap->bounds.left;
 423         if (cap->bounds.width > cptr->hdw->cropw_val) {
 424                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 425         }
 426         return 0;
 427 }
 428
 429 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 430 {
 431         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 432         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 433         if (stat != 0) {
 434                 return stat;
 435         }
 436         *top = cap->bounds.top;
 437         return 0;
 438 }
 439
 440 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 441 {
 442         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 443         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 444         if (stat != 0) {
 445                 return stat;
 446         }
 447         *top = cap->bounds.top;
 448         if (cap->bounds.height > cptr->hdw->croph_val) {
 449                 *top += cap->bounds.height - cptr->hdw->croph_val;
 450         }
 451         return 0;
 452 }
 453
 454 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
 455 {
 456         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 457         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 458         if (stat != 0) {
 459                 return stat;
 460         }
 461         *val = 0;
 462         if (cap->bounds.width > cptr->hdw->cropl_val) {
 463                 *val = cap->bounds.width - cptr->hdw->cropl_val;
 464         }
 465         return 0;
 466 }
 467
 468 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
 469 {
 470         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 471         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 472         if (stat != 0) {
 473                 return stat;
 474         }
 475         *val = 0;
 476         if (cap->bounds.height > cptr->hdw->cropt_val) {
 477                 *val = cap->bounds.height - cptr->hdw->cropt_val;
 478         }
 479         return 0;
 480 }
 481
 482 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 483 {
 484         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 485         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 486         if (stat != 0) {
 487                 return stat;
 488         }
 489         *val = cap->bounds.left;
 490         return 0;
 491 }
 492
 493 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 494 {
 495         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 496         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 497         if (stat != 0) {
 498                 return stat;
 499         }
 500         *val = cap->bounds.top;
 501         return 0;
 502 }
 503
 504 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 505 {
 506         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 507         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 508         if (stat != 0) {
 509                 return stat;
 510         }
 511         *val = cap->bounds.width;
 512         return 0;
 513 }
 514
 515 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 516 {
 517         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 518         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 519         if (stat != 0) {
 520                 return stat;
 521         }
 522         *val = cap->bounds.height;
 523         return 0;
 524 }
 525
 526 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 527 {
 528         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 529         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 530         if (stat != 0) {
 531                 return stat;
 532         }
 533         *val = cap->defrect.left;
 534         return 0;
 535 }
 536
 537 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 538 {
 539         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 540         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 541         if (stat != 0) {
 542                 return stat;
 543         }
 544         *val = cap->defrect.top;
 545         return 0;
 546 }
 547
 548 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 549 {
 550         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 551         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 552         if (stat != 0) {
 553                 return stat;
 554         }
 555         *val = cap->defrect.width;
 556         return 0;
 557 }
 558
 559 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 560 {
 561         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 562         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 563         if (stat != 0) {
 564                 return stat;
 565         }
 566         *val = cap->defrect.height;
 567         return 0;
 568 }
 569
 570 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 571 {
 572         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 573         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 574         if (stat != 0) {
 575                 return stat;
 576         }
 577         *val = cap->pixelaspect.numerator;
 578         return 0;
 579 }
 580
 581 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 582 {
 583         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 584         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 585         if (stat != 0) {
 586                 return stat;
 587         }
 588         *val = cap->pixelaspect.denominator;
 589         return 0;
 590 }
 591
 592 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 593 {
 594         /* Actual maximum depends on the video standard in effect. */
 595         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 596                 *vp = 480;
 597         } else {
 598                 *vp = 576;
 599         }
 600         return 0;
 601 }
 602
 603 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 604 {
 605         /* Actual minimum depends on device digitizer type. */
 606         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 607                 *vp = 75;
 608         } else {
 609                 *vp = 17;
 610         }
 611         return 0;
 612 }
 613
 614 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 615 {
 616         *vp = cptr->hdw->input_val;
 617         return 0;
 618 }
 619
 620 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 621 {
 622         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 623 }
 624
 625 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 626 {
 627         return pvr2_hdw_set_input(cptr->hdw,v);
 628 }
 629
 630 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 631 {
 632         return cptr->hdw->input_dirty != 0;
 633 }
 634
 635 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 636 {
 637         cptr->hdw->input_dirty = 0;
 638 }
 639
 640
 641 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 642 {
 643         unsigned long fv;
 644         struct pvr2_hdw *hdw = cptr->hdw;
 645         if (hdw->tuner_signal_stale) {
 646                 pvr2_hdw_status_poll(hdw);
 647         }
 648         fv = hdw->tuner_signal_info.rangehigh;
 649         if (!fv) {
 650                 /* Safety fallback */
 651                 *vp = TV_MAX_FREQ;
 652                 return 0;
 653         }
 654         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 655                 fv = (fv * 125) / 2;
 656         } else {
 657                 fv = fv * 62500;
 658         }
 659         *vp = fv;
 660         return 0;
 661 }
 662
 663 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 664 {
 665         unsigned long fv;
 666         struct pvr2_hdw *hdw = cptr->hdw;
 667         if (hdw->tuner_signal_stale) {
 668                 pvr2_hdw_status_poll(hdw);
 669         }
 670         fv = hdw->tuner_signal_info.rangelow;
 671         if (!fv) {
 672                 /* Safety fallback */
 673                 *vp = TV_MIN_FREQ;
 674                 return 0;
 675         }
 676         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 677                 fv = (fv * 125) / 2;
 678         } else {
 679                 fv = fv * 62500;
 680         }
 681         *vp = fv;
 682         return 0;
 683 }
 684
 685 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 686 {
 687         return cptr->hdw->enc_stale != 0;
 688 }
 689
 690 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 691 {
 692         cptr->hdw->enc_stale = 0;
 693         cptr->hdw->enc_unsafe_stale = 0;
 694 }
 695
 696 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 697 {
 698         int ret;
 699         struct v4l2_ext_controls cs;
 700         struct v4l2_ext_control c1;
 701         memset(&cs,0,sizeof(cs));
 702         memset(&c1,0,sizeof(c1));
 703         cs.controls = &c1;
 704         cs.count = 1;
 705         c1.id = cptr->info->v4l_id;
 706         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 707                                 VIDIOC_G_EXT_CTRLS);
 708         if (ret) return ret;
 709         *vp = c1.value;
 710         return 0;
 711 }
 712
 713 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 714 {
 715         int ret;
 716         struct pvr2_hdw *hdw = cptr->hdw;
 717         struct v4l2_ext_controls cs;
 718         struct v4l2_ext_control c1;
 719         memset(&cs,0,sizeof(cs));
 720         memset(&c1,0,sizeof(c1));
 721         cs.controls = &c1;
 722         cs.count = 1;
 723         c1.id = cptr->info->v4l_id;
 724         c1.value = v;
 725         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 726                                 hdw->state_encoder_run, &cs,
 727                                 VIDIOC_S_EXT_CTRLS);
 728         if (ret == -EBUSY) {
 729                 /* Oops.  cx2341x is telling us it's not safe to change
 730                    this control while we're capturing.  Make a note of this
 731                    fact so that the pipeline will be stopped the next time
 732                    controls are committed.  Then go on ahead and store this
 733                    change anyway. */
 734                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 735                                         0, &cs,
 736                                         VIDIOC_S_EXT_CTRLS);
 737                 if (!ret) hdw->enc_unsafe_stale = !0;
 738         }
 739         if (ret) return ret;
 740         hdw->enc_stale = !0;
 741         return 0;
 742 }
 743
 744 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 745 {
 746         struct v4l2_queryctrl qctrl;
 747         struct pvr2_ctl_info *info;
 748         qctrl.id = cptr->info->v4l_id;
 749         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 750         /* Strip out the const so we can adjust a function pointer.  It's
 751            OK to do this here because we know this is a dynamically created
 752            control, so the underlying storage for the info pointer is (a)
 753            private to us, and (b) not in read-only storage.  Either we do
 754            this or we significantly complicate the underlying control
 755            implementation. */
 756         info = (struct pvr2_ctl_info *)(cptr->info);
 757         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 758                 if (info->set_value) {
 759                         info->set_value = NULL;
 760                 }
 761         } else {
 762                 if (!(info->set_value)) {
 763                         info->set_value = ctrl_cx2341x_set;
 764                 }
 765         }
 766         return qctrl.flags;
 767 }
 768
 769 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 770 {
 771         *vp = cptr->hdw->state_pipeline_req;
 772         return 0;
 773 }
 774
 775 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 776 {
 777         *vp = cptr->hdw->master_state;
 778         return 0;
 779 }
 780
 781 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 782 {
 783         int result = pvr2_hdw_is_hsm(cptr->hdw);
 784         *vp = PVR2_CVAL_HSM_FULL;
 785         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 786         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 787         return 0;
 788 }
 789
 790 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 791 {
 792         *vp = cptr->hdw->std_mask_avail;
 793         return 0;
 794 }
 795
 796 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 797 {
 798         struct pvr2_hdw *hdw = cptr->hdw;
 799         v4l2_std_id ns;
 800         ns = hdw->std_mask_avail;
 801         ns = (ns & ~m) | (v & m);
 802         if (ns == hdw->std_mask_avail) return 0;
 803         hdw->std_mask_avail = ns;
 804         pvr2_hdw_internal_set_std_avail(hdw);
 805         pvr2_hdw_internal_find_stdenum(hdw);
 806         return 0;
 807 }
 808
 809 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 810                                char *bufPtr,unsigned int bufSize,
 811                                unsigned int *len)
 812 {
 813         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 814         return 0;
 815 }
 816
 817 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 818                                const char *bufPtr,unsigned int bufSize,
 819                                int *mskp,int *valp)
 820 {
 821         int ret;
 822         v4l2_std_id id;
 823         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 824         if (ret < 0) return ret;
 825         if (mskp) *mskp = id;
 826         if (valp) *valp = id;
 827         return 0;
 828 }
 829
 830 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 831 {
 832         *vp = cptr->hdw->std_mask_cur;
 833         return 0;
 834 }
 835
 836 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 837 {
 838         struct pvr2_hdw *hdw = cptr->hdw;
 839         v4l2_std_id ns;
 840         ns = hdw->std_mask_cur;
 841         ns = (ns & ~m) | (v & m);
 842         if (ns == hdw->std_mask_cur) return 0;
 843         hdw->std_mask_cur = ns;
 844         hdw->std_dirty = !0;
 845         pvr2_hdw_internal_find_stdenum(hdw);
 846         return 0;
 847 }
 848
 849 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 850 {
 851         return cptr->hdw->std_dirty != 0;
 852 }
 853
 854 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 855 {
 856         cptr->hdw->std_dirty = 0;
 857 }
 858
 859 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 860 {
 861         struct pvr2_hdw *hdw = cptr->hdw;
 862         pvr2_hdw_status_poll(hdw);
 863         *vp = hdw->tuner_signal_info.signal;
 864         return 0;
 865 }
 866
 867 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 868 {
 869         int val = 0;
 870         unsigned int subchan;
 871         struct pvr2_hdw *hdw = cptr->hdw;
 872         pvr2_hdw_status_poll(hdw);
 873         subchan = hdw->tuner_signal_info.rxsubchans;
 874         if (subchan & V4L2_TUNER_SUB_MONO) {
 875                 val |= (1 << V4L2_TUNER_MODE_MONO);
 876         }
 877         if (subchan & V4L2_TUNER_SUB_STEREO) {
 878                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 879         }
 880         if (subchan & V4L2_TUNER_SUB_LANG1) {
 881                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 882         }
 883         if (subchan & V4L2_TUNER_SUB_LANG2) {
 884                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 885         }
 886         *vp = val;
 887         return 0;
 888 }
 889
 890
 891 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 892 {
 893         struct pvr2_hdw *hdw = cptr->hdw;
 894         if (v < 0) return -EINVAL;
 895         if (v > hdw->std_enum_cnt) return -EINVAL;
 896         hdw->std_enum_cur = v;
 897         if (!v) return 0;
 898         v--;
 899         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 900         hdw->std_mask_cur = hdw->std_defs[v].id;
 901         hdw->std_dirty = !0;
 902         return 0;
 903 }
 904
 905
 906 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 907 {
 908         *vp = cptr->hdw->std_enum_cur;
 909         return 0;
 910 }
 911
 912
 913 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 914 {
 915         return cptr->hdw->std_dirty != 0;
 916 }
 917
 918
 919 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 920 {
 921         cptr->hdw->std_dirty = 0;
 922 }
 923
 924
 925 #define DEFINT(vmin,vmax) \
 926         .type = pvr2_ctl_int, \
 927         .def.type_int.min_value = vmin, \
 928         .def.type_int.max_value = vmax
 929
 930 #define DEFENUM(tab) \
 931         .type = pvr2_ctl_enum, \
 932         .def.type_enum.count = ARRAY_SIZE(tab), \
 933         .def.type_enum.value_names = tab
 934
 935 #define DEFBOOL \
 936         .type = pvr2_ctl_bool
 937
 938 #define DEFMASK(msk,tab) \
 939         .type = pvr2_ctl_bitmask, \
 940         .def.type_bitmask.valid_bits = msk, \
 941         .def.type_bitmask.bit_names = tab
 942
 943 #define DEFREF(vname) \
 944         .set_value = ctrl_set_##vname, \
 945         .get_value = ctrl_get_##vname, \
 946         .is_dirty = ctrl_isdirty_##vname, \
 947         .clear_dirty = ctrl_cleardirty_##vname
 948
 949
 950 #define VCREATE_FUNCS(vname) \
 951 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 952 {*vp = cptr->hdw->vname##_val; return 0;} \
 953 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 954 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 955 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 956 {return cptr->hdw->vname##_dirty != 0;} \
 957 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 958 {cptr->hdw->vname##_dirty = 0;}
 959
 960 VCREATE_FUNCS(brightness)
 961 VCREATE_FUNCS(contrast)
 962 VCREATE_FUNCS(saturation)
 963 VCREATE_FUNCS(hue)
 964 VCREATE_FUNCS(volume)
 965 VCREATE_FUNCS(balance)
 966 VCREATE_FUNCS(bass)
 967 VCREATE_FUNCS(treble)
 968 VCREATE_FUNCS(mute)
 969 VCREATE_FUNCS(cropl)
 970 VCREATE_FUNCS(cropt)
 971 VCREATE_FUNCS(cropw)
 972 VCREATE_FUNCS(croph)
 973 VCREATE_FUNCS(audiomode)
 974 VCREATE_FUNCS(res_hor)
 975 VCREATE_FUNCS(res_ver)
 976 VCREATE_FUNCS(srate)
 977
 978 /* Table definition of all controls which can be manipulated */
 979 static const struct pvr2_ctl_info control_defs[] = {
 980         {
 981                 .v4l_id = V4L2_CID_BRIGHTNESS,
 982                 .desc = "Brightness",
 983                 .name = "brightness",
 984                 .default_value = 128,
 985                 DEFREF(brightness),
 986                 DEFINT(0,255),
 987         },{
 988                 .v4l_id = V4L2_CID_CONTRAST,
 989                 .desc = "Contrast",
 990                 .name = "contrast",
 991                 .default_value = 68,
 992                 DEFREF(contrast),
 993                 DEFINT(0,127),
 994         },{
 995                 .v4l_id = V4L2_CID_SATURATION,
 996                 .desc = "Saturation",
 997                 .name = "saturation",
 998                 .default_value = 64,
 999                 DEFREF(saturation),
1000                 DEFINT(0,127),
1001         },{
1002                 .v4l_id = V4L2_CID_HUE,
1003                 .desc = "Hue",
1004                 .name = "hue",
1005                 .default_value = 0,
1006                 DEFREF(hue),
1007                 DEFINT(-128,127),
1008         },{
1009                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1010                 .desc = "Volume",
1011                 .name = "volume",
1012                 .default_value = 62000,
1013                 DEFREF(volume),
1014                 DEFINT(0,65535),
1015         },{
1016                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1017                 .desc = "Balance",
1018                 .name = "balance",
1019                 .default_value = 0,
1020                 DEFREF(balance),
1021                 DEFINT(-32768,32767),
1022         },{
1023                 .v4l_id = V4L2_CID_AUDIO_BASS,
1024                 .desc = "Bass",
1025                 .name = "bass",
1026                 .default_value = 0,
1027                 DEFREF(bass),
1028                 DEFINT(-32768,32767),
1029         },{
1030                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1031                 .desc = "Treble",
1032                 .name = "treble",
1033                 .default_value = 0,
1034                 DEFREF(treble),
1035                 DEFINT(-32768,32767),
1036         },{
1037                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1038                 .desc = "Mute",
1039                 .name = "mute",
1040                 .default_value = 0,
1041                 DEFREF(mute),
1042                 DEFBOOL,
1043         }, {
1044                 .desc = "Capture crop left margin",
1045                 .name = "crop_left",
1046                 .internal_id = PVR2_CID_CROPL,
1047                 .default_value = 0,
1048                 DEFREF(cropl),
1049                 DEFINT(-129, 340),
1050                 .get_min_value = ctrl_cropl_min_get,
1051                 .get_max_value = ctrl_cropl_max_get,
1052                 .get_def_value = ctrl_get_cropcapdl,
1053         }, {
1054                 .desc = "Capture crop top margin",
1055                 .name = "crop_top",
1056                 .internal_id = PVR2_CID_CROPT,
1057                 .default_value = 0,
1058                 DEFREF(cropt),
1059                 DEFINT(-35, 544),
1060                 .get_min_value = ctrl_cropt_min_get,
1061                 .get_max_value = ctrl_cropt_max_get,
1062                 .get_def_value = ctrl_get_cropcapdt,
1063         }, {
1064                 .desc = "Capture crop width",
1065                 .name = "crop_width",
1066                 .internal_id = PVR2_CID_CROPW,
1067                 .default_value = 720,
1068                 DEFREF(cropw),
1069                 .get_max_value = ctrl_cropw_max_get,
1070                 .get_def_value = ctrl_get_cropcapdw,
1071         }, {
1072                 .desc = "Capture crop height",
1073                 .name = "crop_height",
1074                 .internal_id = PVR2_CID_CROPH,
1075                 .default_value = 480,
1076                 DEFREF(croph),
1077                 .get_max_value = ctrl_croph_max_get,
1078                 .get_def_value = ctrl_get_cropcapdh,
1079         }, {
1080                 .desc = "Capture capability pixel aspect numerator",
1081                 .name = "cropcap_pixel_numerator",
1082                 .internal_id = PVR2_CID_CROPCAPPAN,
1083                 .get_value = ctrl_get_cropcappan,
1084         }, {
1085                 .desc = "Capture capability pixel aspect denominator",
1086                 .name = "cropcap_pixel_denominator",
1087                 .internal_id = PVR2_CID_CROPCAPPAD,
1088                 .get_value = ctrl_get_cropcappad,
1089         }, {
1090                 .desc = "Capture capability bounds top",
1091                 .name = "cropcap_bounds_top",
1092                 .internal_id = PVR2_CID_CROPCAPBT,
1093                 .get_value = ctrl_get_cropcapbt,
1094         }, {
1095                 .desc = "Capture capability bounds left",
1096                 .name = "cropcap_bounds_left",
1097                 .internal_id = PVR2_CID_CROPCAPBL,
1098                 .get_value = ctrl_get_cropcapbl,
1099         }, {
1100                 .desc = "Capture capability bounds width",
1101                 .name = "cropcap_bounds_width",
1102                 .internal_id = PVR2_CID_CROPCAPBW,
1103                 .get_value = ctrl_get_cropcapbw,
1104         }, {
1105                 .desc = "Capture capability bounds height",
1106                 .name = "cropcap_bounds_height",
1107                 .internal_id = PVR2_CID_CROPCAPBH,
1108                 .get_value = ctrl_get_cropcapbh,
1109         },{
1110                 .desc = "Video Source",
1111                 .name = "input",
1112                 .internal_id = PVR2_CID_INPUT,
1113                 .default_value = PVR2_CVAL_INPUT_TV,
1114                 .check_value = ctrl_check_input,
1115                 DEFREF(input),
1116                 DEFENUM(control_values_input),
1117         },{
1118                 .desc = "Audio Mode",
1119                 .name = "audio_mode",
1120                 .internal_id = PVR2_CID_AUDIOMODE,
1121                 .default_value = V4L2_TUNER_MODE_STEREO,
1122                 DEFREF(audiomode),
1123                 DEFENUM(control_values_audiomode),
1124         },{
1125                 .desc = "Horizontal capture resolution",
1126                 .name = "resolution_hor",
1127                 .internal_id = PVR2_CID_HRES,
1128                 .default_value = 720,
1129                 DEFREF(res_hor),
1130                 DEFINT(19,720),
1131         },{
1132                 .desc = "Vertical capture resolution",
1133                 .name = "resolution_ver",
1134                 .internal_id = PVR2_CID_VRES,
1135                 .default_value = 480,
1136                 DEFREF(res_ver),
1137                 DEFINT(17,576),
1138                 /* Hook in check for video standard and adjust maximum
1139                    depending on the standard. */
1140                 .get_max_value = ctrl_vres_max_get,
1141                 .get_min_value = ctrl_vres_min_get,
1142         },{
1143                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1144                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1145                 .desc = "Audio Sampling Frequency",
1146                 .name = "srate",
1147                 DEFREF(srate),
1148                 DEFENUM(control_values_srate),
1149         },{
1150                 .desc = "Tuner Frequency (Hz)",
1151                 .name = "frequency",
1152                 .internal_id = PVR2_CID_FREQUENCY,
1153                 .default_value = 0,
1154                 .set_value = ctrl_freq_set,
1155                 .get_value = ctrl_freq_get,
1156                 .is_dirty = ctrl_freq_is_dirty,
1157                 .clear_dirty = ctrl_freq_clear_dirty,
1158                 DEFINT(0,0),
1159                 /* Hook in check for input value (tv/radio) and adjust
1160                    max/min values accordingly */
1161                 .get_max_value = ctrl_freq_max_get,
1162                 .get_min_value = ctrl_freq_min_get,
1163         },{
1164                 .desc = "Channel",
1165                 .name = "channel",
1166                 .set_value = ctrl_channel_set,
1167                 .get_value = ctrl_channel_get,
1168                 DEFINT(0,FREQTABLE_SIZE),
1169         },{
1170                 .desc = "Channel Program Frequency",
1171                 .name = "freq_table_value",
1172                 .set_value = ctrl_channelfreq_set,
1173                 .get_value = ctrl_channelfreq_get,
1174                 DEFINT(0,0),
1175                 /* Hook in check for input value (tv/radio) and adjust
1176                    max/min values accordingly */
1177                 .get_max_value = ctrl_freq_max_get,
1178                 .get_min_value = ctrl_freq_min_get,
1179         },{
1180                 .desc = "Channel Program ID",
1181                 .name = "freq_table_channel",
1182                 .set_value = ctrl_channelprog_set,
1183                 .get_value = ctrl_channelprog_get,
1184                 DEFINT(0,FREQTABLE_SIZE),
1185         },{
1186                 .desc = "Streaming Enabled",
1187                 .name = "streaming_enabled",
1188                 .get_value = ctrl_streamingenabled_get,
1189                 DEFBOOL,
1190         },{
1191                 .desc = "USB Speed",
1192                 .name = "usb_speed",
1193                 .get_value = ctrl_hsm_get,
1194                 DEFENUM(control_values_hsm),
1195         },{
1196                 .desc = "Master State",
1197                 .name = "master_state",
1198                 .get_value = ctrl_masterstate_get,
1199                 DEFENUM(pvr2_state_names),
1200         },{
1201                 .desc = "Signal Present",
1202                 .name = "signal_present",
1203                 .get_value = ctrl_signal_get,
1204                 DEFINT(0,65535),
1205         },{
1206                 .desc = "Audio Modes Present",
1207                 .name = "audio_modes_present",
1208                 .get_value = ctrl_audio_modes_present_get,
1209                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1210                    v4l.  Nothing outside of this module cares about this,
1211                    but I reuse it in order to also reuse the
1212                    control_values_audiomode string table. */
1213                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1214                          (1 << V4L2_TUNER_MODE_STEREO)|
1215                          (1 << V4L2_TUNER_MODE_LANG1)|
1216                          (1 << V4L2_TUNER_MODE_LANG2)),
1217                         control_values_audiomode),
1218         },{
1219                 .desc = "Video Standards Available Mask",
1220                 .name = "video_standard_mask_available",
1221                 .internal_id = PVR2_CID_STDAVAIL,
1222                 .skip_init = !0,
1223                 .get_value = ctrl_stdavail_get,
1224                 .set_value = ctrl_stdavail_set,
1225                 .val_to_sym = ctrl_std_val_to_sym,
1226                 .sym_to_val = ctrl_std_sym_to_val,
1227                 .type = pvr2_ctl_bitmask,
1228         },{
1229                 .desc = "Video Standards In Use Mask",
1230                 .name = "video_standard_mask_active",
1231                 .internal_id = PVR2_CID_STDCUR,
1232                 .skip_init = !0,
1233                 .get_value = ctrl_stdcur_get,
1234                 .set_value = ctrl_stdcur_set,
1235                 .is_dirty = ctrl_stdcur_is_dirty,
1236                 .clear_dirty = ctrl_stdcur_clear_dirty,
1237                 .val_to_sym = ctrl_std_val_to_sym,
1238                 .sym_to_val = ctrl_std_sym_to_val,
1239                 .type = pvr2_ctl_bitmask,
1240         },{
1241                 .desc = "Video Standard Name",
1242                 .name = "video_standard",
1243                 .internal_id = PVR2_CID_STDENUM,
1244                 .skip_init = !0,
1245                 .get_value = ctrl_stdenumcur_get,
1246                 .set_value = ctrl_stdenumcur_set,
1247                 .is_dirty = ctrl_stdenumcur_is_dirty,
1248                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1249                 .type = pvr2_ctl_enum,
1250         }
1251 };
1252
1253 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1254
1255
1256 const char *pvr2_config_get_name(enum pvr2_config cfg)
1257 {
1258         switch (cfg) {
1259         case pvr2_config_empty: return "empty";
1260         case pvr2_config_mpeg: return "mpeg";
1261         case pvr2_config_vbi: return "vbi";
1262         case pvr2_config_pcm: return "pcm";
1263         case pvr2_config_rawvideo: return "raw video";
1264         }
1265         return "<unknown>";
1266 }
1267
1268
1269 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1270 {
1271         return hdw->usb_dev;
1272 }
1273
1274
1275 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1276 {
1277         return hdw->serial_number;
1278 }
1279
1280
1281 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1282 {
1283         return hdw->bus_info;
1284 }
1285
1286
1287 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1288 {
1289         return hdw->identifier;
1290 }
1291
1292
1293 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1294 {
1295         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1296 }
1297
1298 /* Set the currently tuned frequency and account for all possible
1299    driver-core side effects of this action. */
1300 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1301 {
1302         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1303                 if (hdw->freqSelector) {
1304                         /* Swing over to radio frequency selection */
1305                         hdw->freqSelector = 0;
1306                         hdw->freqDirty = !0;
1307                 }
1308                 if (hdw->freqValRadio != val) {
1309                         hdw->freqValRadio = val;
1310                         hdw->freqSlotRadio = 0;
1311                         hdw->freqDirty = !0;
1312                 }
1313         } else {
1314                 if (!(hdw->freqSelector)) {
1315                         /* Swing over to television frequency selection */
1316                         hdw->freqSelector = 1;
1317                         hdw->freqDirty = !0;
1318                 }
1319                 if (hdw->freqValTelevision != val) {
1320                         hdw->freqValTelevision = val;
1321                         hdw->freqSlotTelevision = 0;
1322                         hdw->freqDirty = !0;
1323                 }
1324         }
1325 }
1326
1327 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1328 {
1329         return hdw->unit_number;
1330 }
1331
1332
1333 /* Attempt to locate one of the given set of files.  Messages are logged
1334    appropriate to what has been found.  The return value will be 0 or
1335    greater on success (it will be the index of the file name found) and
1336    fw_entry will be filled in.  Otherwise a negative error is returned on
1337    failure.  If the return value is -ENOENT then no viable firmware file
1338    could be located. */
1339 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1340                                 const struct firmware **fw_entry,
1341                                 const char *fwtypename,
1342                                 unsigned int fwcount,
1343                                 const char *fwnames[])
1344 {
1345         unsigned int idx;
1346         int ret = -EINVAL;
1347         for (idx = 0; idx < fwcount; idx++) {
1348                 ret = request_firmware(fw_entry,
1349                                        fwnames[idx],
1350                                        &hdw->usb_dev->dev);
1351                 if (!ret) {
1352                         trace_firmware("Located %s firmware: %s;"
1353                                        " uploading...",
1354                                        fwtypename,
1355                                        fwnames[idx]);
1356                         return idx;
1357                 }
1358                 if (ret == -ENOENT) continue;
1359                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1360                            "request_firmware fatal error with code=%d",ret);
1361                 return ret;
1362         }
1363         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1364                    "***WARNING***"
1365                    " Device %s firmware"
1366                    " seems to be missing.",
1367                    fwtypename);
1368         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1369                    "Did you install the pvrusb2 firmware files"
1370                    " in their proper location?");
1371         if (fwcount == 1) {
1372                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1373                            "request_firmware unable to locate %s file %s",
1374                            fwtypename,fwnames[0]);
1375         } else {
1376                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1377                            "request_firmware unable to locate"
1378                            " one of the following %s files:",
1379                            fwtypename);
1380                 for (idx = 0; idx < fwcount; idx++) {
1381                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1382                                    "request_firmware: Failed to find %s",
1383                                    fwnames[idx]);
1384                 }
1385         }
1386         return ret;
1387 }
1388
1389
1390 /*
1391  * pvr2_upload_firmware1().
1392  *
1393  * Send the 8051 firmware to the device.  After the upload, arrange for
1394  * device to re-enumerate.
1395  *
1396  * NOTE : the pointer to the firmware data given by request_firmware()
1397  * is not suitable for an usb transaction.
1398  *
1399  */
1400 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1401 {
1402         const struct firmware *fw_entry = NULL;
1403         void  *fw_ptr;
1404         unsigned int pipe;
1405         int ret;
1406         u16 address;
1407
1408         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1409                 hdw->fw1_state = FW1_STATE_OK;
1410                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1411                            "Connected device type defines"
1412                            " no firmware to upload; ignoring firmware");
1413                 return -ENOTTY;
1414         }
1415
1416         hdw->fw1_state = FW1_STATE_FAILED; // default result
1417
1418         trace_firmware("pvr2_upload_firmware1");
1419
1420         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1421                                    hdw->hdw_desc->fx2_firmware.cnt,
1422                                    hdw->hdw_desc->fx2_firmware.lst);
1423         if (ret < 0) {
1424                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1425                 return ret;
1426         }
1427
1428         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1429         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1430
1431         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1432
1433         if (fw_entry->size != 0x2000){
1434                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1435                 release_firmware(fw_entry);
1436                 return -ENOMEM;
1437         }
1438
1439         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1440         if (fw_ptr == NULL){
1441                 release_firmware(fw_entry);
1442                 return -ENOMEM;
1443         }
1444
1445         /* We have to hold the CPU during firmware upload. */
1446         pvr2_hdw_cpureset_assert(hdw,1);
1447
1448         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1449            chunk. */
1450
1451         ret = 0;
1452         for(address = 0; address < fw_entry->size; address += 0x800) {
1453                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1454                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1455                                        0, fw_ptr, 0x800, HZ);
1456         }
1457
1458         trace_firmware("Upload done, releasing device's CPU");
1459
1460         /* Now release the CPU.  It will disconnect and reconnect later. */
1461         pvr2_hdw_cpureset_assert(hdw,0);
1462
1463         kfree(fw_ptr);
1464         release_firmware(fw_entry);
1465
1466         trace_firmware("Upload done (%d bytes sent)",ret);
1467
1468         /* We should have written 8192 bytes */
1469         if (ret == 8192) {
1470                 hdw->fw1_state = FW1_STATE_RELOAD;
1471                 return 0;
1472         }
1473
1474         return -EIO;
1475 }
1476
1477
1478 /*
1479  * pvr2_upload_firmware2()
1480  *
1481  * This uploads encoder firmware on endpoint 2.
1482  *
1483  */
1484
1485 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1486 {
1487         const struct firmware *fw_entry = NULL;
1488         void  *fw_ptr;
1489         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1490         int actual_length;
1491         int ret = 0;
1492         int fwidx;
1493         static const char *fw_files[] = {
1494                 CX2341X_FIRM_ENC_FILENAME,
1495         };
1496
1497         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1498                 return 0;
1499         }
1500
1501         trace_firmware("pvr2_upload_firmware2");
1502
1503         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1504                                    ARRAY_SIZE(fw_files), fw_files);
1505         if (ret < 0) return ret;
1506         fwidx = ret;
1507         ret = 0;
1508         /* Since we're about to completely reinitialize the encoder,
1509            invalidate our cached copy of its configuration state.  Next
1510            time we configure the encoder, then we'll fully configure it. */
1511         hdw->enc_cur_valid = 0;
1512
1513         /* Encoder is about to be reset so note that as far as we're
1514            concerned now, the encoder has never been run. */
1515         del_timer_sync(&hdw->encoder_run_timer);
1516         if (hdw->state_encoder_runok) {
1517                 hdw->state_encoder_runok = 0;
1518                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1519         }
1520
1521         /* First prepare firmware loading */
1522         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1523         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1524         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1525         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1526         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1527         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1528         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1529         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1530         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1531         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1532         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1533         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1534         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1535         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1536         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1537         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1538         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1539         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1540
1541         if (ret) {
1542                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1543                            "firmware2 upload prep failed, ret=%d",ret);
1544                 release_firmware(fw_entry);
1545                 goto done;
1546         }
1547
1548         /* Now send firmware */
1549
1550         fw_len = fw_entry->size;
1551
1552         if (fw_len % sizeof(u32)) {
1553                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1554                            "size of %s firmware"
1555                            " must be a multiple of %zu bytes",
1556                            fw_files[fwidx],sizeof(u32));
1557                 release_firmware(fw_entry);
1558                 ret = -EINVAL;
1559                 goto done;
1560         }
1561
1562         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1563         if (fw_ptr == NULL){
1564                 release_firmware(fw_entry);
1565                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1566                            "failed to allocate memory for firmware2 upload");
1567                 ret = -ENOMEM;
1568                 goto done;
1569         }
1570
1571         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1572
1573         fw_done = 0;
1574         for (fw_done = 0; fw_done < fw_len;) {
1575                 bcnt = fw_len - fw_done;
1576                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1577                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1578                 /* Usbsnoop log shows that we must swap bytes... */
1579                 /* Some background info: The data being swapped here is a
1580                    firmware image destined for the mpeg encoder chip that
1581                    lives at the other end of a USB endpoint.  The encoder
1582                    chip always talks in 32 bit chunks and its storage is
1583                    organized into 32 bit words.  However from the file
1584                    system to the encoder chip everything is purely a byte
1585                    stream.  The firmware file's contents are always 32 bit
1586                    swapped from what the encoder expects.  Thus the need
1587                    always exists to swap the bytes regardless of the endian
1588                    type of the host processor and therefore swab32() makes
1589                    the most sense. */
1590                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1591                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1592
1593                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1594                                     &actual_length, HZ);
1595                 ret |= (actual_length != bcnt);
1596                 if (ret) break;
1597                 fw_done += bcnt;
1598         }
1599
1600         trace_firmware("upload of %s : %i / %i ",
1601                        fw_files[fwidx],fw_done,fw_len);
1602
1603         kfree(fw_ptr);
1604         release_firmware(fw_entry);
1605
1606         if (ret) {
1607                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1608                            "firmware2 upload transfer failure");
1609                 goto done;
1610         }
1611
1612         /* Finish upload */
1613
1614         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1615         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1616         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1617
1618         if (ret) {
1619                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1620                            "firmware2 upload post-proc failure");
1621         }
1622
1623  done:
1624         if (hdw->hdw_desc->signal_routing_scheme ==
1625             PVR2_ROUTING_SCHEME_GOTVIEW) {
1626                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1627                    hardware. */
1628                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1629         }
1630         return ret;
1631 }
1632
1633
1634 static const char *pvr2_get_state_name(unsigned int st)
1635 {
1636         if (st < ARRAY_SIZE(pvr2_state_names)) {
1637                 return pvr2_state_names[st];
1638         }
1639         return "???";
1640 }
1641
1642 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1643 {
1644         if (!hdw->decoder_ctrl) {
1645                 if (!hdw->flag_decoder_missed) {
1646                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1647                                    "WARNING: No decoder present");
1648                         hdw->flag_decoder_missed = !0;
1649                         trace_stbit("flag_decoder_missed",
1650                                     hdw->flag_decoder_missed);
1651                 }
1652                 return -EIO;
1653         }
1654         hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1655         return 0;
1656 }
1657
1658
1659 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1660 {
1661         if (hdw->decoder_ctrl == ptr) return;
1662         hdw->decoder_ctrl = ptr;
1663         if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1664                 hdw->flag_decoder_missed = 0;
1665                 trace_stbit("flag_decoder_missed",
1666                             hdw->flag_decoder_missed);
1667                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1668                            "Decoder has appeared");
1669                 pvr2_hdw_state_sched(hdw);
1670         }
1671 }
1672
1673
1674 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1675 {
1676         return hdw->master_state;
1677 }
1678
1679
1680 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1681 {
1682         if (!hdw->flag_tripped) return 0;
1683         hdw->flag_tripped = 0;
1684         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1685                    "Clearing driver error statuss");
1686         return !0;
1687 }
1688
1689
1690 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1691 {
1692         int fl;
1693         LOCK_TAKE(hdw->big_lock); do {
1694                 fl = pvr2_hdw_untrip_unlocked(hdw);
1695         } while (0); LOCK_GIVE(hdw->big_lock);
1696         if (fl) pvr2_hdw_state_sched(hdw);
1697         return 0;
1698 }
1699
1700
1701
1702
1703 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1704 {
1705         return hdw->state_pipeline_req != 0;
1706 }
1707
1708
1709 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1710 {
1711         int ret,st;
1712         LOCK_TAKE(hdw->big_lock); do {
1713                 pvr2_hdw_untrip_unlocked(hdw);
1714                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1715                         hdw->state_pipeline_req = enable_flag != 0;
1716                         pvr2_trace(PVR2_TRACE_START_STOP,
1717                                    "/*--TRACE_STREAM--*/ %s",
1718                                    enable_flag ? "enable" : "disable");
1719                 }
1720                 pvr2_hdw_state_sched(hdw);
1721         } while (0); LOCK_GIVE(hdw->big_lock);
1722         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1723         if (enable_flag) {
1724                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1725                         if (st != PVR2_STATE_READY) return -EIO;
1726                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1727                 }
1728         }
1729         return 0;
1730 }
1731
1732
1733 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1734 {
1735         int fl;
1736         LOCK_TAKE(hdw->big_lock);
1737         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1738                 hdw->desired_stream_type = config;
1739                 hdw->state_pipeline_config = 0;
1740                 trace_stbit("state_pipeline_config",
1741                             hdw->state_pipeline_config);
1742                 pvr2_hdw_state_sched(hdw);
1743         }
1744         LOCK_GIVE(hdw->big_lock);
1745         if (fl) return 0;
1746         return pvr2_hdw_wait(hdw,0);
1747 }
1748
1749
1750 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1751 {
1752         int unit_number = hdw->unit_number;
1753         int tp = -1;
1754         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1755                 tp = tuner[unit_number];
1756         }
1757         if (tp < 0) return -EINVAL;
1758         hdw->tuner_type = tp;
1759         hdw->tuner_updated = !0;
1760         return 0;
1761 }
1762
1763
1764 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1765 {
1766         int unit_number = hdw->unit_number;
1767         int tp = 0;
1768         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1769                 tp = video_std[unit_number];
1770                 if (tp) return tp;
1771         }
1772         return 0;
1773 }
1774
1775
1776 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1777 {
1778         int unit_number = hdw->unit_number;
1779         int tp = 0;
1780         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1781                 tp = tolerance[unit_number];
1782         }
1783         return tp;
1784 }
1785
1786
1787 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1788 {
1789         /* Try a harmless request to fetch the eeprom's address over
1790            endpoint 1.  See what happens.  Only the full FX2 image can
1791            respond to this.  If this probe fails then likely the FX2
1792            firmware needs be loaded. */
1793         int result;
1794         LOCK_TAKE(hdw->ctl_lock); do {
1795                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1796                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1797                                            hdw->cmd_buffer,1,
1798                                            hdw->cmd_buffer,1);
1799                 if (result < 0) break;
1800         } while(0); LOCK_GIVE(hdw->ctl_lock);
1801         if (result) {
1802                 pvr2_trace(PVR2_TRACE_INIT,
1803                            "Probe of device endpoint 1 result status %d",
1804                            result);
1805         } else {
1806                 pvr2_trace(PVR2_TRACE_INIT,
1807                            "Probe of device endpoint 1 succeeded");
1808         }
1809         return result == 0;
1810 }
1811
1812 struct pvr2_std_hack {
1813         v4l2_std_id pat;  /* Pattern to match */
1814         v4l2_std_id msk;  /* Which bits we care about */
1815         v4l2_std_id std;  /* What additional standards or default to set */
1816 };
1817
1818 /* This data structure labels specific combinations of standards from
1819    tveeprom that we'll try to recognize.  If we recognize one, then assume
1820    a specified default standard to use.  This is here because tveeprom only
1821    tells us about available standards not the intended default standard (if
1822    any) for the device in question.  We guess the default based on what has
1823    been reported as available.  Note that this is only for guessing a
1824    default - which can always be overridden explicitly - and if the user
1825    has otherwise named a default then that default will always be used in
1826    place of this table. */
1827 static const struct pvr2_std_hack std_eeprom_maps[] = {
1828         {       /* PAL(B/G) */
1829                 .pat = V4L2_STD_B|V4L2_STD_GH,
1830                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1831         },
1832         {       /* NTSC(M) */
1833                 .pat = V4L2_STD_MN,
1834                 .std = V4L2_STD_NTSC_M,
1835         },
1836         {       /* PAL(I) */
1837                 .pat = V4L2_STD_PAL_I,
1838                 .std = V4L2_STD_PAL_I,
1839         },
1840         {       /* SECAM(L/L') */
1841                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1842                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1843         },
1844         {       /* PAL(D/D1/K) */
1845                 .pat = V4L2_STD_DK,
1846                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1847         },
1848 };
1849
1850 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1851 {
1852         char buf[40];
1853         unsigned int bcnt;
1854         v4l2_std_id std1,std2,std3;
1855
1856         std1 = get_default_standard(hdw);
1857         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1858
1859         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1860         pvr2_trace(PVR2_TRACE_STD,
1861                    "Supported video standard(s) reported available"
1862                    " in hardware: %.*s",
1863                    bcnt,buf);
1864
1865         hdw->std_mask_avail = hdw->std_mask_eeprom;
1866
1867         std2 = (std1|std3) & ~hdw->std_mask_avail;
1868         if (std2) {
1869                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1870                 pvr2_trace(PVR2_TRACE_STD,
1871                            "Expanding supported video standards"
1872                            " to include: %.*s",
1873                            bcnt,buf);
1874                 hdw->std_mask_avail |= std2;
1875         }
1876
1877         pvr2_hdw_internal_set_std_avail(hdw);
1878
1879         if (std1) {
1880                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1881                 pvr2_trace(PVR2_TRACE_STD,
1882                            "Initial video standard forced to %.*s",
1883                            bcnt,buf);
1884                 hdw->std_mask_cur = std1;
1885                 hdw->std_dirty = !0;
1886                 pvr2_hdw_internal_find_stdenum(hdw);
1887                 return;
1888         }
1889         if (std3) {
1890                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1891                 pvr2_trace(PVR2_TRACE_STD,
1892                            "Initial video standard"
1893                            " (determined by device type): %.*s",bcnt,buf);
1894                 hdw->std_mask_cur = std3;
1895                 hdw->std_dirty = !0;
1896                 pvr2_hdw_internal_find_stdenum(hdw);
1897                 return;
1898         }
1899
1900         {
1901                 unsigned int idx;
1902                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1903                         if (std_eeprom_maps[idx].msk ?
1904                             ((std_eeprom_maps[idx].pat ^
1905                              hdw->std_mask_eeprom) &
1906                              std_eeprom_maps[idx].msk) :
1907                             (std_eeprom_maps[idx].pat !=
1908                              hdw->std_mask_eeprom)) continue;
1909                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1910                                                   std_eeprom_maps[idx].std);
1911                         pvr2_trace(PVR2_TRACE_STD,
1912                                    "Initial video standard guessed as %.*s",
1913                                    bcnt,buf);
1914                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1915                         hdw->std_dirty = !0;
1916                         pvr2_hdw_internal_find_stdenum(hdw);
1917                         return;
1918                 }
1919         }
1920
1921         if (hdw->std_enum_cnt > 1) {
1922                 // Autoselect the first listed standard
1923                 hdw->std_enum_cur = 1;
1924                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1925                 hdw->std_dirty = !0;
1926                 pvr2_trace(PVR2_TRACE_STD,
1927                            "Initial video standard auto-selected to %s",
1928                            hdw->std_defs[hdw->std_enum_cur-1].name);
1929                 return;
1930         }
1931
1932         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1933                    "Unable to select a viable initial video standard");
1934 }
1935
1936
1937 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1938 {
1939         int ret;
1940         unsigned int idx;
1941         struct pvr2_ctrl *cptr;
1942         int reloadFl = 0;
1943         if (hdw->hdw_desc->fx2_firmware.cnt) {
1944                 if (!reloadFl) {
1945                         reloadFl =
1946                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1947                                  == 0);
1948                         if (reloadFl) {
1949                                 pvr2_trace(PVR2_TRACE_INIT,
1950                                            "USB endpoint config looks strange"
1951                                            "; possibly firmware needs to be"
1952                                            " loaded");
1953                         }
1954                 }
1955                 if (!reloadFl) {
1956                         reloadFl = !pvr2_hdw_check_firmware(hdw);
1957                         if (reloadFl) {
1958                                 pvr2_trace(PVR2_TRACE_INIT,
1959                                            "Check for FX2 firmware failed"
1960                                            "; possibly firmware needs to be"
1961                                            " loaded");
1962                         }
1963                 }
1964                 if (reloadFl) {
1965                         if (pvr2_upload_firmware1(hdw) != 0) {
1966                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1967                                            "Failure uploading firmware1");
1968                         }
1969                         return;
1970                 }
1971         }
1972         hdw->fw1_state = FW1_STATE_OK;
1973
1974         if (!pvr2_hdw_dev_ok(hdw)) return;
1975
1976         for (idx = 0; idx < hdw->hdw_desc->client_modules.cnt; idx++) {
1977                 request_module(hdw->hdw_desc->client_modules.lst[idx]);
1978         }
1979
1980         if (!hdw->hdw_desc->flag_no_powerup) {
1981                 pvr2_hdw_cmd_powerup(hdw);
1982                 if (!pvr2_hdw_dev_ok(hdw)) return;
1983         }
1984
1985         /* Take the IR chip out of reset, if appropriate */
1986         if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
1987                 pvr2_issue_simple_cmd(hdw,
1988                                       FX2CMD_HCW_ZILOG_RESET |
1989                                       (1 << 8) |
1990                                       ((0) << 16));
1991         }
1992
1993         // This step MUST happen after the earlier powerup step.
1994         pvr2_i2c_track_init(hdw);
1995         pvr2_i2c_core_init(hdw);
1996         if (!pvr2_hdw_dev_ok(hdw)) return;
1997
1998         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1999                 cptr = hdw->controls + idx;
2000                 if (cptr->info->skip_init) continue;
2001                 if (!cptr->info->set_value) continue;
2002                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2003         }
2004
2005         /* Set up special default values for the television and radio
2006            frequencies here.  It's not really important what these defaults
2007            are, but I set them to something usable in the Chicago area just
2008            to make driver testing a little easier. */
2009
2010         hdw->freqValTelevision = default_tv_freq;
2011         hdw->freqValRadio = default_radio_freq;
2012
2013         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2014         // thread-safe against the normal pvr2_send_request() mechanism.
2015         // (We should make it thread safe).
2016
2017         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2018                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2019                 if (!pvr2_hdw_dev_ok(hdw)) return;
2020                 if (ret < 0) {
2021                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2022                                    "Unable to determine location of eeprom,"
2023                                    " skipping");
2024                 } else {
2025                         hdw->eeprom_addr = ret;
2026                         pvr2_eeprom_analyze(hdw);
2027                         if (!pvr2_hdw_dev_ok(hdw)) return;
2028                 }
2029         } else {
2030                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2031                 hdw->tuner_updated = !0;
2032                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2033         }
2034
2035         if (hdw->serial_number) {
2036                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2037                                 "sn-%lu", hdw->serial_number);
2038         } else if (hdw->unit_number >= 0) {
2039                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2040                                 "unit-%c",
2041                                 hdw->unit_number + 'a');
2042         } else {
2043                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2044                                 "unit-??");
2045         }
2046         hdw->identifier[idx] = 0;
2047
2048         pvr2_hdw_setup_std(hdw);
2049
2050         if (!get_default_tuner_type(hdw)) {
2051                 pvr2_trace(PVR2_TRACE_INIT,
2052                            "pvr2_hdw_setup: Tuner type overridden to %d",
2053                            hdw->tuner_type);
2054         }
2055
2056         pvr2_i2c_core_check_stale(hdw);
2057         hdw->tuner_updated = 0;
2058
2059         if (!pvr2_hdw_dev_ok(hdw)) return;
2060
2061         if (hdw->hdw_desc->signal_routing_scheme ==
2062             PVR2_ROUTING_SCHEME_GOTVIEW) {
2063                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2064                    hardware. */
2065                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2066         }
2067
2068         pvr2_hdw_commit_setup(hdw);
2069
2070         hdw->vid_stream = pvr2_stream_create();
2071         if (!pvr2_hdw_dev_ok(hdw)) return;
2072         pvr2_trace(PVR2_TRACE_INIT,
2073                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2074         if (hdw->vid_stream) {
2075                 idx = get_default_error_tolerance(hdw);
2076                 if (idx) {
2077                         pvr2_trace(PVR2_TRACE_INIT,
2078                                    "pvr2_hdw_setup: video stream %p"
2079                                    " setting tolerance %u",
2080                                    hdw->vid_stream,idx);
2081                 }
2082                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2083                                   PVR2_VID_ENDPOINT,idx);
2084         }
2085
2086         if (!pvr2_hdw_dev_ok(hdw)) return;
2087
2088         hdw->flag_init_ok = !0;
2089
2090         pvr2_hdw_state_sched(hdw);
2091 }
2092
2093
2094 /* Set up the structure and attempt to put the device into a usable state.
2095    This can be a time-consuming operation, which is why it is not done
2096    internally as part of the create() step. */
2097 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2098 {
2099         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2100         do {
2101                 pvr2_hdw_setup_low(hdw);
2102                 pvr2_trace(PVR2_TRACE_INIT,
2103                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2104                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2105                 if (pvr2_hdw_dev_ok(hdw)) {
2106                         if (hdw->flag_init_ok) {
2107                                 pvr2_trace(
2108                                         PVR2_TRACE_INFO,
2109                                         "Device initialization"
2110                                         " completed successfully.");
2111                                 break;
2112                         }
2113                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2114                                 pvr2_trace(
2115                                         PVR2_TRACE_INFO,
2116                                         "Device microcontroller firmware"
2117                                         " (re)loaded; it should now reset"
2118                                         " and reconnect.");
2119                                 break;
2120                         }
2121                         pvr2_trace(
2122                                 PVR2_TRACE_ERROR_LEGS,
2123                                 "Device initialization was not successful.");
2124                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2125                                 pvr2_trace(
2126                                         PVR2_TRACE_ERROR_LEGS,
2127                                         "Giving up since device"
2128                                         " microcontroller firmware"
2129                                         " appears to be missing.");
2130                                 break;
2131                         }
2132                 }
2133                 if (procreload) {
2134                         pvr2_trace(
2135                                 PVR2_TRACE_ERROR_LEGS,
2136                                 "Attempting pvrusb2 recovery by reloading"
2137                                 " primary firmware.");
2138                         pvr2_trace(
2139                                 PVR2_TRACE_ERROR_LEGS,
2140                                 "If this works, device should disconnect"
2141                                 " and reconnect in a sane state.");
2142                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2143                         pvr2_upload_firmware1(hdw);
2144                 } else {
2145                         pvr2_trace(
2146                                 PVR2_TRACE_ERROR_LEGS,
2147                                 "***WARNING*** pvrusb2 device hardware"
2148                                 " appears to be jammed"
2149                                 " and I can't clear it.");
2150                         pvr2_trace(
2151                                 PVR2_TRACE_ERROR_LEGS,
2152                                 "You might need to power cycle"
2153                                 " the pvrusb2 device"
2154                                 " in order to recover.");
2155                 }
2156         } while (0);
2157         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2158 }
2159
2160
2161 /* Perform second stage initialization.  Set callback pointer first so that
2162    we can avoid a possible initialization race (if the kernel thread runs
2163    before the callback has been set). */
2164 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2165                         void (*callback_func)(void *),
2166                         void *callback_data)
2167 {
2168         LOCK_TAKE(hdw->big_lock); do {
2169                 if (hdw->flag_disconnected) {
2170                         /* Handle a race here: If we're already
2171                            disconnected by this point, then give up.  If we
2172                            get past this then we'll remain connected for
2173                            the duration of initialization since the entire
2174                            initialization sequence is now protected by the
2175                            big_lock. */
2176                         break;
2177                 }
2178                 hdw->state_data = callback_data;
2179                 hdw->state_func = callback_func;
2180                 pvr2_hdw_setup(hdw);
2181         } while (0); LOCK_GIVE(hdw->big_lock);
2182         return hdw->flag_init_ok;
2183 }
2184
2185
2186 /* Create, set up, and return a structure for interacting with the
2187    underlying hardware.  */
2188 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2189                                  const struct usb_device_id *devid)
2190 {
2191         unsigned int idx,cnt1,cnt2,m;
2192         struct pvr2_hdw *hdw = NULL;
2193         int valid_std_mask;
2194         struct pvr2_ctrl *cptr;
2195         struct usb_device *usb_dev;
2196         const struct pvr2_device_desc *hdw_desc;
2197         __u8 ifnum;
2198         struct v4l2_queryctrl qctrl;
2199         struct pvr2_ctl_info *ciptr;
2200
2201         usb_dev = interface_to_usbdev(intf);
2202
2203         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2204
2205         if (hdw_desc == NULL) {
2206                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2207                            " No device description pointer,"
2208                            " unable to continue.");
2209                 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2210                            " please contact Mike Isely <isely@pobox.com>"
2211                            " to get it included in the driver\n");
2212                 goto fail;
2213         }
2214
2215         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2216         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2217                    hdw,hdw_desc->description);
2218         if (!hdw) goto fail;
2219
2220         init_timer(&hdw->quiescent_timer);
2221         hdw->quiescent_timer.data = (unsigned long)hdw;
2222         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2223
2224         init_timer(&hdw->encoder_wait_timer);
2225         hdw->encoder_wait_timer.data = (unsigned long)hdw;
2226         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2227
2228         init_timer(&hdw->encoder_run_timer);
2229         hdw->encoder_run_timer.data = (unsigned long)hdw;
2230         hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2231
2232         hdw->master_state = PVR2_STATE_DEAD;
2233
2234         init_waitqueue_head(&hdw->state_wait_data);
2235
2236         hdw->tuner_signal_stale = !0;
2237         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2238
2239         /* Calculate which inputs are OK */
2240         m = 0;
2241         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2242         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2243                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2244         }
2245         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2246         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2247         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2248         hdw->input_avail_mask = m;
2249         hdw->input_allowed_mask = hdw->input_avail_mask;
2250
2251         /* If not a hybrid device, pathway_state never changes.  So
2252            initialize it here to what it should forever be. */
2253         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2254                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2255         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2256                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2257         }
2258
2259         hdw->control_cnt = CTRLDEF_COUNT;
2260         hdw->control_cnt += MPEGDEF_COUNT;
2261         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2262                                 GFP_KERNEL);
2263         if (!hdw->controls) goto fail;
2264         hdw->hdw_desc = hdw_desc;
2265         for (idx = 0; idx < hdw->control_cnt; idx++) {
2266                 cptr = hdw->controls + idx;
2267                 cptr->hdw = hdw;
2268         }
2269         for (idx = 0; idx < 32; idx++) {
2270                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2271         }
2272         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2273                 cptr = hdw->controls + idx;
2274                 cptr->info = control_defs+idx;
2275         }
2276
2277         /* Ensure that default input choice is a valid one. */
2278         m = hdw->input_avail_mask;
2279         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2280                 if (!((1 << idx) & m)) continue;
2281                 hdw->input_val = idx;
2282                 break;
2283         }
2284
2285         /* Define and configure additional controls from cx2341x module. */
2286         hdw->mpeg_ctrl_info = kzalloc(
2287                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2288         if (!hdw->mpeg_ctrl_info) goto fail;
2289         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2290                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2291                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2292                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2293                 ciptr->name = mpeg_ids[idx].strid;
2294                 ciptr->v4l_id = mpeg_ids[idx].id;
2295                 ciptr->skip_init = !0;
2296                 ciptr->get_value = ctrl_cx2341x_get;
2297                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2298                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2299                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2300                 qctrl.id = ciptr->v4l_id;
2301                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2302                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2303                         ciptr->set_value = ctrl_cx2341x_set;
2304                 }
2305                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2306                         PVR2_CTLD_INFO_DESC_SIZE);
2307                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2308                 ciptr->default_value = qctrl.default_value;
2309                 switch (qctrl.type) {
2310                 default:
2311                 case V4L2_CTRL_TYPE_INTEGER:
2312                         ciptr->type = pvr2_ctl_int;
2313                         ciptr->def.type_int.min_value = qctrl.minimum;
2314                         ciptr->def.type_int.max_value = qctrl.maximum;
2315                         break;
2316                 case V4L2_CTRL_TYPE_BOOLEAN:
2317                         ciptr->type = pvr2_ctl_bool;
2318                         break;
2319                 case V4L2_CTRL_TYPE_MENU:
2320                         ciptr->type = pvr2_ctl_enum;
2321                         ciptr->def.type_enum.value_names =
2322                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2323                                                                 ciptr->v4l_id);
2324                         for (cnt1 = 0;
2325                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2326                              cnt1++) { }
2327                         ciptr->def.type_enum.count = cnt1;
2328                         break;
2329                 }
2330                 cptr->info = ciptr;
2331         }
2332
2333         // Initialize video standard enum dynamic control
2334         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2335         if (cptr) {
2336                 memcpy(&hdw->std_info_enum,cptr->info,
2337                        sizeof(hdw->std_info_enum));
2338                 cptr->info = &hdw->std_info_enum;
2339
2340         }
2341         // Initialize control data regarding video standard masks
2342         valid_std_mask = pvr2_std_get_usable();
2343         for (idx = 0; idx < 32; idx++) {
2344                 if (!(valid_std_mask & (1 << idx))) continue;
2345                 cnt1 = pvr2_std_id_to_str(
2346                         hdw->std_mask_names[idx],
2347                         sizeof(hdw->std_mask_names[idx])-1,
2348                         1 << idx);
2349                 hdw->std_mask_names[idx][cnt1] = 0;
2350         }
2351         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2352         if (cptr) {
2353                 memcpy(&hdw->std_info_avail,cptr->info,
2354                        sizeof(hdw->std_info_avail));
2355                 cptr->info = &hdw->std_info_avail;
2356                 hdw->std_info_avail.def.type_bitmask.bit_names =
2357                         hdw->std_mask_ptrs;
2358                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2359                         valid_std_mask;
2360         }
2361         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2362         if (cptr) {
2363                 memcpy(&hdw->std_info_cur,cptr->info,
2364                        sizeof(hdw->std_info_cur));
2365                 cptr->info = &hdw->std_info_cur;
2366                 hdw->std_info_cur.def.type_bitmask.bit_names =
2367                         hdw->std_mask_ptrs;
2368                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2369                         valid_std_mask;
2370         }
2371
2372         hdw->cropcap_stale = !0;
2373         hdw->eeprom_addr = -1;
2374         hdw->unit_number = -1;
2375         hdw->v4l_minor_number_video = -1;
2376         hdw->v4l_minor_number_vbi = -1;
2377         hdw->v4l_minor_number_radio = -1;
2378         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2379         if (!hdw->ctl_write_buffer) goto fail;
2380         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2381         if (!hdw->ctl_read_buffer) goto fail;
2382         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2383         if (!hdw->ctl_write_urb) goto fail;
2384         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2385         if (!hdw->ctl_read_urb) goto fail;
2386
2387         if (v4l2_device_register(&usb_dev->dev, &hdw->v4l2_dev) != 0) {
2388                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2389                            "Error registering with v4l core, giving up");
2390                 goto fail;
2391         }
2392         mutex_lock(&pvr2_unit_mtx); do {
2393                 for (idx = 0; idx < PVR_NUM; idx++) {
2394                         if (unit_pointers[idx]) continue;
2395                         hdw->unit_number = idx;
2396                         unit_pointers[idx] = hdw;
2397                         break;
2398                 }
2399         } while (0); mutex_unlock(&pvr2_unit_mtx);
2400
2401         cnt1 = 0;
2402         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2403         cnt1 += cnt2;
2404         if (hdw->unit_number >= 0) {
2405                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2406                                  ('a' + hdw->unit_number));
2407                 cnt1 += cnt2;
2408         }
2409         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2410         hdw->name[cnt1] = 0;
2411
2412         hdw->workqueue = create_singlethread_workqueue(hdw->name);
2413         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2414         INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2415
2416         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2417                    hdw->unit_number,hdw->name);
2418
2419         hdw->tuner_type = -1;
2420         hdw->flag_ok = !0;
2421
2422         hdw->usb_intf = intf;
2423         hdw->usb_dev = usb_dev;
2424
2425         usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2426
2427         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2428         usb_set_interface(hdw->usb_dev,ifnum,0);
2429
2430         mutex_init(&hdw->ctl_lock_mutex);
2431         mutex_init(&hdw->big_lock_mutex);
2432
2433         return hdw;
2434  fail:
2435         if (hdw) {
2436                 del_timer_sync(&hdw->quiescent_timer);
2437                 del_timer_sync(&hdw->encoder_run_timer);
2438                 del_timer_sync(&hdw->encoder_wait_timer);
2439                 if (hdw->workqueue) {
2440                         flush_workqueue(hdw->workqueue);
2441                         destroy_workqueue(hdw->workqueue);
2442                         hdw->workqueue = NULL;
2443                 }
2444                 usb_free_urb(hdw->ctl_read_urb);
2445                 usb_free_urb(hdw->ctl_write_urb);
2446                 kfree(hdw->ctl_read_buffer);
2447                 kfree(hdw->ctl_write_buffer);
2448                 kfree(hdw->controls);
2449                 kfree(hdw->mpeg_ctrl_info);
2450                 kfree(hdw->std_defs);
2451                 kfree(hdw->std_enum_names);
2452                 kfree(hdw);
2453         }
2454         return NULL;
2455 }
2456
2457
2458 /* Remove _all_ associations between this driver and the underlying USB
2459    layer. */
2460 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2461 {
2462         if (hdw->flag_disconnected) return;
2463         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2464         if (hdw->ctl_read_urb) {
2465                 usb_kill_urb(hdw->ctl_read_urb);
2466                 usb_free_urb(hdw->ctl_read_urb);
2467                 hdw->ctl_read_urb = NULL;
2468         }
2469         if (hdw->ctl_write_urb) {
2470                 usb_kill_urb(hdw->ctl_write_urb);
2471                 usb_free_urb(hdw->ctl_write_urb);
2472                 hdw->ctl_write_urb = NULL;
2473         }
2474         if (hdw->ctl_read_buffer) {
2475                 kfree(hdw->ctl_read_buffer);
2476                 hdw->ctl_read_buffer = NULL;
2477         }
2478         if (hdw->ctl_write_buffer) {
2479                 kfree(hdw->ctl_write_buffer);
2480                 hdw->ctl_write_buffer = NULL;
2481         }
2482         hdw->flag_disconnected = !0;
2483         /* If we don't do this, then there will be a dangling struct device
2484            reference to our disappearing device persisting inside the V4L
2485            core... */
2486         if (hdw->v4l2_dev.dev) {
2487                 dev_set_drvdata(hdw->v4l2_dev.dev, NULL);
2488                 hdw->v4l2_dev.dev = NULL;
2489         }
2490         hdw->usb_dev = NULL;
2491         hdw->usb_intf = NULL;
2492         pvr2_hdw_render_useless(hdw);
2493 }
2494
2495
2496 /* Destroy hardware interaction structure */
2497 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2498 {
2499         if (!hdw) return;
2500         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2501         if (hdw->workqueue) {
2502                 flush_workqueue(hdw->workqueue);
2503                 destroy_workqueue(hdw->workqueue);
2504                 hdw->workqueue = NULL;
2505         }
2506         del_timer_sync(&hdw->quiescent_timer);
2507         del_timer_sync(&hdw->encoder_run_timer);
2508         del_timer_sync(&hdw->encoder_wait_timer);
2509         if (hdw->fw_buffer) {
2510                 kfree(hdw->fw_buffer);
2511                 hdw->fw_buffer = NULL;
2512         }
2513         if (hdw->vid_stream) {
2514                 pvr2_stream_destroy(hdw->vid_stream);
2515                 hdw->vid_stream = NULL;
2516         }
2517         if (hdw->decoder_ctrl) {
2518                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2519         }
2520         pvr2_i2c_core_done(hdw);
2521         pvr2_i2c_track_done(hdw);
2522         v4l2_device_unregister(&hdw->v4l2_dev);
2523         pvr2_hdw_remove_usb_stuff(hdw);
2524         mutex_lock(&pvr2_unit_mtx); do {
2525                 if ((hdw->unit_number >= 0) &&
2526                     (hdw->unit_number < PVR_NUM) &&
2527                     (unit_pointers[hdw->unit_number] == hdw)) {
2528                         unit_pointers[hdw->unit_number] = NULL;
2529                 }
2530         } while (0); mutex_unlock(&pvr2_unit_mtx);
2531         kfree(hdw->controls);
2532         kfree(hdw->mpeg_ctrl_info);
2533         kfree(hdw->std_defs);
2534         kfree(hdw->std_enum_names);
2535         kfree(hdw);
2536 }
2537
2538
2539 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2540 {
2541         return (hdw && hdw->flag_ok);
2542 }
2543
2544
2545 /* Called when hardware has been unplugged */
2546 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2547 {
2548         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2549         LOCK_TAKE(hdw->big_lock);
2550         LOCK_TAKE(hdw->ctl_lock);
2551         pvr2_hdw_remove_usb_stuff(hdw);
2552         LOCK_GIVE(hdw->ctl_lock);
2553         LOCK_GIVE(hdw->big_lock);
2554 }
2555
2556
2557 // Attempt to autoselect an appropriate value for std_enum_cur given
2558 // whatever is currently in std_mask_cur
2559 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2560 {
2561         unsigned int idx;
2562         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2563                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2564                         hdw->std_enum_cur = idx;
2565                         return;
2566                 }
2567         }
2568         hdw->std_enum_cur = 0;
2569 }
2570
2571
2572 // Calculate correct set of enumerated standards based on currently known
2573 // set of available standards bits.
2574 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2575 {
2576         struct v4l2_standard *newstd;
2577         unsigned int std_cnt;
2578         unsigned int idx;
2579
2580         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2581
2582         if (hdw->std_defs) {
2583                 kfree(hdw->std_defs);
2584                 hdw->std_defs = NULL;
2585         }
2586         hdw->std_enum_cnt = 0;
2587         if (hdw->std_enum_names) {
2588                 kfree(hdw->std_enum_names);
2589                 hdw->std_enum_names = NULL;
2590         }
2591
2592         if (!std_cnt) {
2593                 pvr2_trace(
2594                         PVR2_TRACE_ERROR_LEGS,
2595                         "WARNING: Failed to identify any viable standards");
2596         }
2597         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2598         hdw->std_enum_names[0] = "none";
2599         for (idx = 0; idx < std_cnt; idx++) {
2600                 hdw->std_enum_names[idx+1] =
2601                         newstd[idx].name;
2602         }
2603         // Set up the dynamic control for this standard
2604         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2605         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2606         hdw->std_defs = newstd;
2607         hdw->std_enum_cnt = std_cnt+1;
2608         hdw->std_enum_cur = 0;
2609         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2610 }
2611
2612
2613 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2614                                struct v4l2_standard *std,
2615                                unsigned int idx)
2616 {
2617         int ret = -EINVAL;
2618         if (!idx) return ret;
2619         LOCK_TAKE(hdw->big_lock); do {
2620                 if (idx >= hdw->std_enum_cnt) break;
2621                 idx--;
2622                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2623                 ret = 0;
2624         } while (0); LOCK_GIVE(hdw->big_lock);
2625         return ret;
2626 }
2627
2628
2629 /* Get the number of defined controls */
2630 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2631 {
2632         return hdw->control_cnt;
2633 }
2634
2635
2636 /* Retrieve a control handle given its index (0..count-1) */
2637 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2638                                              unsigned int idx)
2639 {
2640         if (idx >= hdw->control_cnt) return NULL;
2641         return hdw->controls + idx;
2642 }
2643
2644
2645 /* Retrieve a control handle given its index (0..count-1) */
2646 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2647                                           unsigned int ctl_id)
2648 {
2649         struct pvr2_ctrl *cptr;
2650         unsigned int idx;
2651         int i;
2652
2653         /* This could be made a lot more efficient, but for now... */
2654         for (idx = 0; idx < hdw->control_cnt; idx++) {
2655                 cptr = hdw->controls + idx;
2656                 i = cptr->info->internal_id;
2657                 if (i && (i == ctl_id)) return cptr;
2658         }
2659         return NULL;
2660 }
2661
2662
2663 /* Given a V4L ID, retrieve the control structure associated with it. */
2664 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2665 {
2666         struct pvr2_ctrl *cptr;
2667         unsigned int idx;
2668         int i;
2669
2670         /* This could be made a lot more efficient, but for now... */
2671         for (idx = 0; idx < hdw->control_cnt; idx++) {
2672                 cptr = hdw->controls + idx;
2673                 i = cptr->info->v4l_id;
2674                 if (i && (i == ctl_id)) return cptr;
2675         }
2676         return NULL;
2677 }
2678
2679
2680 /* Given a V4L ID for its immediate predecessor, retrieve the control
2681    structure associated with it. */
2682 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2683                                             unsigned int ctl_id)
2684 {
2685         struct pvr2_ctrl *cptr,*cp2;
2686         unsigned int idx;
2687         int i;
2688
2689         /* This could be made a lot more efficient, but for now... */
2690         cp2 = NULL;
2691         for (idx = 0; idx < hdw->control_cnt; idx++) {
2692                 cptr = hdw->controls + idx;
2693                 i = cptr->info->v4l_id;
2694                 if (!i) continue;
2695                 if (i <= ctl_id) continue;
2696                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2697                 cp2 = cptr;
2698         }
2699         return cp2;
2700         return NULL;
2701 }
2702
2703
2704 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2705 {
2706         switch (tp) {
2707         case pvr2_ctl_int: return "integer";
2708         case pvr2_ctl_enum: return "enum";
2709         case pvr2_ctl_bool: return "boolean";
2710         case pvr2_ctl_bitmask: return "bitmask";
2711         }
2712         return "";
2713 }
2714
2715
2716 /* Figure out if we need to commit control changes.  If so, mark internal
2717    state flags to indicate this fact and return true.  Otherwise do nothing
2718    else and return false. */
2719 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2720 {
2721         unsigned int idx;
2722         struct pvr2_ctrl *cptr;
2723         int value;
2724         int commit_flag = 0;
2725         char buf[100];
2726         unsigned int bcnt,ccnt;
2727
2728         for (idx = 0; idx < hdw->control_cnt; idx++) {
2729                 cptr = hdw->controls + idx;
2730                 if (!cptr->info->is_dirty) continue;
2731                 if (!cptr->info->is_dirty(cptr)) continue;
2732                 commit_flag = !0;
2733
2734                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2735                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2736                                  cptr->info->name);
2737                 value = 0;
2738                 cptr->info->get_value(cptr,&value);
2739                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2740                                                 buf+bcnt,
2741                                                 sizeof(buf)-bcnt,&ccnt);
2742                 bcnt += ccnt;
2743                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2744                                   get_ctrl_typename(cptr->info->type));
2745                 pvr2_trace(PVR2_TRACE_CTL,
2746                            "/*--TRACE_COMMIT--*/ %.*s",
2747                            bcnt,buf);
2748         }
2749
2750         if (!commit_flag) {
2751                 /* Nothing has changed */
2752                 return 0;
2753         }
2754
2755         hdw->state_pipeline_config = 0;
2756         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2757         pvr2_hdw_state_sched(hdw);
2758
2759         return !0;
2760 }
2761
2762
2763 /* Perform all operations needed to commit all control changes.  This must
2764    be performed in synchronization with the pipeline state and is thus
2765    expected to be called as part of the driver's worker thread.  Return
2766    true if commit successful, otherwise return false to indicate that
2767    commit isn't possible at this time. */
2768 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
2769 {
2770         unsigned int idx;
2771         struct pvr2_ctrl *cptr;
2772         int disruptive_change;
2773
2774         /* Handle some required side effects when the video standard is
2775            changed.... */
2776         if (hdw->std_dirty) {
2777                 int nvres;
2778                 int gop_size;
2779                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2780                         nvres = 480;
2781                         gop_size = 15;
2782                 } else {
2783                         nvres = 576;
2784                         gop_size = 12;
2785                 }
2786                 /* Rewrite the vertical resolution to be appropriate to the
2787                    video standard that has been selected. */
2788                 if (nvres != hdw->res_ver_val) {
2789                         hdw->res_ver_val = nvres;
2790                         hdw->res_ver_dirty = !0;
2791                 }
2792                 /* Rewrite the GOP size to be appropriate to the video
2793                    standard that has been selected. */
2794                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
2795                         struct v4l2_ext_controls cs;
2796                         struct v4l2_ext_control c1;
2797                         memset(&cs, 0, sizeof(cs));
2798                         memset(&c1, 0, sizeof(c1));
2799                         cs.controls = &c1;
2800                         cs.count = 1;
2801                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
2802                         c1.value = gop_size;
2803                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
2804                                           VIDIOC_S_EXT_CTRLS);
2805                 }
2806         }
2807
2808         if (hdw->input_dirty && hdw->state_pathway_ok &&
2809             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
2810               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
2811              hdw->pathway_state)) {
2812                 /* Change of mode being asked for... */
2813                 hdw->state_pathway_ok = 0;
2814                 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
2815         }
2816         if (!hdw->state_pathway_ok) {
2817                 /* Can't commit anything until pathway is ok. */
2818                 return 0;
2819         }
2820         /* The broadcast decoder can only scale down, so if
2821          * res_*_dirty && crop window < output format ==> enlarge crop.
2822          *
2823          * The mpeg encoder receives fields of res_hor_val dots and
2824          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
2825          */
2826         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
2827                 hdw->cropw_val = hdw->res_hor_val;
2828                 hdw->cropw_dirty = !0;
2829         } else if (hdw->cropw_dirty) {
2830                 hdw->res_hor_dirty = !0;           /* must rescale */
2831                 hdw->res_hor_val = min(720, hdw->cropw_val);
2832         }
2833         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
2834                 hdw->croph_val = hdw->res_ver_val;
2835                 hdw->croph_dirty = !0;
2836         } else if (hdw->croph_dirty) {
2837                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
2838                 hdw->res_ver_dirty = !0;
2839                 hdw->res_ver_val = min(nvres, hdw->croph_val);
2840         }
2841
2842         /* If any of the below has changed, then we can't do the update
2843            while the pipeline is running.  Pipeline must be paused first
2844            and decoder -> encoder connection be made quiescent before we
2845            can proceed. */
2846         disruptive_change =
2847                 (hdw->std_dirty ||
2848                  hdw->enc_unsafe_stale ||
2849                  hdw->srate_dirty ||
2850                  hdw->res_ver_dirty ||
2851                  hdw->res_hor_dirty ||
2852                  hdw->cropw_dirty ||
2853                  hdw->croph_dirty ||
2854                  hdw->input_dirty ||
2855                  (hdw->active_stream_type != hdw->desired_stream_type));
2856         if (disruptive_change && !hdw->state_pipeline_idle) {
2857                 /* Pipeline is not idle; we can't proceed.  Arrange to
2858                    cause pipeline to stop so that we can try this again
2859                    later.... */
2860                 hdw->state_pipeline_pause = !0;
2861                 return 0;
2862         }
2863
2864         if (hdw->srate_dirty) {
2865                 /* Write new sample rate into control structure since
2866                  * the master copy is stale.  We must track srate
2867                  * separate from the mpeg control structure because
2868                  * other logic also uses this value. */
2869                 struct v4l2_ext_controls cs;
2870                 struct v4l2_ext_control c1;
2871                 memset(&cs,0,sizeof(cs));
2872                 memset(&c1,0,sizeof(c1));
2873                 cs.controls = &c1;
2874                 cs.count = 1;
2875                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2876                 c1.value = hdw->srate_val;
2877                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
2878         }
2879
2880         /* Scan i2c core at this point - before we clear all the dirty
2881            bits.  Various parts of the i2c core will notice dirty bits as
2882            appropriate and arrange to broadcast or directly send updates to
2883            the client drivers in order to keep everything in sync */
2884         pvr2_i2c_core_check_stale(hdw);
2885
2886         for (idx = 0; idx < hdw->control_cnt; idx++) {
2887                 cptr = hdw->controls + idx;
2888                 if (!cptr->info->clear_dirty) continue;
2889                 cptr->info->clear_dirty(cptr);
2890         }
2891
2892         if (hdw->active_stream_type != hdw->desired_stream_type) {
2893                 /* Handle any side effects of stream config here */
2894                 hdw->active_stream_type = hdw->desired_stream_type;
2895         }
2896
2897         if (hdw->hdw_desc->signal_routing_scheme ==
2898             PVR2_ROUTING_SCHEME_GOTVIEW) {
2899                 u32 b;
2900                 /* Handle GOTVIEW audio switching */
2901                 pvr2_hdw_gpio_get_out(hdw,&b);
2902                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2903                         /* Set GPIO 11 */
2904                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
2905                 } else {
2906                         /* Clear GPIO 11 */
2907                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
2908                 }
2909         }
2910
2911         /* Now execute i2c core update */
2912         pvr2_i2c_core_sync(hdw);
2913
2914         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
2915             hdw->state_encoder_run) {
2916                 /* If encoder isn't running or it can't be touched, then
2917                    this will get worked out later when we start the
2918                    encoder. */
2919                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
2920         }
2921
2922         hdw->state_pipeline_config = !0;
2923         /* Hardware state may have changed in a way to cause the cropping
2924            capabilities to have changed.  So mark it stale, which will
2925            cause a later re-fetch. */
2926         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2927         return !0;
2928 }
2929
2930
2931 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2932 {
2933         int fl;
2934         LOCK_TAKE(hdw->big_lock);
2935         fl = pvr2_hdw_commit_setup(hdw);
2936         LOCK_GIVE(hdw->big_lock);
2937         if (!fl) return 0;
2938         return pvr2_hdw_wait(hdw,0);
2939 }
2940
2941
2942 static void pvr2_hdw_worker_i2c(struct work_struct *work)
2943 {
2944         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
2945         LOCK_TAKE(hdw->big_lock); do {
2946                 pvr2_i2c_core_sync(hdw);
2947         } while (0); LOCK_GIVE(hdw->big_lock);
2948 }
2949
2950
2951 static void pvr2_hdw_worker_poll(struct work_struct *work)
2952 {
2953         int fl = 0;
2954         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
2955         LOCK_TAKE(hdw->big_lock); do {
2956                 fl = pvr2_hdw_state_eval(hdw);
2957         } while (0); LOCK_GIVE(hdw->big_lock);
2958         if (fl && hdw->state_func) {
2959                 hdw->state_func(hdw->state_data);
2960         }
2961 }
2962
2963
2964 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
2965 {
2966         return wait_event_interruptible(
2967                 hdw->state_wait_data,
2968                 (hdw->state_stale == 0) &&
2969                 (!state || (hdw->master_state != state)));
2970 }
2971
2972
2973 /* Return name for this driver instance */
2974 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2975 {
2976         return hdw->name;
2977 }
2978
2979
2980 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
2981 {
2982         return hdw->hdw_desc->description;
2983 }
2984
2985
2986 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
2987 {
2988         return hdw->hdw_desc->shortname;
2989 }
2990
2991
2992 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2993 {
2994         int result;
2995         LOCK_TAKE(hdw->ctl_lock); do {
2996                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
2997                 result = pvr2_send_request(hdw,
2998                                            hdw->cmd_buffer,1,
2999                                            hdw->cmd_buffer,1);
3000                 if (result < 0) break;
3001                 result = (hdw->cmd_buffer[0] != 0);
3002         } while(0); LOCK_GIVE(hdw->ctl_lock);
3003         return result;
3004 }
3005
3006
3007 /* Execute poll of tuner status */
3008 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3009 {
3010         LOCK_TAKE(hdw->big_lock); do {
3011                 pvr2_hdw_status_poll(hdw);
3012         } while (0); LOCK_GIVE(hdw->big_lock);
3013 }
3014
3015
3016 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3017 {
3018         if (!hdw->cropcap_stale) {
3019                 return 0;
3020         }
3021         pvr2_hdw_status_poll(hdw);
3022         if (hdw->cropcap_stale) {
3023                 return -EIO;
3024         }
3025         return 0;
3026 }
3027
3028
3029 /* Return information about cropping capabilities */
3030 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3031 {
3032         int stat = 0;
3033         LOCK_TAKE(hdw->big_lock);
3034         stat = pvr2_hdw_check_cropcap(hdw);
3035         if (!stat) {
3036                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3037         }
3038         LOCK_GIVE(hdw->big_lock);
3039         return stat;
3040 }
3041
3042
3043 /* Return information about the tuner */
3044 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3045 {
3046         LOCK_TAKE(hdw->big_lock); do {
3047                 if (hdw->tuner_signal_stale) {
3048                         pvr2_hdw_status_poll(hdw);
3049                 }
3050                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3051         } while (0); LOCK_GIVE(hdw->big_lock);
3052         return 0;
3053 }
3054
3055
3056 /* Get handle to video output stream */
3057 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3058 {
3059         return hp->vid_stream;
3060 }
3061
3062
3063 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3064 {
3065         int nr = pvr2_hdw_get_unit_number(hdw);
3066         LOCK_TAKE(hdw->big_lock); do {
3067                 hdw->log_requested = !0;
3068                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3069                 pvr2_i2c_core_check_stale(hdw);
3070                 pvr2_i2c_core_sync(hdw);
3071                 hdw->log_requested = 0;
3072                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3073                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3074                 pvr2_hdw_state_log_state(hdw);
3075                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3076         } while (0); LOCK_GIVE(hdw->big_lock);
3077 }
3078
3079
3080 /* Grab EEPROM contents, needed for direct method. */
3081 #define EEPROM_SIZE 8192
3082 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3083 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3084 {
3085         struct i2c_msg msg[2];
3086         u8 *eeprom;
3087         u8 iadd[2];
3088         u8 addr;
3089         u16 eepromSize;
3090         unsigned int offs;
3091         int ret;
3092         int mode16 = 0;
3093         unsigned pcnt,tcnt;
3094         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3095         if (!eeprom) {
3096                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3097                            "Failed to allocate memory"
3098                            " required to read eeprom");
3099                 return NULL;
3100         }
3101
3102         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3103                      hdw->eeprom_addr);
3104         addr = hdw->eeprom_addr;
3105         /* Seems that if the high bit is set, then the *real* eeprom
3106            address is shifted right now bit position (noticed this in
3107            newer PVR USB2 hardware) */
3108         if (addr & 0x80) addr >>= 1;
3109
3110         /* FX2 documentation states that a 16bit-addressed eeprom is
3111            expected if the I2C address is an odd number (yeah, this is
3112            strange but it's what they do) */
3113         mode16 = (addr & 1);
3114         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3115         trace_eeprom("Examining %d byte eeprom at location 0x%x"
3116                      " using %d bit addressing",eepromSize,addr,
3117                      mode16 ? 16 : 8);
3118
3119         msg[0].addr = addr;
3120         msg[0].flags = 0;
3121         msg[0].len = mode16 ? 2 : 1;
3122         msg[0].buf = iadd;
3123         msg[1].addr = addr;
3124         msg[1].flags = I2C_M_RD;
3125
3126         /* We have to do the actual eeprom data fetch ourselves, because
3127            (1) we're only fetching part of the eeprom, and (2) if we were
3128            getting the whole thing our I2C driver can't grab it in one
3129            pass - which is what tveeprom is otherwise going to attempt */
3130         memset(eeprom,0,EEPROM_SIZE);
3131         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3132                 pcnt = 16;
3133                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3134                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3135                 if (mode16) {
3136                         iadd[0] = offs >> 8;
3137                         iadd[1] = offs;
3138                 } else {
3139                         iadd[0] = offs;
3140                 }
3141                 msg[1].len = pcnt;
3142                 msg[1].buf = eeprom+tcnt;
3143                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3144                                         msg,ARRAY_SIZE(msg))) != 2) {
3145                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3146                                    "eeprom fetch set offs err=%d",ret);
3147                         kfree(eeprom);
3148                         return NULL;
3149                 }
3150         }
3151         return eeprom;
3152 }
3153
3154
3155 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3156                                 int prom_flag,
3157                                 int enable_flag)
3158 {
3159         int ret;
3160         u16 address;
3161         unsigned int pipe;
3162         LOCK_TAKE(hdw->big_lock); do {
3163                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3164
3165                 if (!enable_flag) {
3166                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3167                                    "Cleaning up after CPU firmware fetch");
3168                         kfree(hdw->fw_buffer);
3169                         hdw->fw_buffer = NULL;
3170                         hdw->fw_size = 0;
3171                         if (hdw->fw_cpu_flag) {
3172                                 /* Now release the CPU.  It will disconnect
3173                                    and reconnect later. */
3174                                 pvr2_hdw_cpureset_assert(hdw,0);
3175                         }
3176                         break;
3177                 }
3178
3179                 hdw->fw_cpu_flag = (prom_flag == 0);
3180                 if (hdw->fw_cpu_flag) {
3181                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3182                                    "Preparing to suck out CPU firmware");
3183                         hdw->fw_size = 0x2000;
3184                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3185                         if (!hdw->fw_buffer) {
3186                                 hdw->fw_size = 0;
3187                                 break;
3188                         }
3189
3190                         /* We have to hold the CPU during firmware upload. */
3191                         pvr2_hdw_cpureset_assert(hdw,1);
3192
3193                         /* download the firmware from address 0000-1fff in 2048
3194                            (=0x800) bytes chunk. */
3195
3196                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3197                                    "Grabbing CPU firmware");
3198                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3199                         for(address = 0; address < hdw->fw_size;
3200                             address += 0x800) {
3201                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3202                                                       0xa0,0xc0,
3203                                                       address,0,
3204                                                       hdw->fw_buffer+address,
3205                                                       0x800,HZ);
3206                                 if (ret < 0) break;
3207                         }
3208
3209                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3210                                    "Done grabbing CPU firmware");
3211                 } else {
3212                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3213                                    "Sucking down EEPROM contents");
3214                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3215                         if (!hdw->fw_buffer) {
3216                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3217                                            "EEPROM content suck failed.");
3218                                 break;
3219                         }
3220                         hdw->fw_size = EEPROM_SIZE;
3221                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3222                                    "Done sucking down EEPROM contents");
3223                 }
3224
3225         } while (0); LOCK_GIVE(hdw->big_lock);
3226 }
3227
3228
3229 /* Return true if we're in a mode for retrieval CPU firmware */
3230 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3231 {
3232         return hdw->fw_buffer != NULL;
3233 }
3234
3235
3236 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3237                        char *buf,unsigned int cnt)
3238 {
3239         int ret = -EINVAL;
3240         LOCK_TAKE(hdw->big_lock); do {
3241                 if (!buf) break;
3242                 if (!cnt) break;
3243
3244                 if (!hdw->fw_buffer) {
3245                         ret = -EIO;
3246                         break;
3247                 }
3248
3249                 if (offs >= hdw->fw_size) {
3250                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3251                                    "Read firmware data offs=%d EOF",
3252                                    offs);
3253                         ret = 0;
3254                         break;
3255                 }
3256
3257                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3258
3259                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3260
3261                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3262                            "Read firmware data offs=%d cnt=%d",
3263                            offs,cnt);
3264                 ret = cnt;
3265         } while (0); LOCK_GIVE(hdw->big_lock);
3266
3267         return ret;
3268 }
3269
3270
3271 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3272                                   enum pvr2_v4l_type index)
3273 {
3274         switch (index) {
3275         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3276         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3277         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3278         default: return -1;
3279         }
3280 }
3281
3282
3283 /* Store a v4l minor device number */
3284 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3285                                      enum pvr2_v4l_type index,int v)
3286 {
3287         switch (index) {
3288         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3289         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3290         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
3291         default: break;
3292         }
3293 }
3294
3295
3296 static void pvr2_ctl_write_complete(struct urb *urb)
3297 {
3298         struct pvr2_hdw *hdw = urb->context;
3299         hdw->ctl_write_pend_flag = 0;
3300         if (hdw->ctl_read_pend_flag) return;
3301         complete(&hdw->ctl_done);
3302 }
3303
3304
3305 static void pvr2_ctl_read_complete(struct urb *urb)
3306 {
3307         struct pvr2_hdw *hdw = urb->context;
3308         hdw->ctl_read_pend_flag = 0;
3309         if (hdw->ctl_write_pend_flag) return;
3310         complete(&hdw->ctl_done);
3311 }
3312
3313
3314 static void pvr2_ctl_timeout(unsigned long data)
3315 {
3316         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3317         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3318                 hdw->ctl_timeout_flag = !0;
3319                 if (hdw->ctl_write_pend_flag)
3320                         usb_unlink_urb(hdw->ctl_write_urb);
3321                 if (hdw->ctl_read_pend_flag)
3322                         usb_unlink_urb(hdw->ctl_read_urb);
3323         }
3324 }
3325
3326
3327 /* Issue a command and get a response from the device.  This extended
3328    version includes a probe flag (which if set means that device errors
3329    should not be logged or treated as fatal) and a timeout in jiffies.
3330    This can be used to non-lethally probe the health of endpoint 1. */
3331 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3332                                 unsigned int timeout,int probe_fl,
3333                                 void *write_data,unsigned int write_len,
3334                                 void *read_data,unsigned int read_len)
3335 {
3336         unsigned int idx;
3337         int status = 0;
3338         struct timer_list timer;
3339         if (!hdw->ctl_lock_held) {
3340                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3341                            "Attempted to execute control transfer"
3342                            " without lock!!");
3343                 return -EDEADLK;
3344         }
3345         if (!hdw->flag_ok && !probe_fl) {
3346                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3347                            "Attempted to execute control transfer"
3348                            " when device not ok");
3349                 return -EIO;
3350         }
3351         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3352                 if (!probe_fl) {
3353                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3354                                    "Attempted to execute control transfer"
3355                                    " when USB is disconnected");
3356                 }
3357                 return -ENOTTY;
3358         }
3359
3360         /* Ensure that we have sane parameters */
3361         if (!write_data) write_len = 0;
3362         if (!read_data) read_len = 0;
3363         if (write_len > PVR2_CTL_BUFFSIZE) {
3364                 pvr2_trace(
3365                         PVR2_TRACE_ERROR_LEGS,
3366                         "Attempted to execute %d byte"
3367                         " control-write transfer (limit=%d)",
3368                         write_len,PVR2_CTL_BUFFSIZE);
3369                 return -EINVAL;
3370         }
3371         if (read_len > PVR2_CTL_BUFFSIZE) {
3372                 pvr2_trace(
3373                         PVR2_TRACE_ERROR_LEGS,
3374                         "Attempted to execute %d byte"
3375                         " control-read transfer (limit=%d)",
3376                         write_len,PVR2_CTL_BUFFSIZE);
3377                 return -EINVAL;
3378         }
3379         if ((!write_len) && (!read_len)) {
3380                 pvr2_trace(
3381                         PVR2_TRACE_ERROR_LEGS,
3382                         "Attempted to execute null control transfer?");
3383                 return -EINVAL;
3384         }
3385
3386
3387         hdw->cmd_debug_state = 1;
3388         if (write_len) {
3389                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3390         } else {
3391                 hdw->cmd_debug_code = 0;
3392         }
3393         hdw->cmd_debug_write_len = write_len;
3394         hdw->cmd_debug_read_len = read_len;
3395
3396         /* Initialize common stuff */
3397         init_completion(&hdw->ctl_done);
3398         hdw->ctl_timeout_flag = 0;
3399         hdw->ctl_write_pend_flag = 0;
3400         hdw->ctl_read_pend_flag = 0;
3401         init_timer(&timer);
3402         timer.expires = jiffies + timeout;
3403         timer.data = (unsigned long)hdw;
3404         timer.function = pvr2_ctl_timeout;
3405
3406         if (write_len) {
3407                 hdw->cmd_debug_state = 2;
3408                 /* Transfer write data to internal buffer */
3409                 for (idx = 0; idx < write_len; idx++) {
3410                         hdw->ctl_write_buffer[idx] =
3411                                 ((unsigned char *)write_data)[idx];
3412                 }
3413                 /* Initiate a write request */
3414                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3415                                   hdw->usb_dev,
3416                                   usb_sndbulkpipe(hdw->usb_dev,
3417                                                   PVR2_CTL_WRITE_ENDPOINT),
3418                                   hdw->ctl_write_buffer,
3419                                   write_len,
3420                                   pvr2_ctl_write_complete,
3421                                   hdw);
3422                 hdw->ctl_write_urb->actual_length = 0;
3423                 hdw->ctl_write_pend_flag = !0;
3424                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3425                 if (status < 0) {
3426                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3427                                    "Failed to submit write-control"
3428                                    " URB status=%d",status);
3429                         hdw->ctl_write_pend_flag = 0;
3430                         goto done;
3431                 }
3432         }
3433
3434         if (read_len) {
3435                 hdw->cmd_debug_state = 3;
3436                 memset(hdw->ctl_read_buffer,0x43,read_len);
3437                 /* Initiate a read request */
3438                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3439                                   hdw->usb_dev,
3440                                   usb_rcvbulkpipe(hdw->usb_dev,
3441                                                   PVR2_CTL_READ_ENDPOINT),
3442                                   hdw->ctl_read_buffer,
3443                                   read_len,
3444                                   pvr2_ctl_read_complete,
3445                                   hdw);
3446                 hdw->ctl_read_urb->actual_length = 0;
3447                 hdw->ctl_read_pend_flag = !0;
3448                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3449                 if (status < 0) {
3450                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3451                                    "Failed to submit read-control"
3452                                    " URB status=%d",status);
3453                         hdw->ctl_read_pend_flag = 0;
3454                         goto done;
3455                 }
3456         }
3457
3458         /* Start timer */
3459         add_timer(&timer);
3460
3461         /* Now wait for all I/O to complete */
3462         hdw->cmd_debug_state = 4;
3463         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3464                 wait_for_completion(&hdw->ctl_done);
3465         }
3466         hdw->cmd_debug_state = 5;
3467
3468         /* Stop timer */
3469         del_timer_sync(&timer);
3470
3471         hdw->cmd_debug_state = 6;
3472         status = 0;
3473
3474         if (hdw->ctl_timeout_flag) {
3475                 status = -ETIMEDOUT;
3476                 if (!probe_fl) {
3477                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3478                                    "Timed out control-write");
3479                 }
3480                 goto done;
3481         }
3482
3483         if (write_len) {
3484                 /* Validate results of write request */
3485                 if ((hdw->ctl_write_urb->status != 0) &&
3486                     (hdw->ctl_write_urb->status != -ENOENT) &&
3487                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3488                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3489                         /* USB subsystem is reporting some kind of failure
3490                            on the write */
3491                         status = hdw->ctl_write_urb->status;
3492                         if (!probe_fl) {
3493                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3494                                            "control-write URB failure,"
3495                                            " status=%d",
3496                                            status);
3497                         }
3498                         goto done;
3499                 }
3500                 if (hdw->ctl_write_urb->actual_length < write_len) {
3501                         /* Failed to write enough data */
3502                         status = -EIO;
3503                         if (!probe_fl) {
3504                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3505                                            "control-write URB short,"
3506                                            " expected=%d got=%d",
3507                                            write_len,
3508                                            hdw->ctl_write_urb->actual_length);
3509                         }
3510                         goto done;
3511                 }
3512         }
3513         if (read_len) {
3514                 /* Validate results of read request */
3515                 if ((hdw->ctl_read_urb->status != 0) &&
3516                     (hdw->ctl_read_urb->status != -ENOENT) &&
3517                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3518                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3519                         /* USB subsystem is reporting some kind of failure
3520                            on the read */
3521                         status = hdw->ctl_read_urb->status;
3522                         if (!probe_fl) {
3523                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3524                                            "control-read URB failure,"
3525                                            " status=%d",
3526                                            status);
3527                         }
3528                         goto done;
3529                 }
3530                 if (hdw->ctl_read_urb->actual_length < read_len) {
3531                         /* Failed to read enough data */
3532                         status = -EIO;
3533                         if (!probe_fl) {
3534                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3535                                            "control-read URB short,"
3536                                            " expected=%d got=%d",
3537                                            read_len,
3538                                            hdw->ctl_read_urb->actual_length);
3539                         }
3540                         goto done;
3541                 }
3542                 /* Transfer retrieved data out from internal buffer */
3543                 for (idx = 0; idx < read_len; idx++) {
3544                         ((unsigned char *)read_data)[idx] =
3545                                 hdw->ctl_read_buffer[idx];
3546                 }
3547         }
3548
3549  done:
3550
3551         hdw->cmd_debug_state = 0;
3552         if ((status < 0) && (!probe_fl)) {
3553                 pvr2_hdw_render_useless(hdw);
3554         }
3555         return status;
3556 }
3557
3558
3559 int pvr2_send_request(struct pvr2_hdw *hdw,
3560                       void *write_data,unsigned int write_len,
3561                       void *read_data,unsigned int read_len)
3562 {
3563         return pvr2_send_request_ex(hdw,HZ*4,0,
3564                                     write_data,write_len,
3565                                     read_data,read_len);
3566 }
3567
3568
3569 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3570 {
3571         int ret;
3572         unsigned int cnt = 1;
3573         unsigned int args = 0;
3574         LOCK_TAKE(hdw->ctl_lock);
3575         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3576         args = (cmdcode >> 8) & 0xffu;
3577         args = (args > 2) ? 2 : args;
3578         if (args) {
3579                 cnt += args;
3580                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3581                 if (args > 1) {
3582                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3583                 }
3584         }
3585         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3586                 unsigned int idx;
3587                 unsigned int ccnt,bcnt;
3588                 char tbuf[50];
3589                 cmdcode &= 0xffu;
3590                 bcnt = 0;
3591                 ccnt = scnprintf(tbuf+bcnt,
3592                                  sizeof(tbuf)-bcnt,
3593                                  "Sending FX2 command 0x%x",cmdcode);
3594                 bcnt += ccnt;
3595                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3596                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3597                                 ccnt = scnprintf(tbuf+bcnt,
3598                                                  sizeof(tbuf)-bcnt,
3599                                                  " \"%s\"",
3600                                                  pvr2_fx2cmd_desc[idx].desc);
3601                                 bcnt += ccnt;
3602                                 break;
3603                         }
3604                 }
3605                 if (args) {
3606                         ccnt = scnprintf(tbuf+bcnt,
3607                                          sizeof(tbuf)-bcnt,
3608                                          " (%u",hdw->cmd_buffer[1]);
3609                         bcnt += ccnt;
3610                         if (args > 1) {
3611                                 ccnt = scnprintf(tbuf+bcnt,
3612                                                  sizeof(tbuf)-bcnt,
3613                                                  ",%u",hdw->cmd_buffer[2]);
3614                                 bcnt += ccnt;
3615                         }
3616                         ccnt = scnprintf(tbuf+bcnt,
3617                                          sizeof(tbuf)-bcnt,
3618                                          ")");
3619                         bcnt += ccnt;
3620                 }
3621                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3622         }
3623         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3624         LOCK_GIVE(hdw->ctl_lock);
3625         return ret;
3626 }
3627
3628
3629 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3630 {
3631         int ret;
3632
3633         LOCK_TAKE(hdw->ctl_lock);
3634
3635         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3636         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3637         hdw->cmd_buffer[5] = 0;
3638         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3639         hdw->cmd_buffer[7] = reg & 0xff;
3640
3641
3642         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3643
3644         LOCK_GIVE(hdw->ctl_lock);
3645
3646         return ret;
3647 }
3648
3649
3650 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3651 {
3652         int ret = 0;
3653
3654         LOCK_TAKE(hdw->ctl_lock);
3655
3656         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3657         hdw->cmd_buffer[1] = 0;
3658         hdw->cmd_buffer[2] = 0;
3659         hdw->cmd_buffer[3] = 0;
3660         hdw->cmd_buffer[4] = 0;
3661         hdw->cmd_buffer[5] = 0;
3662         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3663         hdw->cmd_buffer[7] = reg & 0xff;
3664
3665         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3666         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3667
3668         LOCK_GIVE(hdw->ctl_lock);
3669
3670         return ret;
3671 }
3672
3673
3674 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3675 {
3676         if (!hdw->flag_ok) return;
3677         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3678                    "Device being rendered inoperable");
3679         if (hdw->vid_stream) {
3680                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3681         }
3682         hdw->flag_ok = 0;
3683         trace_stbit("flag_ok",hdw->flag_ok);
3684         pvr2_hdw_state_sched(hdw);
3685 }
3686
3687
3688 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3689 {
3690         int ret;
3691         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3692         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3693         if (ret == 0) {
3694                 ret = usb_reset_device(hdw->usb_dev);
3695                 usb_unlock_device(hdw->usb_dev);
3696         } else {
3697                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3698                            "Failed to lock USB device ret=%d",ret);
3699         }
3700         if (init_pause_msec) {
3701                 pvr2_trace(PVR2_TRACE_INFO,
3702                            "Waiting %u msec for hardware to settle",
3703                            init_pause_msec);
3704                 msleep(init_pause_msec);
3705         }
3706
3707 }
3708
3709
3710 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3711 {
3712         char da[1];
3713         unsigned int pipe;
3714         int ret;
3715
3716         if (!hdw->usb_dev) return;
3717
3718         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3719
3720         da[0] = val ? 0x01 : 0x00;
3721
3722         /* Write the CPUCS register on the 8051.  The lsb of the register
3723            is the reset bit; a 1 asserts reset while a 0 clears it. */
3724         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3725         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3726         if (ret < 0) {
3727                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3728                            "cpureset_assert(%d) error=%d",val,ret);
3729                 pvr2_hdw_render_useless(hdw);
3730         }
3731 }
3732
3733
3734 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3735 {
3736         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
3737 }
3738
3739
3740 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3741 {
3742         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
3743 }
3744
3745
3746 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
3747 {
3748         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
3749 }
3750
3751
3752 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3753 {
3754         if (!hdw->decoder_ctrl) {
3755                 pvr2_trace(PVR2_TRACE_INIT,
3756                            "Unable to reset decoder: nothing attached");
3757                 return -ENOTTY;
3758         }
3759
3760         if (!hdw->decoder_ctrl->force_reset) {
3761                 pvr2_trace(PVR2_TRACE_INIT,
3762                            "Unable to reset decoder: not implemented");
3763                 return -ENOTTY;
3764         }
3765
3766         pvr2_trace(PVR2_TRACE_INIT,
3767                    "Requesting decoder reset");
3768         hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3769         return 0;
3770 }
3771
3772
3773 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
3774 {
3775         hdw->flag_ok = !0;
3776         return pvr2_issue_simple_cmd(hdw,
3777                                      FX2CMD_HCW_DEMOD_RESETIN |
3778                                      (1 << 8) |
3779                                      ((onoff ? 1 : 0) << 16));
3780 }
3781
3782
3783 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
3784 {
3785         hdw->flag_ok = !0;
3786         return pvr2_issue_simple_cmd(hdw,(onoff ?
3787                                           FX2CMD_ONAIR_DTV_POWER_ON :
3788                                           FX2CMD_ONAIR_DTV_POWER_OFF));
3789 }
3790
3791
3792 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
3793                                                 int onoff)
3794 {
3795         return pvr2_issue_simple_cmd(hdw,(onoff ?
3796                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
3797                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
3798 }
3799
3800
3801 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
3802 {
3803         int cmode;
3804         /* Compare digital/analog desired setting with current setting.  If
3805            they don't match, fix it... */
3806         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
3807         if (cmode == hdw->pathway_state) {
3808                 /* They match; nothing to do */
3809                 return;
3810         }
3811
3812         switch (hdw->hdw_desc->digital_control_scheme) {
3813         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3814                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
3815                 if (cmode == PVR2_PATHWAY_ANALOG) {
3816                         /* If moving to analog mode, also force the decoder
3817                            to reset.  If no decoder is attached, then it's
3818                            ok to ignore this because if/when the decoder
3819                            attaches, it will reset itself at that time. */
3820                         pvr2_hdw_cmd_decoder_reset(hdw);
3821                 }
3822                 break;
3823         case PVR2_DIGITAL_SCHEME_ONAIR:
3824                 /* Supposedly we should always have the power on whether in
3825                    digital or analog mode.  But for now do what appears to
3826                    work... */
3827                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
3828                 break;
3829         default: break;
3830         }
3831
3832         pvr2_hdw_untrip_unlocked(hdw);
3833         hdw->pathway_state = cmode;
3834 }
3835
3836
3837 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
3838 {
3839         /* change some GPIO data
3840          *
3841          * note: bit d7 of dir appears to control the LED,
3842          * so we shut it off here.
3843          *
3844          */
3845         if (onoff) {
3846                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
3847         } else {
3848                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
3849         }
3850         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
3851 }
3852
3853
3854 typedef void (*led_method_func)(struct pvr2_hdw *,int);
3855
3856 static led_method_func led_methods[] = {
3857         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
3858 };
3859
3860
3861 /* Toggle LED */
3862 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
3863 {
3864         unsigned int scheme_id;
3865         led_method_func fp;
3866
3867         if ((!onoff) == (!hdw->led_on)) return;
3868
3869         hdw->led_on = onoff != 0;
3870
3871         scheme_id = hdw->hdw_desc->led_scheme;
3872         if (scheme_id < ARRAY_SIZE(led_methods)) {
3873                 fp = led_methods[scheme_id];
3874         } else {
3875                 fp = NULL;
3876         }
3877
3878         if (fp) (*fp)(hdw,onoff);
3879 }
3880
3881
3882 /* Stop / start video stream transport */
3883 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
3884 {
3885         int ret;
3886
3887         /* If we're in analog mode, then just issue the usual analog
3888            command. */
3889         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3890                 return pvr2_issue_simple_cmd(hdw,
3891                                              (runFl ?
3892                                               FX2CMD_STREAMING_ON :
3893                                               FX2CMD_STREAMING_OFF));
3894                 /*Note: Not reached */
3895         }
3896
3897         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
3898                 /* Whoops, we don't know what mode we're in... */
3899                 return -EINVAL;
3900         }
3901
3902         /* To get here we have to be in digital mode.  The mechanism here
3903            is unfortunately different for different vendors.  So we switch
3904            on the device's digital scheme attribute in order to figure out
3905            what to do. */
3906         switch (hdw->hdw_desc->digital_control_scheme) {
3907         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3908                 return pvr2_issue_simple_cmd(hdw,
3909                                              (runFl ?
3910                                               FX2CMD_HCW_DTV_STREAMING_ON :
3911                                               FX2CMD_HCW_DTV_STREAMING_OFF));
3912         case PVR2_DIGITAL_SCHEME_ONAIR:
3913                 ret = pvr2_issue_simple_cmd(hdw,
3914                                             (runFl ?
3915                                              FX2CMD_STREAMING_ON :
3916                                              FX2CMD_STREAMING_OFF));
3917                 if (ret) return ret;
3918                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
3919         default:
3920                 return -EINVAL;
3921         }
3922 }
3923
3924
3925 /* Evaluate whether or not state_pathway_ok can change */
3926 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
3927 {
3928         if (hdw->state_pathway_ok) {
3929                 /* Nothing to do if pathway is already ok */
3930                 return 0;
3931         }
3932         if (!hdw->state_pipeline_idle) {
3933                 /* Not allowed to change anything if pipeline is not idle */
3934                 return 0;
3935         }
3936         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
3937         hdw->state_pathway_ok = !0;
3938         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3939         return !0;
3940 }
3941
3942
3943 /* Evaluate whether or not state_encoder_ok can change */
3944 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
3945 {
3946         if (hdw->state_encoder_ok) return 0;
3947         if (hdw->flag_tripped) return 0;
3948         if (hdw->state_encoder_run) return 0;
3949         if (hdw->state_encoder_config) return 0;
3950         if (hdw->state_decoder_run) return 0;
3951         if (hdw->state_usbstream_run) return 0;
3952         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
3953                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
3954         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
3955                 return 0;
3956         }
3957
3958         if (pvr2_upload_firmware2(hdw) < 0) {
3959                 hdw->flag_tripped = !0;
3960                 trace_stbit("flag_tripped",hdw->flag_tripped);
3961                 return !0;
3962         }
3963         hdw->state_encoder_ok = !0;
3964         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
3965         return !0;
3966 }
3967
3968
3969 /* Evaluate whether or not state_encoder_config can change */
3970 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
3971 {
3972         if (hdw->state_encoder_config) {
3973                 if (hdw->state_encoder_ok) {
3974                         if (hdw->state_pipeline_req &&
3975                             !hdw->state_pipeline_pause) return 0;
3976                 }
3977                 hdw->state_encoder_config = 0;
3978                 hdw->state_encoder_waitok = 0;
3979                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3980                 /* paranoia - solve race if timer just completed */
3981                 del_timer_sync(&hdw->encoder_wait_timer);
3982         } else {
3983                 if (!hdw->state_pathway_ok ||
3984                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3985                     !hdw->state_encoder_ok ||
3986                     !hdw->state_pipeline_idle ||
3987                     hdw->state_pipeline_pause ||
3988                     !hdw->state_pipeline_req ||
3989                     !hdw->state_pipeline_config) {
3990                         /* We must reset the enforced wait interval if
3991                            anything has happened that might have disturbed
3992                            the encoder.  This should be a rare case. */
3993                         if (timer_pending(&hdw->encoder_wait_timer)) {
3994                                 del_timer_sync(&hdw->encoder_wait_timer);
3995                         }
3996                         if (hdw->state_encoder_waitok) {
3997                                 /* Must clear the state - therefore we did
3998                                    something to a state bit and must also
3999                                    return true. */
4000                                 hdw->state_encoder_waitok = 0;
4001                                 trace_stbit("state_encoder_waitok",
4002                                             hdw->state_encoder_waitok);
4003                                 return !0;
4004                         }
4005                         return 0;
4006                 }
4007                 if (!hdw->state_encoder_waitok) {
4008                         if (!timer_pending(&hdw->encoder_wait_timer)) {
4009                                 /* waitok flag wasn't set and timer isn't
4010                                    running.  Check flag once more to avoid
4011                                    a race then start the timer.  This is
4012                                    the point when we measure out a minimal
4013                                    quiet interval before doing something to
4014                                    the encoder. */
4015                                 if (!hdw->state_encoder_waitok) {
4016                                         hdw->encoder_wait_timer.expires =
4017                                                 jiffies +
4018                                                 (HZ * TIME_MSEC_ENCODER_WAIT
4019                                                  / 1000);
4020                                         add_timer(&hdw->encoder_wait_timer);
4021                                 }
4022                         }
4023                         /* We can't continue until we know we have been
4024                            quiet for the interval measured by this
4025                            timer. */
4026                         return 0;
4027                 }
4028                 pvr2_encoder_configure(hdw);
4029                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4030         }
4031         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4032         return !0;
4033 }
4034
4035
4036 /* Return true if the encoder should not be running. */
4037 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4038 {
4039         if (!hdw->state_encoder_ok) {
4040                 /* Encoder isn't healthy at the moment, so stop it. */
4041                 return !0;
4042         }
4043         if (!hdw->state_pathway_ok) {
4044                 /* Mode is not understood at the moment (i.e. it wants to
4045                    change), so encoder must be stopped. */
4046                 return !0;
4047         }
4048
4049         switch (hdw->pathway_state) {
4050         case PVR2_PATHWAY_ANALOG:
4051                 if (!hdw->state_decoder_run) {
4052                         /* We're in analog mode and the decoder is not
4053                            running; thus the encoder should be stopped as
4054                            well. */
4055                         return !0;
4056                 }
4057                 break;
4058         case PVR2_PATHWAY_DIGITAL:
4059                 if (hdw->state_encoder_runok) {
4060                         /* This is a funny case.  We're in digital mode so
4061                            really the encoder should be stopped.  However
4062                            if it really is running, only kill it after
4063                            runok has been set.  This gives a chance for the
4064                            onair quirk to function (encoder must run
4065                            briefly first, at least once, before onair
4066                            digital streaming can work). */
4067                         return !0;
4068                 }
4069                 break;
4070         default:
4071                 /* Unknown mode; so encoder should be stopped. */
4072                 return !0;
4073         }
4074
4075         /* If we get here, we haven't found a reason to stop the
4076            encoder. */
4077         return 0;
4078 }
4079
4080
4081 /* Return true if the encoder should be running. */
4082 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4083 {
4084         if (!hdw->state_encoder_ok) {
4085                 /* Don't run the encoder if it isn't healthy... */
4086                 return 0;
4087         }
4088         if (!hdw->state_pathway_ok) {
4089                 /* Don't run the encoder if we don't (yet) know what mode
4090                    we need to be in... */
4091                 return 0;
4092         }
4093
4094         switch (hdw->pathway_state) {
4095         case PVR2_PATHWAY_ANALOG:
4096                 if (hdw->state_decoder_run) {
4097                         /* In analog mode, if the decoder is running, then
4098                            run the encoder. */
4099                         return !0;
4100                 }
4101                 break;
4102         case PVR2_PATHWAY_DIGITAL:
4103                 if ((hdw->hdw_desc->digital_control_scheme ==
4104                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4105                     !hdw->state_encoder_runok) {
4106                         /* This is a quirk.  OnAir hardware won't stream
4107                            digital until the encoder has been run at least
4108                            once, for a minimal period of time (empiricially
4109                            measured to be 1/4 second).  So if we're on
4110                            OnAir hardware and the encoder has never been
4111                            run at all, then start the encoder.  Normal
4112                            state machine logic in the driver will
4113                            automatically handle the remaining bits. */
4114                         return !0;
4115                 }
4116                 break;
4117         default:
4118                 /* For completeness (unknown mode; encoder won't run ever) */
4119                 break;
4120         }
4121         /* If we get here, then we haven't found any reason to run the
4122            encoder, so don't run it. */
4123         return 0;
4124 }
4125
4126
4127 /* Evaluate whether or not state_encoder_run can change */
4128 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4129 {
4130         if (hdw->state_encoder_run) {
4131                 if (!state_check_disable_encoder_run(hdw)) return 0;
4132                 if (hdw->state_encoder_ok) {
4133                         del_timer_sync(&hdw->encoder_run_timer);
4134                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4135                 }
4136                 hdw->state_encoder_run = 0;
4137         } else {
4138                 if (!state_check_enable_encoder_run(hdw)) return 0;
4139                 if (pvr2_encoder_start(hdw) < 0) return !0;
4140                 hdw->state_encoder_run = !0;
4141                 if (!hdw->state_encoder_runok) {
4142                         hdw->encoder_run_timer.expires =
4143                                 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4144                         add_timer(&hdw->encoder_run_timer);
4145                 }
4146         }
4147         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4148         return !0;
4149 }
4150
4151
4152 /* Timeout function for quiescent timer. */
4153 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4154 {
4155         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4156         hdw->state_decoder_quiescent = !0;
4157         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4158         hdw->state_stale = !0;
4159         queue_work(hdw->workqueue,&hdw->workpoll);
4160 }
4161
4162
4163 /* Timeout function for encoder wait timer. */
4164 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4165 {
4166         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4167         hdw->state_encoder_waitok = !0;
4168         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4169         hdw->state_stale = !0;
4170         queue_work(hdw->workqueue,&hdw->workpoll);
4171 }
4172
4173
4174 /* Timeout function for encoder run timer. */
4175 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4176 {
4177         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4178         if (!hdw->state_encoder_runok) {
4179                 hdw->state_encoder_runok = !0;
4180                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4181                 hdw->state_stale = !0;
4182                 queue_work(hdw->workqueue,&hdw->workpoll);
4183         }
4184 }
4185
4186
4187 /* Evaluate whether or not state_decoder_run can change */
4188 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4189 {
4190         if (hdw->state_decoder_run) {
4191                 if (hdw->state_encoder_ok) {
4192                         if (hdw->state_pipeline_req &&
4193                             !hdw->state_pipeline_pause &&
4194                             hdw->state_pathway_ok) return 0;
4195                 }
4196                 if (!hdw->flag_decoder_missed) {
4197                         pvr2_decoder_enable(hdw,0);
4198                 }
4199                 hdw->state_decoder_quiescent = 0;
4200                 hdw->state_decoder_run = 0;
4201                 /* paranoia - solve race if timer just completed */
4202                 del_timer_sync(&hdw->quiescent_timer);
4203         } else {
4204                 if (!hdw->state_decoder_quiescent) {
4205                         if (!timer_pending(&hdw->quiescent_timer)) {
4206                                 /* We don't do something about the
4207                                    quiescent timer until right here because
4208                                    we also want to catch cases where the
4209                                    decoder was already not running (like
4210                                    after initialization) as opposed to
4211                                    knowing that we had just stopped it.
4212                                    The second flag check is here to cover a
4213                                    race - the timer could have run and set
4214                                    this flag just after the previous check
4215                                    but before we did the pending check. */
4216                                 if (!hdw->state_decoder_quiescent) {
4217                                         hdw->quiescent_timer.expires =
4218                                                 jiffies +
4219                                                 (HZ * TIME_MSEC_DECODER_WAIT
4220                                                  / 1000);
4221                                         add_timer(&hdw->quiescent_timer);
4222                                 }
4223                         }
4224                         /* Don't allow decoder to start again until it has
4225                            been quiesced first.  This little detail should
4226                            hopefully further stabilize the encoder. */
4227                         return 0;
4228                 }
4229                 if (!hdw->state_pathway_ok ||
4230                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4231                     !hdw->state_pipeline_req ||
4232                     hdw->state_pipeline_pause ||
4233                     !hdw->state_pipeline_config ||
4234                     !hdw->state_encoder_config ||
4235                     !hdw->state_encoder_ok) return 0;
4236                 del_timer_sync(&hdw->quiescent_timer);
4237                 if (hdw->flag_decoder_missed) return 0;
4238                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4239                 hdw->state_decoder_quiescent = 0;
4240                 hdw->state_decoder_run = !0;
4241         }
4242         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4243         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4244         return !0;
4245 }
4246
4247
4248 /* Evaluate whether or not state_usbstream_run can change */
4249 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4250 {
4251         if (hdw->state_usbstream_run) {
4252                 int fl = !0;
4253                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4254                         fl = (hdw->state_encoder_ok &&
4255                               hdw->state_encoder_run);
4256                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4257                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4258                         fl = hdw->state_encoder_ok;
4259                 }
4260                 if (fl &&
4261                     hdw->state_pipeline_req &&
4262                     !hdw->state_pipeline_pause &&
4263                     hdw->state_pathway_ok) {
4264                         return 0;
4265                 }
4266                 pvr2_hdw_cmd_usbstream(hdw,0);
4267                 hdw->state_usbstream_run = 0;
4268         } else {
4269                 if (!hdw->state_pipeline_req ||
4270                     hdw->state_pipeline_pause ||
4271                     !hdw->state_pathway_ok) return 0;
4272                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4273                         if (!hdw->state_encoder_ok ||
4274                             !hdw->state_encoder_run) return 0;
4275                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4276                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4277                         if (!hdw->state_encoder_ok) return 0;
4278                         if (hdw->state_encoder_run) return 0;
4279                         if (hdw->hdw_desc->digital_control_scheme ==
4280                             PVR2_DIGITAL_SCHEME_ONAIR) {
4281                                 /* OnAir digital receivers won't stream
4282                                    unless the analog encoder has run first.
4283                                    Why?  I have no idea.  But don't even
4284                                    try until we know the analog side is
4285                                    known to have run. */
4286                                 if (!hdw->state_encoder_runok) return 0;
4287                         }
4288                 }
4289                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4290                 hdw->state_usbstream_run = !0;
4291         }
4292         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4293         return !0;
4294 }
4295
4296
4297 /* Attempt to configure pipeline, if needed */
4298 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4299 {
4300         if (hdw->state_pipeline_config ||
4301             hdw->state_pipeline_pause) return 0;
4302         pvr2_hdw_commit_execute(hdw);
4303         return !0;
4304 }
4305
4306
4307 /* Update pipeline idle and pipeline pause tracking states based on other
4308    inputs.  This must be called whenever the other relevant inputs have
4309    changed. */
4310 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4311 {
4312         unsigned int st;
4313         int updatedFl = 0;
4314         /* Update pipeline state */
4315         st = !(hdw->state_encoder_run ||
4316                hdw->state_decoder_run ||
4317                hdw->state_usbstream_run ||
4318                (!hdw->state_decoder_quiescent));
4319         if (!st != !hdw->state_pipeline_idle) {
4320                 hdw->state_pipeline_idle = st;
4321                 updatedFl = !0;
4322         }
4323         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4324                 hdw->state_pipeline_pause = 0;
4325                 updatedFl = !0;
4326         }
4327         return updatedFl;
4328 }
4329
4330
4331 typedef int (*state_eval_func)(struct pvr2_hdw *);
4332
4333 /* Set of functions to be run to evaluate various states in the driver. */
4334 static const state_eval_func eval_funcs[] = {
4335         state_eval_pathway_ok,
4336         state_eval_pipeline_config,
4337         state_eval_encoder_ok,
4338         state_eval_encoder_config,
4339         state_eval_decoder_run,
4340         state_eval_encoder_run,
4341         state_eval_usbstream_run,
4342 };
4343
4344
4345 /* Process various states and return true if we did anything interesting. */
4346 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4347 {
4348         unsigned int i;
4349         int state_updated = 0;
4350         int check_flag;
4351
4352         if (!hdw->state_stale) return 0;
4353         if ((hdw->fw1_state != FW1_STATE_OK) ||
4354             !hdw->flag_ok) {
4355                 hdw->state_stale = 0;
4356                 return !0;
4357         }
4358         /* This loop is the heart of the entire driver.  It keeps trying to
4359            evaluate various bits of driver state until nothing changes for
4360            one full iteration.  Each "bit of state" tracks some global
4361            aspect of the driver, e.g. whether decoder should run, if
4362            pipeline is configured, usb streaming is on, etc.  We separately
4363            evaluate each of those questions based on other driver state to
4364            arrive at the correct running configuration. */
4365         do {
4366                 check_flag = 0;
4367                 state_update_pipeline_state(hdw);
4368                 /* Iterate over each bit of state */
4369                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4370                         if ((*eval_funcs[i])(hdw)) {
4371                                 check_flag = !0;
4372                                 state_updated = !0;
4373                                 state_update_pipeline_state(hdw);
4374                         }
4375                 }
4376         } while (check_flag && hdw->flag_ok);
4377         hdw->state_stale = 0;
4378         trace_stbit("state_stale",hdw->state_stale);
4379         return state_updated;
4380 }
4381
4382
4383 static unsigned int print_input_mask(unsigned int msk,
4384                                      char *buf,unsigned int acnt)
4385 {
4386         unsigned int idx,ccnt;
4387         unsigned int tcnt = 0;
4388         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4389                 if (!((1 << idx) & msk)) continue;
4390                 ccnt = scnprintf(buf+tcnt,
4391                                  acnt-tcnt,
4392                                  "%s%s",
4393                                  (tcnt ? ", " : ""),
4394                                  control_values_input[idx]);
4395                 tcnt += ccnt;
4396         }
4397         return tcnt;
4398 }
4399
4400
4401 static const char *pvr2_pathway_state_name(int id)
4402 {
4403         switch (id) {
4404         case PVR2_PATHWAY_ANALOG: return "analog";
4405         case PVR2_PATHWAY_DIGITAL: return "digital";
4406         default: return "unknown";
4407         }
4408 }
4409
4410
4411 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4412                                              char *buf,unsigned int acnt)
4413 {
4414         switch (which) {
4415         case 0:
4416                 return scnprintf(
4417                         buf,acnt,
4418                         "driver:%s%s%s%s%s <mode=%s>",
4419                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4420                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4421                         (hdw->flag_disconnected ? " <disconnected>" :
4422                          " <connected>"),
4423                         (hdw->flag_tripped ? " <tripped>" : ""),
4424                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4425                         pvr2_pathway_state_name(hdw->pathway_state));
4426
4427         case 1:
4428                 return scnprintf(
4429                         buf,acnt,
4430                         "pipeline:%s%s%s%s",
4431                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4432                         (hdw->state_pipeline_config ?
4433                          " <configok>" : " <stale>"),
4434                         (hdw->state_pipeline_req ? " <req>" : ""),
4435                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4436         case 2:
4437                 return scnprintf(
4438                         buf,acnt,
4439                         "worker:%s%s%s%s%s%s%s",
4440                         (hdw->state_decoder_run ?
4441                          " <decode:run>" :
4442                          (hdw->state_decoder_quiescent ?
4443                           "" : " <decode:stop>")),
4444                         (hdw->state_decoder_quiescent ?
4445                          " <decode:quiescent>" : ""),
4446                         (hdw->state_encoder_ok ?
4447                          "" : " <encode:init>"),
4448                         (hdw->state_encoder_run ?
4449                          (hdw->state_encoder_runok ?
4450                           " <encode:run>" :
4451                           " <encode:firstrun>") :
4452                          (hdw->state_encoder_runok ?
4453                           " <encode:stop>" :
4454                           " <encode:virgin>")),
4455                         (hdw->state_encoder_config ?
4456                          " <encode:configok>" :
4457                          (hdw->state_encoder_waitok ?
4458                           "" : " <encode:waitok>")),
4459                         (hdw->state_usbstream_run ?
4460                          " <usb:run>" : " <usb:stop>"),
4461                         (hdw->state_pathway_ok ?
4462                          " <pathway:ok>" : ""));
4463         case 3:
4464                 return scnprintf(
4465                         buf,acnt,
4466                         "state: %s",
4467                         pvr2_get_state_name(hdw->master_state));
4468         case 4: {
4469                 unsigned int tcnt = 0;
4470                 unsigned int ccnt;
4471
4472                 ccnt = scnprintf(buf,
4473                                  acnt,
4474                                  "Hardware supported inputs: ");
4475                 tcnt += ccnt;
4476                 tcnt += print_input_mask(hdw->input_avail_mask,
4477                                          buf+tcnt,
4478                                          acnt-tcnt);
4479                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4480                         ccnt = scnprintf(buf+tcnt,
4481                                          acnt-tcnt,
4482                                          "; allowed inputs: ");
4483                         tcnt += ccnt;
4484                         tcnt += print_input_mask(hdw->input_allowed_mask,
4485                                                  buf+tcnt,
4486                                                  acnt-tcnt);
4487                 }
4488                 return tcnt;
4489         }
4490         case 5: {
4491                 struct pvr2_stream_stats stats;
4492                 if (!hdw->vid_stream) break;
4493                 pvr2_stream_get_stats(hdw->vid_stream,
4494                                       &stats,
4495                                       0);
4496                 return scnprintf(
4497                         buf,acnt,
4498                         "Bytes streamed=%u"
4499                         " URBs: queued=%u idle=%u ready=%u"
4500                         " processed=%u failed=%u",
4501                         stats.bytes_processed,
4502                         stats.buffers_in_queue,
4503                         stats.buffers_in_idle,
4504                         stats.buffers_in_ready,
4505                         stats.buffers_processed,
4506                         stats.buffers_failed);
4507         }
4508         default: break;
4509         }
4510         return 0;
4511 }
4512
4513
4514 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4515                                    char *buf,unsigned int acnt)
4516 {
4517         unsigned int bcnt,ccnt,idx;
4518         bcnt = 0;
4519         LOCK_TAKE(hdw->big_lock);
4520         for (idx = 0; ; idx++) {
4521                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4522                 if (!ccnt) break;
4523                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4524                 if (!acnt) break;
4525                 buf[0] = '\n'; ccnt = 1;
4526                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4527         }
4528         LOCK_GIVE(hdw->big_lock);
4529         return bcnt;
4530 }
4531
4532
4533 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4534 {
4535         char buf[128];
4536         unsigned int idx,ccnt;
4537
4538         for (idx = 0; ; idx++) {
4539                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4540                 if (!ccnt) break;
4541                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4542         }
4543 }
4544
4545
4546 /* Evaluate and update the driver's current state, taking various actions
4547    as appropriate for the update. */
4548 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4549 {
4550         unsigned int st;
4551         int state_updated = 0;
4552         int callback_flag = 0;
4553         int analog_mode;
4554
4555         pvr2_trace(PVR2_TRACE_STBITS,
4556                    "Drive state check START");
4557         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4558                 pvr2_hdw_state_log_state(hdw);
4559         }
4560
4561         /* Process all state and get back over disposition */
4562         state_updated = pvr2_hdw_state_update(hdw);
4563
4564         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4565
4566         /* Update master state based upon all other states. */
4567         if (!hdw->flag_ok) {
4568                 st = PVR2_STATE_DEAD;
4569         } else if (hdw->fw1_state != FW1_STATE_OK) {
4570                 st = PVR2_STATE_COLD;
4571         } else if ((analog_mode ||
4572                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4573                    !hdw->state_encoder_ok) {
4574                 st = PVR2_STATE_WARM;
4575         } else if (hdw->flag_tripped ||
4576                    (analog_mode && hdw->flag_decoder_missed)) {
4577                 st = PVR2_STATE_ERROR;
4578         } else if (hdw->state_usbstream_run &&
4579                    (!analog_mode ||
4580                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4581                 st = PVR2_STATE_RUN;
4582         } else {
4583                 st = PVR2_STATE_READY;
4584         }
4585         if (hdw->master_state != st) {
4586                 pvr2_trace(PVR2_TRACE_STATE,
4587                            "Device state change from %s to %s",
4588                            pvr2_get_state_name(hdw->master_state),
4589                            pvr2_get_state_name(st));
4590                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4591                 hdw->master_state = st;
4592                 state_updated = !0;
4593                 callback_flag = !0;
4594         }
4595         if (state_updated) {
4596                 /* Trigger anyone waiting on any state changes here. */
4597                 wake_up(&hdw->state_wait_data);
4598         }
4599
4600         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4601                 pvr2_hdw_state_log_state(hdw);
4602         }
4603         pvr2_trace(PVR2_TRACE_STBITS,
4604                    "Drive state check DONE callback=%d",callback_flag);
4605
4606         return callback_flag;
4607 }
4608
4609
4610 /* Cause kernel thread to check / update driver state */
4611 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4612 {
4613         if (hdw->state_stale) return;
4614         hdw->state_stale = !0;
4615         trace_stbit("state_stale",hdw->state_stale);
4616         queue_work(hdw->workqueue,&hdw->workpoll);
4617 }
4618
4619
4620 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4621 {
4622         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4623 }
4624
4625
4626 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4627 {
4628         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4629 }
4630
4631
4632 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4633 {
4634         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4635 }
4636
4637
4638 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4639 {
4640         u32 cval,nval;
4641         int ret;
4642         if (~msk) {
4643                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4644                 if (ret) return ret;
4645                 nval = (cval & ~msk) | (val & msk);
4646                 pvr2_trace(PVR2_TRACE_GPIO,
4647                            "GPIO direction changing 0x%x:0x%x"
4648                            " from 0x%x to 0x%x",
4649                            msk,val,cval,nval);
4650         } else {
4651                 nval = val;
4652                 pvr2_trace(PVR2_TRACE_GPIO,
4653                            "GPIO direction changing to 0x%x",nval);
4654         }
4655         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4656 }
4657
4658
4659 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4660 {
4661         u32 cval,nval;
4662         int ret;
4663         if (~msk) {
4664                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
4665                 if (ret) return ret;
4666                 nval = (cval & ~msk) | (val & msk);
4667                 pvr2_trace(PVR2_TRACE_GPIO,
4668                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
4669                            msk,val,cval,nval);
4670         } else {
4671                 nval = val;
4672                 pvr2_trace(PVR2_TRACE_GPIO,
4673                            "GPIO output changing to 0x%x",nval);
4674         }
4675         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
4676 }
4677
4678
4679 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
4680 {
4681         pvr2_i2c_core_status_poll(hdw);
4682 }
4683
4684
4685 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
4686 {
4687         return hdw->input_avail_mask;
4688 }
4689
4690
4691 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
4692 {
4693         return hdw->input_allowed_mask;
4694 }
4695
4696
4697 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
4698 {
4699         if (hdw->input_val != v) {
4700                 hdw->input_val = v;
4701                 hdw->input_dirty = !0;
4702         }
4703
4704         /* Handle side effects - if we switch to a mode that needs the RF
4705            tuner, then select the right frequency choice as well and mark
4706            it dirty. */
4707         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
4708                 hdw->freqSelector = 0;
4709                 hdw->freqDirty = !0;
4710         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
4711                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
4712                 hdw->freqSelector = 1;
4713                 hdw->freqDirty = !0;
4714         }
4715         return 0;
4716 }
4717
4718
4719 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
4720                                unsigned int change_mask,
4721                                unsigned int change_val)
4722 {
4723         int ret = 0;
4724         unsigned int nv,m,idx;
4725         LOCK_TAKE(hdw->big_lock);
4726         do {
4727                 nv = hdw->input_allowed_mask & ~change_mask;
4728                 nv |= (change_val & change_mask);
4729                 nv &= hdw->input_avail_mask;
4730                 if (!nv) {
4731                         /* No legal modes left; return error instead. */
4732                         ret = -EPERM;
4733                         break;
4734                 }
4735                 hdw->input_allowed_mask = nv;
4736                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
4737                         /* Current mode is still in the allowed mask, so
4738                            we're done. */
4739                         break;
4740                 }
4741                 /* Select and switch to a mode that is still in the allowed
4742                    mask */
4743                 if (!hdw->input_allowed_mask) {
4744                         /* Nothing legal; give up */
4745                         break;
4746                 }
4747                 m = hdw->input_allowed_mask;
4748                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
4749                         if (!((1 << idx) & m)) continue;
4750                         pvr2_hdw_set_input(hdw,idx);
4751                         break;
4752                 }
4753         } while (0);
4754         LOCK_GIVE(hdw->big_lock);
4755         return ret;
4756 }
4757
4758
4759 /* Find I2C address of eeprom */
4760 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
4761 {
4762         int result;
4763         LOCK_TAKE(hdw->ctl_lock); do {
4764                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
4765                 result = pvr2_send_request(hdw,
4766                                            hdw->cmd_buffer,1,
4767                                            hdw->cmd_buffer,1);
4768                 if (result < 0) break;
4769                 result = hdw->cmd_buffer[0];
4770         } while(0); LOCK_GIVE(hdw->ctl_lock);
4771         return result;
4772 }
4773
4774
4775 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
4776                              struct v4l2_dbg_match *match, u64 reg_id,
4777                              int setFl, u64 *val_ptr)
4778 {
4779 #ifdef CONFIG_VIDEO_ADV_DEBUG
4780         struct pvr2_i2c_client *cp;
4781         struct v4l2_dbg_register req;
4782         int stat = 0;
4783         int okFl = 0;
4784
4785         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
4786
4787         req.match = *match;
4788         req.reg = reg_id;
4789         if (setFl) req.val = *val_ptr;
4790         mutex_lock(&hdw->i2c_list_lock); do {
4791                 list_for_each_entry(cp, &hdw->i2c_clients, list) {
4792                         if (!v4l2_chip_match_i2c_client(
4793                                     cp->client,
4794                                     &req.match)) {
4795                                 continue;
4796                         }
4797                         stat = pvr2_i2c_client_cmd(
4798                                 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
4799                                     VIDIOC_DBG_G_REGISTER),&req);
4800                         if (!setFl) *val_ptr = req.val;
4801                         okFl = !0;
4802                         break;
4803                 }
4804         } while (0); mutex_unlock(&hdw->i2c_list_lock);
4805         if (okFl) {
4806                 return stat;
4807         }
4808         return -EINVAL;
4809 #else
4810         return -ENOSYS;
4811 #endif
4812 }
4813
4814
4815 /*
4816   Stuff for Emacs to see, in order to encourage consistent editing style:
4817   *** Local Variables: ***
4818   *** mode: c ***
4819   *** fill-column: 75 ***
4820   *** tab-width: 8 ***
4821   *** c-basic-offset: 8 ***
4822   *** End: ***
4823   */