SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  *
  19  */
  20
  21 #include <linux/errno.h>
  22 #include <linux/string.h>
  23 #include <linux/slab.h>
  24 #include <linux/firmware.h>
  25 #include <linux/videodev2.h>
  26 #include <media/v4l2-common.h>
  27 #include <media/tuner.h>
  28 #include "pvrusb2.h"
  29 #include "pvrusb2-std.h"
  30 #include "pvrusb2-util.h"
  31 #include "pvrusb2-hdw.h"
  32 #include "pvrusb2-i2c-core.h"
  33 #include "pvrusb2-eeprom.h"
  34 #include "pvrusb2-hdw-internal.h"
  35 #include "pvrusb2-encoder.h"
  36 #include "pvrusb2-debug.h"
  37 #include "pvrusb2-fx2-cmd.h"
  38 #include "pvrusb2-wm8775.h"
  39 #include "pvrusb2-video-v4l.h"
  40 #include "pvrusb2-cx2584x-v4l.h"
  41 #include "pvrusb2-cs53l32a.h"
  42 #include "pvrusb2-audio.h"
  43
  44 #define TV_MIN_FREQ     55250000L
  45 #define TV_MAX_FREQ    850000000L
  46
  47 /* This defines a minimum interval that the decoder must remain quiet
  48    before we are allowed to start it running. */
  49 #define TIME_MSEC_DECODER_WAIT 50
  50
  51 /* This defines a minimum interval that the encoder must remain quiet
  52    before we are allowed to configure it.  I had this originally set to
  53    50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
  54    things work better when it's set to 100msec. */
  55 #define TIME_MSEC_ENCODER_WAIT 100
  56
  57 /* This defines the minimum interval that the encoder must successfully run
  58    before we consider that the encoder has run at least once since its
  59    firmware has been loaded.  This measurement is in important for cases
  60    where we can't do something until we know that the encoder has been run
  61    at least once. */
  62 #define TIME_MSEC_ENCODER_OK 250
  63
  64 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  65 static DEFINE_MUTEX(pvr2_unit_mtx);
  66
  67 static int ctlchg;
  68 static int procreload;
  69 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  70 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  71 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  72 static int init_pause_msec;
  73
  74 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  75 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  76 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  77 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  78 module_param(procreload, int, S_IRUGO|S_IWUSR);
  79 MODULE_PARM_DESC(procreload,
  80                  "Attempt init failure recovery with firmware reload");
  81 module_param_array(tuner,    int, NULL, 0444);
  82 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  83 module_param_array(video_std,    int, NULL, 0444);
  84 MODULE_PARM_DESC(video_std,"specify initial video standard");
  85 module_param_array(tolerance,    int, NULL, 0444);
  86 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  87
  88 /* US Broadcast channel 3 (61.25 MHz), to help with testing */
  89 static int default_tv_freq    = 61250000L;
  90 /* 104.3 MHz, a usable FM station for my area */
  91 static int default_radio_freq = 104300000L;
  92
  93 module_param_named(tv_freq, default_tv_freq, int, 0444);
  94 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  95 module_param_named(radio_freq, default_radio_freq, int, 0444);
  96 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  97
  98 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  99 #define PVR2_CTL_READ_ENDPOINT   0x81
 100
 101 #define PVR2_GPIO_IN 0x9008
 102 #define PVR2_GPIO_OUT 0x900c
 103 #define PVR2_GPIO_DIR 0x9020
 104
 105 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 106
 107 #define PVR2_FIRMWARE_ENDPOINT   0x02
 108
 109 /* size of a firmware chunk */
 110 #define FIRMWARE_CHUNK_SIZE 0x2000
 111
 112 typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
 113                                         struct v4l2_subdev *);
 114
 115 static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
 116         [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
 117         [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
 118         [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
 119         [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
 120         [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
 121 };
 122
 123 static const char *module_names[] = {
 124         [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 125         [PVR2_CLIENT_ID_CX25840] = "cx25840",
 126         [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 127         [PVR2_CLIENT_ID_TUNER] = "tuner",
 128         [PVR2_CLIENT_ID_DEMOD] = "tuner",
 129         [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
 130         [PVR2_CLIENT_ID_WM8775] = "wm8775",
 131 };
 132
 133
 134 static const unsigned char *module_i2c_addresses[] = {
 135         [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 136         [PVR2_CLIENT_ID_DEMOD] = "\x43",
 137         [PVR2_CLIENT_ID_MSP3400] = "\x40",
 138         [PVR2_CLIENT_ID_SAA7115] = "\x21",
 139         [PVR2_CLIENT_ID_WM8775] = "\x1b",
 140         [PVR2_CLIENT_ID_CX25840] = "\x44",
 141         [PVR2_CLIENT_ID_CS53L32A] = "\x11",
 142 };
 143
 144
 145 static const char *ir_scheme_names[] = {
 146         [PVR2_IR_SCHEME_NONE] = "none",
 147         [PVR2_IR_SCHEME_29XXX] = "29xxx",
 148         [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
 149         [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
 150         [PVR2_IR_SCHEME_ZILOG] = "Zilog",
 151 };
 152
 153
 154 /* Define the list of additional controls we'll dynamically construct based
 155    on query of the cx2341x module. */
 156 struct pvr2_mpeg_ids {
 157         const char *strid;
 158         int id;
 159 };
 160 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 161         {
 162                 .strid = "audio_layer",
 163                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 164         },{
 165                 .strid = "audio_bitrate",
 166                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 167         },{
 168                 /* Already using audio_mode elsewhere :-( */
 169                 .strid = "mpeg_audio_mode",
 170                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 171         },{
 172                 .strid = "mpeg_audio_mode_extension",
 173                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 174         },{
 175                 .strid = "audio_emphasis",
 176                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 177         },{
 178                 .strid = "audio_crc",
 179                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 180         },{
 181                 .strid = "video_aspect",
 182                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 183         },{
 184                 .strid = "video_b_frames",
 185                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 186         },{
 187                 .strid = "video_gop_size",
 188                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 189         },{
 190                 .strid = "video_gop_closure",
 191                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 192         },{
 193                 .strid = "video_bitrate_mode",
 194                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 195         },{
 196                 .strid = "video_bitrate",
 197                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 198         },{
 199                 .strid = "video_bitrate_peak",
 200                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 201         },{
 202                 .strid = "video_temporal_decimation",
 203                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 204         },{
 205                 .strid = "stream_type",
 206                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 207         },{
 208                 .strid = "video_spatial_filter_mode",
 209                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 210         },{
 211                 .strid = "video_spatial_filter",
 212                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 213         },{
 214                 .strid = "video_luma_spatial_filter_type",
 215                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 216         },{
 217                 .strid = "video_chroma_spatial_filter_type",
 218                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 219         },{
 220                 .strid = "video_temporal_filter_mode",
 221                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 222         },{
 223                 .strid = "video_temporal_filter",
 224                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 225         },{
 226                 .strid = "video_median_filter_type",
 227                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 228         },{
 229                 .strid = "video_luma_median_filter_top",
 230                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 231         },{
 232                 .strid = "video_luma_median_filter_bottom",
 233                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 234         },{
 235                 .strid = "video_chroma_median_filter_top",
 236                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 237         },{
 238                 .strid = "video_chroma_median_filter_bottom",
 239                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 240         }
 241 };
 242 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 243
 244
 245 static const char *control_values_srate[] = {
 246         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 247         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 248         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 249 };
 250
 251
 252
 253 static const char *control_values_input[] = {
 254         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 255         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 256         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 257         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 258         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 259 };
 260
 261
 262 static const char *control_values_audiomode[] = {
 263         [V4L2_TUNER_MODE_MONO]   = "Mono",
 264         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 265         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 266         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 267         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 268 };
 269
 270
 271 static const char *control_values_hsm[] = {
 272         [PVR2_CVAL_HSM_FAIL] = "Fail",
 273         [PVR2_CVAL_HSM_HIGH] = "High",
 274         [PVR2_CVAL_HSM_FULL] = "Full",
 275 };
 276
 277
 278 static const char *pvr2_state_names[] = {
 279         [PVR2_STATE_NONE] =    "none",
 280         [PVR2_STATE_DEAD] =    "dead",
 281         [PVR2_STATE_COLD] =    "cold",
 282         [PVR2_STATE_WARM] =    "warm",
 283         [PVR2_STATE_ERROR] =   "error",
 284         [PVR2_STATE_READY] =   "ready",
 285         [PVR2_STATE_RUN] =     "run",
 286 };
 287
 288
 289 struct pvr2_fx2cmd_descdef {
 290         unsigned char id;
 291         unsigned char *desc;
 292 };
 293
 294 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 295         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 296         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 297         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 298         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 299         {FX2CMD_REG_WRITE, "write encoder register"},
 300         {FX2CMD_REG_READ, "read encoder register"},
 301         {FX2CMD_MEMSEL, "encoder memsel"},
 302         {FX2CMD_I2C_WRITE, "i2c write"},
 303         {FX2CMD_I2C_READ, "i2c read"},
 304         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 305         {FX2CMD_STREAMING_ON, "stream on"},
 306         {FX2CMD_STREAMING_OFF, "stream off"},
 307         {FX2CMD_FWPOST1, "fwpost1"},
 308         {FX2CMD_POWER_OFF, "power off"},
 309         {FX2CMD_POWER_ON, "power on"},
 310         {FX2CMD_DEEP_RESET, "deep reset"},
 311         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 312         {FX2CMD_GET_IR_CODE, "get IR code"},
 313         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 314         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 315         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 316         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 317         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 318         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 319         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 320 };
 321
 322
 323 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 324 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 325 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 326 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 327 static void pvr2_hdw_worker_poll(struct work_struct *work);
 328 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 329 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 330 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 331 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 332 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 333 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 334 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 335 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 336 static void pvr2_hdw_quiescent_timeout(unsigned long);
 337 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 338 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 339 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 340 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 341                                 unsigned int timeout,int probe_fl,
 342                                 void *write_data,unsigned int write_len,
 343                                 void *read_data,unsigned int read_len);
 344 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 345
 346
 347 static void trace_stbit(const char *name,int val)
 348 {
 349         pvr2_trace(PVR2_TRACE_STBITS,
 350                    "State bit %s <-- %s",
 351                    name,(val ? "true" : "false"));
 352 }
 353
 354 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 355 {
 356         struct pvr2_hdw *hdw = cptr->hdw;
 357         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 358                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 359         } else {
 360                 *vp = 0;
 361         }
 362         return 0;
 363 }
 364
 365 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 366 {
 367         struct pvr2_hdw *hdw = cptr->hdw;
 368         unsigned int slotId = hdw->freqProgSlot;
 369         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 370                 hdw->freqTable[slotId-1] = v;
 371                 /* Handle side effects correctly - if we're tuned to this
 372                    slot, then forgot the slot id relation since the stored
 373                    frequency has been changed. */
 374                 if (hdw->freqSelector) {
 375                         if (hdw->freqSlotRadio == slotId) {
 376                                 hdw->freqSlotRadio = 0;
 377                         }
 378                 } else {
 379                         if (hdw->freqSlotTelevision == slotId) {
 380                                 hdw->freqSlotTelevision = 0;
 381                         }
 382                 }
 383         }
 384         return 0;
 385 }
 386
 387 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 388 {
 389         *vp = cptr->hdw->freqProgSlot;
 390         return 0;
 391 }
 392
 393 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 394 {
 395         struct pvr2_hdw *hdw = cptr->hdw;
 396         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 397                 hdw->freqProgSlot = v;
 398         }
 399         return 0;
 400 }
 401
 402 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 403 {
 404         struct pvr2_hdw *hdw = cptr->hdw;
 405         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 406         return 0;
 407 }
 408
 409 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 410 {
 411         unsigned freq = 0;
 412         struct pvr2_hdw *hdw = cptr->hdw;
 413         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 414         if (slotId > 0) {
 415                 freq = hdw->freqTable[slotId-1];
 416                 if (!freq) return 0;
 417                 pvr2_hdw_set_cur_freq(hdw,freq);
 418         }
 419         if (hdw->freqSelector) {
 420                 hdw->freqSlotRadio = slotId;
 421         } else {
 422                 hdw->freqSlotTelevision = slotId;
 423         }
 424         return 0;
 425 }
 426
 427 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 428 {
 429         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 430         return 0;
 431 }
 432
 433 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 434 {
 435         return cptr->hdw->freqDirty != 0;
 436 }
 437
 438 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 439 {
 440         cptr->hdw->freqDirty = 0;
 441 }
 442
 443 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 444 {
 445         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 446         return 0;
 447 }
 448
 449 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 450 {
 451         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 452         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 453         if (stat != 0) {
 454                 return stat;
 455         }
 456         *left = cap->bounds.left;
 457         return 0;
 458 }
 459
 460 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 461 {
 462         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 463         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 464         if (stat != 0) {
 465                 return stat;
 466         }
 467         *left = cap->bounds.left;
 468         if (cap->bounds.width > cptr->hdw->cropw_val) {
 469                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 470         }
 471         return 0;
 472 }
 473
 474 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 475 {
 476         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 477         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 478         if (stat != 0) {
 479                 return stat;
 480         }
 481         *top = cap->bounds.top;
 482         return 0;
 483 }
 484
 485 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 486 {
 487         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 488         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 489         if (stat != 0) {
 490                 return stat;
 491         }
 492         *top = cap->bounds.top;
 493         if (cap->bounds.height > cptr->hdw->croph_val) {
 494                 *top += cap->bounds.height - cptr->hdw->croph_val;
 495         }
 496         return 0;
 497 }
 498
 499 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
 500 {
 501         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 502         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 503         if (stat != 0) {
 504                 return stat;
 505         }
 506         *val = 0;
 507         if (cap->bounds.width > cptr->hdw->cropl_val) {
 508                 *val = cap->bounds.width - cptr->hdw->cropl_val;
 509         }
 510         return 0;
 511 }
 512
 513 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
 514 {
 515         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 516         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 517         if (stat != 0) {
 518                 return stat;
 519         }
 520         *val = 0;
 521         if (cap->bounds.height > cptr->hdw->cropt_val) {
 522                 *val = cap->bounds.height - cptr->hdw->cropt_val;
 523         }
 524         return 0;
 525 }
 526
 527 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 528 {
 529         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 530         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 531         if (stat != 0) {
 532                 return stat;
 533         }
 534         *val = cap->bounds.left;
 535         return 0;
 536 }
 537
 538 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 539 {
 540         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 541         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 542         if (stat != 0) {
 543                 return stat;
 544         }
 545         *val = cap->bounds.top;
 546         return 0;
 547 }
 548
 549 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 550 {
 551         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 552         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 553         if (stat != 0) {
 554                 return stat;
 555         }
 556         *val = cap->bounds.width;
 557         return 0;
 558 }
 559
 560 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 561 {
 562         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 563         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 564         if (stat != 0) {
 565                 return stat;
 566         }
 567         *val = cap->bounds.height;
 568         return 0;
 569 }
 570
 571 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 572 {
 573         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 574         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 575         if (stat != 0) {
 576                 return stat;
 577         }
 578         *val = cap->defrect.left;
 579         return 0;
 580 }
 581
 582 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 583 {
 584         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 585         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 586         if (stat != 0) {
 587                 return stat;
 588         }
 589         *val = cap->defrect.top;
 590         return 0;
 591 }
 592
 593 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 594 {
 595         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 596         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 597         if (stat != 0) {
 598                 return stat;
 599         }
 600         *val = cap->defrect.width;
 601         return 0;
 602 }
 603
 604 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 605 {
 606         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 607         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 608         if (stat != 0) {
 609                 return stat;
 610         }
 611         *val = cap->defrect.height;
 612         return 0;
 613 }
 614
 615 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 616 {
 617         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 618         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 619         if (stat != 0) {
 620                 return stat;
 621         }
 622         *val = cap->pixelaspect.numerator;
 623         return 0;
 624 }
 625
 626 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 627 {
 628         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 629         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 630         if (stat != 0) {
 631                 return stat;
 632         }
 633         *val = cap->pixelaspect.denominator;
 634         return 0;
 635 }
 636
 637 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 638 {
 639         /* Actual maximum depends on the video standard in effect. */
 640         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 641                 *vp = 480;
 642         } else {
 643                 *vp = 576;
 644         }
 645         return 0;
 646 }
 647
 648 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 649 {
 650         /* Actual minimum depends on device digitizer type. */
 651         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 652                 *vp = 75;
 653         } else {
 654                 *vp = 17;
 655         }
 656         return 0;
 657 }
 658
 659 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 660 {
 661         *vp = cptr->hdw->input_val;
 662         return 0;
 663 }
 664
 665 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 666 {
 667         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 668 }
 669
 670 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 671 {
 672         return pvr2_hdw_set_input(cptr->hdw,v);
 673 }
 674
 675 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 676 {
 677         return cptr->hdw->input_dirty != 0;
 678 }
 679
 680 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 681 {
 682         cptr->hdw->input_dirty = 0;
 683 }
 684
 685
 686 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 687 {
 688         unsigned long fv;
 689         struct pvr2_hdw *hdw = cptr->hdw;
 690         if (hdw->tuner_signal_stale) {
 691                 pvr2_hdw_status_poll(hdw);
 692         }
 693         fv = hdw->tuner_signal_info.rangehigh;
 694         if (!fv) {
 695                 /* Safety fallback */
 696                 *vp = TV_MAX_FREQ;
 697                 return 0;
 698         }
 699         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 700                 fv = (fv * 125) / 2;
 701         } else {
 702                 fv = fv * 62500;
 703         }
 704         *vp = fv;
 705         return 0;
 706 }
 707
 708 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 709 {
 710         unsigned long fv;
 711         struct pvr2_hdw *hdw = cptr->hdw;
 712         if (hdw->tuner_signal_stale) {
 713                 pvr2_hdw_status_poll(hdw);
 714         }
 715         fv = hdw->tuner_signal_info.rangelow;
 716         if (!fv) {
 717                 /* Safety fallback */
 718                 *vp = TV_MIN_FREQ;
 719                 return 0;
 720         }
 721         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 722                 fv = (fv * 125) / 2;
 723         } else {
 724                 fv = fv * 62500;
 725         }
 726         *vp = fv;
 727         return 0;
 728 }
 729
 730 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 731 {
 732         return cptr->hdw->enc_stale != 0;
 733 }
 734
 735 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 736 {
 737         cptr->hdw->enc_stale = 0;
 738         cptr->hdw->enc_unsafe_stale = 0;
 739 }
 740
 741 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 742 {
 743         int ret;
 744         struct v4l2_ext_controls cs;
 745         struct v4l2_ext_control c1;
 746         memset(&cs,0,sizeof(cs));
 747         memset(&c1,0,sizeof(c1));
 748         cs.controls = &c1;
 749         cs.count = 1;
 750         c1.id = cptr->info->v4l_id;
 751         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 752                                 VIDIOC_G_EXT_CTRLS);
 753         if (ret) return ret;
 754         *vp = c1.value;
 755         return 0;
 756 }
 757
 758 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 759 {
 760         int ret;
 761         struct pvr2_hdw *hdw = cptr->hdw;
 762         struct v4l2_ext_controls cs;
 763         struct v4l2_ext_control c1;
 764         memset(&cs,0,sizeof(cs));
 765         memset(&c1,0,sizeof(c1));
 766         cs.controls = &c1;
 767         cs.count = 1;
 768         c1.id = cptr->info->v4l_id;
 769         c1.value = v;
 770         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 771                                 hdw->state_encoder_run, &cs,
 772                                 VIDIOC_S_EXT_CTRLS);
 773         if (ret == -EBUSY) {
 774                 /* Oops.  cx2341x is telling us it's not safe to change
 775                    this control while we're capturing.  Make a note of this
 776                    fact so that the pipeline will be stopped the next time
 777                    controls are committed.  Then go on ahead and store this
 778                    change anyway. */
 779                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 780                                         0, &cs,
 781                                         VIDIOC_S_EXT_CTRLS);
 782                 if (!ret) hdw->enc_unsafe_stale = !0;
 783         }
 784         if (ret) return ret;
 785         hdw->enc_stale = !0;
 786         return 0;
 787 }
 788
 789 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 790 {
 791         struct v4l2_queryctrl qctrl;
 792         struct pvr2_ctl_info *info;
 793         qctrl.id = cptr->info->v4l_id;
 794         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 795         /* Strip out the const so we can adjust a function pointer.  It's
 796            OK to do this here because we know this is a dynamically created
 797            control, so the underlying storage for the info pointer is (a)
 798            private to us, and (b) not in read-only storage.  Either we do
 799            this or we significantly complicate the underlying control
 800            implementation. */
 801         info = (struct pvr2_ctl_info *)(cptr->info);
 802         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 803                 if (info->set_value) {
 804                         info->set_value = NULL;
 805                 }
 806         } else {
 807                 if (!(info->set_value)) {
 808                         info->set_value = ctrl_cx2341x_set;
 809                 }
 810         }
 811         return qctrl.flags;
 812 }
 813
 814 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 815 {
 816         *vp = cptr->hdw->state_pipeline_req;
 817         return 0;
 818 }
 819
 820 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 821 {
 822         *vp = cptr->hdw->master_state;
 823         return 0;
 824 }
 825
 826 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 827 {
 828         int result = pvr2_hdw_is_hsm(cptr->hdw);
 829         *vp = PVR2_CVAL_HSM_FULL;
 830         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 831         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 832         return 0;
 833 }
 834
 835 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 836 {
 837         *vp = cptr->hdw->std_mask_avail;
 838         return 0;
 839 }
 840
 841 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 842 {
 843         struct pvr2_hdw *hdw = cptr->hdw;
 844         v4l2_std_id ns;
 845         ns = hdw->std_mask_avail;
 846         ns = (ns & ~m) | (v & m);
 847         if (ns == hdw->std_mask_avail) return 0;
 848         hdw->std_mask_avail = ns;
 849         pvr2_hdw_internal_set_std_avail(hdw);
 850         pvr2_hdw_internal_find_stdenum(hdw);
 851         return 0;
 852 }
 853
 854 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 855                                char *bufPtr,unsigned int bufSize,
 856                                unsigned int *len)
 857 {
 858         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 859         return 0;
 860 }
 861
 862 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 863                                const char *bufPtr,unsigned int bufSize,
 864                                int *mskp,int *valp)
 865 {
 866         int ret;
 867         v4l2_std_id id;
 868         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 869         if (ret < 0) return ret;
 870         if (mskp) *mskp = id;
 871         if (valp) *valp = id;
 872         return 0;
 873 }
 874
 875 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 876 {
 877         *vp = cptr->hdw->std_mask_cur;
 878         return 0;
 879 }
 880
 881 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 882 {
 883         struct pvr2_hdw *hdw = cptr->hdw;
 884         v4l2_std_id ns;
 885         ns = hdw->std_mask_cur;
 886         ns = (ns & ~m) | (v & m);
 887         if (ns == hdw->std_mask_cur) return 0;
 888         hdw->std_mask_cur = ns;
 889         hdw->std_dirty = !0;
 890         pvr2_hdw_internal_find_stdenum(hdw);
 891         return 0;
 892 }
 893
 894 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 895 {
 896         return cptr->hdw->std_dirty != 0;
 897 }
 898
 899 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 900 {
 901         cptr->hdw->std_dirty = 0;
 902 }
 903
 904 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 905 {
 906         struct pvr2_hdw *hdw = cptr->hdw;
 907         pvr2_hdw_status_poll(hdw);
 908         *vp = hdw->tuner_signal_info.signal;
 909         return 0;
 910 }
 911
 912 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 913 {
 914         int val = 0;
 915         unsigned int subchan;
 916         struct pvr2_hdw *hdw = cptr->hdw;
 917         pvr2_hdw_status_poll(hdw);
 918         subchan = hdw->tuner_signal_info.rxsubchans;
 919         if (subchan & V4L2_TUNER_SUB_MONO) {
 920                 val |= (1 << V4L2_TUNER_MODE_MONO);
 921         }
 922         if (subchan & V4L2_TUNER_SUB_STEREO) {
 923                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 924         }
 925         if (subchan & V4L2_TUNER_SUB_LANG1) {
 926                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 927         }
 928         if (subchan & V4L2_TUNER_SUB_LANG2) {
 929                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 930         }
 931         *vp = val;
 932         return 0;
 933 }
 934
 935
 936 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 937 {
 938         struct pvr2_hdw *hdw = cptr->hdw;
 939         if (v < 0) return -EINVAL;
 940         if (v > hdw->std_enum_cnt) return -EINVAL;
 941         hdw->std_enum_cur = v;
 942         if (!v) return 0;
 943         v--;
 944         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 945         hdw->std_mask_cur = hdw->std_defs[v].id;
 946         hdw->std_dirty = !0;
 947         return 0;
 948 }
 949
 950
 951 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 952 {
 953         *vp = cptr->hdw->std_enum_cur;
 954         return 0;
 955 }
 956
 957
 958 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 959 {
 960         return cptr->hdw->std_dirty != 0;
 961 }
 962
 963
 964 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 965 {
 966         cptr->hdw->std_dirty = 0;
 967 }
 968
 969
 970 #define DEFINT(vmin,vmax) \
 971         .type = pvr2_ctl_int, \
 972         .def.type_int.min_value = vmin, \
 973         .def.type_int.max_value = vmax
 974
 975 #define DEFENUM(tab) \
 976         .type = pvr2_ctl_enum, \
 977         .def.type_enum.count = ARRAY_SIZE(tab), \
 978         .def.type_enum.value_names = tab
 979
 980 #define DEFBOOL \
 981         .type = pvr2_ctl_bool
 982
 983 #define DEFMASK(msk,tab) \
 984         .type = pvr2_ctl_bitmask, \
 985         .def.type_bitmask.valid_bits = msk, \
 986         .def.type_bitmask.bit_names = tab
 987
 988 #define DEFREF(vname) \
 989         .set_value = ctrl_set_##vname, \
 990         .get_value = ctrl_get_##vname, \
 991         .is_dirty = ctrl_isdirty_##vname, \
 992         .clear_dirty = ctrl_cleardirty_##vname
 993
 994
 995 #define VCREATE_FUNCS(vname) \
 996 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 997 {*vp = cptr->hdw->vname##_val; return 0;} \
 998 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 999 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
1000 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
1001 {return cptr->hdw->vname##_dirty != 0;} \
1002 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
1003 {cptr->hdw->vname##_dirty = 0;}
1004
1005 VCREATE_FUNCS(brightness)
1006 VCREATE_FUNCS(contrast)
1007 VCREATE_FUNCS(saturation)
1008 VCREATE_FUNCS(hue)
1009 VCREATE_FUNCS(volume)
1010 VCREATE_FUNCS(balance)
1011 VCREATE_FUNCS(bass)
1012 VCREATE_FUNCS(treble)
1013 VCREATE_FUNCS(mute)
1014 VCREATE_FUNCS(cropl)
1015 VCREATE_FUNCS(cropt)
1016 VCREATE_FUNCS(cropw)
1017 VCREATE_FUNCS(croph)
1018 VCREATE_FUNCS(audiomode)
1019 VCREATE_FUNCS(res_hor)
1020 VCREATE_FUNCS(res_ver)
1021 VCREATE_FUNCS(srate)
1022
1023 /* Table definition of all controls which can be manipulated */
1024 static const struct pvr2_ctl_info control_defs[] = {
1025         {
1026                 .v4l_id = V4L2_CID_BRIGHTNESS,
1027                 .desc = "Brightness",
1028                 .name = "brightness",
1029                 .default_value = 128,
1030                 DEFREF(brightness),
1031                 DEFINT(0,255),
1032         },{
1033                 .v4l_id = V4L2_CID_CONTRAST,
1034                 .desc = "Contrast",
1035                 .name = "contrast",
1036                 .default_value = 68,
1037                 DEFREF(contrast),
1038                 DEFINT(0,127),
1039         },{
1040                 .v4l_id = V4L2_CID_SATURATION,
1041                 .desc = "Saturation",
1042                 .name = "saturation",
1043                 .default_value = 64,
1044                 DEFREF(saturation),
1045                 DEFINT(0,127),
1046         },{
1047                 .v4l_id = V4L2_CID_HUE,
1048                 .desc = "Hue",
1049                 .name = "hue",
1050                 .default_value = 0,
1051                 DEFREF(hue),
1052                 DEFINT(-128,127),
1053         },{
1054                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1055                 .desc = "Volume",
1056                 .name = "volume",
1057                 .default_value = 62000,
1058                 DEFREF(volume),
1059                 DEFINT(0,65535),
1060         },{
1061                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1062                 .desc = "Balance",
1063                 .name = "balance",
1064                 .default_value = 0,
1065                 DEFREF(balance),
1066                 DEFINT(-32768,32767),
1067         },{
1068                 .v4l_id = V4L2_CID_AUDIO_BASS,
1069                 .desc = "Bass",
1070                 .name = "bass",
1071                 .default_value = 0,
1072                 DEFREF(bass),
1073                 DEFINT(-32768,32767),
1074         },{
1075                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1076                 .desc = "Treble",
1077                 .name = "treble",
1078                 .default_value = 0,
1079                 DEFREF(treble),
1080                 DEFINT(-32768,32767),
1081         },{
1082                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1083                 .desc = "Mute",
1084                 .name = "mute",
1085                 .default_value = 0,
1086                 DEFREF(mute),
1087                 DEFBOOL,
1088         }, {
1089                 .desc = "Capture crop left margin",
1090                 .name = "crop_left",
1091                 .internal_id = PVR2_CID_CROPL,
1092                 .default_value = 0,
1093                 DEFREF(cropl),
1094                 DEFINT(-129, 340),
1095                 .get_min_value = ctrl_cropl_min_get,
1096                 .get_max_value = ctrl_cropl_max_get,
1097                 .get_def_value = ctrl_get_cropcapdl,
1098         }, {
1099                 .desc = "Capture crop top margin",
1100                 .name = "crop_top",
1101                 .internal_id = PVR2_CID_CROPT,
1102                 .default_value = 0,
1103                 DEFREF(cropt),
1104                 DEFINT(-35, 544),
1105                 .get_min_value = ctrl_cropt_min_get,
1106                 .get_max_value = ctrl_cropt_max_get,
1107                 .get_def_value = ctrl_get_cropcapdt,
1108         }, {
1109                 .desc = "Capture crop width",
1110                 .name = "crop_width",
1111                 .internal_id = PVR2_CID_CROPW,
1112                 .default_value = 720,
1113                 DEFREF(cropw),
1114                 .get_max_value = ctrl_cropw_max_get,
1115                 .get_def_value = ctrl_get_cropcapdw,
1116         }, {
1117                 .desc = "Capture crop height",
1118                 .name = "crop_height",
1119                 .internal_id = PVR2_CID_CROPH,
1120                 .default_value = 480,
1121                 DEFREF(croph),
1122                 .get_max_value = ctrl_croph_max_get,
1123                 .get_def_value = ctrl_get_cropcapdh,
1124         }, {
1125                 .desc = "Capture capability pixel aspect numerator",
1126                 .name = "cropcap_pixel_numerator",
1127                 .internal_id = PVR2_CID_CROPCAPPAN,
1128                 .get_value = ctrl_get_cropcappan,
1129         }, {
1130                 .desc = "Capture capability pixel aspect denominator",
1131                 .name = "cropcap_pixel_denominator",
1132                 .internal_id = PVR2_CID_CROPCAPPAD,
1133                 .get_value = ctrl_get_cropcappad,
1134         }, {
1135                 .desc = "Capture capability bounds top",
1136                 .name = "cropcap_bounds_top",
1137                 .internal_id = PVR2_CID_CROPCAPBT,
1138                 .get_value = ctrl_get_cropcapbt,
1139         }, {
1140                 .desc = "Capture capability bounds left",
1141                 .name = "cropcap_bounds_left",
1142                 .internal_id = PVR2_CID_CROPCAPBL,
1143                 .get_value = ctrl_get_cropcapbl,
1144         }, {
1145                 .desc = "Capture capability bounds width",
1146                 .name = "cropcap_bounds_width",
1147                 .internal_id = PVR2_CID_CROPCAPBW,
1148                 .get_value = ctrl_get_cropcapbw,
1149         }, {
1150                 .desc = "Capture capability bounds height",
1151                 .name = "cropcap_bounds_height",
1152                 .internal_id = PVR2_CID_CROPCAPBH,
1153                 .get_value = ctrl_get_cropcapbh,
1154         },{
1155                 .desc = "Video Source",
1156                 .name = "input",
1157                 .internal_id = PVR2_CID_INPUT,
1158                 .default_value = PVR2_CVAL_INPUT_TV,
1159                 .check_value = ctrl_check_input,
1160                 DEFREF(input),
1161                 DEFENUM(control_values_input),
1162         },{
1163                 .desc = "Audio Mode",
1164                 .name = "audio_mode",
1165                 .internal_id = PVR2_CID_AUDIOMODE,
1166                 .default_value = V4L2_TUNER_MODE_STEREO,
1167                 DEFREF(audiomode),
1168                 DEFENUM(control_values_audiomode),
1169         },{
1170                 .desc = "Horizontal capture resolution",
1171                 .name = "resolution_hor",
1172                 .internal_id = PVR2_CID_HRES,
1173                 .default_value = 720,
1174                 DEFREF(res_hor),
1175                 DEFINT(19,720),
1176         },{
1177                 .desc = "Vertical capture resolution",
1178                 .name = "resolution_ver",
1179                 .internal_id = PVR2_CID_VRES,
1180                 .default_value = 480,
1181                 DEFREF(res_ver),
1182                 DEFINT(17,576),
1183                 /* Hook in check for video standard and adjust maximum
1184                    depending on the standard. */
1185                 .get_max_value = ctrl_vres_max_get,
1186                 .get_min_value = ctrl_vres_min_get,
1187         },{
1188                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1189                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1190                 .desc = "Audio Sampling Frequency",
1191                 .name = "srate",
1192                 DEFREF(srate),
1193                 DEFENUM(control_values_srate),
1194         },{
1195                 .desc = "Tuner Frequency (Hz)",
1196                 .name = "frequency",
1197                 .internal_id = PVR2_CID_FREQUENCY,
1198                 .default_value = 0,
1199                 .set_value = ctrl_freq_set,
1200                 .get_value = ctrl_freq_get,
1201                 .is_dirty = ctrl_freq_is_dirty,
1202                 .clear_dirty = ctrl_freq_clear_dirty,
1203                 DEFINT(0,0),
1204                 /* Hook in check for input value (tv/radio) and adjust
1205                    max/min values accordingly */
1206                 .get_max_value = ctrl_freq_max_get,
1207                 .get_min_value = ctrl_freq_min_get,
1208         },{
1209                 .desc = "Channel",
1210                 .name = "channel",
1211                 .set_value = ctrl_channel_set,
1212                 .get_value = ctrl_channel_get,
1213                 DEFINT(0,FREQTABLE_SIZE),
1214         },{
1215                 .desc = "Channel Program Frequency",
1216                 .name = "freq_table_value",
1217                 .set_value = ctrl_channelfreq_set,
1218                 .get_value = ctrl_channelfreq_get,
1219                 DEFINT(0,0),
1220                 /* Hook in check for input value (tv/radio) and adjust
1221                    max/min values accordingly */
1222                 .get_max_value = ctrl_freq_max_get,
1223                 .get_min_value = ctrl_freq_min_get,
1224         },{
1225                 .desc = "Channel Program ID",
1226                 .name = "freq_table_channel",
1227                 .set_value = ctrl_channelprog_set,
1228                 .get_value = ctrl_channelprog_get,
1229                 DEFINT(0,FREQTABLE_SIZE),
1230         },{
1231                 .desc = "Streaming Enabled",
1232                 .name = "streaming_enabled",
1233                 .get_value = ctrl_streamingenabled_get,
1234                 DEFBOOL,
1235         },{
1236                 .desc = "USB Speed",
1237                 .name = "usb_speed",
1238                 .get_value = ctrl_hsm_get,
1239                 DEFENUM(control_values_hsm),
1240         },{
1241                 .desc = "Master State",
1242                 .name = "master_state",
1243                 .get_value = ctrl_masterstate_get,
1244                 DEFENUM(pvr2_state_names),
1245         },{
1246                 .desc = "Signal Present",
1247                 .name = "signal_present",
1248                 .get_value = ctrl_signal_get,
1249                 DEFINT(0,65535),
1250         },{
1251                 .desc = "Audio Modes Present",
1252                 .name = "audio_modes_present",
1253                 .get_value = ctrl_audio_modes_present_get,
1254                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1255                    v4l.  Nothing outside of this module cares about this,
1256                    but I reuse it in order to also reuse the
1257                    control_values_audiomode string table. */
1258                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1259                          (1 << V4L2_TUNER_MODE_STEREO)|
1260                          (1 << V4L2_TUNER_MODE_LANG1)|
1261                          (1 << V4L2_TUNER_MODE_LANG2)),
1262                         control_values_audiomode),
1263         },{
1264                 .desc = "Video Standards Available Mask",
1265                 .name = "video_standard_mask_available",
1266                 .internal_id = PVR2_CID_STDAVAIL,
1267                 .skip_init = !0,
1268                 .get_value = ctrl_stdavail_get,
1269                 .set_value = ctrl_stdavail_set,
1270                 .val_to_sym = ctrl_std_val_to_sym,
1271                 .sym_to_val = ctrl_std_sym_to_val,
1272                 .type = pvr2_ctl_bitmask,
1273         },{
1274                 .desc = "Video Standards In Use Mask",
1275                 .name = "video_standard_mask_active",
1276                 .internal_id = PVR2_CID_STDCUR,
1277                 .skip_init = !0,
1278                 .get_value = ctrl_stdcur_get,
1279                 .set_value = ctrl_stdcur_set,
1280                 .is_dirty = ctrl_stdcur_is_dirty,
1281                 .clear_dirty = ctrl_stdcur_clear_dirty,
1282                 .val_to_sym = ctrl_std_val_to_sym,
1283                 .sym_to_val = ctrl_std_sym_to_val,
1284                 .type = pvr2_ctl_bitmask,
1285         },{
1286                 .desc = "Video Standard Name",
1287                 .name = "video_standard",
1288                 .internal_id = PVR2_CID_STDENUM,
1289                 .skip_init = !0,
1290                 .get_value = ctrl_stdenumcur_get,
1291                 .set_value = ctrl_stdenumcur_set,
1292                 .is_dirty = ctrl_stdenumcur_is_dirty,
1293                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1294                 .type = pvr2_ctl_enum,
1295         }
1296 };
1297
1298 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1299
1300
1301 const char *pvr2_config_get_name(enum pvr2_config cfg)
1302 {
1303         switch (cfg) {
1304         case pvr2_config_empty: return "empty";
1305         case pvr2_config_mpeg: return "mpeg";
1306         case pvr2_config_vbi: return "vbi";
1307         case pvr2_config_pcm: return "pcm";
1308         case pvr2_config_rawvideo: return "raw video";
1309         }
1310         return "<unknown>";
1311 }
1312
1313
1314 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1315 {
1316         return hdw->usb_dev;
1317 }
1318
1319
1320 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1321 {
1322         return hdw->serial_number;
1323 }
1324
1325
1326 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1327 {
1328         return hdw->bus_info;
1329 }
1330
1331
1332 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1333 {
1334         return hdw->identifier;
1335 }
1336
1337
1338 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1339 {
1340         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1341 }
1342
1343 /* Set the currently tuned frequency and account for all possible
1344    driver-core side effects of this action. */
1345 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1346 {
1347         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1348                 if (hdw->freqSelector) {
1349                         /* Swing over to radio frequency selection */
1350                         hdw->freqSelector = 0;
1351                         hdw->freqDirty = !0;
1352                 }
1353                 if (hdw->freqValRadio != val) {
1354                         hdw->freqValRadio = val;
1355                         hdw->freqSlotRadio = 0;
1356                         hdw->freqDirty = !0;
1357                 }
1358         } else {
1359                 if (!(hdw->freqSelector)) {
1360                         /* Swing over to television frequency selection */
1361                         hdw->freqSelector = 1;
1362                         hdw->freqDirty = !0;
1363                 }
1364                 if (hdw->freqValTelevision != val) {
1365                         hdw->freqValTelevision = val;
1366                         hdw->freqSlotTelevision = 0;
1367                         hdw->freqDirty = !0;
1368                 }
1369         }
1370 }
1371
1372 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1373 {
1374         return hdw->unit_number;
1375 }
1376
1377
1378 /* Attempt to locate one of the given set of files.  Messages are logged
1379    appropriate to what has been found.  The return value will be 0 or
1380    greater on success (it will be the index of the file name found) and
1381    fw_entry will be filled in.  Otherwise a negative error is returned on
1382    failure.  If the return value is -ENOENT then no viable firmware file
1383    could be located. */
1384 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1385                                 const struct firmware **fw_entry,
1386                                 const char *fwtypename,
1387                                 unsigned int fwcount,
1388                                 const char *fwnames[])
1389 {
1390         unsigned int idx;
1391         int ret = -EINVAL;
1392         for (idx = 0; idx < fwcount; idx++) {
1393                 ret = request_firmware(fw_entry,
1394                                        fwnames[idx],
1395                                        &hdw->usb_dev->dev);
1396                 if (!ret) {
1397                         trace_firmware("Located %s firmware: %s;"
1398                                        " uploading...",
1399                                        fwtypename,
1400                                        fwnames[idx]);
1401                         return idx;
1402                 }
1403                 if (ret == -ENOENT) continue;
1404                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1405                            "request_firmware fatal error with code=%d",ret);
1406                 return ret;
1407         }
1408         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1409                    "***WARNING***"
1410                    " Device %s firmware"
1411                    " seems to be missing.",
1412                    fwtypename);
1413         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1414                    "Did you install the pvrusb2 firmware files"
1415                    " in their proper location?");
1416         if (fwcount == 1) {
1417                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1418                            "request_firmware unable to locate %s file %s",
1419                            fwtypename,fwnames[0]);
1420         } else {
1421                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1422                            "request_firmware unable to locate"
1423                            " one of the following %s files:",
1424                            fwtypename);
1425                 for (idx = 0; idx < fwcount; idx++) {
1426                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1427                                    "request_firmware: Failed to find %s",
1428                                    fwnames[idx]);
1429                 }
1430         }
1431         return ret;
1432 }
1433
1434
1435 /*
1436  * pvr2_upload_firmware1().
1437  *
1438  * Send the 8051 firmware to the device.  After the upload, arrange for
1439  * device to re-enumerate.
1440  *
1441  * NOTE : the pointer to the firmware data given by request_firmware()
1442  * is not suitable for an usb transaction.
1443  *
1444  */
1445 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1446 {
1447         const struct firmware *fw_entry = NULL;
1448         void  *fw_ptr;
1449         unsigned int pipe;
1450         unsigned int fwsize;
1451         int ret;
1452         u16 address;
1453
1454         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1455                 hdw->fw1_state = FW1_STATE_OK;
1456                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1457                            "Connected device type defines"
1458                            " no firmware to upload; ignoring firmware");
1459                 return -ENOTTY;
1460         }
1461
1462         hdw->fw1_state = FW1_STATE_FAILED; // default result
1463
1464         trace_firmware("pvr2_upload_firmware1");
1465
1466         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1467                                    hdw->hdw_desc->fx2_firmware.cnt,
1468                                    hdw->hdw_desc->fx2_firmware.lst);
1469         if (ret < 0) {
1470                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1471                 return ret;
1472         }
1473
1474         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1475
1476         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1477         fwsize = fw_entry->size;
1478
1479         if ((fwsize != 0x2000) &&
1480             (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
1481                 if (hdw->hdw_desc->flag_fx2_16kb) {
1482                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1483                                    "Wrong fx2 firmware size"
1484                                    " (expected 8192 or 16384, got %u)",
1485                                    fwsize);
1486                 } else {
1487                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1488                                    "Wrong fx2 firmware size"
1489                                    " (expected 8192, got %u)",
1490                                    fwsize);
1491                 }
1492                 release_firmware(fw_entry);
1493                 return -ENOMEM;
1494         }
1495
1496         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1497         if (fw_ptr == NULL){
1498                 release_firmware(fw_entry);
1499                 return -ENOMEM;
1500         }
1501
1502         /* We have to hold the CPU during firmware upload. */
1503         pvr2_hdw_cpureset_assert(hdw,1);
1504
1505         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1506            chunk. */
1507
1508         ret = 0;
1509         for (address = 0; address < fwsize; address += 0x800) {
1510                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1511                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1512                                        0, fw_ptr, 0x800, HZ);
1513         }
1514
1515         trace_firmware("Upload done, releasing device's CPU");
1516
1517         /* Now release the CPU.  It will disconnect and reconnect later. */
1518         pvr2_hdw_cpureset_assert(hdw,0);
1519
1520         kfree(fw_ptr);
1521         release_firmware(fw_entry);
1522
1523         trace_firmware("Upload done (%d bytes sent)",ret);
1524
1525         /* We should have written fwsize bytes */
1526         if (ret == fwsize) {
1527                 hdw->fw1_state = FW1_STATE_RELOAD;
1528                 return 0;
1529         }
1530
1531         return -EIO;
1532 }
1533
1534
1535 /*
1536  * pvr2_upload_firmware2()
1537  *
1538  * This uploads encoder firmware on endpoint 2.
1539  *
1540  */
1541
1542 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1543 {
1544         const struct firmware *fw_entry = NULL;
1545         void  *fw_ptr;
1546         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1547         int actual_length;
1548         int ret = 0;
1549         int fwidx;
1550         static const char *fw_files[] = {
1551                 CX2341X_FIRM_ENC_FILENAME,
1552         };
1553
1554         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1555                 return 0;
1556         }
1557
1558         trace_firmware("pvr2_upload_firmware2");
1559
1560         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1561                                    ARRAY_SIZE(fw_files), fw_files);
1562         if (ret < 0) return ret;
1563         fwidx = ret;
1564         ret = 0;
1565         /* Since we're about to completely reinitialize the encoder,
1566            invalidate our cached copy of its configuration state.  Next
1567            time we configure the encoder, then we'll fully configure it. */
1568         hdw->enc_cur_valid = 0;
1569
1570         /* Encoder is about to be reset so note that as far as we're
1571            concerned now, the encoder has never been run. */
1572         del_timer_sync(&hdw->encoder_run_timer);
1573         if (hdw->state_encoder_runok) {
1574                 hdw->state_encoder_runok = 0;
1575                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1576         }
1577
1578         /* First prepare firmware loading */
1579         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1580         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1581         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1582         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1583         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1584         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1585         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1586         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1587         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1588         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1589         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1590         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1591         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1592         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1593         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1594         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1595         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1596         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1597
1598         if (ret) {
1599                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1600                            "firmware2 upload prep failed, ret=%d",ret);
1601                 release_firmware(fw_entry);
1602                 goto done;
1603         }
1604
1605         /* Now send firmware */
1606
1607         fw_len = fw_entry->size;
1608
1609         if (fw_len % sizeof(u32)) {
1610                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1611                            "size of %s firmware"
1612                            " must be a multiple of %zu bytes",
1613                            fw_files[fwidx],sizeof(u32));
1614                 release_firmware(fw_entry);
1615                 ret = -EINVAL;
1616                 goto done;
1617         }
1618
1619         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1620         if (fw_ptr == NULL){
1621                 release_firmware(fw_entry);
1622                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1623                            "failed to allocate memory for firmware2 upload");
1624                 ret = -ENOMEM;
1625                 goto done;
1626         }
1627
1628         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1629
1630         fw_done = 0;
1631         for (fw_done = 0; fw_done < fw_len;) {
1632                 bcnt = fw_len - fw_done;
1633                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1634                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1635                 /* Usbsnoop log shows that we must swap bytes... */
1636                 /* Some background info: The data being swapped here is a
1637                    firmware image destined for the mpeg encoder chip that
1638                    lives at the other end of a USB endpoint.  The encoder
1639                    chip always talks in 32 bit chunks and its storage is
1640                    organized into 32 bit words.  However from the file
1641                    system to the encoder chip everything is purely a byte
1642                    stream.  The firmware file's contents are always 32 bit
1643                    swapped from what the encoder expects.  Thus the need
1644                    always exists to swap the bytes regardless of the endian
1645                    type of the host processor and therefore swab32() makes
1646                    the most sense. */
1647                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1648                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1649
1650                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1651                                     &actual_length, HZ);
1652                 ret |= (actual_length != bcnt);
1653                 if (ret) break;
1654                 fw_done += bcnt;
1655         }
1656
1657         trace_firmware("upload of %s : %i / %i ",
1658                        fw_files[fwidx],fw_done,fw_len);
1659
1660         kfree(fw_ptr);
1661         release_firmware(fw_entry);
1662
1663         if (ret) {
1664                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1665                            "firmware2 upload transfer failure");
1666                 goto done;
1667         }
1668
1669         /* Finish upload */
1670
1671         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1672         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1673         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1674
1675         if (ret) {
1676                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1677                            "firmware2 upload post-proc failure");
1678         }
1679
1680  done:
1681         if (hdw->hdw_desc->signal_routing_scheme ==
1682             PVR2_ROUTING_SCHEME_GOTVIEW) {
1683                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1684                    hardware. */
1685                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1686         }
1687         return ret;
1688 }
1689
1690
1691 static const char *pvr2_get_state_name(unsigned int st)
1692 {
1693         if (st < ARRAY_SIZE(pvr2_state_names)) {
1694                 return pvr2_state_names[st];
1695         }
1696         return "???";
1697 }
1698
1699 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1700 {
1701         /* Even though we really only care about the video decoder chip at
1702            this point, we'll broadcast stream on/off to all sub-devices
1703            anyway, just in case somebody else wants to hear the
1704            command... */
1705         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1706                    (enablefl ? "on" : "off"));
1707         v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1708         v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
1709         if (hdw->decoder_client_id) {
1710                 /* We get here if the encoder has been noticed.  Otherwise
1711                    we'll issue a warning to the user (which should
1712                    normally never happen). */
1713                 return 0;
1714         }
1715         if (!hdw->flag_decoder_missed) {
1716                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1717                            "WARNING: No decoder present");
1718                 hdw->flag_decoder_missed = !0;
1719                 trace_stbit("flag_decoder_missed",
1720                             hdw->flag_decoder_missed);
1721         }
1722         return -EIO;
1723 }
1724
1725
1726 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1727 {
1728         return hdw->master_state;
1729 }
1730
1731
1732 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1733 {
1734         if (!hdw->flag_tripped) return 0;
1735         hdw->flag_tripped = 0;
1736         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1737                    "Clearing driver error statuss");
1738         return !0;
1739 }
1740
1741
1742 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1743 {
1744         int fl;
1745         LOCK_TAKE(hdw->big_lock); do {
1746                 fl = pvr2_hdw_untrip_unlocked(hdw);
1747         } while (0); LOCK_GIVE(hdw->big_lock);
1748         if (fl) pvr2_hdw_state_sched(hdw);
1749         return 0;
1750 }
1751
1752
1753
1754
1755 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1756 {
1757         return hdw->state_pipeline_req != 0;
1758 }
1759
1760
1761 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1762 {
1763         int ret,st;
1764         LOCK_TAKE(hdw->big_lock); do {
1765                 pvr2_hdw_untrip_unlocked(hdw);
1766                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1767                         hdw->state_pipeline_req = enable_flag != 0;
1768                         pvr2_trace(PVR2_TRACE_START_STOP,
1769                                    "/*--TRACE_STREAM--*/ %s",
1770                                    enable_flag ? "enable" : "disable");
1771                 }
1772                 pvr2_hdw_state_sched(hdw);
1773         } while (0); LOCK_GIVE(hdw->big_lock);
1774         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1775         if (enable_flag) {
1776                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1777                         if (st != PVR2_STATE_READY) return -EIO;
1778                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1779                 }
1780         }
1781         return 0;
1782 }
1783
1784
1785 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1786 {
1787         int fl;
1788         LOCK_TAKE(hdw->big_lock);
1789         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1790                 hdw->desired_stream_type = config;
1791                 hdw->state_pipeline_config = 0;
1792                 trace_stbit("state_pipeline_config",
1793                             hdw->state_pipeline_config);
1794                 pvr2_hdw_state_sched(hdw);
1795         }
1796         LOCK_GIVE(hdw->big_lock);
1797         if (fl) return 0;
1798         return pvr2_hdw_wait(hdw,0);
1799 }
1800
1801
1802 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1803 {
1804         int unit_number = hdw->unit_number;
1805         int tp = -1;
1806         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1807                 tp = tuner[unit_number];
1808         }
1809         if (tp < 0) return -EINVAL;
1810         hdw->tuner_type = tp;
1811         hdw->tuner_updated = !0;
1812         return 0;
1813 }
1814
1815
1816 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1817 {
1818         int unit_number = hdw->unit_number;
1819         int tp = 0;
1820         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1821                 tp = video_std[unit_number];
1822                 if (tp) return tp;
1823         }
1824         return 0;
1825 }
1826
1827
1828 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1829 {
1830         int unit_number = hdw->unit_number;
1831         int tp = 0;
1832         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1833                 tp = tolerance[unit_number];
1834         }
1835         return tp;
1836 }
1837
1838
1839 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1840 {
1841         /* Try a harmless request to fetch the eeprom's address over
1842            endpoint 1.  See what happens.  Only the full FX2 image can
1843            respond to this.  If this probe fails then likely the FX2
1844            firmware needs be loaded. */
1845         int result;
1846         LOCK_TAKE(hdw->ctl_lock); do {
1847                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1848                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1849                                            hdw->cmd_buffer,1,
1850                                            hdw->cmd_buffer,1);
1851                 if (result < 0) break;
1852         } while(0); LOCK_GIVE(hdw->ctl_lock);
1853         if (result) {
1854                 pvr2_trace(PVR2_TRACE_INIT,
1855                            "Probe of device endpoint 1 result status %d",
1856                            result);
1857         } else {
1858                 pvr2_trace(PVR2_TRACE_INIT,
1859                            "Probe of device endpoint 1 succeeded");
1860         }
1861         return result == 0;
1862 }
1863
1864 struct pvr2_std_hack {
1865         v4l2_std_id pat;  /* Pattern to match */
1866         v4l2_std_id msk;  /* Which bits we care about */
1867         v4l2_std_id std;  /* What additional standards or default to set */
1868 };
1869
1870 /* This data structure labels specific combinations of standards from
1871    tveeprom that we'll try to recognize.  If we recognize one, then assume
1872    a specified default standard to use.  This is here because tveeprom only
1873    tells us about available standards not the intended default standard (if
1874    any) for the device in question.  We guess the default based on what has
1875    been reported as available.  Note that this is only for guessing a
1876    default - which can always be overridden explicitly - and if the user
1877    has otherwise named a default then that default will always be used in
1878    place of this table. */
1879 static const struct pvr2_std_hack std_eeprom_maps[] = {
1880         {       /* PAL(B/G) */
1881                 .pat = V4L2_STD_B|V4L2_STD_GH,
1882                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1883         },
1884         {       /* NTSC(M) */
1885                 .pat = V4L2_STD_MN,
1886                 .std = V4L2_STD_NTSC_M,
1887         },
1888         {       /* PAL(I) */
1889                 .pat = V4L2_STD_PAL_I,
1890                 .std = V4L2_STD_PAL_I,
1891         },
1892         {       /* SECAM(L/L') */
1893                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1894                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1895         },
1896         {       /* PAL(D/D1/K) */
1897                 .pat = V4L2_STD_DK,
1898                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1899         },
1900 };
1901
1902 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1903 {
1904         char buf[40];
1905         unsigned int bcnt;
1906         v4l2_std_id std1,std2,std3;
1907
1908         std1 = get_default_standard(hdw);
1909         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1910
1911         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1912         pvr2_trace(PVR2_TRACE_STD,
1913                    "Supported video standard(s) reported available"
1914                    " in hardware: %.*s",
1915                    bcnt,buf);
1916
1917         hdw->std_mask_avail = hdw->std_mask_eeprom;
1918
1919         std2 = (std1|std3) & ~hdw->std_mask_avail;
1920         if (std2) {
1921                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1922                 pvr2_trace(PVR2_TRACE_STD,
1923                            "Expanding supported video standards"
1924                            " to include: %.*s",
1925                            bcnt,buf);
1926                 hdw->std_mask_avail |= std2;
1927         }
1928
1929         pvr2_hdw_internal_set_std_avail(hdw);
1930
1931         if (std1) {
1932                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1933                 pvr2_trace(PVR2_TRACE_STD,
1934                            "Initial video standard forced to %.*s",
1935                            bcnt,buf);
1936                 hdw->std_mask_cur = std1;
1937                 hdw->std_dirty = !0;
1938                 pvr2_hdw_internal_find_stdenum(hdw);
1939                 return;
1940         }
1941         if (std3) {
1942                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1943                 pvr2_trace(PVR2_TRACE_STD,
1944                            "Initial video standard"
1945                            " (determined by device type): %.*s",bcnt,buf);
1946                 hdw->std_mask_cur = std3;
1947                 hdw->std_dirty = !0;
1948                 pvr2_hdw_internal_find_stdenum(hdw);
1949                 return;
1950         }
1951
1952         {
1953                 unsigned int idx;
1954                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1955                         if (std_eeprom_maps[idx].msk ?
1956                             ((std_eeprom_maps[idx].pat ^
1957                              hdw->std_mask_eeprom) &
1958                              std_eeprom_maps[idx].msk) :
1959                             (std_eeprom_maps[idx].pat !=
1960                              hdw->std_mask_eeprom)) continue;
1961                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1962                                                   std_eeprom_maps[idx].std);
1963                         pvr2_trace(PVR2_TRACE_STD,
1964                                    "Initial video standard guessed as %.*s",
1965                                    bcnt,buf);
1966                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1967                         hdw->std_dirty = !0;
1968                         pvr2_hdw_internal_find_stdenum(hdw);
1969                         return;
1970                 }
1971         }
1972
1973         if (hdw->std_enum_cnt > 1) {
1974                 // Autoselect the first listed standard
1975                 hdw->std_enum_cur = 1;
1976                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1977                 hdw->std_dirty = !0;
1978                 pvr2_trace(PVR2_TRACE_STD,
1979                            "Initial video standard auto-selected to %s",
1980                            hdw->std_defs[hdw->std_enum_cur-1].name);
1981                 return;
1982         }
1983
1984         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1985                    "Unable to select a viable initial video standard");
1986 }
1987
1988
1989 static unsigned int pvr2_copy_i2c_addr_list(
1990         unsigned short *dst, const unsigned char *src,
1991         unsigned int dst_max)
1992 {
1993         unsigned int cnt = 0;
1994         if (!src) return 0;
1995         while (src[cnt] && (cnt + 1) < dst_max) {
1996                 dst[cnt] = src[cnt];
1997                 cnt++;
1998         }
1999         dst[cnt] = I2C_CLIENT_END;
2000         return cnt;
2001 }
2002
2003
2004 static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
2005 {
2006         /*
2007           Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
2008           for cx25840 causes that module to correctly set up its video
2009           scaling.  This is really a problem in the cx25840 module itself,
2010           but we work around it here.  The problem has not been seen in
2011           ivtv because there VBI is supported and set up.  We don't do VBI
2012           here (at least not yet) and thus we never attempted to even set
2013           it up.
2014         */
2015         struct v4l2_format fmt;
2016         if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
2017                 /* We're not using a cx25840 so don't enable the hack */
2018                 return;
2019         }
2020
2021         pvr2_trace(PVR2_TRACE_INIT,
2022                    "Module ID %u:"
2023                    " Executing cx25840 VBI hack",
2024                    hdw->decoder_client_id);
2025         memset(&fmt, 0, sizeof(fmt));
2026         fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2027         v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
2028                              video, s_fmt, &fmt);
2029 }
2030
2031
2032 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
2033                                 const struct pvr2_device_client_desc *cd)
2034 {
2035         const char *fname;
2036         unsigned char mid;
2037         struct v4l2_subdev *sd;
2038         unsigned int i2ccnt;
2039         const unsigned char *p;
2040         /* Arbitrary count - max # i2c addresses we will probe */
2041         unsigned short i2caddr[25];
2042
2043         mid = cd->module_id;
2044         fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2045         if (!fname) {
2046                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2047                            "Module ID %u for device %s has no name?"
2048                            "  The driver might have a configuration problem.",
2049                            mid,
2050                            hdw->hdw_desc->description);
2051                 return -EINVAL;
2052         }
2053         pvr2_trace(PVR2_TRACE_INIT,
2054                    "Module ID %u (%s) for device %s being loaded...",
2055                    mid, fname,
2056                    hdw->hdw_desc->description);
2057
2058         i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2059                                          ARRAY_SIZE(i2caddr));
2060         if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2061                          module_i2c_addresses[mid] : NULL) != NULL)) {
2062                 /* Second chance: Try default i2c address list */
2063                 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2064                                                  ARRAY_SIZE(i2caddr));
2065                 if (i2ccnt) {
2066                         pvr2_trace(PVR2_TRACE_INIT,
2067                                    "Module ID %u:"
2068                                    " Using default i2c address list",
2069                                    mid);
2070                 }
2071         }
2072
2073         if (!i2ccnt) {
2074                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2075                            "Module ID %u (%s) for device %s:"
2076                            " No i2c addresses."
2077                            "  The driver might have a configuration problem.",
2078                            mid, fname, hdw->hdw_desc->description);
2079                 return -EINVAL;
2080         }
2081
2082         /* Note how the 2nd and 3rd arguments are the same for
2083          * v4l2_i2c_new_subdev().  Why?
2084          * Well the 2nd argument is the module name to load, while the 3rd
2085          * argument is documented in the framework as being the "chipid" -
2086          * and every other place where I can find examples of this, the
2087          * "chipid" appears to just be the module name again.  So here we
2088          * just do the same thing. */
2089         if (i2ccnt == 1) {
2090                 pvr2_trace(PVR2_TRACE_INIT,
2091                            "Module ID %u:"
2092                            " Setting up with specified i2c address 0x%x",
2093                            mid, i2caddr[0]);
2094                 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2095                                          fname, fname,
2096                                          i2caddr[0], NULL);
2097         } else {
2098                 pvr2_trace(PVR2_TRACE_INIT,
2099                            "Module ID %u:"
2100                            " Setting up with address probe list",
2101                            mid);
2102                 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2103                                                 fname, fname,
2104                                                 0, i2caddr);
2105         }
2106
2107         if (!sd) {
2108                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2109                            "Module ID %u (%s) for device %s failed to load."
2110                            "  Possible missing sub-device kernel module or"
2111                            " initialization failure within module.",
2112                            mid, fname, hdw->hdw_desc->description);
2113                 return -EIO;
2114         }
2115
2116         /* Tag this sub-device instance with the module ID we know about.
2117            In other places we'll use that tag to determine if the instance
2118            requires special handling. */
2119         sd->grp_id = mid;
2120
2121         pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
2122
2123
2124         /* client-specific setup... */
2125         switch (mid) {
2126         case PVR2_CLIENT_ID_CX25840:
2127         case PVR2_CLIENT_ID_SAA7115:
2128                 hdw->decoder_client_id = mid;
2129                 break;
2130         default: break;
2131         }
2132
2133         return 0;
2134 }
2135
2136
2137 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2138 {
2139         unsigned int idx;
2140         const struct pvr2_string_table *cm;
2141         const struct pvr2_device_client_table *ct;
2142         int okFl = !0;
2143
2144         cm = &hdw->hdw_desc->client_modules;
2145         for (idx = 0; idx < cm->cnt; idx++) {
2146                 request_module(cm->lst[idx]);
2147         }
2148
2149         ct = &hdw->hdw_desc->client_table;
2150         for (idx = 0; idx < ct->cnt; idx++) {
2151                 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
2152         }
2153         if (!okFl) {
2154                 hdw->flag_modulefail = !0;
2155                 pvr2_hdw_render_useless(hdw);
2156         }
2157 }
2158
2159
2160 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2161 {
2162         int ret;
2163         unsigned int idx;
2164         struct pvr2_ctrl *cptr;
2165         int reloadFl = 0;
2166         if (hdw->hdw_desc->fx2_firmware.cnt) {
2167                 if (!reloadFl) {
2168                         reloadFl =
2169                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2170                                  == 0);
2171                         if (reloadFl) {
2172                                 pvr2_trace(PVR2_TRACE_INIT,
2173                                            "USB endpoint config looks strange"
2174                                            "; possibly firmware needs to be"
2175                                            " loaded");
2176                         }
2177                 }
2178                 if (!reloadFl) {
2179                         reloadFl = !pvr2_hdw_check_firmware(hdw);
2180                         if (reloadFl) {
2181                                 pvr2_trace(PVR2_TRACE_INIT,
2182                                            "Check for FX2 firmware failed"
2183                                            "; possibly firmware needs to be"
2184                                            " loaded");
2185                         }
2186                 }
2187                 if (reloadFl) {
2188                         if (pvr2_upload_firmware1(hdw) != 0) {
2189                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2190                                            "Failure uploading firmware1");
2191                         }
2192                         return;
2193                 }
2194         }
2195         hdw->fw1_state = FW1_STATE_OK;
2196
2197         if (!pvr2_hdw_dev_ok(hdw)) return;
2198
2199         hdw->force_dirty = !0;
2200
2201         if (!hdw->hdw_desc->flag_no_powerup) {
2202                 pvr2_hdw_cmd_powerup(hdw);
2203                 if (!pvr2_hdw_dev_ok(hdw)) return;
2204         }
2205
2206         /* Take the IR chip out of reset, if appropriate */
2207         if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
2208                 pvr2_issue_simple_cmd(hdw,
2209                                       FX2CMD_HCW_ZILOG_RESET |
2210                                       (1 << 8) |
2211                                       ((0) << 16));
2212         }
2213
2214         // This step MUST happen after the earlier powerup step.
2215         pvr2_i2c_core_init(hdw);
2216         if (!pvr2_hdw_dev_ok(hdw)) return;
2217
2218         pvr2_hdw_load_modules(hdw);
2219         if (!pvr2_hdw_dev_ok(hdw)) return;
2220
2221         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
2222
2223         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2224                 cptr = hdw->controls + idx;
2225                 if (cptr->info->skip_init) continue;
2226                 if (!cptr->info->set_value) continue;
2227                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2228         }
2229
2230         pvr2_hdw_cx25840_vbi_hack(hdw);
2231
2232         /* Set up special default values for the television and radio
2233            frequencies here.  It's not really important what these defaults
2234            are, but I set them to something usable in the Chicago area just
2235            to make driver testing a little easier. */
2236
2237         hdw->freqValTelevision = default_tv_freq;
2238         hdw->freqValRadio = default_radio_freq;
2239
2240         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2241         // thread-safe against the normal pvr2_send_request() mechanism.
2242         // (We should make it thread safe).
2243
2244         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2245                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2246                 if (!pvr2_hdw_dev_ok(hdw)) return;
2247                 if (ret < 0) {
2248                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2249                                    "Unable to determine location of eeprom,"
2250                                    " skipping");
2251                 } else {
2252                         hdw->eeprom_addr = ret;
2253                         pvr2_eeprom_analyze(hdw);
2254                         if (!pvr2_hdw_dev_ok(hdw)) return;
2255                 }
2256         } else {
2257                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2258                 hdw->tuner_updated = !0;
2259                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2260         }
2261
2262         if (hdw->serial_number) {
2263                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2264                                 "sn-%lu", hdw->serial_number);
2265         } else if (hdw->unit_number >= 0) {
2266                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2267                                 "unit-%c",
2268                                 hdw->unit_number + 'a');
2269         } else {
2270                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2271                                 "unit-??");
2272         }
2273         hdw->identifier[idx] = 0;
2274
2275         pvr2_hdw_setup_std(hdw);
2276
2277         if (!get_default_tuner_type(hdw)) {
2278                 pvr2_trace(PVR2_TRACE_INIT,
2279                            "pvr2_hdw_setup: Tuner type overridden to %d",
2280                            hdw->tuner_type);
2281         }
2282
2283
2284         if (!pvr2_hdw_dev_ok(hdw)) return;
2285
2286         if (hdw->hdw_desc->signal_routing_scheme ==
2287             PVR2_ROUTING_SCHEME_GOTVIEW) {
2288                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2289                    hardware. */
2290                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2291         }
2292
2293         pvr2_hdw_commit_setup(hdw);
2294
2295         hdw->vid_stream = pvr2_stream_create();
2296         if (!pvr2_hdw_dev_ok(hdw)) return;
2297         pvr2_trace(PVR2_TRACE_INIT,
2298                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2299         if (hdw->vid_stream) {
2300                 idx = get_default_error_tolerance(hdw);
2301                 if (idx) {
2302                         pvr2_trace(PVR2_TRACE_INIT,
2303                                    "pvr2_hdw_setup: video stream %p"
2304                                    " setting tolerance %u",
2305                                    hdw->vid_stream,idx);
2306                 }
2307                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2308                                   PVR2_VID_ENDPOINT,idx);
2309         }
2310
2311         if (!pvr2_hdw_dev_ok(hdw)) return;
2312
2313         hdw->flag_init_ok = !0;
2314
2315         pvr2_hdw_state_sched(hdw);
2316 }
2317
2318
2319 /* Set up the structure and attempt to put the device into a usable state.
2320    This can be a time-consuming operation, which is why it is not done
2321    internally as part of the create() step. */
2322 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2323 {
2324         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2325         do {
2326                 pvr2_hdw_setup_low(hdw);
2327                 pvr2_trace(PVR2_TRACE_INIT,
2328                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2329                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2330                 if (pvr2_hdw_dev_ok(hdw)) {
2331                         if (hdw->flag_init_ok) {
2332                                 pvr2_trace(
2333                                         PVR2_TRACE_INFO,
2334                                         "Device initialization"
2335                                         " completed successfully.");
2336                                 break;
2337                         }
2338                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2339                                 pvr2_trace(
2340                                         PVR2_TRACE_INFO,
2341                                         "Device microcontroller firmware"
2342                                         " (re)loaded; it should now reset"
2343                                         " and reconnect.");
2344                                 break;
2345                         }
2346                         pvr2_trace(
2347                                 PVR2_TRACE_ERROR_LEGS,
2348                                 "Device initialization was not successful.");
2349                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2350                                 pvr2_trace(
2351                                         PVR2_TRACE_ERROR_LEGS,
2352                                         "Giving up since device"
2353                                         " microcontroller firmware"
2354                                         " appears to be missing.");
2355                                 break;
2356                         }
2357                 }
2358                 if (hdw->flag_modulefail) {
2359                         pvr2_trace(
2360                                 PVR2_TRACE_ERROR_LEGS,
2361                                 "***WARNING*** pvrusb2 driver initialization"
2362                                 " failed due to the failure of one or more"
2363                                 " sub-device kernel modules.");
2364                         pvr2_trace(
2365                                 PVR2_TRACE_ERROR_LEGS,
2366                                 "You need to resolve the failing condition"
2367                                 " before this driver can function.  There"
2368                                 " should be some earlier messages giving more"
2369                                 " information about the problem.");
2370                         break;
2371                 }
2372                 if (procreload) {
2373                         pvr2_trace(
2374                                 PVR2_TRACE_ERROR_LEGS,
2375                                 "Attempting pvrusb2 recovery by reloading"
2376                                 " primary firmware.");
2377                         pvr2_trace(
2378                                 PVR2_TRACE_ERROR_LEGS,
2379                                 "If this works, device should disconnect"
2380                                 " and reconnect in a sane state.");
2381                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2382                         pvr2_upload_firmware1(hdw);
2383                 } else {
2384                         pvr2_trace(
2385                                 PVR2_TRACE_ERROR_LEGS,
2386                                 "***WARNING*** pvrusb2 device hardware"
2387                                 " appears to be jammed"
2388                                 " and I can't clear it.");
2389                         pvr2_trace(
2390                                 PVR2_TRACE_ERROR_LEGS,
2391                                 "You might need to power cycle"
2392                                 " the pvrusb2 device"
2393                                 " in order to recover.");
2394                 }
2395         } while (0);
2396         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2397 }
2398
2399
2400 /* Perform second stage initialization.  Set callback pointer first so that
2401    we can avoid a possible initialization race (if the kernel thread runs
2402    before the callback has been set). */
2403 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2404                         void (*callback_func)(void *),
2405                         void *callback_data)
2406 {
2407         LOCK_TAKE(hdw->big_lock); do {
2408                 if (hdw->flag_disconnected) {
2409                         /* Handle a race here: If we're already
2410                            disconnected by this point, then give up.  If we
2411                            get past this then we'll remain connected for
2412                            the duration of initialization since the entire
2413                            initialization sequence is now protected by the
2414                            big_lock. */
2415                         break;
2416                 }
2417                 hdw->state_data = callback_data;
2418                 hdw->state_func = callback_func;
2419                 pvr2_hdw_setup(hdw);
2420         } while (0); LOCK_GIVE(hdw->big_lock);
2421         return hdw->flag_init_ok;
2422 }
2423
2424
2425 /* Create, set up, and return a structure for interacting with the
2426    underlying hardware.  */
2427 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2428                                  const struct usb_device_id *devid)
2429 {
2430         unsigned int idx,cnt1,cnt2,m;
2431         struct pvr2_hdw *hdw = NULL;
2432         int valid_std_mask;
2433         struct pvr2_ctrl *cptr;
2434         struct usb_device *usb_dev;
2435         const struct pvr2_device_desc *hdw_desc;
2436         __u8 ifnum;
2437         struct v4l2_queryctrl qctrl;
2438         struct pvr2_ctl_info *ciptr;
2439
2440         usb_dev = interface_to_usbdev(intf);
2441
2442         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2443
2444         if (hdw_desc == NULL) {
2445                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2446                            " No device description pointer,"
2447                            " unable to continue.");
2448                 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2449                            " please contact Mike Isely <isely@pobox.com>"
2450                            " to get it included in the driver\n");
2451                 goto fail;
2452         }
2453
2454         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2455         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2456                    hdw,hdw_desc->description);
2457         pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
2458                 hdw_desc->description);
2459         if (!hdw) goto fail;
2460
2461         init_timer(&hdw->quiescent_timer);
2462         hdw->quiescent_timer.data = (unsigned long)hdw;
2463         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2464
2465         init_timer(&hdw->encoder_wait_timer);
2466         hdw->encoder_wait_timer.data = (unsigned long)hdw;
2467         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2468
2469         init_timer(&hdw->encoder_run_timer);
2470         hdw->encoder_run_timer.data = (unsigned long)hdw;
2471         hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2472
2473         hdw->master_state = PVR2_STATE_DEAD;
2474
2475         init_waitqueue_head(&hdw->state_wait_data);
2476
2477         hdw->tuner_signal_stale = !0;
2478         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2479
2480         /* Calculate which inputs are OK */
2481         m = 0;
2482         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2483         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2484                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2485         }
2486         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2487         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2488         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2489         hdw->input_avail_mask = m;
2490         hdw->input_allowed_mask = hdw->input_avail_mask;
2491
2492         /* If not a hybrid device, pathway_state never changes.  So
2493            initialize it here to what it should forever be. */
2494         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2495                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2496         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2497                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2498         }
2499
2500         hdw->control_cnt = CTRLDEF_COUNT;
2501         hdw->control_cnt += MPEGDEF_COUNT;
2502         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2503                                 GFP_KERNEL);
2504         if (!hdw->controls) goto fail;
2505         hdw->hdw_desc = hdw_desc;
2506         hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
2507         for (idx = 0; idx < hdw->control_cnt; idx++) {
2508                 cptr = hdw->controls + idx;
2509                 cptr->hdw = hdw;
2510         }
2511         for (idx = 0; idx < 32; idx++) {
2512                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2513         }
2514         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2515                 cptr = hdw->controls + idx;
2516                 cptr->info = control_defs+idx;
2517         }
2518
2519         /* Ensure that default input choice is a valid one. */
2520         m = hdw->input_avail_mask;
2521         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2522                 if (!((1 << idx) & m)) continue;
2523                 hdw->input_val = idx;
2524                 break;
2525         }
2526
2527         /* Define and configure additional controls from cx2341x module. */
2528         hdw->mpeg_ctrl_info = kzalloc(
2529                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2530         if (!hdw->mpeg_ctrl_info) goto fail;
2531         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2532                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2533                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2534                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2535                 ciptr->name = mpeg_ids[idx].strid;
2536                 ciptr->v4l_id = mpeg_ids[idx].id;
2537                 ciptr->skip_init = !0;
2538                 ciptr->get_value = ctrl_cx2341x_get;
2539                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2540                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2541                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2542                 qctrl.id = ciptr->v4l_id;
2543                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2544                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2545                         ciptr->set_value = ctrl_cx2341x_set;
2546                 }
2547                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2548                         PVR2_CTLD_INFO_DESC_SIZE);
2549                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2550                 ciptr->default_value = qctrl.default_value;
2551                 switch (qctrl.type) {
2552                 default:
2553                 case V4L2_CTRL_TYPE_INTEGER:
2554                         ciptr->type = pvr2_ctl_int;
2555                         ciptr->def.type_int.min_value = qctrl.minimum;
2556                         ciptr->def.type_int.max_value = qctrl.maximum;
2557                         break;
2558                 case V4L2_CTRL_TYPE_BOOLEAN:
2559                         ciptr->type = pvr2_ctl_bool;
2560                         break;
2561                 case V4L2_CTRL_TYPE_MENU:
2562                         ciptr->type = pvr2_ctl_enum;
2563                         ciptr->def.type_enum.value_names =
2564                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2565                                                                 ciptr->v4l_id);
2566                         for (cnt1 = 0;
2567                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2568                              cnt1++) { }
2569                         ciptr->def.type_enum.count = cnt1;
2570                         break;
2571                 }
2572                 cptr->info = ciptr;
2573         }
2574
2575         // Initialize video standard enum dynamic control
2576         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2577         if (cptr) {
2578                 memcpy(&hdw->std_info_enum,cptr->info,
2579                        sizeof(hdw->std_info_enum));
2580                 cptr->info = &hdw->std_info_enum;
2581
2582         }
2583         // Initialize control data regarding video standard masks
2584         valid_std_mask = pvr2_std_get_usable();
2585         for (idx = 0; idx < 32; idx++) {
2586                 if (!(valid_std_mask & (1 << idx))) continue;
2587                 cnt1 = pvr2_std_id_to_str(
2588                         hdw->std_mask_names[idx],
2589                         sizeof(hdw->std_mask_names[idx])-1,
2590                         1 << idx);
2591                 hdw->std_mask_names[idx][cnt1] = 0;
2592         }
2593         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2594         if (cptr) {
2595                 memcpy(&hdw->std_info_avail,cptr->info,
2596                        sizeof(hdw->std_info_avail));
2597                 cptr->info = &hdw->std_info_avail;
2598                 hdw->std_info_avail.def.type_bitmask.bit_names =
2599                         hdw->std_mask_ptrs;
2600                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2601                         valid_std_mask;
2602         }
2603         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2604         if (cptr) {
2605                 memcpy(&hdw->std_info_cur,cptr->info,
2606                        sizeof(hdw->std_info_cur));
2607                 cptr->info = &hdw->std_info_cur;
2608                 hdw->std_info_cur.def.type_bitmask.bit_names =
2609                         hdw->std_mask_ptrs;
2610                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2611                         valid_std_mask;
2612         }
2613
2614         hdw->cropcap_stale = !0;
2615         hdw->eeprom_addr = -1;
2616         hdw->unit_number = -1;
2617         hdw->v4l_minor_number_video = -1;
2618         hdw->v4l_minor_number_vbi = -1;
2619         hdw->v4l_minor_number_radio = -1;
2620         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2621         if (!hdw->ctl_write_buffer) goto fail;
2622         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2623         if (!hdw->ctl_read_buffer) goto fail;
2624         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2625         if (!hdw->ctl_write_urb) goto fail;
2626         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2627         if (!hdw->ctl_read_urb) goto fail;
2628
2629         if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
2630                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2631                            "Error registering with v4l core, giving up");
2632                 goto fail;
2633         }
2634         mutex_lock(&pvr2_unit_mtx); do {
2635                 for (idx = 0; idx < PVR_NUM; idx++) {
2636                         if (unit_pointers[idx]) continue;
2637                         hdw->unit_number = idx;
2638                         unit_pointers[idx] = hdw;
2639                         break;
2640                 }
2641         } while (0); mutex_unlock(&pvr2_unit_mtx);
2642
2643         cnt1 = 0;
2644         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2645         cnt1 += cnt2;
2646         if (hdw->unit_number >= 0) {
2647                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2648                                  ('a' + hdw->unit_number));
2649                 cnt1 += cnt2;
2650         }
2651         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2652         hdw->name[cnt1] = 0;
2653
2654         hdw->workqueue = create_singlethread_workqueue(hdw->name);
2655         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2656
2657         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2658                    hdw->unit_number,hdw->name);
2659
2660         hdw->tuner_type = -1;
2661         hdw->flag_ok = !0;
2662
2663         hdw->usb_intf = intf;
2664         hdw->usb_dev = usb_dev;
2665
2666         usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2667
2668         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2669         usb_set_interface(hdw->usb_dev,ifnum,0);
2670
2671         mutex_init(&hdw->ctl_lock_mutex);
2672         mutex_init(&hdw->big_lock_mutex);
2673
2674         return hdw;
2675  fail:
2676         if (hdw) {
2677                 del_timer_sync(&hdw->quiescent_timer);
2678                 del_timer_sync(&hdw->encoder_run_timer);
2679                 del_timer_sync(&hdw->encoder_wait_timer);
2680                 if (hdw->workqueue) {
2681                         flush_workqueue(hdw->workqueue);
2682                         destroy_workqueue(hdw->workqueue);
2683                         hdw->workqueue = NULL;
2684                 }
2685                 usb_free_urb(hdw->ctl_read_urb);
2686                 usb_free_urb(hdw->ctl_write_urb);
2687                 kfree(hdw->ctl_read_buffer);
2688                 kfree(hdw->ctl_write_buffer);
2689                 kfree(hdw->controls);
2690                 kfree(hdw->mpeg_ctrl_info);
2691                 kfree(hdw->std_defs);
2692                 kfree(hdw->std_enum_names);
2693                 kfree(hdw);
2694         }
2695         return NULL;
2696 }
2697
2698
2699 /* Remove _all_ associations between this driver and the underlying USB
2700    layer. */
2701 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2702 {
2703         if (hdw->flag_disconnected) return;
2704         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2705         if (hdw->ctl_read_urb) {
2706                 usb_kill_urb(hdw->ctl_read_urb);
2707                 usb_free_urb(hdw->ctl_read_urb);
2708                 hdw->ctl_read_urb = NULL;
2709         }
2710         if (hdw->ctl_write_urb) {
2711                 usb_kill_urb(hdw->ctl_write_urb);
2712                 usb_free_urb(hdw->ctl_write_urb);
2713                 hdw->ctl_write_urb = NULL;
2714         }
2715         if (hdw->ctl_read_buffer) {
2716                 kfree(hdw->ctl_read_buffer);
2717                 hdw->ctl_read_buffer = NULL;
2718         }
2719         if (hdw->ctl_write_buffer) {
2720                 kfree(hdw->ctl_write_buffer);
2721                 hdw->ctl_write_buffer = NULL;
2722         }
2723         hdw->flag_disconnected = !0;
2724         /* If we don't do this, then there will be a dangling struct device
2725            reference to our disappearing device persisting inside the V4L
2726            core... */
2727         v4l2_device_disconnect(&hdw->v4l2_dev);
2728         hdw->usb_dev = NULL;
2729         hdw->usb_intf = NULL;
2730         pvr2_hdw_render_useless(hdw);
2731 }
2732
2733
2734 /* Destroy hardware interaction structure */
2735 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2736 {
2737         if (!hdw) return;
2738         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2739         if (hdw->workqueue) {
2740                 flush_workqueue(hdw->workqueue);
2741                 destroy_workqueue(hdw->workqueue);
2742                 hdw->workqueue = NULL;
2743         }
2744         del_timer_sync(&hdw->quiescent_timer);
2745         del_timer_sync(&hdw->encoder_run_timer);
2746         del_timer_sync(&hdw->encoder_wait_timer);
2747         if (hdw->fw_buffer) {
2748                 kfree(hdw->fw_buffer);
2749                 hdw->fw_buffer = NULL;
2750         }
2751         if (hdw->vid_stream) {
2752                 pvr2_stream_destroy(hdw->vid_stream);
2753                 hdw->vid_stream = NULL;
2754         }
2755         pvr2_i2c_core_done(hdw);
2756         v4l2_device_unregister(&hdw->v4l2_dev);
2757         pvr2_hdw_remove_usb_stuff(hdw);
2758         mutex_lock(&pvr2_unit_mtx); do {
2759                 if ((hdw->unit_number >= 0) &&
2760                     (hdw->unit_number < PVR_NUM) &&
2761                     (unit_pointers[hdw->unit_number] == hdw)) {
2762                         unit_pointers[hdw->unit_number] = NULL;
2763                 }
2764         } while (0); mutex_unlock(&pvr2_unit_mtx);
2765         kfree(hdw->controls);
2766         kfree(hdw->mpeg_ctrl_info);
2767         kfree(hdw->std_defs);
2768         kfree(hdw->std_enum_names);
2769         kfree(hdw);
2770 }
2771
2772
2773 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2774 {
2775         return (hdw && hdw->flag_ok);
2776 }
2777
2778
2779 /* Called when hardware has been unplugged */
2780 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2781 {
2782         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2783         LOCK_TAKE(hdw->big_lock);
2784         LOCK_TAKE(hdw->ctl_lock);
2785         pvr2_hdw_remove_usb_stuff(hdw);
2786         LOCK_GIVE(hdw->ctl_lock);
2787         LOCK_GIVE(hdw->big_lock);
2788 }
2789
2790
2791 // Attempt to autoselect an appropriate value for std_enum_cur given
2792 // whatever is currently in std_mask_cur
2793 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2794 {
2795         unsigned int idx;
2796         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2797                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2798                         hdw->std_enum_cur = idx;
2799                         return;
2800                 }
2801         }
2802         hdw->std_enum_cur = 0;
2803 }
2804
2805
2806 // Calculate correct set of enumerated standards based on currently known
2807 // set of available standards bits.
2808 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2809 {
2810         struct v4l2_standard *newstd;
2811         unsigned int std_cnt;
2812         unsigned int idx;
2813
2814         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2815
2816         if (hdw->std_defs) {
2817                 kfree(hdw->std_defs);
2818                 hdw->std_defs = NULL;
2819         }
2820         hdw->std_enum_cnt = 0;
2821         if (hdw->std_enum_names) {
2822                 kfree(hdw->std_enum_names);
2823                 hdw->std_enum_names = NULL;
2824         }
2825
2826         if (!std_cnt) {
2827                 pvr2_trace(
2828                         PVR2_TRACE_ERROR_LEGS,
2829                         "WARNING: Failed to identify any viable standards");
2830         }
2831         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2832         hdw->std_enum_names[0] = "none";
2833         for (idx = 0; idx < std_cnt; idx++) {
2834                 hdw->std_enum_names[idx+1] =
2835                         newstd[idx].name;
2836         }
2837         // Set up the dynamic control for this standard
2838         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2839         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2840         hdw->std_defs = newstd;
2841         hdw->std_enum_cnt = std_cnt+1;
2842         hdw->std_enum_cur = 0;
2843         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2844 }
2845
2846
2847 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2848                                struct v4l2_standard *std,
2849                                unsigned int idx)
2850 {
2851         int ret = -EINVAL;
2852         if (!idx) return ret;
2853         LOCK_TAKE(hdw->big_lock); do {
2854                 if (idx >= hdw->std_enum_cnt) break;
2855                 idx--;
2856                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2857                 ret = 0;
2858         } while (0); LOCK_GIVE(hdw->big_lock);
2859         return ret;
2860 }
2861
2862
2863 /* Get the number of defined controls */
2864 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2865 {
2866         return hdw->control_cnt;
2867 }
2868
2869
2870 /* Retrieve a control handle given its index (0..count-1) */
2871 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2872                                              unsigned int idx)
2873 {
2874         if (idx >= hdw->control_cnt) return NULL;
2875         return hdw->controls + idx;
2876 }
2877
2878
2879 /* Retrieve a control handle given its index (0..count-1) */
2880 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2881                                           unsigned int ctl_id)
2882 {
2883         struct pvr2_ctrl *cptr;
2884         unsigned int idx;
2885         int i;
2886
2887         /* This could be made a lot more efficient, but for now... */
2888         for (idx = 0; idx < hdw->control_cnt; idx++) {
2889                 cptr = hdw->controls + idx;
2890                 i = cptr->info->internal_id;
2891                 if (i && (i == ctl_id)) return cptr;
2892         }
2893         return NULL;
2894 }
2895
2896
2897 /* Given a V4L ID, retrieve the control structure associated with it. */
2898 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2899 {
2900         struct pvr2_ctrl *cptr;
2901         unsigned int idx;
2902         int i;
2903
2904         /* This could be made a lot more efficient, but for now... */
2905         for (idx = 0; idx < hdw->control_cnt; idx++) {
2906                 cptr = hdw->controls + idx;
2907                 i = cptr->info->v4l_id;
2908                 if (i && (i == ctl_id)) return cptr;
2909         }
2910         return NULL;
2911 }
2912
2913
2914 /* Given a V4L ID for its immediate predecessor, retrieve the control
2915    structure associated with it. */
2916 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2917                                             unsigned int ctl_id)
2918 {
2919         struct pvr2_ctrl *cptr,*cp2;
2920         unsigned int idx;
2921         int i;
2922
2923         /* This could be made a lot more efficient, but for now... */
2924         cp2 = NULL;
2925         for (idx = 0; idx < hdw->control_cnt; idx++) {
2926                 cptr = hdw->controls + idx;
2927                 i = cptr->info->v4l_id;
2928                 if (!i) continue;
2929                 if (i <= ctl_id) continue;
2930                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2931                 cp2 = cptr;
2932         }
2933         return cp2;
2934         return NULL;
2935 }
2936
2937
2938 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2939 {
2940         switch (tp) {
2941         case pvr2_ctl_int: return "integer";
2942         case pvr2_ctl_enum: return "enum";
2943         case pvr2_ctl_bool: return "boolean";
2944         case pvr2_ctl_bitmask: return "bitmask";
2945         }
2946         return "";
2947 }
2948
2949
2950 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2951                                     const char *name, int val)
2952 {
2953         struct v4l2_control ctrl;
2954         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2955         memset(&ctrl, 0, sizeof(ctrl));
2956         ctrl.id = id;
2957         ctrl.value = val;
2958         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2959 }
2960
2961 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2962         if ((hdw)->lab##_dirty || (hdw)->force_dirty) {         \
2963                 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2964         }
2965
2966 /* Execute whatever commands are required to update the state of all the
2967    sub-devices so that they match our current control values. */
2968 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2969 {
2970         struct v4l2_subdev *sd;
2971         unsigned int id;
2972         pvr2_subdev_update_func fp;
2973
2974         pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2975
2976         if (hdw->tuner_updated || hdw->force_dirty) {
2977                 struct tuner_setup setup;
2978                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2979                            hdw->tuner_type);
2980                 if (((int)(hdw->tuner_type)) >= 0) {
2981                         memset(&setup, 0, sizeof(setup));
2982                         setup.addr = ADDR_UNSET;
2983                         setup.type = hdw->tuner_type;
2984                         setup.mode_mask = T_RADIO | T_ANALOG_TV;
2985                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2986                                              tuner, s_type_addr, &setup);
2987                 }
2988         }
2989
2990         if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
2991                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2992                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2993                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2994                                              tuner, s_radio);
2995                 } else {
2996                         v4l2_std_id vs;
2997                         vs = hdw->std_mask_cur;
2998                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2999                                              core, s_std, vs);
3000                         pvr2_hdw_cx25840_vbi_hack(hdw);
3001                 }
3002                 hdw->tuner_signal_stale = !0;
3003                 hdw->cropcap_stale = !0;
3004         }
3005
3006         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
3007         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
3008         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
3009         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
3010         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
3011         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
3012         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
3013         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
3014         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
3015
3016         if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
3017                 struct v4l2_tuner vt;
3018                 memset(&vt, 0, sizeof(vt));
3019                 vt.audmode = hdw->audiomode_val;
3020                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
3021         }
3022
3023         if (hdw->freqDirty || hdw->force_dirty) {
3024                 unsigned long fv;
3025                 struct v4l2_frequency freq;
3026                 fv = pvr2_hdw_get_cur_freq(hdw);
3027                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
3028                 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
3029                 memset(&freq, 0, sizeof(freq));
3030                 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
3031                         /* ((fv * 1000) / 62500) */
3032                         freq.frequency = (fv * 2) / 125;
3033                 } else {
3034                         freq.frequency = fv / 62500;
3035                 }
3036                 /* tuner-core currently doesn't seem to care about this, but
3037                    let's set it anyway for completeness. */
3038                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3039                         freq.type = V4L2_TUNER_RADIO;
3040                 } else {
3041                         freq.type = V4L2_TUNER_ANALOG_TV;
3042                 }
3043                 freq.tuner = 0;
3044                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
3045                                      s_frequency, &freq);
3046         }
3047
3048         if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
3049                 struct v4l2_format fmt;
3050                 memset(&fmt, 0, sizeof(fmt));
3051                 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
3052                 fmt.fmt.pix.width = hdw->res_hor_val;
3053                 fmt.fmt.pix.height = hdw->res_ver_val;
3054                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
3055                            fmt.fmt.pix.width, fmt.fmt.pix.height);
3056                 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
3057         }
3058
3059         if (hdw->srate_dirty || hdw->force_dirty) {
3060                 u32 val;
3061                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3062                            hdw->srate_val);
3063                 switch (hdw->srate_val) {
3064                 default:
3065                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3066                         val = 48000;
3067                         break;
3068                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3069                         val = 44100;
3070                         break;
3071                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3072                         val = 32000;
3073                         break;
3074                 }
3075                 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3076                                      audio, s_clock_freq, val);
3077         }
3078
3079         /* Unable to set crop parameters; there is apparently no equivalent
3080            for VIDIOC_S_CROP */
3081
3082         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3083                 id = sd->grp_id;
3084                 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3085                 fp = pvr2_module_update_functions[id];
3086                 if (!fp) continue;
3087                 (*fp)(hdw, sd);
3088         }
3089
3090         if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
3091                 pvr2_hdw_status_poll(hdw);
3092         }
3093 }
3094
3095
3096 /* Figure out if we need to commit control changes.  If so, mark internal
3097    state flags to indicate this fact and return true.  Otherwise do nothing
3098    else and return false. */
3099 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
3100 {
3101         unsigned int idx;
3102         struct pvr2_ctrl *cptr;
3103         int value;
3104         int commit_flag = hdw->force_dirty;
3105         char buf[100];
3106         unsigned int bcnt,ccnt;
3107
3108         for (idx = 0; idx < hdw->control_cnt; idx++) {
3109                 cptr = hdw->controls + idx;
3110                 if (!cptr->info->is_dirty) continue;
3111                 if (!cptr->info->is_dirty(cptr)) continue;
3112                 commit_flag = !0;
3113
3114                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
3115                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3116                                  cptr->info->name);
3117                 value = 0;
3118                 cptr->info->get_value(cptr,&value);
3119                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3120                                                 buf+bcnt,
3121                                                 sizeof(buf)-bcnt,&ccnt);
3122                 bcnt += ccnt;
3123                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3124                                   get_ctrl_typename(cptr->info->type));
3125                 pvr2_trace(PVR2_TRACE_CTL,
3126                            "/*--TRACE_COMMIT--*/ %.*s",
3127                            bcnt,buf);
3128         }
3129
3130         if (!commit_flag) {
3131                 /* Nothing has changed */
3132                 return 0;
3133         }
3134
3135         hdw->state_pipeline_config = 0;
3136         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3137         pvr2_hdw_state_sched(hdw);
3138
3139         return !0;
3140 }
3141
3142
3143 /* Perform all operations needed to commit all control changes.  This must
3144    be performed in synchronization with the pipeline state and is thus
3145    expected to be called as part of the driver's worker thread.  Return
3146    true if commit successful, otherwise return false to indicate that
3147    commit isn't possible at this time. */
3148 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3149 {
3150         unsigned int idx;
3151         struct pvr2_ctrl *cptr;
3152         int disruptive_change;
3153
3154         /* Handle some required side effects when the video standard is
3155            changed.... */
3156         if (hdw->std_dirty) {
3157                 int nvres;
3158                 int gop_size;
3159                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3160                         nvres = 480;
3161                         gop_size = 15;
3162                 } else {
3163                         nvres = 576;
3164                         gop_size = 12;
3165                 }
3166                 /* Rewrite the vertical resolution to be appropriate to the
3167                    video standard that has been selected. */
3168                 if (nvres != hdw->res_ver_val) {
3169                         hdw->res_ver_val = nvres;
3170                         hdw->res_ver_dirty = !0;
3171                 }
3172                 /* Rewrite the GOP size to be appropriate to the video
3173                    standard that has been selected. */
3174                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3175                         struct v4l2_ext_controls cs;
3176                         struct v4l2_ext_control c1;
3177                         memset(&cs, 0, sizeof(cs));
3178                         memset(&c1, 0, sizeof(c1));
3179                         cs.controls = &c1;
3180                         cs.count = 1;
3181                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3182                         c1.value = gop_size;
3183                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3184                                           VIDIOC_S_EXT_CTRLS);
3185                 }
3186         }
3187
3188         if (hdw->input_dirty && hdw->state_pathway_ok &&
3189             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3190               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3191              hdw->pathway_state)) {
3192                 /* Change of mode being asked for... */
3193                 hdw->state_pathway_ok = 0;
3194                 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3195         }
3196         if (!hdw->state_pathway_ok) {
3197                 /* Can't commit anything until pathway is ok. */
3198                 return 0;
3199         }
3200         /* The broadcast decoder can only scale down, so if
3201          * res_*_dirty && crop window < output format ==> enlarge crop.
3202          *
3203          * The mpeg encoder receives fields of res_hor_val dots and
3204          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3205          */
3206         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3207                 hdw->cropw_val = hdw->res_hor_val;
3208                 hdw->cropw_dirty = !0;
3209         } else if (hdw->cropw_dirty) {
3210                 hdw->res_hor_dirty = !0;           /* must rescale */
3211                 hdw->res_hor_val = min(720, hdw->cropw_val);
3212         }
3213         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3214                 hdw->croph_val = hdw->res_ver_val;
3215                 hdw->croph_dirty = !0;
3216         } else if (hdw->croph_dirty) {
3217                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3218                 hdw->res_ver_dirty = !0;
3219                 hdw->res_ver_val = min(nvres, hdw->croph_val);
3220         }
3221
3222         /* If any of the below has changed, then we can't do the update
3223            while the pipeline is running.  Pipeline must be paused first
3224            and decoder -> encoder connection be made quiescent before we
3225            can proceed. */
3226         disruptive_change =
3227                 (hdw->std_dirty ||
3228                  hdw->enc_unsafe_stale ||
3229                  hdw->srate_dirty ||
3230                  hdw->res_ver_dirty ||
3231                  hdw->res_hor_dirty ||
3232                  hdw->cropw_dirty ||
3233                  hdw->croph_dirty ||
3234                  hdw->input_dirty ||
3235                  (hdw->active_stream_type != hdw->desired_stream_type));
3236         if (disruptive_change && !hdw->state_pipeline_idle) {
3237                 /* Pipeline is not idle; we can't proceed.  Arrange to
3238                    cause pipeline to stop so that we can try this again
3239                    later.... */
3240                 hdw->state_pipeline_pause = !0;
3241                 return 0;
3242         }
3243
3244         if (hdw->srate_dirty) {
3245                 /* Write new sample rate into control structure since
3246                  * the master copy is stale.  We must track srate
3247                  * separate from the mpeg control structure because
3248                  * other logic also uses this value. */
3249                 struct v4l2_ext_controls cs;
3250                 struct v4l2_ext_control c1;
3251                 memset(&cs,0,sizeof(cs));
3252                 memset(&c1,0,sizeof(c1));
3253                 cs.controls = &c1;
3254                 cs.count = 1;
3255                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3256                 c1.value = hdw->srate_val;
3257                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3258         }
3259
3260         if (hdw->active_stream_type != hdw->desired_stream_type) {
3261                 /* Handle any side effects of stream config here */
3262                 hdw->active_stream_type = hdw->desired_stream_type;
3263         }
3264
3265         if (hdw->hdw_desc->signal_routing_scheme ==
3266             PVR2_ROUTING_SCHEME_GOTVIEW) {
3267                 u32 b;
3268                 /* Handle GOTVIEW audio switching */
3269                 pvr2_hdw_gpio_get_out(hdw,&b);
3270                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3271                         /* Set GPIO 11 */
3272                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3273                 } else {
3274                         /* Clear GPIO 11 */
3275                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3276                 }
3277         }
3278
3279         /* Check and update state for all sub-devices. */
3280         pvr2_subdev_update(hdw);
3281
3282         hdw->tuner_updated = 0;
3283         hdw->force_dirty = 0;
3284         for (idx = 0; idx < hdw->control_cnt; idx++) {
3285                 cptr = hdw->controls + idx;
3286                 if (!cptr->info->clear_dirty) continue;
3287                 cptr->info->clear_dirty(cptr);
3288         }
3289
3290         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3291             hdw->state_encoder_run) {
3292                 /* If encoder isn't running or it can't be touched, then
3293                    this will get worked out later when we start the
3294                    encoder. */
3295                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3296         }
3297
3298         hdw->state_pipeline_config = !0;
3299         /* Hardware state may have changed in a way to cause the cropping
3300            capabilities to have changed.  So mark it stale, which will
3301            cause a later re-fetch. */
3302         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3303         return !0;
3304 }
3305
3306
3307 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3308 {
3309         int fl;
3310         LOCK_TAKE(hdw->big_lock);
3311         fl = pvr2_hdw_commit_setup(hdw);
3312         LOCK_GIVE(hdw->big_lock);
3313         if (!fl) return 0;
3314         return pvr2_hdw_wait(hdw,0);
3315 }
3316
3317
3318 static void pvr2_hdw_worker_poll(struct work_struct *work)
3319 {
3320         int fl = 0;
3321         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3322         LOCK_TAKE(hdw->big_lock); do {
3323                 fl = pvr2_hdw_state_eval(hdw);
3324         } while (0); LOCK_GIVE(hdw->big_lock);
3325         if (fl && hdw->state_func) {
3326                 hdw->state_func(hdw->state_data);
3327         }
3328 }
3329
3330
3331 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3332 {
3333         return wait_event_interruptible(
3334                 hdw->state_wait_data,
3335                 (hdw->state_stale == 0) &&
3336                 (!state || (hdw->master_state != state)));
3337 }
3338
3339
3340 /* Return name for this driver instance */
3341 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3342 {
3343         return hdw->name;
3344 }
3345
3346
3347 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3348 {
3349         return hdw->hdw_desc->description;
3350 }
3351
3352
3353 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3354 {
3355         return hdw->hdw_desc->shortname;
3356 }
3357
3358
3359 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3360 {
3361         int result;
3362         LOCK_TAKE(hdw->ctl_lock); do {
3363                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3364                 result = pvr2_send_request(hdw,
3365                                            hdw->cmd_buffer,1,
3366                                            hdw->cmd_buffer,1);
3367                 if (result < 0) break;
3368                 result = (hdw->cmd_buffer[0] != 0);
3369         } while(0); LOCK_GIVE(hdw->ctl_lock);
3370         return result;
3371 }
3372
3373
3374 /* Execute poll of tuner status */
3375 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3376 {
3377         LOCK_TAKE(hdw->big_lock); do {
3378                 pvr2_hdw_status_poll(hdw);
3379         } while (0); LOCK_GIVE(hdw->big_lock);
3380 }
3381
3382
3383 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3384 {
3385         if (!hdw->cropcap_stale) {
3386                 return 0;
3387         }
3388         pvr2_hdw_status_poll(hdw);
3389         if (hdw->cropcap_stale) {
3390                 return -EIO;
3391         }
3392         return 0;
3393 }
3394
3395
3396 /* Return information about cropping capabilities */
3397 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3398 {
3399         int stat = 0;
3400         LOCK_TAKE(hdw->big_lock);
3401         stat = pvr2_hdw_check_cropcap(hdw);
3402         if (!stat) {
3403                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3404         }
3405         LOCK_GIVE(hdw->big_lock);
3406         return stat;
3407 }
3408
3409
3410 /* Return information about the tuner */
3411 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3412 {
3413         LOCK_TAKE(hdw->big_lock); do {
3414                 if (hdw->tuner_signal_stale) {
3415                         pvr2_hdw_status_poll(hdw);
3416                 }
3417                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3418         } while (0); LOCK_GIVE(hdw->big_lock);
3419         return 0;
3420 }
3421
3422
3423 /* Get handle to video output stream */
3424 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3425 {
3426         return hp->vid_stream;
3427 }
3428
3429
3430 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3431 {
3432         int nr = pvr2_hdw_get_unit_number(hdw);
3433         LOCK_TAKE(hdw->big_lock); do {
3434                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3435                 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3436                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3437                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3438                 pvr2_hdw_state_log_state(hdw);
3439                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3440         } while (0); LOCK_GIVE(hdw->big_lock);
3441 }
3442
3443
3444 /* Grab EEPROM contents, needed for direct method. */
3445 #define EEPROM_SIZE 8192
3446 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3447 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3448 {
3449         struct i2c_msg msg[2];
3450         u8 *eeprom;
3451         u8 iadd[2];
3452         u8 addr;
3453         u16 eepromSize;
3454         unsigned int offs;
3455         int ret;
3456         int mode16 = 0;
3457         unsigned pcnt,tcnt;
3458         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3459         if (!eeprom) {
3460                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3461                            "Failed to allocate memory"
3462                            " required to read eeprom");
3463                 return NULL;
3464         }
3465
3466         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3467                      hdw->eeprom_addr);
3468         addr = hdw->eeprom_addr;
3469         /* Seems that if the high bit is set, then the *real* eeprom
3470            address is shifted right now bit position (noticed this in
3471            newer PVR USB2 hardware) */
3472         if (addr & 0x80) addr >>= 1;
3473
3474         /* FX2 documentation states that a 16bit-addressed eeprom is
3475            expected if the I2C address is an odd number (yeah, this is
3476            strange but it's what they do) */
3477         mode16 = (addr & 1);
3478         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3479         trace_eeprom("Examining %d byte eeprom at location 0x%x"
3480                      " using %d bit addressing",eepromSize,addr,
3481                      mode16 ? 16 : 8);
3482
3483         msg[0].addr = addr;
3484         msg[0].flags = 0;
3485         msg[0].len = mode16 ? 2 : 1;
3486         msg[0].buf = iadd;
3487         msg[1].addr = addr;
3488         msg[1].flags = I2C_M_RD;
3489
3490         /* We have to do the actual eeprom data fetch ourselves, because
3491            (1) we're only fetching part of the eeprom, and (2) if we were
3492            getting the whole thing our I2C driver can't grab it in one
3493            pass - which is what tveeprom is otherwise going to attempt */
3494         memset(eeprom,0,EEPROM_SIZE);
3495         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3496                 pcnt = 16;
3497                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3498                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3499                 if (mode16) {
3500                         iadd[0] = offs >> 8;
3501                         iadd[1] = offs;
3502                 } else {
3503                         iadd[0] = offs;
3504                 }
3505                 msg[1].len = pcnt;
3506                 msg[1].buf = eeprom+tcnt;
3507                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3508                                         msg,ARRAY_SIZE(msg))) != 2) {
3509                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3510                                    "eeprom fetch set offs err=%d",ret);
3511                         kfree(eeprom);
3512                         return NULL;
3513                 }
3514         }
3515         return eeprom;
3516 }
3517
3518
3519 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3520                                 int mode,
3521                                 int enable_flag)
3522 {
3523         int ret;
3524         u16 address;
3525         unsigned int pipe;
3526         LOCK_TAKE(hdw->big_lock); do {
3527                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3528
3529                 if (!enable_flag) {
3530                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3531                                    "Cleaning up after CPU firmware fetch");
3532                         kfree(hdw->fw_buffer);
3533                         hdw->fw_buffer = NULL;
3534                         hdw->fw_size = 0;
3535                         if (hdw->fw_cpu_flag) {
3536                                 /* Now release the CPU.  It will disconnect
3537                                    and reconnect later. */
3538                                 pvr2_hdw_cpureset_assert(hdw,0);
3539                         }
3540                         break;
3541                 }
3542
3543                 hdw->fw_cpu_flag = (mode != 2);
3544                 if (hdw->fw_cpu_flag) {
3545                         hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
3546                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3547                                    "Preparing to suck out CPU firmware"
3548                                    " (size=%u)", hdw->fw_size);
3549                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3550                         if (!hdw->fw_buffer) {
3551                                 hdw->fw_size = 0;
3552                                 break;
3553                         }
3554
3555                         /* We have to hold the CPU during firmware upload. */
3556                         pvr2_hdw_cpureset_assert(hdw,1);
3557
3558                         /* download the firmware from address 0000-1fff in 2048
3559                            (=0x800) bytes chunk. */
3560
3561                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3562                                    "Grabbing CPU firmware");
3563                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3564                         for(address = 0; address < hdw->fw_size;
3565                             address += 0x800) {
3566                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3567                                                       0xa0,0xc0,
3568                                                       address,0,
3569                                                       hdw->fw_buffer+address,
3570                                                       0x800,HZ);
3571                                 if (ret < 0) break;
3572                         }
3573
3574                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3575                                    "Done grabbing CPU firmware");
3576                 } else {
3577                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3578                                    "Sucking down EEPROM contents");
3579                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3580                         if (!hdw->fw_buffer) {
3581                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3582                                            "EEPROM content suck failed.");
3583                                 break;
3584                         }
3585                         hdw->fw_size = EEPROM_SIZE;
3586                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3587                                    "Done sucking down EEPROM contents");
3588                 }
3589
3590         } while (0); LOCK_GIVE(hdw->big_lock);
3591 }
3592
3593
3594 /* Return true if we're in a mode for retrieval CPU firmware */
3595 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3596 {
3597         return hdw->fw_buffer != NULL;
3598 }
3599
3600
3601 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3602                        char *buf,unsigned int cnt)
3603 {
3604         int ret = -EINVAL;
3605         LOCK_TAKE(hdw->big_lock); do {
3606                 if (!buf) break;
3607                 if (!cnt) break;
3608
3609                 if (!hdw->fw_buffer) {
3610                         ret = -EIO;
3611                         break;
3612                 }
3613
3614                 if (offs >= hdw->fw_size) {
3615                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3616                                    "Read firmware data offs=%d EOF",
3617                                    offs);
3618                         ret = 0;
3619                         break;
3620                 }
3621
3622                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3623
3624                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3625
3626                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3627                            "Read firmware data offs=%d cnt=%d",
3628                            offs,cnt);
3629                 ret = cnt;
3630         } while (0); LOCK_GIVE(hdw->big_lock);
3631
3632         return ret;
3633 }
3634
3635
3636 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3637                                   enum pvr2_v4l_type index)
3638 {
3639         switch (index) {
3640         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3641         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3642         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3643         default: return -1;
3644         }
3645 }
3646
3647
3648 /* Store a v4l minor device number */
3649 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3650                                      enum pvr2_v4l_type index,int v)
3651 {
3652         switch (index) {
3653         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3654         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3655         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
3656         default: break;
3657         }
3658 }
3659
3660
3661 static void pvr2_ctl_write_complete(struct urb *urb)
3662 {
3663         struct pvr2_hdw *hdw = urb->context;
3664         hdw->ctl_write_pend_flag = 0;
3665         if (hdw->ctl_read_pend_flag) return;
3666         complete(&hdw->ctl_done);
3667 }
3668
3669
3670 static void pvr2_ctl_read_complete(struct urb *urb)
3671 {
3672         struct pvr2_hdw *hdw = urb->context;
3673         hdw->ctl_read_pend_flag = 0;
3674         if (hdw->ctl_write_pend_flag) return;
3675         complete(&hdw->ctl_done);
3676 }
3677
3678
3679 static void pvr2_ctl_timeout(unsigned long data)
3680 {
3681         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3682         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3683                 hdw->ctl_timeout_flag = !0;
3684                 if (hdw->ctl_write_pend_flag)
3685                         usb_unlink_urb(hdw->ctl_write_urb);
3686                 if (hdw->ctl_read_pend_flag)
3687                         usb_unlink_urb(hdw->ctl_read_urb);
3688         }
3689 }
3690
3691
3692 /* Issue a command and get a response from the device.  This extended
3693    version includes a probe flag (which if set means that device errors
3694    should not be logged or treated as fatal) and a timeout in jiffies.
3695    This can be used to non-lethally probe the health of endpoint 1. */
3696 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3697                                 unsigned int timeout,int probe_fl,
3698                                 void *write_data,unsigned int write_len,
3699                                 void *read_data,unsigned int read_len)
3700 {
3701         unsigned int idx;
3702         int status = 0;
3703         struct timer_list timer;
3704         if (!hdw->ctl_lock_held) {
3705                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3706                            "Attempted to execute control transfer"
3707                            " without lock!!");
3708                 return -EDEADLK;
3709         }
3710         if (!hdw->flag_ok && !probe_fl) {
3711                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3712                            "Attempted to execute control transfer"
3713                            " when device not ok");
3714                 return -EIO;
3715         }
3716         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3717                 if (!probe_fl) {
3718                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3719                                    "Attempted to execute control transfer"
3720                                    " when USB is disconnected");
3721                 }
3722                 return -ENOTTY;
3723         }
3724
3725         /* Ensure that we have sane parameters */
3726         if (!write_data) write_len = 0;
3727         if (!read_data) read_len = 0;
3728         if (write_len > PVR2_CTL_BUFFSIZE) {
3729                 pvr2_trace(
3730                         PVR2_TRACE_ERROR_LEGS,
3731                         "Attempted to execute %d byte"
3732                         " control-write transfer (limit=%d)",
3733                         write_len,PVR2_CTL_BUFFSIZE);
3734                 return -EINVAL;
3735         }
3736         if (read_len > PVR2_CTL_BUFFSIZE) {
3737                 pvr2_trace(
3738                         PVR2_TRACE_ERROR_LEGS,
3739                         "Attempted to execute %d byte"
3740                         " control-read transfer (limit=%d)",
3741                         write_len,PVR2_CTL_BUFFSIZE);
3742                 return -EINVAL;
3743         }
3744         if ((!write_len) && (!read_len)) {
3745                 pvr2_trace(
3746                         PVR2_TRACE_ERROR_LEGS,
3747                         "Attempted to execute null control transfer?");
3748                 return -EINVAL;
3749         }
3750
3751
3752         hdw->cmd_debug_state = 1;
3753         if (write_len) {
3754                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3755         } else {
3756                 hdw->cmd_debug_code = 0;
3757         }
3758         hdw->cmd_debug_write_len = write_len;
3759         hdw->cmd_debug_read_len = read_len;
3760
3761         /* Initialize common stuff */
3762         init_completion(&hdw->ctl_done);
3763         hdw->ctl_timeout_flag = 0;
3764         hdw->ctl_write_pend_flag = 0;
3765         hdw->ctl_read_pend_flag = 0;
3766         init_timer(&timer);
3767         timer.expires = jiffies + timeout;
3768         timer.data = (unsigned long)hdw;
3769         timer.function = pvr2_ctl_timeout;
3770
3771         if (write_len) {
3772                 hdw->cmd_debug_state = 2;
3773                 /* Transfer write data to internal buffer */
3774                 for (idx = 0; idx < write_len; idx++) {
3775                         hdw->ctl_write_buffer[idx] =
3776                                 ((unsigned char *)write_data)[idx];
3777                 }
3778                 /* Initiate a write request */
3779                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3780                                   hdw->usb_dev,
3781                                   usb_sndbulkpipe(hdw->usb_dev,
3782                                                   PVR2_CTL_WRITE_ENDPOINT),
3783                                   hdw->ctl_write_buffer,
3784                                   write_len,
3785                                   pvr2_ctl_write_complete,
3786                                   hdw);
3787                 hdw->ctl_write_urb->actual_length = 0;
3788                 hdw->ctl_write_pend_flag = !0;
3789                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3790                 if (status < 0) {
3791                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3792                                    "Failed to submit write-control"
3793                                    " URB status=%d",status);
3794                         hdw->ctl_write_pend_flag = 0;
3795                         goto done;
3796                 }
3797         }
3798
3799         if (read_len) {
3800                 hdw->cmd_debug_state = 3;
3801                 memset(hdw->ctl_read_buffer,0x43,read_len);
3802                 /* Initiate a read request */
3803                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3804                                   hdw->usb_dev,
3805                                   usb_rcvbulkpipe(hdw->usb_dev,
3806                                                   PVR2_CTL_READ_ENDPOINT),
3807                                   hdw->ctl_read_buffer,
3808                                   read_len,
3809                                   pvr2_ctl_read_complete,
3810                                   hdw);
3811                 hdw->ctl_read_urb->actual_length = 0;
3812                 hdw->ctl_read_pend_flag = !0;
3813                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3814                 if (status < 0) {
3815                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3816                                    "Failed to submit read-control"
3817                                    " URB status=%d",status);
3818                         hdw->ctl_read_pend_flag = 0;
3819                         goto done;
3820                 }
3821         }
3822
3823         /* Start timer */
3824         add_timer(&timer);
3825
3826         /* Now wait for all I/O to complete */
3827         hdw->cmd_debug_state = 4;
3828         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3829                 wait_for_completion(&hdw->ctl_done);
3830         }
3831         hdw->cmd_debug_state = 5;
3832
3833         /* Stop timer */
3834         del_timer_sync(&timer);
3835
3836         hdw->cmd_debug_state = 6;
3837         status = 0;
3838
3839         if (hdw->ctl_timeout_flag) {
3840                 status = -ETIMEDOUT;
3841                 if (!probe_fl) {
3842                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3843                                    "Timed out control-write");
3844                 }
3845                 goto done;
3846         }
3847
3848         if (write_len) {
3849                 /* Validate results of write request */
3850                 if ((hdw->ctl_write_urb->status != 0) &&
3851                     (hdw->ctl_write_urb->status != -ENOENT) &&
3852                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3853                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3854                         /* USB subsystem is reporting some kind of failure
3855                            on the write */
3856                         status = hdw->ctl_write_urb->status;
3857                         if (!probe_fl) {
3858                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3859                                            "control-write URB failure,"
3860                                            " status=%d",
3861                                            status);
3862                         }
3863                         goto done;
3864                 }
3865                 if (hdw->ctl_write_urb->actual_length < write_len) {
3866                         /* Failed to write enough data */
3867                         status = -EIO;
3868                         if (!probe_fl) {
3869                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3870                                            "control-write URB short,"
3871                                            " expected=%d got=%d",
3872                                            write_len,
3873                                            hdw->ctl_write_urb->actual_length);
3874                         }
3875                         goto done;
3876                 }
3877         }
3878         if (read_len) {
3879                 /* Validate results of read request */
3880                 if ((hdw->ctl_read_urb->status != 0) &&
3881                     (hdw->ctl_read_urb->status != -ENOENT) &&
3882                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3883                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3884                         /* USB subsystem is reporting some kind of failure
3885                            on the read */
3886                         status = hdw->ctl_read_urb->status;
3887                         if (!probe_fl) {
3888                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3889                                            "control-read URB failure,"
3890                                            " status=%d",
3891                                            status);
3892                         }
3893                         goto done;
3894                 }
3895                 if (hdw->ctl_read_urb->actual_length < read_len) {
3896                         /* Failed to read enough data */
3897                         status = -EIO;
3898                         if (!probe_fl) {
3899                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3900                                            "control-read URB short,"
3901                                            " expected=%d got=%d",
3902                                            read_len,
3903                                            hdw->ctl_read_urb->actual_length);
3904                         }
3905                         goto done;
3906                 }
3907                 /* Transfer retrieved data out from internal buffer */
3908                 for (idx = 0; idx < read_len; idx++) {
3909                         ((unsigned char *)read_data)[idx] =
3910                                 hdw->ctl_read_buffer[idx];
3911                 }
3912         }
3913
3914  done:
3915
3916         hdw->cmd_debug_state = 0;
3917         if ((status < 0) && (!probe_fl)) {
3918                 pvr2_hdw_render_useless(hdw);
3919         }
3920         return status;
3921 }
3922
3923
3924 int pvr2_send_request(struct pvr2_hdw *hdw,
3925                       void *write_data,unsigned int write_len,
3926                       void *read_data,unsigned int read_len)
3927 {
3928         return pvr2_send_request_ex(hdw,HZ*4,0,
3929                                     write_data,write_len,
3930                                     read_data,read_len);
3931 }
3932
3933
3934 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3935 {
3936         int ret;
3937         unsigned int cnt = 1;
3938         unsigned int args = 0;
3939         LOCK_TAKE(hdw->ctl_lock);
3940         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3941         args = (cmdcode >> 8) & 0xffu;
3942         args = (args > 2) ? 2 : args;
3943         if (args) {
3944                 cnt += args;
3945                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3946                 if (args > 1) {
3947                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3948                 }
3949         }
3950         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3951                 unsigned int idx;
3952                 unsigned int ccnt,bcnt;
3953                 char tbuf[50];
3954                 cmdcode &= 0xffu;
3955                 bcnt = 0;
3956                 ccnt = scnprintf(tbuf+bcnt,
3957                                  sizeof(tbuf)-bcnt,
3958                                  "Sending FX2 command 0x%x",cmdcode);
3959                 bcnt += ccnt;
3960                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3961                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3962                                 ccnt = scnprintf(tbuf+bcnt,
3963                                                  sizeof(tbuf)-bcnt,
3964                                                  " \"%s\"",
3965                                                  pvr2_fx2cmd_desc[idx].desc);
3966                                 bcnt += ccnt;
3967                                 break;
3968                         }
3969                 }
3970                 if (args) {
3971                         ccnt = scnprintf(tbuf+bcnt,
3972                                          sizeof(tbuf)-bcnt,
3973                                          " (%u",hdw->cmd_buffer[1]);
3974                         bcnt += ccnt;
3975                         if (args > 1) {
3976                                 ccnt = scnprintf(tbuf+bcnt,
3977                                                  sizeof(tbuf)-bcnt,
3978                                                  ",%u",hdw->cmd_buffer[2]);
3979                                 bcnt += ccnt;
3980                         }
3981                         ccnt = scnprintf(tbuf+bcnt,
3982                                          sizeof(tbuf)-bcnt,
3983                                          ")");
3984                         bcnt += ccnt;
3985                 }
3986                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3987         }
3988         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3989         LOCK_GIVE(hdw->ctl_lock);
3990         return ret;
3991 }
3992
3993
3994 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3995 {
3996         int ret;
3997
3998         LOCK_TAKE(hdw->ctl_lock);
3999
4000         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
4001         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
4002         hdw->cmd_buffer[5] = 0;
4003         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4004         hdw->cmd_buffer[7] = reg & 0xff;
4005
4006
4007         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
4008
4009         LOCK_GIVE(hdw->ctl_lock);
4010
4011         return ret;
4012 }
4013
4014
4015 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
4016 {
4017         int ret = 0;
4018
4019         LOCK_TAKE(hdw->ctl_lock);
4020
4021         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
4022         hdw->cmd_buffer[1] = 0;
4023         hdw->cmd_buffer[2] = 0;
4024         hdw->cmd_buffer[3] = 0;
4025         hdw->cmd_buffer[4] = 0;
4026         hdw->cmd_buffer[5] = 0;
4027         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4028         hdw->cmd_buffer[7] = reg & 0xff;
4029
4030         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
4031         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
4032
4033         LOCK_GIVE(hdw->ctl_lock);
4034
4035         return ret;
4036 }
4037
4038
4039 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
4040 {
4041         if (!hdw->flag_ok) return;
4042         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4043                    "Device being rendered inoperable");
4044         if (hdw->vid_stream) {
4045                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
4046         }
4047         hdw->flag_ok = 0;
4048         trace_stbit("flag_ok",hdw->flag_ok);
4049         pvr2_hdw_state_sched(hdw);
4050 }
4051
4052
4053 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4054 {
4055         int ret;
4056         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
4057         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
4058         if (ret == 0) {
4059                 ret = usb_reset_device(hdw->usb_dev);
4060                 usb_unlock_device(hdw->usb_dev);
4061         } else {
4062                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4063                            "Failed to lock USB device ret=%d",ret);
4064         }
4065         if (init_pause_msec) {
4066                 pvr2_trace(PVR2_TRACE_INFO,
4067                            "Waiting %u msec for hardware to settle",
4068                            init_pause_msec);
4069                 msleep(init_pause_msec);
4070         }
4071
4072 }
4073
4074
4075 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4076 {
4077         char da[1];
4078         unsigned int pipe;
4079         int ret;
4080
4081         if (!hdw->usb_dev) return;
4082
4083         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4084
4085         da[0] = val ? 0x01 : 0x00;
4086
4087         /* Write the CPUCS register on the 8051.  The lsb of the register
4088            is the reset bit; a 1 asserts reset while a 0 clears it. */
4089         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4090         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4091         if (ret < 0) {
4092                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4093                            "cpureset_assert(%d) error=%d",val,ret);
4094                 pvr2_hdw_render_useless(hdw);
4095         }
4096 }
4097
4098
4099 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4100 {
4101         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
4102 }
4103
4104
4105 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4106 {
4107         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4108 }
4109
4110
4111 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4112 {
4113         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
4114 }
4115
4116
4117 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4118 {
4119         pvr2_trace(PVR2_TRACE_INIT,
4120                    "Requesting decoder reset");
4121         if (hdw->decoder_client_id) {
4122                 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4123                                      core, reset, 0);
4124                 pvr2_hdw_cx25840_vbi_hack(hdw);
4125                 return 0;
4126         }
4127         pvr2_trace(PVR2_TRACE_INIT,
4128                    "Unable to reset decoder: nothing attached");
4129         return -ENOTTY;
4130 }
4131
4132
4133 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4134 {
4135         hdw->flag_ok = !0;
4136         return pvr2_issue_simple_cmd(hdw,
4137                                      FX2CMD_HCW_DEMOD_RESETIN |
4138                                      (1 << 8) |
4139                                      ((onoff ? 1 : 0) << 16));
4140 }
4141
4142
4143 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4144 {
4145         hdw->flag_ok = !0;
4146         return pvr2_issue_simple_cmd(hdw,(onoff ?
4147                                           FX2CMD_ONAIR_DTV_POWER_ON :
4148                                           FX2CMD_ONAIR_DTV_POWER_OFF));
4149 }
4150
4151
4152 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4153                                                 int onoff)
4154 {
4155         return pvr2_issue_simple_cmd(hdw,(onoff ?
4156                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
4157                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
4158 }
4159
4160
4161 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4162 {
4163         int cmode;
4164         /* Compare digital/analog desired setting with current setting.  If
4165            they don't match, fix it... */
4166         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4167         if (cmode == hdw->pathway_state) {
4168                 /* They match; nothing to do */
4169                 return;
4170         }
4171
4172         switch (hdw->hdw_desc->digital_control_scheme) {
4173         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4174                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4175                 if (cmode == PVR2_PATHWAY_ANALOG) {
4176                         /* If moving to analog mode, also force the decoder
4177                            to reset.  If no decoder is attached, then it's
4178                            ok to ignore this because if/when the decoder
4179                            attaches, it will reset itself at that time. */
4180                         pvr2_hdw_cmd_decoder_reset(hdw);
4181                 }
4182                 break;
4183         case PVR2_DIGITAL_SCHEME_ONAIR:
4184                 /* Supposedly we should always have the power on whether in
4185                    digital or analog mode.  But for now do what appears to
4186                    work... */
4187                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4188                 break;
4189         default: break;
4190         }
4191
4192         pvr2_hdw_untrip_unlocked(hdw);
4193         hdw->pathway_state = cmode;
4194 }
4195
4196
4197 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4198 {
4199         /* change some GPIO data
4200          *
4201          * note: bit d7 of dir appears to control the LED,
4202          * so we shut it off here.
4203          *
4204          */
4205         if (onoff) {
4206                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4207         } else {
4208                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4209         }
4210         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4211 }
4212
4213
4214 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4215
4216 static led_method_func led_methods[] = {
4217         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4218 };
4219
4220
4221 /* Toggle LED */
4222 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4223 {
4224         unsigned int scheme_id;
4225         led_method_func fp;
4226
4227         if ((!onoff) == (!hdw->led_on)) return;
4228
4229         hdw->led_on = onoff != 0;
4230
4231         scheme_id = hdw->hdw_desc->led_scheme;
4232         if (scheme_id < ARRAY_SIZE(led_methods)) {
4233                 fp = led_methods[scheme_id];
4234         } else {
4235                 fp = NULL;
4236         }
4237
4238         if (fp) (*fp)(hdw,onoff);
4239 }
4240
4241
4242 /* Stop / start video stream transport */
4243 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4244 {
4245         int ret;
4246
4247         /* If we're in analog mode, then just issue the usual analog
4248            command. */
4249         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4250                 return pvr2_issue_simple_cmd(hdw,
4251                                              (runFl ?
4252                                               FX2CMD_STREAMING_ON :
4253                                               FX2CMD_STREAMING_OFF));
4254                 /*Note: Not reached */
4255         }
4256
4257         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4258                 /* Whoops, we don't know what mode we're in... */
4259                 return -EINVAL;
4260         }
4261
4262         /* To get here we have to be in digital mode.  The mechanism here
4263            is unfortunately different for different vendors.  So we switch
4264            on the device's digital scheme attribute in order to figure out
4265            what to do. */
4266         switch (hdw->hdw_desc->digital_control_scheme) {
4267         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4268                 return pvr2_issue_simple_cmd(hdw,
4269                                              (runFl ?
4270                                               FX2CMD_HCW_DTV_STREAMING_ON :
4271                                               FX2CMD_HCW_DTV_STREAMING_OFF));
4272         case PVR2_DIGITAL_SCHEME_ONAIR:
4273                 ret = pvr2_issue_simple_cmd(hdw,
4274                                             (runFl ?
4275                                              FX2CMD_STREAMING_ON :
4276                                              FX2CMD_STREAMING_OFF));
4277                 if (ret) return ret;
4278                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4279         default:
4280                 return -EINVAL;
4281         }
4282 }
4283
4284
4285 /* Evaluate whether or not state_pathway_ok can change */
4286 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4287 {
4288         if (hdw->state_pathway_ok) {
4289                 /* Nothing to do if pathway is already ok */
4290                 return 0;
4291         }
4292         if (!hdw->state_pipeline_idle) {
4293                 /* Not allowed to change anything if pipeline is not idle */
4294                 return 0;
4295         }
4296         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4297         hdw->state_pathway_ok = !0;
4298         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4299         return !0;
4300 }
4301
4302
4303 /* Evaluate whether or not state_encoder_ok can change */
4304 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4305 {
4306         if (hdw->state_encoder_ok) return 0;
4307         if (hdw->flag_tripped) return 0;
4308         if (hdw->state_encoder_run) return 0;
4309         if (hdw->state_encoder_config) return 0;
4310         if (hdw->state_decoder_run) return 0;
4311         if (hdw->state_usbstream_run) return 0;
4312         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4313                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4314         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4315                 return 0;
4316         }
4317
4318         if (pvr2_upload_firmware2(hdw) < 0) {
4319                 hdw->flag_tripped = !0;
4320                 trace_stbit("flag_tripped",hdw->flag_tripped);
4321                 return !0;
4322         }
4323         hdw->state_encoder_ok = !0;
4324         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4325         return !0;
4326 }
4327
4328
4329 /* Evaluate whether or not state_encoder_config can change */
4330 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4331 {
4332         if (hdw->state_encoder_config) {
4333                 if (hdw->state_encoder_ok) {
4334                         if (hdw->state_pipeline_req &&
4335                             !hdw->state_pipeline_pause) return 0;
4336                 }
4337                 hdw->state_encoder_config = 0;
4338                 hdw->state_encoder_waitok = 0;
4339                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4340                 /* paranoia - solve race if timer just completed */
4341                 del_timer_sync(&hdw->encoder_wait_timer);
4342         } else {
4343                 if (!hdw->state_pathway_ok ||
4344                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4345                     !hdw->state_encoder_ok ||
4346                     !hdw->state_pipeline_idle ||
4347                     hdw->state_pipeline_pause ||
4348                     !hdw->state_pipeline_req ||
4349                     !hdw->state_pipeline_config) {
4350                         /* We must reset the enforced wait interval if
4351                            anything has happened that might have disturbed
4352                            the encoder.  This should be a rare case. */
4353                         if (timer_pending(&hdw->encoder_wait_timer)) {
4354                                 del_timer_sync(&hdw->encoder_wait_timer);
4355                         }
4356                         if (hdw->state_encoder_waitok) {
4357                                 /* Must clear the state - therefore we did
4358                                    something to a state bit and must also
4359                                    return true. */
4360                                 hdw->state_encoder_waitok = 0;
4361                                 trace_stbit("state_encoder_waitok",
4362                                             hdw->state_encoder_waitok);
4363                                 return !0;
4364                         }
4365                         return 0;
4366                 }
4367                 if (!hdw->state_encoder_waitok) {
4368                         if (!timer_pending(&hdw->encoder_wait_timer)) {
4369                                 /* waitok flag wasn't set and timer isn't
4370                                    running.  Check flag once more to avoid
4371                                    a race then start the timer.  This is
4372                                    the point when we measure out a minimal
4373                                    quiet interval before doing something to
4374                                    the encoder. */
4375                                 if (!hdw->state_encoder_waitok) {
4376                                         hdw->encoder_wait_timer.expires =
4377                                                 jiffies +
4378                                                 (HZ * TIME_MSEC_ENCODER_WAIT
4379                                                  / 1000);
4380                                         add_timer(&hdw->encoder_wait_timer);
4381                                 }
4382                         }
4383                         /* We can't continue until we know we have been
4384                            quiet for the interval measured by this
4385                            timer. */
4386                         return 0;
4387                 }
4388                 pvr2_encoder_configure(hdw);
4389                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4390         }
4391         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4392         return !0;
4393 }
4394
4395
4396 /* Return true if the encoder should not be running. */
4397 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4398 {
4399         if (!hdw->state_encoder_ok) {
4400                 /* Encoder isn't healthy at the moment, so stop it. */
4401                 return !0;
4402         }
4403         if (!hdw->state_pathway_ok) {
4404                 /* Mode is not understood at the moment (i.e. it wants to
4405                    change), so encoder must be stopped. */
4406                 return !0;
4407         }
4408
4409         switch (hdw->pathway_state) {
4410         case PVR2_PATHWAY_ANALOG:
4411                 if (!hdw->state_decoder_run) {
4412                         /* We're in analog mode and the decoder is not
4413                            running; thus the encoder should be stopped as
4414                            well. */
4415                         return !0;
4416                 }
4417                 break;
4418         case PVR2_PATHWAY_DIGITAL:
4419                 if (hdw->state_encoder_runok) {
4420                         /* This is a funny case.  We're in digital mode so
4421                            really the encoder should be stopped.  However
4422                            if it really is running, only kill it after
4423                            runok has been set.  This gives a chance for the
4424                            onair quirk to function (encoder must run
4425                            briefly first, at least once, before onair
4426                            digital streaming can work). */
4427                         return !0;
4428                 }
4429                 break;
4430         default:
4431                 /* Unknown mode; so encoder should be stopped. */
4432                 return !0;
4433         }
4434
4435         /* If we get here, we haven't found a reason to stop the
4436            encoder. */
4437         return 0;
4438 }
4439
4440
4441 /* Return true if the encoder should be running. */
4442 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4443 {
4444         if (!hdw->state_encoder_ok) {
4445                 /* Don't run the encoder if it isn't healthy... */
4446                 return 0;
4447         }
4448         if (!hdw->state_pathway_ok) {
4449                 /* Don't run the encoder if we don't (yet) know what mode
4450                    we need to be in... */
4451                 return 0;
4452         }
4453
4454         switch (hdw->pathway_state) {
4455         case PVR2_PATHWAY_ANALOG:
4456                 if (hdw->state_decoder_run) {
4457                         /* In analog mode, if the decoder is running, then
4458                            run the encoder. */
4459                         return !0;
4460                 }
4461                 break;
4462         case PVR2_PATHWAY_DIGITAL:
4463                 if ((hdw->hdw_desc->digital_control_scheme ==
4464                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4465                     !hdw->state_encoder_runok) {
4466                         /* This is a quirk.  OnAir hardware won't stream
4467                            digital until the encoder has been run at least
4468                            once, for a minimal period of time (empiricially
4469                            measured to be 1/4 second).  So if we're on
4470                            OnAir hardware and the encoder has never been
4471                            run at all, then start the encoder.  Normal
4472                            state machine logic in the driver will
4473                            automatically handle the remaining bits. */
4474                         return !0;
4475                 }
4476                 break;
4477         default:
4478                 /* For completeness (unknown mode; encoder won't run ever) */
4479                 break;
4480         }
4481         /* If we get here, then we haven't found any reason to run the
4482            encoder, so don't run it. */
4483         return 0;
4484 }
4485
4486
4487 /* Evaluate whether or not state_encoder_run can change */
4488 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4489 {
4490         if (hdw->state_encoder_run) {
4491                 if (!state_check_disable_encoder_run(hdw)) return 0;
4492                 if (hdw->state_encoder_ok) {
4493                         del_timer_sync(&hdw->encoder_run_timer);
4494                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4495                 }
4496                 hdw->state_encoder_run = 0;
4497         } else {
4498                 if (!state_check_enable_encoder_run(hdw)) return 0;
4499                 if (pvr2_encoder_start(hdw) < 0) return !0;
4500                 hdw->state_encoder_run = !0;
4501                 if (!hdw->state_encoder_runok) {
4502                         hdw->encoder_run_timer.expires =
4503                                 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4504                         add_timer(&hdw->encoder_run_timer);
4505                 }
4506         }
4507         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4508         return !0;
4509 }
4510
4511
4512 /* Timeout function for quiescent timer. */
4513 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4514 {
4515         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4516         hdw->state_decoder_quiescent = !0;
4517         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4518         hdw->state_stale = !0;
4519         queue_work(hdw->workqueue,&hdw->workpoll);
4520 }
4521
4522
4523 /* Timeout function for encoder wait timer. */
4524 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4525 {
4526         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4527         hdw->state_encoder_waitok = !0;
4528         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4529         hdw->state_stale = !0;
4530         queue_work(hdw->workqueue,&hdw->workpoll);
4531 }
4532
4533
4534 /* Timeout function for encoder run timer. */
4535 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4536 {
4537         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4538         if (!hdw->state_encoder_runok) {
4539                 hdw->state_encoder_runok = !0;
4540                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4541                 hdw->state_stale = !0;
4542                 queue_work(hdw->workqueue,&hdw->workpoll);
4543         }
4544 }
4545
4546
4547 /* Evaluate whether or not state_decoder_run can change */
4548 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4549 {
4550         if (hdw->state_decoder_run) {
4551                 if (hdw->state_encoder_ok) {
4552                         if (hdw->state_pipeline_req &&
4553                             !hdw->state_pipeline_pause &&
4554                             hdw->state_pathway_ok) return 0;
4555                 }
4556                 if (!hdw->flag_decoder_missed) {
4557                         pvr2_decoder_enable(hdw,0);
4558                 }
4559                 hdw->state_decoder_quiescent = 0;
4560                 hdw->state_decoder_run = 0;
4561                 /* paranoia - solve race if timer just completed */
4562                 del_timer_sync(&hdw->quiescent_timer);
4563         } else {
4564                 if (!hdw->state_decoder_quiescent) {
4565                         if (!timer_pending(&hdw->quiescent_timer)) {
4566                                 /* We don't do something about the
4567                                    quiescent timer until right here because
4568                                    we also want to catch cases where the
4569                                    decoder was already not running (like
4570                                    after initialization) as opposed to
4571                                    knowing that we had just stopped it.
4572                                    The second flag check is here to cover a
4573                                    race - the timer could have run and set
4574                                    this flag just after the previous check
4575                                    but before we did the pending check. */
4576                                 if (!hdw->state_decoder_quiescent) {
4577                                         hdw->quiescent_timer.expires =
4578                                                 jiffies +
4579                                                 (HZ * TIME_MSEC_DECODER_WAIT
4580                                                  / 1000);
4581                                         add_timer(&hdw->quiescent_timer);
4582                                 }
4583                         }
4584                         /* Don't allow decoder to start again until it has
4585                            been quiesced first.  This little detail should
4586                            hopefully further stabilize the encoder. */
4587                         return 0;
4588                 }
4589                 if (!hdw->state_pathway_ok ||
4590                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4591                     !hdw->state_pipeline_req ||
4592                     hdw->state_pipeline_pause ||
4593                     !hdw->state_pipeline_config ||
4594                     !hdw->state_encoder_config ||
4595                     !hdw->state_encoder_ok) return 0;
4596                 del_timer_sync(&hdw->quiescent_timer);
4597                 if (hdw->flag_decoder_missed) return 0;
4598                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4599                 hdw->state_decoder_quiescent = 0;
4600                 hdw->state_decoder_run = !0;
4601         }
4602         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4603         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4604         return !0;
4605 }
4606
4607
4608 /* Evaluate whether or not state_usbstream_run can change */
4609 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4610 {
4611         if (hdw->state_usbstream_run) {
4612                 int fl = !0;
4613                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4614                         fl = (hdw->state_encoder_ok &&
4615                               hdw->state_encoder_run);
4616                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4617                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4618                         fl = hdw->state_encoder_ok;
4619                 }
4620                 if (fl &&
4621                     hdw->state_pipeline_req &&
4622                     !hdw->state_pipeline_pause &&
4623                     hdw->state_pathway_ok) {
4624                         return 0;
4625                 }
4626                 pvr2_hdw_cmd_usbstream(hdw,0);
4627                 hdw->state_usbstream_run = 0;
4628         } else {
4629                 if (!hdw->state_pipeline_req ||
4630                     hdw->state_pipeline_pause ||
4631                     !hdw->state_pathway_ok) return 0;
4632                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4633                         if (!hdw->state_encoder_ok ||
4634                             !hdw->state_encoder_run) return 0;
4635                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4636                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4637                         if (!hdw->state_encoder_ok) return 0;
4638                         if (hdw->state_encoder_run) return 0;
4639                         if (hdw->hdw_desc->digital_control_scheme ==
4640                             PVR2_DIGITAL_SCHEME_ONAIR) {
4641                                 /* OnAir digital receivers won't stream
4642                                    unless the analog encoder has run first.
4643                                    Why?  I have no idea.  But don't even
4644                                    try until we know the analog side is
4645                                    known to have run. */
4646                                 if (!hdw->state_encoder_runok) return 0;
4647                         }
4648                 }
4649                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4650                 hdw->state_usbstream_run = !0;
4651         }
4652         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4653         return !0;
4654 }
4655
4656
4657 /* Attempt to configure pipeline, if needed */
4658 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4659 {
4660         if (hdw->state_pipeline_config ||
4661             hdw->state_pipeline_pause) return 0;
4662         pvr2_hdw_commit_execute(hdw);
4663         return !0;
4664 }
4665
4666
4667 /* Update pipeline idle and pipeline pause tracking states based on other
4668    inputs.  This must be called whenever the other relevant inputs have
4669    changed. */
4670 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4671 {
4672         unsigned int st;
4673         int updatedFl = 0;
4674         /* Update pipeline state */
4675         st = !(hdw->state_encoder_run ||
4676                hdw->state_decoder_run ||
4677                hdw->state_usbstream_run ||
4678                (!hdw->state_decoder_quiescent));
4679         if (!st != !hdw->state_pipeline_idle) {
4680                 hdw->state_pipeline_idle = st;
4681                 updatedFl = !0;
4682         }
4683         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4684                 hdw->state_pipeline_pause = 0;
4685                 updatedFl = !0;
4686         }
4687         return updatedFl;
4688 }
4689
4690
4691 typedef int (*state_eval_func)(struct pvr2_hdw *);
4692
4693 /* Set of functions to be run to evaluate various states in the driver. */
4694 static const state_eval_func eval_funcs[] = {
4695         state_eval_pathway_ok,
4696         state_eval_pipeline_config,
4697         state_eval_encoder_ok,
4698         state_eval_encoder_config,
4699         state_eval_decoder_run,
4700         state_eval_encoder_run,
4701         state_eval_usbstream_run,
4702 };
4703
4704
4705 /* Process various states and return true if we did anything interesting. */
4706 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4707 {
4708         unsigned int i;
4709         int state_updated = 0;
4710         int check_flag;
4711
4712         if (!hdw->state_stale) return 0;
4713         if ((hdw->fw1_state != FW1_STATE_OK) ||
4714             !hdw->flag_ok) {
4715                 hdw->state_stale = 0;
4716                 return !0;
4717         }
4718         /* This loop is the heart of the entire driver.  It keeps trying to
4719            evaluate various bits of driver state until nothing changes for
4720            one full iteration.  Each "bit of state" tracks some global
4721            aspect of the driver, e.g. whether decoder should run, if
4722            pipeline is configured, usb streaming is on, etc.  We separately
4723            evaluate each of those questions based on other driver state to
4724            arrive at the correct running configuration. */
4725         do {
4726                 check_flag = 0;
4727                 state_update_pipeline_state(hdw);
4728                 /* Iterate over each bit of state */
4729                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4730                         if ((*eval_funcs[i])(hdw)) {
4731                                 check_flag = !0;
4732                                 state_updated = !0;
4733                                 state_update_pipeline_state(hdw);
4734                         }
4735                 }
4736         } while (check_flag && hdw->flag_ok);
4737         hdw->state_stale = 0;
4738         trace_stbit("state_stale",hdw->state_stale);
4739         return state_updated;
4740 }
4741
4742
4743 static unsigned int print_input_mask(unsigned int msk,
4744                                      char *buf,unsigned int acnt)
4745 {
4746         unsigned int idx,ccnt;
4747         unsigned int tcnt = 0;
4748         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4749                 if (!((1 << idx) & msk)) continue;
4750                 ccnt = scnprintf(buf+tcnt,
4751                                  acnt-tcnt,
4752                                  "%s%s",
4753                                  (tcnt ? ", " : ""),
4754                                  control_values_input[idx]);
4755                 tcnt += ccnt;
4756         }
4757         return tcnt;
4758 }
4759
4760
4761 static const char *pvr2_pathway_state_name(int id)
4762 {
4763         switch (id) {
4764         case PVR2_PATHWAY_ANALOG: return "analog";
4765         case PVR2_PATHWAY_DIGITAL: return "digital";
4766         default: return "unknown";
4767         }
4768 }
4769
4770
4771 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4772                                              char *buf,unsigned int acnt)
4773 {
4774         switch (which) {
4775         case 0:
4776                 return scnprintf(
4777                         buf,acnt,
4778                         "driver:%s%s%s%s%s <mode=%s>",
4779                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4780                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4781                         (hdw->flag_disconnected ? " <disconnected>" :
4782                          " <connected>"),
4783                         (hdw->flag_tripped ? " <tripped>" : ""),
4784                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4785                         pvr2_pathway_state_name(hdw->pathway_state));
4786
4787         case 1:
4788                 return scnprintf(
4789                         buf,acnt,
4790                         "pipeline:%s%s%s%s",
4791                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4792                         (hdw->state_pipeline_config ?
4793                          " <configok>" : " <stale>"),
4794                         (hdw->state_pipeline_req ? " <req>" : ""),
4795                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4796         case 2:
4797                 return scnprintf(
4798                         buf,acnt,
4799                         "worker:%s%s%s%s%s%s%s",
4800                         (hdw->state_decoder_run ?
4801                          " <decode:run>" :
4802                          (hdw->state_decoder_quiescent ?
4803                           "" : " <decode:stop>")),
4804                         (hdw->state_decoder_quiescent ?
4805                          " <decode:quiescent>" : ""),
4806                         (hdw->state_encoder_ok ?
4807                          "" : " <encode:init>"),
4808                         (hdw->state_encoder_run ?
4809                          (hdw->state_encoder_runok ?
4810                           " <encode:run>" :
4811                           " <encode:firstrun>") :
4812                          (hdw->state_encoder_runok ?
4813                           " <encode:stop>" :
4814                           " <encode:virgin>")),
4815                         (hdw->state_encoder_config ?
4816                          " <encode:configok>" :
4817                          (hdw->state_encoder_waitok ?
4818                           "" : " <encode:waitok>")),
4819                         (hdw->state_usbstream_run ?
4820                          " <usb:run>" : " <usb:stop>"),
4821                         (hdw->state_pathway_ok ?
4822                          " <pathway:ok>" : ""));
4823         case 3:
4824                 return scnprintf(
4825                         buf,acnt,
4826                         "state: %s",
4827                         pvr2_get_state_name(hdw->master_state));
4828         case 4: {
4829                 unsigned int tcnt = 0;
4830                 unsigned int ccnt;
4831
4832                 ccnt = scnprintf(buf,
4833                                  acnt,
4834                                  "Hardware supported inputs: ");
4835                 tcnt += ccnt;
4836                 tcnt += print_input_mask(hdw->input_avail_mask,
4837                                          buf+tcnt,
4838                                          acnt-tcnt);
4839                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4840                         ccnt = scnprintf(buf+tcnt,
4841                                          acnt-tcnt,
4842                                          "; allowed inputs: ");
4843                         tcnt += ccnt;
4844                         tcnt += print_input_mask(hdw->input_allowed_mask,
4845                                                  buf+tcnt,
4846                                                  acnt-tcnt);
4847                 }
4848                 return tcnt;
4849         }
4850         case 5: {
4851                 struct pvr2_stream_stats stats;
4852                 if (!hdw->vid_stream) break;
4853                 pvr2_stream_get_stats(hdw->vid_stream,
4854                                       &stats,
4855                                       0);
4856                 return scnprintf(
4857                         buf,acnt,
4858                         "Bytes streamed=%u"
4859                         " URBs: queued=%u idle=%u ready=%u"
4860                         " processed=%u failed=%u",
4861                         stats.bytes_processed,
4862                         stats.buffers_in_queue,
4863                         stats.buffers_in_idle,
4864                         stats.buffers_in_ready,
4865                         stats.buffers_processed,
4866                         stats.buffers_failed);
4867         }
4868         case 6: {
4869                 unsigned int id = hdw->ir_scheme_active;
4870                 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4871                                  (id >= ARRAY_SIZE(ir_scheme_names) ?
4872                                   "?" : ir_scheme_names[id]));
4873         }
4874         default: break;
4875         }
4876         return 0;
4877 }
4878
4879
4880 /* Generate report containing info about attached sub-devices and attached
4881    i2c clients, including an indication of which attached i2c clients are
4882    actually sub-devices. */
4883 static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4884                                             char *buf, unsigned int acnt)
4885 {
4886         struct v4l2_subdev *sd;
4887         unsigned int tcnt = 0;
4888         unsigned int ccnt;
4889         struct i2c_client *client;
4890         const char *p;
4891         unsigned int id;
4892
4893         ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
4894         tcnt += ccnt;
4895         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4896                 id = sd->grp_id;
4897                 p = NULL;
4898                 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4899                 if (p) {
4900                         ccnt = scnprintf(buf + tcnt, acnt - tcnt, "  %s:", p);
4901                         tcnt += ccnt;
4902                 } else {
4903                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4904                                          "  (unknown id=%u):", id);
4905                         tcnt += ccnt;
4906                 }
4907                 client = v4l2_get_subdevdata(sd);
4908                 if (client) {
4909                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4910                                          " %s @ %02x\n", client->name,
4911                                          client->addr);
4912                         tcnt += ccnt;
4913                 } else {
4914                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4915                                          " no i2c client\n");
4916                         tcnt += ccnt;
4917                 }
4918         }
4919         return tcnt;
4920 }
4921
4922
4923 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4924                                    char *buf,unsigned int acnt)
4925 {
4926         unsigned int bcnt,ccnt,idx;
4927         bcnt = 0;
4928         LOCK_TAKE(hdw->big_lock);
4929         for (idx = 0; ; idx++) {
4930                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4931                 if (!ccnt) break;
4932                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4933                 if (!acnt) break;
4934                 buf[0] = '\n'; ccnt = 1;
4935                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4936         }
4937         ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4938         bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4939         LOCK_GIVE(hdw->big_lock);
4940         return bcnt;
4941 }
4942
4943
4944 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4945 {
4946         char buf[256];
4947         unsigned int idx, ccnt;
4948         unsigned int lcnt, ucnt;
4949
4950         for (idx = 0; ; idx++) {
4951                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4952                 if (!ccnt) break;
4953                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4954         }
4955         ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
4956         ucnt = 0;
4957         while (ucnt < ccnt) {
4958                 lcnt = 0;
4959                 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4960                         lcnt++;
4961                 }
4962                 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4963                 ucnt += lcnt + 1;
4964         }
4965 }
4966
4967
4968 /* Evaluate and update the driver's current state, taking various actions
4969    as appropriate for the update. */
4970 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4971 {
4972         unsigned int st;
4973         int state_updated = 0;
4974         int callback_flag = 0;
4975         int analog_mode;
4976
4977         pvr2_trace(PVR2_TRACE_STBITS,
4978                    "Drive state check START");
4979         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4980                 pvr2_hdw_state_log_state(hdw);
4981         }
4982
4983         /* Process all state and get back over disposition */
4984         state_updated = pvr2_hdw_state_update(hdw);
4985
4986         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4987
4988         /* Update master state based upon all other states. */
4989         if (!hdw->flag_ok) {
4990                 st = PVR2_STATE_DEAD;
4991         } else if (hdw->fw1_state != FW1_STATE_OK) {
4992                 st = PVR2_STATE_COLD;
4993         } else if ((analog_mode ||
4994                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4995                    !hdw->state_encoder_ok) {
4996                 st = PVR2_STATE_WARM;
4997         } else if (hdw->flag_tripped ||
4998                    (analog_mode && hdw->flag_decoder_missed)) {
4999                 st = PVR2_STATE_ERROR;
5000         } else if (hdw->state_usbstream_run &&
5001                    (!analog_mode ||
5002                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
5003                 st = PVR2_STATE_RUN;
5004         } else {
5005                 st = PVR2_STATE_READY;
5006         }
5007         if (hdw->master_state != st) {
5008                 pvr2_trace(PVR2_TRACE_STATE,
5009                            "Device state change from %s to %s",
5010                            pvr2_get_state_name(hdw->master_state),
5011                            pvr2_get_state_name(st));
5012                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
5013                 hdw->master_state = st;
5014                 state_updated = !0;
5015                 callback_flag = !0;
5016         }
5017         if (state_updated) {
5018                 /* Trigger anyone waiting on any state changes here. */
5019                 wake_up(&hdw->state_wait_data);
5020         }
5021
5022         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5023                 pvr2_hdw_state_log_state(hdw);
5024         }
5025         pvr2_trace(PVR2_TRACE_STBITS,
5026                    "Drive state check DONE callback=%d",callback_flag);
5027
5028         return callback_flag;
5029 }
5030
5031
5032 /* Cause kernel thread to check / update driver state */
5033 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
5034 {
5035         if (hdw->state_stale) return;
5036         hdw->state_stale = !0;
5037         trace_stbit("state_stale",hdw->state_stale);
5038         queue_work(hdw->workqueue,&hdw->workpoll);
5039 }
5040
5041
5042 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
5043 {
5044         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5045 }
5046
5047
5048 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5049 {
5050         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5051 }
5052
5053
5054 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5055 {
5056         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5057 }
5058
5059
5060 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5061 {
5062         u32 cval,nval;
5063         int ret;
5064         if (~msk) {
5065                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5066                 if (ret) return ret;
5067                 nval = (cval & ~msk) | (val & msk);
5068                 pvr2_trace(PVR2_TRACE_GPIO,
5069                            "GPIO direction changing 0x%x:0x%x"
5070                            " from 0x%x to 0x%x",
5071                            msk,val,cval,nval);
5072         } else {
5073                 nval = val;
5074                 pvr2_trace(PVR2_TRACE_GPIO,
5075                            "GPIO direction changing to 0x%x",nval);
5076         }
5077         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5078 }
5079
5080
5081 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5082 {
5083         u32 cval,nval;
5084         int ret;
5085         if (~msk) {
5086                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5087                 if (ret) return ret;
5088                 nval = (cval & ~msk) | (val & msk);
5089                 pvr2_trace(PVR2_TRACE_GPIO,
5090                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5091                            msk,val,cval,nval);
5092         } else {
5093                 nval = val;
5094                 pvr2_trace(PVR2_TRACE_GPIO,
5095                            "GPIO output changing to 0x%x",nval);
5096         }
5097         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5098 }
5099
5100
5101 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5102 {
5103         struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5104         memset(vtp, 0, sizeof(*vtp));
5105         hdw->tuner_signal_stale = 0;
5106         /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5107            using v4l2-subdev - therefore we can't support that AT ALL right
5108            now.  (Of course, no sub-drivers seem to implement it either.
5109            But now it's a a chicken and egg problem...) */
5110         v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5111                              &hdw->tuner_signal_info);
5112         pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
5113                    " type=%u strength=%u audio=0x%x cap=0x%x"
5114                    " low=%u hi=%u",
5115                    vtp->type,
5116                    vtp->signal, vtp->rxsubchans, vtp->capability,
5117                    vtp->rangelow, vtp->rangehigh);
5118
5119         /* We have to do this to avoid getting into constant polling if
5120            there's nobody to answer a poll of cropcap info. */
5121         hdw->cropcap_stale = 0;
5122 }
5123
5124
5125 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5126 {
5127         return hdw->input_avail_mask;
5128 }
5129
5130
5131 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5132 {
5133         return hdw->input_allowed_mask;
5134 }
5135
5136
5137 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5138 {
5139         if (hdw->input_val != v) {
5140                 hdw->input_val = v;
5141                 hdw->input_dirty = !0;
5142         }
5143
5144         /* Handle side effects - if we switch to a mode that needs the RF
5145            tuner, then select the right frequency choice as well and mark
5146            it dirty. */
5147         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5148                 hdw->freqSelector = 0;
5149                 hdw->freqDirty = !0;
5150         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5151                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5152                 hdw->freqSelector = 1;
5153                 hdw->freqDirty = !0;
5154         }
5155         return 0;
5156 }
5157
5158
5159 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5160                                unsigned int change_mask,
5161                                unsigned int change_val)
5162 {
5163         int ret = 0;
5164         unsigned int nv,m,idx;
5165         LOCK_TAKE(hdw->big_lock);
5166         do {
5167                 nv = hdw->input_allowed_mask & ~change_mask;
5168                 nv |= (change_val & change_mask);
5169                 nv &= hdw->input_avail_mask;
5170                 if (!nv) {
5171                         /* No legal modes left; return error instead. */
5172                         ret = -EPERM;
5173                         break;
5174                 }
5175                 hdw->input_allowed_mask = nv;
5176                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5177                         /* Current mode is still in the allowed mask, so
5178                            we're done. */
5179                         break;
5180                 }
5181                 /* Select and switch to a mode that is still in the allowed
5182                    mask */
5183                 if (!hdw->input_allowed_mask) {
5184                         /* Nothing legal; give up */
5185                         break;
5186                 }
5187                 m = hdw->input_allowed_mask;
5188                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5189                         if (!((1 << idx) & m)) continue;
5190                         pvr2_hdw_set_input(hdw,idx);
5191                         break;
5192                 }
5193         } while (0);
5194         LOCK_GIVE(hdw->big_lock);
5195         return ret;
5196 }
5197
5198
5199 /* Find I2C address of eeprom */
5200 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5201 {
5202         int result;
5203         LOCK_TAKE(hdw->ctl_lock); do {
5204                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5205                 result = pvr2_send_request(hdw,
5206                                            hdw->cmd_buffer,1,
5207                                            hdw->cmd_buffer,1);
5208                 if (result < 0) break;
5209                 result = hdw->cmd_buffer[0];
5210         } while(0); LOCK_GIVE(hdw->ctl_lock);
5211         return result;
5212 }
5213
5214
5215 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
5216                              struct v4l2_dbg_match *match, u64 reg_id,
5217                              int setFl, u64 *val_ptr)
5218 {
5219 #ifdef CONFIG_VIDEO_ADV_DEBUG
5220         struct v4l2_dbg_register req;
5221         int stat = 0;
5222         int okFl = 0;
5223
5224         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5225
5226         req.match = *match;
5227         req.reg = reg_id;
5228         if (setFl) req.val = *val_ptr;
5229         /* It would be nice to know if a sub-device answered the request */
5230         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5231         if (!setFl) *val_ptr = req.val;
5232         if (okFl) {
5233                 return stat;
5234         }
5235         return -EINVAL;
5236 #else
5237         return -ENOSYS;
5238 #endif
5239 }
5240
5241
5242 /*
5243   Stuff for Emacs to see, in order to encourage consistent editing style:
5244   *** Local Variables: ***
5245   *** mode: c ***
5246   *** fill-column: 75 ***
5247   *** tab-width: 8 ***
5248   *** c-basic-offset: 8 ***
5249   *** End: ***
5250   */