2 * vpif - DM646x Video Port Interface driver
3 * VPIF is a receiver and transmitter for video data. It has two channels(0, 1)
4 * that receiveing video byte stream and two channels(2, 3) for video output.
5 * The hardware supports SDTV, HDTV formats, raw data capture.
6 * Currently, the driver supports NTSC and PAL standards.
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation version 2.
14 * This program is distributed .as is. WITHOUT ANY WARRANTY of any
15 * kind, whether express or implied; without even the implied warranty
16 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/kernel.h>
26 MODULE_DESCRIPTION("TI DaVinci Video Port Interface driver");
27 MODULE_LICENSE("GPL");
29 #define VPIF_CH0_MAX_MODES (22)
30 #define VPIF_CH1_MAX_MODES (02)
31 #define VPIF_CH2_MAX_MODES (15)
32 #define VPIF_CH3_MAX_MODES (02)
34 static inline void vpif_wr_bit(u32 reg, u32 bit, u32 val)
37 vpif_set_bit(reg, bit);
39 vpif_clr_bit(reg, bit);
42 /* This structure is used to keep track of VPIF size register's offsets */
43 struct vpif_registers {
44 u32 h_cfg, v_cfg_00, v_cfg_01, v_cfg_02, v_cfg, ch_ctrl;
45 u32 line_offset, vanc0_strt, vanc0_size, vanc1_strt;
46 u32 vanc1_size, width_mask, len_mask;
50 static const struct vpif_registers vpifregs[VPIF_NUM_CHANNELS] = {
53 VPIF_CH0_H_CFG, VPIF_CH0_V_CFG_00, VPIF_CH0_V_CFG_01,
54 VPIF_CH0_V_CFG_02, VPIF_CH0_V_CFG_03, VPIF_CH0_CTRL,
55 VPIF_CH0_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
60 VPIF_CH1_H_CFG, VPIF_CH1_V_CFG_00, VPIF_CH1_V_CFG_01,
61 VPIF_CH1_V_CFG_02, VPIF_CH1_V_CFG_03, VPIF_CH1_CTRL,
62 VPIF_CH1_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
67 VPIF_CH2_H_CFG, VPIF_CH2_V_CFG_00, VPIF_CH2_V_CFG_01,
68 VPIF_CH2_V_CFG_02, VPIF_CH2_V_CFG_03, VPIF_CH2_CTRL,
69 VPIF_CH2_IMG_ADD_OFST, VPIF_CH2_VANC0_STRT, VPIF_CH2_VANC0_SIZE,
70 VPIF_CH2_VANC1_STRT, VPIF_CH2_VANC1_SIZE, 0x7FF, 0x7FF,
75 VPIF_CH3_H_CFG, VPIF_CH3_V_CFG_00, VPIF_CH3_V_CFG_01,
76 VPIF_CH3_V_CFG_02, VPIF_CH3_V_CFG_03, VPIF_CH3_CTRL,
77 VPIF_CH3_IMG_ADD_OFST, VPIF_CH3_VANC0_STRT, VPIF_CH3_VANC0_SIZE,
78 VPIF_CH3_VANC1_STRT, VPIF_CH3_VANC1_SIZE, 0x7FF, 0x7FF,
83 /* vpif_set_mode_info:
84 * This function is used to set horizontal and vertical config parameters
85 * As per the standard in the channel, configure the values of L1, L3,
86 * L5, L7 L9, L11 in VPIF Register , also write width and height
88 static void vpif_set_mode_info(const struct vpif_channel_config_params *config,
89 u8 channel_id, u8 config_channel_id)
93 value = (config->eav2sav & vpifregs[config_channel_id].width_mask);
94 value <<= VPIF_CH_LEN_SHIFT;
95 value |= (config->sav2eav & vpifregs[config_channel_id].width_mask);
96 regw(value, vpifregs[channel_id].h_cfg);
98 value = (config->l1 & vpifregs[config_channel_id].len_mask);
99 value <<= VPIF_CH_LEN_SHIFT;
100 value |= (config->l3 & vpifregs[config_channel_id].len_mask);
101 regw(value, vpifregs[channel_id].v_cfg_00);
103 value = (config->l5 & vpifregs[config_channel_id].len_mask);
104 value <<= VPIF_CH_LEN_SHIFT;
105 value |= (config->l7 & vpifregs[config_channel_id].len_mask);
106 regw(value, vpifregs[channel_id].v_cfg_01);
108 value = (config->l9 & vpifregs[config_channel_id].len_mask);
109 value <<= VPIF_CH_LEN_SHIFT;
110 value |= (config->l11 & vpifregs[config_channel_id].len_mask);
111 regw(value, vpifregs[channel_id].v_cfg_02);
113 value = (config->vsize & vpifregs[config_channel_id].len_mask);
114 regw(value, vpifregs[channel_id].v_cfg);
117 /* config_vpif_params
118 * Function to set the parameters of a channel
119 * Mainly modifies the channel ciontrol register
120 * It sets frame format, yc mux mode
122 static void config_vpif_params(struct vpif_params *vpifparams,
123 u8 channel_id, u8 found)
125 const struct vpif_channel_config_params *config = &vpifparams->std_info;
126 u32 value, ch_nip, reg;
131 end = channel_id + found;
133 for (i = start; i < end; i++) {
134 reg = vpifregs[i].ch_ctrl;
136 ch_nip = VPIF_CAPTURE_CH_NIP;
138 ch_nip = VPIF_DISPLAY_CH_NIP;
140 vpif_wr_bit(reg, ch_nip, config->frm_fmt);
141 vpif_wr_bit(reg, VPIF_CH_YC_MUX_BIT, config->ycmux_mode);
142 vpif_wr_bit(reg, VPIF_CH_INPUT_FIELD_FRAME_BIT,
143 vpifparams->video_params.storage_mode);
145 /* Set raster scanning SDR Format */
146 vpif_clr_bit(reg, VPIF_CH_SDR_FMT_BIT);
147 vpif_wr_bit(reg, VPIF_CH_DATA_MODE_BIT, config->capture_format);
149 if (channel_id > 1) /* Set the Pixel enable bit */
150 vpif_set_bit(reg, VPIF_DISPLAY_PIX_EN_BIT);
151 else if (config->capture_format) {
152 /* Set the polarity of various pins */
153 vpif_wr_bit(reg, VPIF_CH_FID_POLARITY_BIT,
154 vpifparams->params.raw_params.fid_pol);
155 vpif_wr_bit(reg, VPIF_CH_V_VALID_POLARITY_BIT,
156 vpifparams->params.raw_params.vd_pol);
157 vpif_wr_bit(reg, VPIF_CH_H_VALID_POLARITY_BIT,
158 vpifparams->params.raw_params.hd_pol);
162 value &= ((~(unsigned int)(0x3)) <<
163 VPIF_CH_DATA_WIDTH_BIT);
164 value |= ((vpifparams->params.raw_params.data_sz) <<
165 VPIF_CH_DATA_WIDTH_BIT);
169 /* Write the pitch in the driver */
170 regw((vpifparams->video_params.hpitch),
171 vpifregs[i].line_offset);
175 /* vpif_set_video_params
176 * This function is used to set video parameters in VPIF register
178 int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id)
180 const struct vpif_channel_config_params *config = &vpifparams->std_info;
183 vpif_set_mode_info(config, channel_id, channel_id);
184 if (!config->ycmux_mode) {
185 /* YC are on separate channels (HDTV formats) */
186 vpif_set_mode_info(config, channel_id + 1, channel_id);
190 config_vpif_params(vpifparams, channel_id, found);
192 regw(0x80, VPIF_REQ_SIZE);
193 regw(0x01, VPIF_EMULATION_CTRL);
197 EXPORT_SYMBOL(vpif_set_video_params);
199 void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams,
204 value = 0x3F8 & (vbiparams->hstart0);
205 value |= 0x3FFFFFF & ((vbiparams->vstart0) << 16);
206 regw(value, vpifregs[channel_id].vanc0_strt);
208 value = 0x3F8 & (vbiparams->hstart1);
209 value |= 0x3FFFFFF & ((vbiparams->vstart1) << 16);
210 regw(value, vpifregs[channel_id].vanc1_strt);
212 value = 0x3F8 & (vbiparams->hsize0);
213 value |= 0x3FFFFFF & ((vbiparams->vsize0) << 16);
214 regw(value, vpifregs[channel_id].vanc0_size);
216 value = 0x3F8 & (vbiparams->hsize1);
217 value |= 0x3FFFFFF & ((vbiparams->vsize1) << 16);
218 regw(value, vpifregs[channel_id].vanc1_size);
221 EXPORT_SYMBOL(vpif_set_vbi_display_params);
223 int vpif_channel_getfid(u8 channel_id)
225 return (regr(vpifregs[channel_id].ch_ctrl) & VPIF_CH_FID_MASK)
226 >> VPIF_CH_FID_SHIFT;
228 EXPORT_SYMBOL(vpif_channel_getfid);
230 void vpif_base_addr_init(void __iomem *base)
234 EXPORT_SYMBOL(vpif_base_addr_init);