3 * device driver for Conexant 2388x based TV cards
4 * MPEG Transport Stream (DVB) routines
6 * (c) 2004, 2005 Chris Pascoe <c.pascoe@itee.uq.edu.au>
7 * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/device.h>
28 #include <linux/kthread.h>
29 #include <linux/file.h>
30 #include <linux/suspend.h>
34 #include <media/v4l2-common.h>
37 #include "mt352_priv.h"
38 #include "cx88-vp3054-i2c.h"
47 MODULE_DESCRIPTION("driver for cx2388x based DVB cards");
48 MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
49 MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
50 MODULE_LICENSE("GPL");
52 static unsigned int debug = 0;
53 module_param(debug, int, 0644);
54 MODULE_PARM_DESC(debug,"enable debug messages [dvb]");
56 #define dprintk(level,fmt, arg...) if (debug >= level) \
57 printk(KERN_DEBUG "%s/2-dvb: " fmt, core->name, ## arg)
59 /* ------------------------------------------------------------------ */
61 static int dvb_buf_setup(struct videobuf_queue *q,
62 unsigned int *count, unsigned int *size)
64 struct cx8802_dev *dev = q->priv_data;
66 dev->ts_packet_size = 188 * 4;
67 dev->ts_packet_count = 32;
69 *size = dev->ts_packet_size * dev->ts_packet_count;
74 static int dvb_buf_prepare(struct videobuf_queue *q,
75 struct videobuf_buffer *vb, enum v4l2_field field)
77 struct cx8802_dev *dev = q->priv_data;
78 return cx8802_buf_prepare(q, dev, (struct cx88_buffer*)vb,field);
81 static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
83 struct cx8802_dev *dev = q->priv_data;
84 cx8802_buf_queue(dev, (struct cx88_buffer*)vb);
87 static void dvb_buf_release(struct videobuf_queue *q,
88 struct videobuf_buffer *vb)
90 cx88_free_buffer(q, (struct cx88_buffer*)vb);
93 static struct videobuf_queue_ops dvb_qops = {
94 .buf_setup = dvb_buf_setup,
95 .buf_prepare = dvb_buf_prepare,
96 .buf_queue = dvb_buf_queue,
97 .buf_release = dvb_buf_release,
100 /* ------------------------------------------------------------------ */
102 static int cx88_dvb_bus_ctrl(struct dvb_frontend* fe, int acquire)
104 struct cx8802_dev *dev= fe->dvb->priv;
105 struct cx8802_driver *drv = NULL;
108 drv = cx8802_get_driver(dev, CX88_MPEG_DVB);
111 ret = drv->request_acquire(drv);
113 ret = drv->request_release(drv);
119 /* ------------------------------------------------------------------ */
121 static int dvico_fusionhdtv_demod_init(struct dvb_frontend* fe)
123 static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x39 };
124 static u8 reset [] = { RESET, 0x80 };
125 static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
126 static u8 agc_cfg [] = { AGC_TARGET, 0x24, 0x20 };
127 static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
128 static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
130 mt352_write(fe, clock_config, sizeof(clock_config));
132 mt352_write(fe, reset, sizeof(reset));
133 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
135 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
136 mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
137 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
141 static int dvico_dual_demod_init(struct dvb_frontend *fe)
143 static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x38 };
144 static u8 reset [] = { RESET, 0x80 };
145 static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
146 static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0x20 };
147 static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
148 static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
150 mt352_write(fe, clock_config, sizeof(clock_config));
152 mt352_write(fe, reset, sizeof(reset));
153 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
155 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
156 mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
157 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
162 static int dntv_live_dvbt_demod_init(struct dvb_frontend* fe)
164 static u8 clock_config [] = { 0x89, 0x38, 0x39 };
165 static u8 reset [] = { 0x50, 0x80 };
166 static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
167 static u8 agc_cfg [] = { 0x67, 0x10, 0x23, 0x00, 0xFF, 0xFF,
168 0x00, 0xFF, 0x00, 0x40, 0x40 };
169 static u8 dntv_extra[] = { 0xB5, 0x7A };
170 static u8 capt_range_cfg[] = { 0x75, 0x32 };
172 mt352_write(fe, clock_config, sizeof(clock_config));
174 mt352_write(fe, reset, sizeof(reset));
175 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
177 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
179 mt352_write(fe, dntv_extra, sizeof(dntv_extra));
180 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
185 static struct mt352_config dvico_fusionhdtv = {
186 .demod_address = 0x0f,
187 .demod_init = dvico_fusionhdtv_demod_init,
190 static struct mt352_config dntv_live_dvbt_config = {
191 .demod_address = 0x0f,
192 .demod_init = dntv_live_dvbt_demod_init,
195 static struct mt352_config dvico_fusionhdtv_dual = {
196 .demod_address = 0x0f,
197 .demod_init = dvico_dual_demod_init,
200 #if defined(CONFIG_VIDEO_CX88_VP3054) || (defined(CONFIG_VIDEO_CX88_VP3054_MODULE) && defined(MODULE))
201 static int dntv_live_dvbt_pro_demod_init(struct dvb_frontend* fe)
203 static u8 clock_config [] = { 0x89, 0x38, 0x38 };
204 static u8 reset [] = { 0x50, 0x80 };
205 static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
206 static u8 agc_cfg [] = { 0x67, 0x10, 0x20, 0x00, 0xFF, 0xFF,
207 0x00, 0xFF, 0x00, 0x40, 0x40 };
208 static u8 dntv_extra[] = { 0xB5, 0x7A };
209 static u8 capt_range_cfg[] = { 0x75, 0x32 };
211 mt352_write(fe, clock_config, sizeof(clock_config));
213 mt352_write(fe, reset, sizeof(reset));
214 mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
216 mt352_write(fe, agc_cfg, sizeof(agc_cfg));
218 mt352_write(fe, dntv_extra, sizeof(dntv_extra));
219 mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
224 static int philips_fmd1216_pll_init(struct dvb_frontend *fe)
226 struct cx8802_dev *dev= fe->dvb->priv;
228 /* this message is to set up ATC and ALC */
229 static u8 fmd1216_init[] = { 0x0b, 0xdc, 0x9c, 0xa0 };
231 { .addr = dev->core->pll_addr, .flags = 0,
232 .buf = fmd1216_init, .len = sizeof(fmd1216_init) };
235 if (fe->ops.i2c_gate_ctrl)
236 fe->ops.i2c_gate_ctrl(fe, 1);
237 if ((err = i2c_transfer(&dev->core->i2c_adap, &msg, 1)) != 1) {
247 static int dntv_live_dvbt_pro_tuner_set_params(struct dvb_frontend* fe,
248 struct dvb_frontend_parameters* params)
250 struct cx8802_dev *dev= fe->dvb->priv;
253 { .addr = dev->core->pll_addr, .flags = 0,
254 .buf = buf, .len = 4 };
257 /* Switch PLL to DVB mode */
258 err = philips_fmd1216_pll_init(fe);
263 dvb_pll_configure(dev->core->pll_desc, buf, params);
264 if (fe->ops.i2c_gate_ctrl)
265 fe->ops.i2c_gate_ctrl(fe, 1);
266 if ((err = i2c_transfer(&dev->core->i2c_adap, &msg, 1)) != 1) {
268 printk(KERN_WARNING "cx88-dvb: %s error "
269 "(addr %02x <- %02x, err = %i)\n",
270 __FUNCTION__, dev->core->pll_addr, buf[0], err);
280 static struct mt352_config dntv_live_dvbt_pro_config = {
281 .demod_address = 0x0f,
283 .demod_init = dntv_live_dvbt_pro_demod_init,
287 static struct zl10353_config dvico_fusionhdtv_hybrid = {
288 .demod_address = 0x0f,
292 static struct zl10353_config dvico_fusionhdtv_plus_v1_1 = {
293 .demod_address = 0x0f,
296 static struct cx22702_config connexant_refboard_config = {
297 .demod_address = 0x43,
298 .output_mode = CX22702_SERIAL_OUTPUT,
301 static struct cx22702_config hauppauge_hvr_config = {
302 .demod_address = 0x63,
303 .output_mode = CX22702_SERIAL_OUTPUT,
306 static int or51132_set_ts_param(struct dvb_frontend* fe, int is_punctured)
308 struct cx8802_dev *dev= fe->dvb->priv;
309 dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
313 static struct or51132_config pchdtv_hd3000 = {
314 .demod_address = 0x15,
315 .set_ts_params = or51132_set_ts_param,
318 static int lgdt330x_pll_rf_set(struct dvb_frontend* fe, int index)
320 struct cx8802_dev *dev= fe->dvb->priv;
321 struct cx88_core *core = dev->core;
323 dprintk(1, "%s: index = %d\n", __FUNCTION__, index);
325 cx_clear(MO_GP0_IO, 8);
327 cx_set(MO_GP0_IO, 8);
331 static int lgdt330x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
333 struct cx8802_dev *dev= fe->dvb->priv;
335 dev->ts_gen_cntrl |= 0x04;
337 dev->ts_gen_cntrl &= ~0x04;
341 static struct lgdt330x_config fusionhdtv_3_gold = {
342 .demod_address = 0x0e,
343 .demod_chip = LGDT3302,
344 .serial_mpeg = 0x04, /* TPSERIAL for 3302 in TOP_CONTROL */
345 .set_ts_params = lgdt330x_set_ts_param,
348 static struct lgdt330x_config fusionhdtv_5_gold = {
349 .demod_address = 0x0e,
350 .demod_chip = LGDT3303,
351 .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
352 .set_ts_params = lgdt330x_set_ts_param,
355 static struct lgdt330x_config pchdtv_hd5500 = {
356 .demod_address = 0x59,
357 .demod_chip = LGDT3303,
358 .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
359 .set_ts_params = lgdt330x_set_ts_param,
362 static int nxt200x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
364 struct cx8802_dev *dev= fe->dvb->priv;
365 dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
369 static int nxt200x_set_pll_input(u8* buf, int input)
378 static struct nxt200x_config ati_hdtvwonder = {
379 .demod_address = 0x0a,
380 .set_pll_input = nxt200x_set_pll_input,
381 .set_ts_params = nxt200x_set_ts_param,
384 static int cx24123_set_ts_param(struct dvb_frontend* fe,
387 struct cx8802_dev *dev= fe->dvb->priv;
388 dev->ts_gen_cntrl = 0x02;
392 static int kworld_dvbs_100_set_voltage(struct dvb_frontend* fe,
393 fe_sec_voltage_t voltage)
395 struct cx8802_dev *dev= fe->dvb->priv;
396 struct cx88_core *core = dev->core;
398 if (voltage == SEC_VOLTAGE_OFF)
399 cx_write(MO_GP0_IO, 0x000006fb);
401 cx_write(MO_GP0_IO, 0x000006f9);
403 if (core->prev_set_voltage)
404 return core->prev_set_voltage(fe, voltage);
408 static int geniatech_dvbs_set_voltage(struct dvb_frontend *fe,
409 fe_sec_voltage_t voltage)
411 struct cx8802_dev *dev= fe->dvb->priv;
412 struct cx88_core *core = dev->core;
414 if (voltage == SEC_VOLTAGE_OFF) {
415 dprintk(1,"LNB Voltage OFF\n");
416 cx_write(MO_GP0_IO, 0x0000efff);
419 if (core->prev_set_voltage)
420 return core->prev_set_voltage(fe, voltage);
424 static struct cx24123_config geniatech_dvbs_config = {
425 .demod_address = 0x55,
426 .set_ts_params = cx24123_set_ts_param,
429 static struct cx24123_config hauppauge_novas_config = {
430 .demod_address = 0x55,
431 .set_ts_params = cx24123_set_ts_param,
434 static struct cx24123_config kworld_dvbs_100_config = {
435 .demod_address = 0x15,
436 .set_ts_params = cx24123_set_ts_param,
440 static int dvb_register(struct cx8802_dev *dev)
442 /* init struct videobuf_dvb */
443 dev->dvb.name = dev->core->name;
444 dev->ts_gen_cntrl = 0x0c;
447 switch (dev->core->board) {
448 case CX88_BOARD_HAUPPAUGE_DVB_T1:
449 dev->dvb.frontend = dvb_attach(cx22702_attach,
450 &connexant_refboard_config,
451 &dev->core->i2c_adap);
452 if (dev->dvb.frontend != NULL) {
453 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
454 &dev->core->i2c_adap,
455 &dvb_pll_thomson_dtt759x);
458 case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1:
459 case CX88_BOARD_CONEXANT_DVB_T1:
460 case CX88_BOARD_KWORLD_DVB_T_CX22702:
461 case CX88_BOARD_WINFAST_DTV1000:
462 dev->dvb.frontend = dvb_attach(cx22702_attach,
463 &connexant_refboard_config,
464 &dev->core->i2c_adap);
465 if (dev->dvb.frontend != NULL) {
466 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
467 &dev->core->i2c_adap,
468 &dvb_pll_thomson_dtt7579);
471 case CX88_BOARD_WINFAST_DTV2000H:
472 case CX88_BOARD_HAUPPAUGE_HVR1100:
473 case CX88_BOARD_HAUPPAUGE_HVR1100LP:
474 case CX88_BOARD_HAUPPAUGE_HVR1300:
475 case CX88_BOARD_HAUPPAUGE_HVR3000:
476 dev->dvb.frontend = dvb_attach(cx22702_attach,
477 &hauppauge_hvr_config,
478 &dev->core->i2c_adap);
479 if (dev->dvb.frontend != NULL) {
480 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
481 &dev->core->i2c_adap, &dvb_pll_fmd1216me);
484 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS:
485 dev->dvb.frontend = dvb_attach(mt352_attach,
487 &dev->core->i2c_adap);
488 if (dev->dvb.frontend != NULL) {
489 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
490 NULL, &dvb_pll_thomson_dtt7579);
493 /* ZL10353 replaces MT352 on later cards */
494 dev->dvb.frontend = dvb_attach(zl10353_attach,
495 &dvico_fusionhdtv_plus_v1_1,
496 &dev->core->i2c_adap);
497 if (dev->dvb.frontend != NULL) {
498 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
499 NULL, &dvb_pll_thomson_dtt7579);
502 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL:
503 /* The tin box says DEE1601, but it seems to be DTT7579
504 * compatible, with a slightly different MT352 AGC gain. */
505 dev->dvb.frontend = dvb_attach(mt352_attach,
506 &dvico_fusionhdtv_dual,
507 &dev->core->i2c_adap);
508 if (dev->dvb.frontend != NULL) {
509 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
510 NULL, &dvb_pll_thomson_dtt7579);
513 /* ZL10353 replaces MT352 on later cards */
514 dev->dvb.frontend = dvb_attach(zl10353_attach,
515 &dvico_fusionhdtv_plus_v1_1,
516 &dev->core->i2c_adap);
517 if (dev->dvb.frontend != NULL) {
518 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
519 NULL, &dvb_pll_thomson_dtt7579);
522 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1:
523 dev->dvb.frontend = dvb_attach(mt352_attach,
525 &dev->core->i2c_adap);
526 if (dev->dvb.frontend != NULL) {
527 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
528 NULL, &dvb_pll_lg_z201);
531 case CX88_BOARD_KWORLD_DVB_T:
532 case CX88_BOARD_DNTV_LIVE_DVB_T:
533 case CX88_BOARD_ADSTECH_DVB_T_PCI:
534 dev->dvb.frontend = dvb_attach(mt352_attach,
535 &dntv_live_dvbt_config,
536 &dev->core->i2c_adap);
537 if (dev->dvb.frontend != NULL) {
538 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
539 NULL, &dvb_pll_unknown_1);
542 case CX88_BOARD_DNTV_LIVE_DVB_T_PRO:
543 #if defined(CONFIG_VIDEO_CX88_VP3054) || (defined(CONFIG_VIDEO_CX88_VP3054_MODULE) && defined(MODULE))
544 dev->core->pll_addr = 0x61;
545 dev->core->pll_desc = &dvb_pll_fmd1216me;
546 dev->dvb.frontend = dvb_attach(mt352_attach, &dntv_live_dvbt_pro_config,
547 &((struct vp3054_i2c_state *)dev->card_priv)->adap);
548 if (dev->dvb.frontend != NULL) {
549 dev->dvb.frontend->ops.tuner_ops.set_params = dntv_live_dvbt_pro_tuner_set_params;
552 printk("%s: built without vp3054 support\n", dev->core->name);
555 case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID:
556 dev->dvb.frontend = dvb_attach(zl10353_attach,
557 &dvico_fusionhdtv_hybrid,
558 &dev->core->i2c_adap);
559 if (dev->dvb.frontend != NULL) {
560 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
561 &dev->core->i2c_adap,
562 &dvb_pll_thomson_fe6600);
565 case CX88_BOARD_PCHDTV_HD3000:
566 dev->dvb.frontend = dvb_attach(or51132_attach, &pchdtv_hd3000,
567 &dev->core->i2c_adap);
568 if (dev->dvb.frontend != NULL) {
569 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
570 &dev->core->i2c_adap,
571 &dvb_pll_thomson_dtt761x);
574 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:
575 dev->ts_gen_cntrl = 0x08;
577 /* Do a hardware reset of chip before using it. */
578 struct cx88_core *core = dev->core;
580 cx_clear(MO_GP0_IO, 1);
582 cx_set(MO_GP0_IO, 1);
585 /* Select RF connector callback */
586 fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set;
587 dev->dvb.frontend = dvb_attach(lgdt330x_attach,
589 &dev->core->i2c_adap);
590 if (dev->dvb.frontend != NULL) {
591 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
592 &dev->core->i2c_adap,
593 &dvb_pll_microtune_4042);
597 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T:
598 dev->ts_gen_cntrl = 0x08;
600 /* Do a hardware reset of chip before using it. */
601 struct cx88_core *core = dev->core;
603 cx_clear(MO_GP0_IO, 1);
605 cx_set(MO_GP0_IO, 9);
607 dev->dvb.frontend = dvb_attach(lgdt330x_attach,
609 &dev->core->i2c_adap);
610 if (dev->dvb.frontend != NULL) {
611 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
612 &dev->core->i2c_adap,
613 &dvb_pll_thomson_dtt761x);
617 case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
618 dev->ts_gen_cntrl = 0x08;
620 /* Do a hardware reset of chip before using it. */
621 struct cx88_core *core = dev->core;
623 cx_clear(MO_GP0_IO, 1);
625 cx_set(MO_GP0_IO, 1);
627 dev->dvb.frontend = dvb_attach(lgdt330x_attach,
629 &dev->core->i2c_adap);
630 if (dev->dvb.frontend != NULL) {
631 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
632 &dev->core->i2c_adap,
633 &dvb_pll_lg_tdvs_h06xf);
637 case CX88_BOARD_PCHDTV_HD5500:
638 dev->ts_gen_cntrl = 0x08;
640 /* Do a hardware reset of chip before using it. */
641 struct cx88_core *core = dev->core;
643 cx_clear(MO_GP0_IO, 1);
645 cx_set(MO_GP0_IO, 1);
647 dev->dvb.frontend = dvb_attach(lgdt330x_attach,
649 &dev->core->i2c_adap);
650 if (dev->dvb.frontend != NULL) {
651 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
652 &dev->core->i2c_adap,
653 &dvb_pll_lg_tdvs_h06xf);
657 case CX88_BOARD_ATI_HDTVWONDER:
658 dev->dvb.frontend = dvb_attach(nxt200x_attach,
660 &dev->core->i2c_adap);
661 if (dev->dvb.frontend != NULL) {
662 dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
663 NULL, &dvb_pll_tuv1236d);
666 case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1:
667 case CX88_BOARD_HAUPPAUGE_NOVASE2_S1:
668 dev->dvb.frontend = dvb_attach(cx24123_attach,
669 &hauppauge_novas_config,
670 &dev->core->i2c_adap);
671 if (dev->dvb.frontend) {
672 dvb_attach(isl6421_attach, dev->dvb.frontend,
673 &dev->core->i2c_adap, 0x08, 0x00, 0x00);
676 case CX88_BOARD_KWORLD_DVBS_100:
677 dev->dvb.frontend = dvb_attach(cx24123_attach,
678 &kworld_dvbs_100_config,
679 &dev->core->i2c_adap);
680 if (dev->dvb.frontend) {
681 dev->core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage;
682 dev->dvb.frontend->ops.set_voltage = kworld_dvbs_100_set_voltage;
685 case CX88_BOARD_GENIATECH_DVBS:
686 dev->dvb.frontend = dvb_attach(cx24123_attach,
687 &geniatech_dvbs_config,
688 &dev->core->i2c_adap);
689 if (dev->dvb.frontend) {
690 dev->core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage;
691 dev->dvb.frontend->ops.set_voltage = geniatech_dvbs_set_voltage;
695 printk("%s: The frontend of your DVB/ATSC card isn't supported yet\n",
699 if (NULL == dev->dvb.frontend) {
700 printk("%s: frontend initialization failed\n",dev->core->name);
704 if (dev->core->pll_desc) {
705 dev->dvb.frontend->ops.info.frequency_min = dev->core->pll_desc->min;
706 dev->dvb.frontend->ops.info.frequency_max = dev->core->pll_desc->max;
708 /* Ensure all frontends negotiate bus access */
709 dev->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl;
711 /* Put the analog decoder in standby to keep it quiet */
712 cx88_call_i2c_clients (dev->core, TUNER_SET_STANDBY, NULL);
714 /* register everything */
715 return videobuf_dvb_register(&dev->dvb, THIS_MODULE, dev, &dev->pci->dev);
718 /* ----------------------------------------------------------- */
720 /* CX8802 MPEG -> mini driver - We have been given the hardware */
721 static int cx8802_dvb_advise_acquire(struct cx8802_driver *drv)
723 struct cx88_core *core = drv->core;
725 dprintk( 1, "%s\n", __FUNCTION__);
727 switch (core->board) {
728 case CX88_BOARD_HAUPPAUGE_HVR1300:
729 /* We arrive here with either the cx23416 or the cx22702
730 * on the bus. Take the bus from the cx23416 and enable the
733 cx_set(MO_GP0_IO, 0x00000080); /* cx22702 out of reset and enable */
734 cx_clear(MO_GP0_IO, 0x00000004);
743 /* CX8802 MPEG -> mini driver - We no longer have the hardware */
744 static int cx8802_dvb_advise_release(struct cx8802_driver *drv)
746 struct cx88_core *core = drv->core;
748 dprintk( 1, "%s\n", __FUNCTION__);
750 switch (core->board) {
751 case CX88_BOARD_HAUPPAUGE_HVR1300:
752 /* Do Nothing, leave the cx22702 on the bus. */
760 static int cx8802_dvb_probe(struct cx8802_driver *drv)
762 struct cx88_core *core = drv->core;
763 struct cx8802_dev *dev = drv->core->dvbdev;
766 dprintk( 1, "%s\n", __FUNCTION__);
767 dprintk( 1, " ->being probed by Card=%d Name=%s, PCI %02x:%02x\n",
774 if (!(cx88_boards[core->board].mpeg & CX88_MPEG_DVB))
777 /* If vp3054 isn't enabled, a stub will just return 0 */
778 err = vp3054_i2c_probe(dev);
783 printk("%s/2: cx2388x based dvb card\n", core->name);
784 videobuf_queue_init(&dev->dvb.dvbq, &dvb_qops,
785 dev->pci, &dev->slock,
786 V4L2_BUF_TYPE_VIDEO_CAPTURE,
788 sizeof(struct cx88_buffer),
790 err = dvb_register(dev);
792 printk("%s dvb_register failed err = %d\n", __FUNCTION__, err);
798 static int cx8802_dvb_remove(struct cx8802_driver *drv)
800 struct cx8802_dev *dev = drv->core->dvbdev;
803 videobuf_dvb_unregister(&dev->dvb);
805 vp3054_i2c_remove(dev);
810 static struct cx8802_driver cx8802_dvb_driver = {
811 .type_id = CX88_MPEG_DVB,
812 .hw_access = CX8802_DRVCTL_SHARED,
813 .probe = cx8802_dvb_probe,
814 .remove = cx8802_dvb_remove,
815 .advise_acquire = cx8802_dvb_advise_acquire,
816 .advise_release = cx8802_dvb_advise_release,
819 static int dvb_init(void)
821 printk(KERN_INFO "cx2388x dvb driver version %d.%d.%d loaded\n",
822 (CX88_VERSION_CODE >> 16) & 0xff,
823 (CX88_VERSION_CODE >> 8) & 0xff,
824 CX88_VERSION_CODE & 0xff);
826 printk(KERN_INFO "cx2388x: snapshot date %04d-%02d-%02d\n",
827 SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
829 return cx8802_register_driver(&cx8802_dvb_driver);
832 static void dvb_fini(void)
834 cx8802_unregister_driver(&cx8802_dvb_driver);
837 module_init(dvb_init);
838 module_exit(dvb_fini);
843 * compile-command: "make DVB=1"