SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/media/video/cx23885/cx23885-core.c

   1 /*
   2  *  Driver for the Conexant CX23885 PCIe bridge
   3  *
   4  *  Copyright (c) 2006 Steven Toth <stoth@hauppauge.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/kmod.h>
  27 #include <linux/kernel.h>
  28 #include <linux/slab.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31 #include <asm/div64.h>
  32
  33 #include "cx23885.h"
  34
  35 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
  36 MODULE_AUTHOR("Steven Toth <stoth@hauppauge.com>");
  37 MODULE_LICENSE("GPL");
  38
  39 static unsigned int debug;
  40 module_param(debug,int,0644);
  41 MODULE_PARM_DESC(debug,"enable debug messages");
  42
  43 static unsigned int card[]  = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
  44 module_param_array(card,  int, NULL, 0444);
  45 MODULE_PARM_DESC(card,"card type");
  46
  47 #define dprintk(level, fmt, arg...)\
  48         do { if (debug >= level)\
  49                 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  50         } while (0)
  51
  52 static unsigned int cx23885_devcount;
  53
  54 static DEFINE_MUTEX(devlist);
  55 LIST_HEAD(cx23885_devlist);
  56
  57 #define NO_SYNC_LINE (-1U)
  58
  59 /* FIXME, these allocations will change when
  60  * analog arrives. The be reviewed.
  61  * CX23887 Assumptions
  62  * 1 line = 16 bytes of CDT
  63  * cmds size = 80
  64  * cdt size = 16 * linesize
  65  * iqsize = 64
  66  * maxlines = 6
  67  *
  68  * Address Space:
  69  * 0x00000000 0x00008fff FIFO clusters
  70  * 0x00010000 0x000104af Channel Management Data Structures
  71  * 0x000104b0 0x000104ff Free
  72  * 0x00010500 0x000108bf 15 channels * iqsize
  73  * 0x000108c0 0x000108ff Free
  74  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
  75  *                       15 channels * (iqsize + (maxlines * linesize))
  76  * 0x00010ea0 0x00010xxx Free
  77  */
  78
  79 static struct sram_channel cx23887_sram_channels[] = {
  80         [SRAM_CH01] = {
  81                 .name           = "VID A",
  82                 .cmds_start     = 0x10000,
  83                 .ctrl_start     = 0x105b0,
  84                 .cdt            = 0x107b0,
  85                 .fifo_start     = 0x40,
  86                 .fifo_size      = 0x2800,
  87                 .ptr1_reg       = DMA1_PTR1,
  88                 .ptr2_reg       = DMA1_PTR2,
  89                 .cnt1_reg       = DMA1_CNT1,
  90                 .cnt2_reg       = DMA1_CNT2,
  91         },
  92         [SRAM_CH02] = {
  93                 .name           = "ch2",
  94                 .cmds_start     = 0x0,
  95                 .ctrl_start     = 0x0,
  96                 .cdt            = 0x0,
  97                 .fifo_start     = 0x0,
  98                 .fifo_size      = 0x0,
  99                 .ptr1_reg       = DMA2_PTR1,
 100                 .ptr2_reg       = DMA2_PTR2,
 101                 .cnt1_reg       = DMA2_CNT1,
 102                 .cnt2_reg       = DMA2_CNT2,
 103         },
 104         [SRAM_CH03] = {
 105                 .name           = "TS1 B",
 106                 .cmds_start     = 0x100A0,
 107                 .ctrl_start     = 0x10780,
 108                 .cdt            = 0x10400,
 109                 .fifo_start     = 0x5000,
 110                 .fifo_size      = 0x1000,
 111                 .ptr1_reg       = DMA3_PTR1,
 112                 .ptr2_reg       = DMA3_PTR2,
 113                 .cnt1_reg       = DMA3_CNT1,
 114                 .cnt2_reg       = DMA3_CNT2,
 115         },
 116         [SRAM_CH04] = {
 117                 .name           = "ch4",
 118                 .cmds_start     = 0x0,
 119                 .ctrl_start     = 0x0,
 120                 .cdt            = 0x0,
 121                 .fifo_start     = 0x0,
 122                 .fifo_size      = 0x0,
 123                 .ptr1_reg       = DMA4_PTR1,
 124                 .ptr2_reg       = DMA4_PTR2,
 125                 .cnt1_reg       = DMA4_CNT1,
 126                 .cnt2_reg       = DMA4_CNT2,
 127         },
 128         [SRAM_CH05] = {
 129                 .name           = "ch5",
 130                 .cmds_start     = 0x0,
 131                 .ctrl_start     = 0x0,
 132                 .cdt            = 0x0,
 133                 .fifo_start     = 0x0,
 134                 .fifo_size      = 0x0,
 135                 .ptr1_reg       = DMA5_PTR1,
 136                 .ptr2_reg       = DMA5_PTR2,
 137                 .cnt1_reg       = DMA5_CNT1,
 138                 .cnt2_reg       = DMA5_CNT2,
 139         },
 140         [SRAM_CH06] = {
 141                 .name           = "TS2 C",
 142                 .cmds_start     = 0x10140,
 143                 .ctrl_start     = 0x10680,
 144                 .cdt            = 0x108d0,
 145                 .fifo_start     = 0x6000,
 146                 .fifo_size      = 0x1000,
 147                 .ptr1_reg       = DMA5_PTR1,
 148                 .ptr2_reg       = DMA5_PTR2,
 149                 .cnt1_reg       = DMA5_CNT1,
 150                 .cnt2_reg       = DMA5_CNT2,
 151         },
 152         [SRAM_CH07] = {
 153                 .name           = "ch7",
 154                 .cmds_start     = 0x0,
 155                 .ctrl_start     = 0x0,
 156                 .cdt            = 0x0,
 157                 .fifo_start     = 0x0,
 158                 .fifo_size      = 0x0,
 159                 .ptr1_reg       = DMA6_PTR1,
 160                 .ptr2_reg       = DMA6_PTR2,
 161                 .cnt1_reg       = DMA6_CNT1,
 162                 .cnt2_reg       = DMA6_CNT2,
 163         },
 164         [SRAM_CH08] = {
 165                 .name           = "ch8",
 166                 .cmds_start     = 0x0,
 167                 .ctrl_start     = 0x0,
 168                 .cdt            = 0x0,
 169                 .fifo_start     = 0x0,
 170                 .fifo_size      = 0x0,
 171                 .ptr1_reg       = DMA7_PTR1,
 172                 .ptr2_reg       = DMA7_PTR2,
 173                 .cnt1_reg       = DMA7_CNT1,
 174                 .cnt2_reg       = DMA7_CNT2,
 175         },
 176         [SRAM_CH09] = {
 177                 .name           = "ch9",
 178                 .cmds_start     = 0x0,
 179                 .ctrl_start     = 0x0,
 180                 .cdt            = 0x0,
 181                 .fifo_start     = 0x0,
 182                 .fifo_size      = 0x0,
 183                 .ptr1_reg       = DMA8_PTR1,
 184                 .ptr2_reg       = DMA8_PTR2,
 185                 .cnt1_reg       = DMA8_CNT1,
 186                 .cnt2_reg       = DMA8_CNT2,
 187         },
 188 };
 189
 190 static int cx23885_risc_decode(u32 risc)
 191 {
 192         static char *instr[16] = {
 193                 [ RISC_SYNC    >> 28 ] = "sync",
 194                 [ RISC_WRITE   >> 28 ] = "write",
 195                 [ RISC_WRITEC  >> 28 ] = "writec",
 196                 [ RISC_READ    >> 28 ] = "read",
 197                 [ RISC_READC   >> 28 ] = "readc",
 198                 [ RISC_JUMP    >> 28 ] = "jump",
 199                 [ RISC_SKIP    >> 28 ] = "skip",
 200                 [ RISC_WRITERM >> 28 ] = "writerm",
 201                 [ RISC_WRITECM >> 28 ] = "writecm",
 202                 [ RISC_WRITECR >> 28 ] = "writecr",
 203         };
 204         static int incr[16] = {
 205                 [ RISC_WRITE   >> 28 ] = 3,
 206                 [ RISC_JUMP    >> 28 ] = 3,
 207                 [ RISC_SKIP    >> 28 ] = 1,
 208                 [ RISC_SYNC    >> 28 ] = 1,
 209                 [ RISC_WRITERM >> 28 ] = 3,
 210                 [ RISC_WRITECM >> 28 ] = 3,
 211                 [ RISC_WRITECR >> 28 ] = 4,
 212         };
 213         static char *bits[] = {
 214                 "12",   "13",   "14",   "resync",
 215                 "cnt0", "cnt1", "18",   "19",
 216                 "20",   "21",   "22",   "23",
 217                 "irq1", "irq2", "eol",  "sol",
 218         };
 219         int i;
 220
 221         printk("0x%08x [ %s", risc,
 222                instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
 223         for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
 224                 if (risc & (1 << (i + 12)))
 225                         printk(" %s", bits[i]);
 226         printk(" count=%d ]\n", risc & 0xfff);
 227         return incr[risc >> 28] ? incr[risc >> 28] : 1;
 228 }
 229
 230 void cx23885_wakeup(struct cx23885_tsport *port,
 231                            struct cx23885_dmaqueue *q, u32 count)
 232 {
 233         struct cx23885_dev *dev = port->dev;
 234         struct cx23885_buffer *buf;
 235         int bc;
 236
 237         for (bc = 0;; bc++) {
 238                 if (list_empty(&q->active))
 239                         break;
 240                 buf = list_entry(q->active.next,
 241                                  struct cx23885_buffer, vb.queue);
 242
 243                 /* count comes from the hw and is is 16bit wide --
 244                  * this trick handles wrap-arounds correctly for
 245                  * up to 32767 buffers in flight... */
 246                 if ((s16) (count - buf->count) < 0)
 247                         break;
 248
 249                 do_gettimeofday(&buf->vb.ts);
 250                 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
 251                         count, buf->count);
 252                 buf->vb.state = VIDEOBUF_DONE;
 253                 list_del(&buf->vb.queue);
 254                 wake_up(&buf->vb.done);
 255         }
 256         if (list_empty(&q->active)) {
 257                 del_timer(&q->timeout);
 258         } else {
 259                 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
 260         }
 261         if (bc != 1)
 262                 printk("%s: %d buffers handled (should be 1)\n",
 263                        __func__, bc);
 264 }
 265
 266 int cx23885_sram_channel_setup(struct cx23885_dev *dev,
 267                                       struct sram_channel *ch,
 268                                       unsigned int bpl, u32 risc)
 269 {
 270         unsigned int i, lines;
 271         u32 cdt;
 272
 273         if (ch->cmds_start == 0)
 274         {
 275                 dprintk(1, "%s() Erasing channel [%s]\n", __func__,
 276                         ch->name);
 277                 cx_write(ch->ptr1_reg, 0);
 278                 cx_write(ch->ptr2_reg, 0);
 279                 cx_write(ch->cnt2_reg, 0);
 280                 cx_write(ch->cnt1_reg, 0);
 281                 return 0;
 282         } else {
 283                 dprintk(1, "%s() Configuring channel [%s]\n", __func__,
 284                         ch->name);
 285         }
 286
 287         bpl   = (bpl + 7) & ~7; /* alignment */
 288         cdt   = ch->cdt;
 289         lines = ch->fifo_size / bpl;
 290         if (lines > 6)
 291                 lines = 6;
 292         BUG_ON(lines < 2);
 293
 294         cx_write(8 + 0, cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC) );
 295         cx_write(8 + 4, cpu_to_le32(8) );
 296         cx_write(8 + 8, cpu_to_le32(0) );
 297
 298         /* write CDT */
 299         for (i = 0; i < lines; i++) {
 300                 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __func__, cdt + 16*i,
 301                         ch->fifo_start + bpl*i);
 302                 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
 303                 cx_write(cdt + 16*i +  4, 0);
 304                 cx_write(cdt + 16*i +  8, 0);
 305                 cx_write(cdt + 16*i + 12, 0);
 306         }
 307
 308         /* write CMDS */
 309         if (ch->jumponly)
 310                 cx_write(ch->cmds_start +  0, 8);
 311         else
 312                 cx_write(ch->cmds_start +  0, risc);
 313         cx_write(ch->cmds_start +  4, 0); /* 64 bits 63-32 */
 314         cx_write(ch->cmds_start +  8, cdt);
 315         cx_write(ch->cmds_start + 12, (lines*16) >> 3);
 316         cx_write(ch->cmds_start + 16, ch->ctrl_start);
 317         if (ch->jumponly)
 318                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2) );
 319         else
 320                 cx_write(ch->cmds_start + 20, 64 >> 2);
 321         for (i = 24; i < 80; i += 4)
 322                 cx_write(ch->cmds_start + i, 0);
 323
 324         /* fill registers */
 325         cx_write(ch->ptr1_reg, ch->fifo_start);
 326         cx_write(ch->ptr2_reg, cdt);
 327         cx_write(ch->cnt2_reg, (lines*16) >> 3);
 328         cx_write(ch->cnt1_reg, (bpl >> 3) -1);
 329
 330         dprintk(2,"[bridge %d] sram setup %s: bpl=%d lines=%d\n",
 331                 dev->bridge,
 332                 ch->name,
 333                 bpl,
 334                 lines);
 335
 336         return 0;
 337 }
 338
 339 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 340                                       struct sram_channel *ch)
 341 {
 342         static char *name[] = {
 343                 "init risc lo",
 344                 "init risc hi",
 345                 "cdt base",
 346                 "cdt size",
 347                 "iq base",
 348                 "iq size",
 349                 "risc pc lo",
 350                 "risc pc hi",
 351                 "iq wr ptr",
 352                 "iq rd ptr",
 353                 "cdt current",
 354                 "pci target lo",
 355                 "pci target hi",
 356                 "line / byte",
 357         };
 358         u32 risc;
 359         unsigned int i, j, n;
 360
 361         printk("%s: %s - dma channel status dump\n",
 362                dev->name, ch->name);
 363         for (i = 0; i < ARRAY_SIZE(name); i++)
 364                 printk("%s:   cmds: %-15s: 0x%08x\n",
 365                        dev->name, name[i],
 366                        cx_read(ch->cmds_start + 4*i));
 367
 368         for (i = 0; i < 4; i++) {
 369                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
 370                 printk("%s:   risc%d: ", dev->name, i);
 371                 cx23885_risc_decode(risc);
 372         }
 373         for (i = 0; i < (64 >> 2); i += n) {
 374                 risc = cx_read(ch->ctrl_start + 4 * i);
 375                 /* No consideration for bits 63-32 */
 376
 377                 printk("%s:   (0x%08x) iq %x: ", dev->name,
 378                        ch->ctrl_start + 4 * i, i);
 379                 n = cx23885_risc_decode(risc);
 380                 for (j = 1; j < n; j++) {
 381                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
 382                         printk("%s:   iq %x: 0x%08x [ arg #%d ]\n",
 383                                dev->name, i+j, risc, j);
 384                 }
 385         }
 386
 387         printk("%s: fifo: 0x%08x -> 0x%x\n",
 388                dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
 389         printk("%s: ctrl: 0x%08x -> 0x%x\n",
 390                dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
 391         printk("%s:   ptr1_reg: 0x%08x\n",
 392                dev->name, cx_read(ch->ptr1_reg));
 393         printk("%s:   ptr2_reg: 0x%08x\n",
 394                dev->name, cx_read(ch->ptr2_reg));
 395         printk("%s:   cnt1_reg: 0x%08x\n",
 396                dev->name, cx_read(ch->cnt1_reg));
 397         printk("%s:   cnt2_reg: 0x%08x\n",
 398                dev->name, cx_read(ch->cnt2_reg));
 399 }
 400
 401 static void cx23885_risc_disasm(struct cx23885_tsport *port,
 402                                 struct btcx_riscmem *risc)
 403 {
 404         struct cx23885_dev *dev = port->dev;
 405         unsigned int i, j, n;
 406
 407         printk("%s: risc disasm: %p [dma=0x%08lx]\n",
 408                dev->name, risc->cpu, (unsigned long)risc->dma);
 409         for (i = 0; i < (risc->size >> 2); i += n) {
 410                 printk("%s:   %04d: ", dev->name, i);
 411                 n = cx23885_risc_decode(risc->cpu[i]);
 412                 for (j = 1; j < n; j++)
 413                         printk("%s:   %04d: 0x%08x [ arg #%d ]\n",
 414                                dev->name, i + j, risc->cpu[i + j], j);
 415                 if (risc->cpu[i] == RISC_JUMP)
 416                         break;
 417         }
 418 }
 419
 420 static void cx23885_shutdown(struct cx23885_dev *dev)
 421 {
 422         /* disable RISC controller */
 423         cx_write(DEV_CNTRL2, 0);
 424
 425         /* Disable all IR activity */
 426         cx_write(IR_CNTRL_REG, 0);
 427
 428         /* Disable Video A/B activity */
 429         cx_write(VID_A_DMA_CTL, 0);
 430         cx_write(VID_B_DMA_CTL, 0);
 431         cx_write(VID_C_DMA_CTL, 0);
 432
 433         /* Disable Audio activity */
 434         cx_write(AUD_INT_DMA_CTL, 0);
 435         cx_write(AUD_EXT_DMA_CTL, 0);
 436
 437         /* Disable Serial port */
 438         cx_write(UART_CTL, 0);
 439
 440         /* Disable Interrupts */
 441         cx_write(PCI_INT_MSK, 0);
 442         cx_write(VID_A_INT_MSK, 0);
 443         cx_write(VID_B_INT_MSK, 0);
 444         cx_write(VID_C_INT_MSK, 0);
 445         cx_write(AUDIO_INT_INT_MSK, 0);
 446         cx_write(AUDIO_EXT_INT_MSK, 0);
 447
 448 }
 449
 450 static void cx23885_reset(struct cx23885_dev *dev)
 451 {
 452         dprintk(1, "%s()\n", __func__);
 453
 454         cx23885_shutdown(dev);
 455
 456         cx_write(PCI_INT_STAT, 0xffffffff);
 457         cx_write(VID_A_INT_STAT, 0xffffffff);
 458         cx_write(VID_B_INT_STAT, 0xffffffff);
 459         cx_write(VID_C_INT_STAT, 0xffffffff);
 460         cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
 461         cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
 462         cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
 463
 464         mdelay(100);
 465
 466         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
 467                 720*4, 0);
 468         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0);
 469         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03],
 470                 188*4, 0);
 471         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0);
 472         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0);
 473         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06],
 474                 188*4, 0);
 475         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0);
 476         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0);
 477         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
 478
 479         cx23885_gpio_setup(dev);
 480 }
 481
 482
 483 static int cx23885_pci_quirks(struct cx23885_dev *dev)
 484 {
 485         dprintk(1, "%s()\n", __func__);
 486
 487         /* The cx23885 bridge has a weird bug which causes NMI to be asserted
 488          * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
 489          * occur on the cx23887 bridge.
 490          */
 491         if(dev->bridge == CX23885_BRIDGE_885)
 492                 cx_clear(RDR_TLCTL0, 1 << 4);
 493
 494         return 0;
 495 }
 496
 497 static int get_resources(struct cx23885_dev *dev)
 498 {
 499         if (request_mem_region(pci_resource_start(dev->pci,0),
 500                                pci_resource_len(dev->pci,0),
 501                                dev->name))
 502                 return 0;
 503
 504         printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
 505                 dev->name, (unsigned long long)pci_resource_start(dev->pci,0));
 506
 507         return -EBUSY;
 508 }
 509
 510 static void cx23885_timeout(unsigned long data);
 511 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
 512                                 u32 reg, u32 mask, u32 value);
 513
 514 static int cx23885_init_tsport(struct cx23885_dev *dev, struct cx23885_tsport *port, int portno)
 515 {
 516         dprintk(1, "%s(portno=%d)\n", __func__, portno);
 517
 518         /* Transport bus init dma queue  - Common settings */
 519         port->dma_ctl_val        = 0x11; /* Enable RISC controller and Fifo */
 520         port->ts_int_msk_val     = 0x1111; /* TS port bits for RISC */
 521
 522         spin_lock_init(&port->slock);
 523         port->dev = dev;
 524         port->nr = portno;
 525
 526         INIT_LIST_HEAD(&port->mpegq.active);
 527         INIT_LIST_HEAD(&port->mpegq.queued);
 528         port->mpegq.timeout.function = cx23885_timeout;
 529         port->mpegq.timeout.data = (unsigned long)port;
 530         init_timer(&port->mpegq.timeout);
 531
 532         switch(portno) {
 533         case 1:
 534                 port->reg_gpcnt          = VID_B_GPCNT;
 535                 port->reg_gpcnt_ctl      = VID_B_GPCNT_CTL;
 536                 port->reg_dma_ctl        = VID_B_DMA_CTL;
 537                 port->reg_lngth          = VID_B_LNGTH;
 538                 port->reg_hw_sop_ctrl    = VID_B_HW_SOP_CTL;
 539                 port->reg_gen_ctrl       = VID_B_GEN_CTL;
 540                 port->reg_bd_pkt_status  = VID_B_BD_PKT_STATUS;
 541                 port->reg_sop_status     = VID_B_SOP_STATUS;
 542                 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
 543                 port->reg_vld_misc       = VID_B_VLD_MISC;
 544                 port->reg_ts_clk_en      = VID_B_TS_CLK_EN;
 545                 port->reg_src_sel        = VID_B_SRC_SEL;
 546                 port->reg_ts_int_msk     = VID_B_INT_MSK;
 547                 port->reg_ts_int_stat   = VID_B_INT_STAT;
 548                 port->sram_chno          = SRAM_CH03; /* VID_B */
 549                 port->pci_irqmask        = 0x02; /* VID_B bit1 */
 550                 break;
 551         case 2:
 552                 port->reg_gpcnt          = VID_C_GPCNT;
 553                 port->reg_gpcnt_ctl      = VID_C_GPCNT_CTL;
 554                 port->reg_dma_ctl        = VID_C_DMA_CTL;
 555                 port->reg_lngth          = VID_C_LNGTH;
 556                 port->reg_hw_sop_ctrl    = VID_C_HW_SOP_CTL;
 557                 port->reg_gen_ctrl       = VID_C_GEN_CTL;
 558                 port->reg_bd_pkt_status  = VID_C_BD_PKT_STATUS;
 559                 port->reg_sop_status     = VID_C_SOP_STATUS;
 560                 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
 561                 port->reg_vld_misc       = VID_C_VLD_MISC;
 562                 port->reg_ts_clk_en      = VID_C_TS_CLK_EN;
 563                 port->reg_src_sel        = 0;
 564                 port->reg_ts_int_msk     = VID_C_INT_MSK;
 565                 port->reg_ts_int_stat    = VID_C_INT_STAT;
 566                 port->sram_chno          = SRAM_CH06; /* VID_C */
 567                 port->pci_irqmask        = 0x04; /* VID_C bit2 */
 568                 break;
 569         default:
 570                 BUG();
 571         }
 572
 573         cx23885_risc_stopper(dev->pci, &port->mpegq.stopper,
 574                      port->reg_dma_ctl, port->dma_ctl_val, 0x00);
 575
 576         return 0;
 577 }
 578
 579 static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
 580 {
 581         switch (cx_read(RDR_CFG2) & 0xff) {
 582         case 0x00:
 583                 /* cx23885 */
 584                 dev->hwrevision = 0xa0;
 585                 break;
 586         case 0x01:
 587                 /* CX23885-12Z */
 588                 dev->hwrevision = 0xa1;
 589                 break;
 590         case 0x02:
 591                 /* CX23885-13Z */
 592                 dev->hwrevision = 0xb0;
 593                 break;
 594         case 0x03:
 595                 /* CX23888-22Z */
 596                 dev->hwrevision = 0xc0;
 597                 break;
 598         case 0x0e:
 599                 /* CX23887-15Z */
 600                 dev->hwrevision = 0xc0;
 601         case 0x0f:
 602                 /* CX23887-14Z */
 603                 dev->hwrevision = 0xb1;
 604                 break;
 605         default:
 606                 printk(KERN_ERR "%s() New hardware revision found 0x%x\n",
 607                         __func__, dev->hwrevision);
 608         }
 609         if (dev->hwrevision)
 610                 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n",
 611                         __func__, dev->hwrevision);
 612         else
 613                 printk(KERN_ERR "%s() Hardware revision unknown 0x%x\n",
 614                         __func__, dev->hwrevision);
 615 }
 616
 617 static int cx23885_dev_setup(struct cx23885_dev *dev)
 618 {
 619         int i;
 620
 621         mutex_init(&dev->lock);
 622
 623         atomic_inc(&dev->refcount);
 624
 625         dev->nr = cx23885_devcount++;
 626         dev->sram_channels = cx23887_sram_channels;
 627         sprintf(dev->name, "cx23885[%d]", dev->nr);
 628
 629         mutex_lock(&devlist);
 630         list_add_tail(&dev->devlist, &cx23885_devlist);
 631         mutex_unlock(&devlist);
 632
 633         /* Configure the internal memory */
 634         if(dev->pci->device == 0x8880) {
 635                 dev->bridge = CX23885_BRIDGE_887;
 636                 /* Apply a sensible clock frequency for the PCIe bridge */
 637                 dev->clk_freq = 25000000;
 638         } else
 639         if(dev->pci->device == 0x8852) {
 640                 dev->bridge = CX23885_BRIDGE_885;
 641                 /* Apply a sensible clock frequency for the PCIe bridge */
 642                 dev->clk_freq = 28000000;
 643         } else
 644                 BUG();
 645
 646         dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
 647                 __func__, dev->bridge);
 648
 649         /* board config */
 650         dev->board = UNSET;
 651         if (card[dev->nr] < cx23885_bcount)
 652                 dev->board = card[dev->nr];
 653         for (i = 0; UNSET == dev->board  &&  i < cx23885_idcount; i++)
 654                 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
 655                     dev->pci->subsystem_device == cx23885_subids[i].subdevice)
 656                         dev->board = cx23885_subids[i].card;
 657         if (UNSET == dev->board) {
 658                 dev->board = CX23885_BOARD_UNKNOWN;
 659                 cx23885_card_list(dev);
 660         }
 661
 662         /* If the user specific a clk freq override, apply it */
 663         if (cx23885_boards[dev->board].clk_freq > 0)
 664                 dev->clk_freq = cx23885_boards[dev->board].clk_freq;
 665
 666         dev->pci_bus  = dev->pci->bus->number;
 667         dev->pci_slot = PCI_SLOT(dev->pci->devfn);
 668         dev->pci_irqmask = 0x001f00;
 669
 670         /* External Master 1 Bus */
 671         dev->i2c_bus[0].nr = 0;
 672         dev->i2c_bus[0].dev = dev;
 673         dev->i2c_bus[0].reg_stat  = I2C1_STAT;
 674         dev->i2c_bus[0].reg_ctrl  = I2C1_CTRL;
 675         dev->i2c_bus[0].reg_addr  = I2C1_ADDR;
 676         dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
 677         dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
 678         dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
 679
 680         /* External Master 2 Bus */
 681         dev->i2c_bus[1].nr = 1;
 682         dev->i2c_bus[1].dev = dev;
 683         dev->i2c_bus[1].reg_stat  = I2C2_STAT;
 684         dev->i2c_bus[1].reg_ctrl  = I2C2_CTRL;
 685         dev->i2c_bus[1].reg_addr  = I2C2_ADDR;
 686         dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
 687         dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
 688         dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
 689
 690         /* Internal Master 3 Bus */
 691         dev->i2c_bus[2].nr = 2;
 692         dev->i2c_bus[2].dev = dev;
 693         dev->i2c_bus[2].reg_stat  = I2C3_STAT;
 694         dev->i2c_bus[2].reg_ctrl  = I2C3_CTRL;
 695         dev->i2c_bus[2].reg_addr  = I2C3_ADDR;
 696         dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
 697         dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
 698         dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
 699
 700         if(cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
 701                 cx23885_init_tsport(dev, &dev->ts1, 1);
 702
 703         if(cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
 704                 cx23885_init_tsport(dev, &dev->ts2, 2);
 705
 706         if (get_resources(dev) < 0) {
 707                 printk(KERN_ERR "CORE %s No more PCIe resources for "
 708                        "subsystem: %04x:%04x\n",
 709                        dev->name, dev->pci->subsystem_vendor,
 710                        dev->pci->subsystem_device);
 711
 712                 cx23885_devcount--;
 713                 return -ENODEV;
 714         }
 715
 716         /* PCIe stuff */
 717         dev->lmmio = ioremap(pci_resource_start(dev->pci,0),
 718                              pci_resource_len(dev->pci,0));
 719
 720         dev->bmmio = (u8 __iomem *)dev->lmmio;
 721
 722         printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
 723                dev->name, dev->pci->subsystem_vendor,
 724                dev->pci->subsystem_device, cx23885_boards[dev->board].name,
 725                dev->board, card[dev->nr] == dev->board ?
 726                "insmod option" : "autodetected");
 727
 728         cx23885_pci_quirks(dev);
 729
 730         /* Assume some sensible defaults */
 731         dev->tuner_type = cx23885_boards[dev->board].tuner_type;
 732         dev->tuner_addr = cx23885_boards[dev->board].tuner_addr;
 733         dev->radio_type = cx23885_boards[dev->board].radio_type;
 734         dev->radio_addr = cx23885_boards[dev->board].radio_addr;
 735
 736         dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x\n",
 737                 __func__, dev->tuner_type, dev->tuner_addr);
 738         dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
 739                 __func__, dev->radio_type, dev->radio_addr);
 740
 741         /* init hardware */
 742         cx23885_reset(dev);
 743
 744         cx23885_i2c_register(&dev->i2c_bus[0]);
 745         cx23885_i2c_register(&dev->i2c_bus[1]);
 746         cx23885_i2c_register(&dev->i2c_bus[2]);
 747         cx23885_card_setup(dev);
 748         cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
 749         cx23885_ir_init(dev);
 750
 751         if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
 752                 if (cx23885_video_register(dev) < 0) {
 753                         printk(KERN_ERR "%s() Failed to register analog "
 754                                 "video adapters on VID_A\n", __func__);
 755                 }
 756         }
 757
 758         if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
 759                 if (cx23885_dvb_register(&dev->ts1) < 0) {
 760                         printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
 761                                __func__);
 762                 }
 763         }
 764
 765         if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
 766                 if (cx23885_dvb_register(&dev->ts2) < 0) {
 767                         printk(KERN_ERR "%s() Failed to register dvb adapters on VID_C\n",
 768                                __func__);
 769                 }
 770         }
 771
 772         cx23885_dev_checkrevision(dev);
 773
 774         return 0;
 775 }
 776
 777 static void cx23885_dev_unregister(struct cx23885_dev *dev)
 778 {
 779         release_mem_region(pci_resource_start(dev->pci,0),
 780                            pci_resource_len(dev->pci,0));
 781
 782         if (!atomic_dec_and_test(&dev->refcount))
 783                 return;
 784
 785         if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
 786                 cx23885_video_unregister(dev);
 787
 788         if(cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
 789                 cx23885_dvb_unregister(&dev->ts1);
 790
 791         if(cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
 792                 cx23885_dvb_unregister(&dev->ts2);
 793
 794         cx23885_i2c_unregister(&dev->i2c_bus[2]);
 795         cx23885_i2c_unregister(&dev->i2c_bus[1]);
 796         cx23885_i2c_unregister(&dev->i2c_bus[0]);
 797
 798         iounmap(dev->lmmio);
 799 }
 800
 801 static u32* cx23885_risc_field(u32 *rp, struct scatterlist *sglist,
 802                                unsigned int offset, u32 sync_line,
 803                                unsigned int bpl, unsigned int padding,
 804                                unsigned int lines)
 805 {
 806         struct scatterlist *sg;
 807         unsigned int line, todo;
 808
 809         /* sync instruction */
 810         if (sync_line != NO_SYNC_LINE)
 811                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
 812
 813         /* scan lines */
 814         sg = sglist;
 815         for (line = 0; line < lines; line++) {
 816                 while (offset && offset >= sg_dma_len(sg)) {
 817                         offset -= sg_dma_len(sg);
 818                         sg++;
 819                 }
 820                 if (bpl <= sg_dma_len(sg)-offset) {
 821                         /* fits into current chunk */
 822                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
 823                         *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
 824                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 825                         offset+=bpl;
 826                 } else {
 827                         /* scanline needs to be split */
 828                         todo = bpl;
 829                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|
 830                                             (sg_dma_len(sg)-offset));
 831                         *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
 832                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 833                         todo -= (sg_dma_len(sg)-offset);
 834                         offset = 0;
 835                         sg++;
 836                         while (todo > sg_dma_len(sg)) {
 837                                 *(rp++)=cpu_to_le32(RISC_WRITE|
 838                                                     sg_dma_len(sg));
 839                                 *(rp++)=cpu_to_le32(sg_dma_address(sg));
 840                                 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 841                                 todo -= sg_dma_len(sg);
 842                                 sg++;
 843                         }
 844                         *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
 845                         *(rp++)=cpu_to_le32(sg_dma_address(sg));
 846                         *(rp++)=cpu_to_le32(0); /* bits 63-32 */
 847                         offset += todo;
 848                 }
 849                 offset += padding;
 850         }
 851
 852         return rp;
 853 }
 854
 855 int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
 856                         struct scatterlist *sglist, unsigned int top_offset,
 857                         unsigned int bottom_offset, unsigned int bpl,
 858                         unsigned int padding, unsigned int lines)
 859 {
 860         u32 instructions, fields;
 861         u32 *rp;
 862         int rc;
 863
 864         fields = 0;
 865         if (UNSET != top_offset)
 866                 fields++;
 867         if (UNSET != bottom_offset)
 868                 fields++;
 869
 870         /* estimate risc mem: worst case is one write per page border +
 871            one write per scan line + syncs + jump (all 2 dwords).  Padding
 872            can cause next bpl to start close to a page border.  First DMA
 873            region may be smaller than PAGE_SIZE */
 874         /* write and jump need and extra dword */
 875         instructions  = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
 876         instructions += 2;
 877         if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
 878                 return rc;
 879
 880         /* write risc instructions */
 881         rp = risc->cpu;
 882         if (UNSET != top_offset)
 883                 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
 884                                         bpl, padding, lines);
 885         if (UNSET != bottom_offset)
 886                 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
 887                                         bpl, padding, lines);
 888
 889         /* save pointer to jmp instruction address */
 890         risc->jmp = rp;
 891         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
 892         return 0;
 893 }
 894
 895 static int cx23885_risc_databuffer(struct pci_dev *pci,
 896                                    struct btcx_riscmem *risc,
 897                                    struct scatterlist *sglist,
 898                                    unsigned int bpl,
 899                                    unsigned int lines)
 900 {
 901         u32 instructions;
 902         u32 *rp;
 903         int rc;
 904
 905         /* estimate risc mem: worst case is one write per page border +
 906            one write per scan line + syncs + jump (all 2 dwords).  Here
 907            there is no padding and no sync.  First DMA region may be smaller
 908            than PAGE_SIZE */
 909         /* Jump and write need an extra dword */
 910         instructions  = 1 + (bpl * lines) / PAGE_SIZE + lines;
 911         instructions += 1;
 912
 913         if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
 914                 return rc;
 915
 916         /* write risc instructions */
 917         rp = risc->cpu;
 918         rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
 919
 920         /* save pointer to jmp instruction address */
 921         risc->jmp = rp;
 922         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
 923         return 0;
 924 }
 925
 926 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
 927                                 u32 reg, u32 mask, u32 value)
 928 {
 929         u32 *rp;
 930         int rc;
 931
 932         if ((rc = btcx_riscmem_alloc(pci, risc, 4*16)) < 0)
 933                 return rc;
 934
 935         /* write risc instructions */
 936         rp = risc->cpu;
 937         *(rp++) = cpu_to_le32(RISC_WRITECR  | RISC_IRQ2);
 938         *(rp++) = cpu_to_le32(reg);
 939         *(rp++) = cpu_to_le32(value);
 940         *(rp++) = cpu_to_le32(mask);
 941         *(rp++) = cpu_to_le32(RISC_JUMP);
 942         *(rp++) = cpu_to_le32(risc->dma);
 943         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
 944         return 0;
 945 }
 946
 947 void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
 948 {
 949         struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
 950
 951         BUG_ON(in_interrupt());
 952         videobuf_waiton(&buf->vb, 0, 0);
 953         videobuf_dma_unmap(q, dma);
 954         videobuf_dma_free(dma);
 955         btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
 956         buf->vb.state = VIDEOBUF_NEEDS_INIT;
 957 }
 958
 959 static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
 960 {
 961         struct cx23885_dev *dev = port->dev;
 962
 963         dprintk(1, "%s() Register Dump\n", __func__);
 964         dprintk(1, "%s() DEV_CNTRL2               0x%08X\n", __func__,
 965                 cx_read(DEV_CNTRL2));
 966         dprintk(1, "%s() PCI_INT_MSK              0x%08X\n", __func__,
 967                 cx_read(PCI_INT_MSK));
 968         dprintk(1, "%s() AUD_INT_INT_MSK          0x%08X\n", __func__,
 969                 cx_read(AUDIO_INT_INT_MSK));
 970         dprintk(1, "%s() AUD_INT_DMA_CTL          0x%08X\n", __func__,
 971                 cx_read(AUD_INT_DMA_CTL));
 972         dprintk(1, "%s() AUD_EXT_INT_MSK          0x%08X\n", __func__,
 973                 cx_read(AUDIO_EXT_INT_MSK));
 974         dprintk(1, "%s() AUD_EXT_DMA_CTL          0x%08X\n", __func__,
 975                 cx_read(AUD_EXT_DMA_CTL));
 976         dprintk(1, "%s() PAD_CTRL                 0x%08X\n", __func__,
 977                 cx_read(PAD_CTRL));
 978         dprintk(1, "%s() ALT_PIN_OUT_SEL          0x%08X\n", __func__,
 979                 cx_read(ALT_PIN_OUT_SEL));
 980         dprintk(1, "%s() GPIO2                    0x%08X\n", __func__,
 981                 cx_read(GPIO2));
 982         dprintk(1, "%s() gpcnt(0x%08X)          0x%08X\n", __func__,
 983                 port->reg_gpcnt, cx_read(port->reg_gpcnt));
 984         dprintk(1, "%s() gpcnt_ctl(0x%08X)      0x%08x\n", __func__,
 985                 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
 986         dprintk(1, "%s() dma_ctl(0x%08X)        0x%08x\n", __func__,
 987                 port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
 988         dprintk(1, "%s() src_sel(0x%08X)        0x%08x\n", __func__,
 989                 port->reg_src_sel, cx_read(port->reg_src_sel));
 990         dprintk(1, "%s() lngth(0x%08X)          0x%08x\n", __func__,
 991                 port->reg_lngth, cx_read(port->reg_lngth));
 992         dprintk(1, "%s() hw_sop_ctrl(0x%08X)    0x%08x\n", __func__,
 993                 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
 994         dprintk(1, "%s() gen_ctrl(0x%08X)       0x%08x\n", __func__,
 995                 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
 996         dprintk(1, "%s() bd_pkt_status(0x%08X)  0x%08x\n", __func__,
 997                 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
 998         dprintk(1, "%s() sop_status(0x%08X)     0x%08x\n", __func__,
 999                 port->reg_sop_status, cx_read(port->reg_sop_status));
1000         dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __func__,
1001                 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
1002         dprintk(1, "%s() vld_misc(0x%08X)       0x%08x\n", __func__,
1003                 port->reg_vld_misc, cx_read(port->reg_vld_misc));
1004         dprintk(1, "%s() ts_clk_en(0x%08X)      0x%08x\n", __func__,
1005                 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
1006         dprintk(1, "%s() ts_int_msk(0x%08X)     0x%08x\n", __func__,
1007                 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
1008 }
1009
1010 static int cx23885_start_dma(struct cx23885_tsport *port,
1011                              struct cx23885_dmaqueue *q,
1012                              struct cx23885_buffer   *buf)
1013 {
1014         struct cx23885_dev *dev = port->dev;
1015
1016         dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
1017                 buf->vb.width, buf->vb.height, buf->vb.field);
1018
1019         /* setup fifo + format */
1020         cx23885_sram_channel_setup(dev,
1021                                    &dev->sram_channels[ port->sram_chno ],
1022                                    port->ts_packet_size, buf->risc.dma);
1023         if(debug > 5) {
1024                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ] );
1025                 cx23885_risc_disasm(port, &buf->risc);
1026         }
1027
1028         /* write TS length to chip */
1029         cx_write(port->reg_lngth, buf->vb.width);
1030
1031         if ( (!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1032                 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) ) {
1033                 printk( "%s() Failed. Unsupported value in .portb/c (0x%08x)/(0x%08x)\n",
1034                         __func__,
1035                         cx23885_boards[dev->board].portb,
1036                         cx23885_boards[dev->board].portc );
1037                 return -EINVAL;
1038         }
1039
1040         udelay(100);
1041
1042         /* If the port supports SRC SELECT, configure it */
1043         if(port->reg_src_sel)
1044                 cx_write(port->reg_src_sel, port->src_sel_val);
1045
1046         cx_write(port->reg_hw_sop_ctrl, 0x47 << 16 | 188 << 4);
1047         cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1048         cx_write(port->reg_vld_misc, 0x00);
1049         cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1050         udelay(100);
1051
1052         // NOTE: this is 2 (reserved) for portb, does it matter?
1053         /* reset counter to zero */
1054         cx_write(port->reg_gpcnt_ctl, 3);
1055         q->count = 1;
1056
1057         switch(dev->bridge) {
1058         case CX23885_BRIDGE_885:
1059         case CX23885_BRIDGE_887:
1060                 /* enable irqs */
1061                 dprintk(1, "%s() enabling TS int's and DMA\n", __func__ );
1062                 cx_set(port->reg_ts_int_msk,  port->ts_int_msk_val);
1063                 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1064                 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1065                 break;
1066         default:
1067                 BUG();
1068         }
1069
1070         cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1071
1072         if (debug > 4)
1073                 cx23885_tsport_reg_dump(port);
1074
1075         return 0;
1076 }
1077
1078 static int cx23885_stop_dma(struct cx23885_tsport *port)
1079 {
1080         struct cx23885_dev *dev = port->dev;
1081         dprintk(1, "%s()\n", __func__);
1082
1083         /* Stop interrupts and DMA */
1084         cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1085         cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1086
1087         return 0;
1088 }
1089
1090 int cx23885_restart_queue(struct cx23885_tsport *port,
1091                                 struct cx23885_dmaqueue *q)
1092 {
1093         struct cx23885_dev *dev = port->dev;
1094         struct cx23885_buffer *buf;
1095
1096         dprintk(5, "%s()\n", __func__);
1097         if (list_empty(&q->active))
1098         {
1099                 struct cx23885_buffer *prev;
1100                 prev = NULL;
1101
1102                 dprintk(5, "%s() queue is empty\n", __func__);
1103
1104                 for (;;) {
1105                         if (list_empty(&q->queued))
1106                                 return 0;
1107                         buf = list_entry(q->queued.next, struct cx23885_buffer,
1108                                          vb.queue);
1109                         if (NULL == prev) {
1110                                 list_del(&buf->vb.queue);
1111                                 list_add_tail(&buf->vb.queue, &q->active);
1112                                 cx23885_start_dma(port, q, buf);
1113                                 buf->vb.state = VIDEOBUF_ACTIVE;
1114                                 buf->count    = q->count++;
1115                                 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1116                                 dprintk(5, "[%p/%d] restart_queue - first active\n",
1117                                         buf, buf->vb.i);
1118
1119                         } else if (prev->vb.width  == buf->vb.width  &&
1120                                    prev->vb.height == buf->vb.height &&
1121                                    prev->fmt       == buf->fmt) {
1122                                 list_del(&buf->vb.queue);
1123                                 list_add_tail(&buf->vb.queue, &q->active);
1124                                 buf->vb.state = VIDEOBUF_ACTIVE;
1125                                 buf->count    = q->count++;
1126                                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1127                                 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1128                                 dprintk(5,"[%p/%d] restart_queue - move to active\n",
1129                                         buf, buf->vb.i);
1130                         } else {
1131                                 return 0;
1132                         }
1133                         prev = buf;
1134                 }
1135                 return 0;
1136         }
1137
1138         buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1139         dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1140                 buf, buf->vb.i);
1141         cx23885_start_dma(port, q, buf);
1142         list_for_each_entry(buf, &q->active, vb.queue)
1143                 buf->count = q->count++;
1144         mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
1145         return 0;
1146 }
1147
1148 /* ------------------------------------------------------------------ */
1149
1150 int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1151                         struct cx23885_buffer *buf, enum v4l2_field field)
1152 {
1153         struct cx23885_dev *dev = port->dev;
1154         int size = port->ts_packet_size * port->ts_packet_count;
1155         int rc;
1156
1157         dprintk(1, "%s: %p\n", __func__, buf);
1158         if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
1159                 return -EINVAL;
1160
1161         if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1162                 buf->vb.width  = port->ts_packet_size;
1163                 buf->vb.height = port->ts_packet_count;
1164                 buf->vb.size   = size;
1165                 buf->vb.field  = field /*V4L2_FIELD_TOP*/;
1166
1167                 if (0 != (rc = videobuf_iolock(q, &buf->vb, NULL)))
1168                         goto fail;
1169                 cx23885_risc_databuffer(dev->pci, &buf->risc,
1170                                         videobuf_to_dma(&buf->vb)->sglist,
1171                                         buf->vb.width, buf->vb.height);
1172         }
1173         buf->vb.state = VIDEOBUF_PREPARED;
1174         return 0;
1175
1176  fail:
1177         cx23885_free_buffer(q, buf);
1178         return rc;
1179 }
1180
1181 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1182 {
1183         struct cx23885_buffer    *prev;
1184         struct cx23885_dev *dev = port->dev;
1185         struct cx23885_dmaqueue  *cx88q = &port->mpegq;
1186
1187         /* add jump to stopper */
1188         buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1189         buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1190         buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1191
1192         if (list_empty(&cx88q->active)) {
1193                 dprintk( 1, "queue is empty - first active\n" );
1194                 list_add_tail(&buf->vb.queue, &cx88q->active);
1195                 cx23885_start_dma(port, cx88q, buf);
1196                 buf->vb.state = VIDEOBUF_ACTIVE;
1197                 buf->count    = cx88q->count++;
1198                 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1199                 dprintk(1, "[%p/%d] %s - first active\n",
1200                         buf, buf->vb.i, __func__);
1201         } else {
1202                 dprintk( 1, "queue is not empty - append to active\n" );
1203                 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1204                                   vb.queue);
1205                 list_add_tail(&buf->vb.queue, &cx88q->active);
1206                 buf->vb.state = VIDEOBUF_ACTIVE;
1207                 buf->count    = cx88q->count++;
1208                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1209                 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1210                 dprintk( 1, "[%p/%d] %s - append to active\n",
1211                          buf, buf->vb.i, __func__);
1212         }
1213 }
1214
1215 /* ----------------------------------------------------------- */
1216
1217 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1218                               int restart)
1219 {
1220         struct cx23885_dev *dev = port->dev;
1221         struct cx23885_dmaqueue *q = &port->mpegq;
1222         struct cx23885_buffer *buf;
1223         unsigned long flags;
1224
1225         spin_lock_irqsave(&port->slock, flags);
1226         while (!list_empty(&q->active)) {
1227                 buf = list_entry(q->active.next, struct cx23885_buffer,
1228                                  vb.queue);
1229                 list_del(&buf->vb.queue);
1230                 buf->vb.state = VIDEOBUF_ERROR;
1231                 wake_up(&buf->vb.done);
1232                 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1233                         buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1234         }
1235         if (restart) {
1236                 dprintk(1, "restarting queue\n" );
1237                 cx23885_restart_queue(port, q);
1238         }
1239         spin_unlock_irqrestore(&port->slock, flags);
1240 }
1241
1242
1243 static void cx23885_timeout(unsigned long data)
1244 {
1245         struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1246         struct cx23885_dev *dev = port->dev;
1247
1248         dprintk(1, "%s()\n",__func__);
1249
1250         if (debug > 5)
1251                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1252
1253         cx23885_stop_dma(port);
1254         do_cancel_buffers(port, "timeout", 1);
1255 }
1256
1257 static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1258 {
1259         struct cx23885_dev *dev = port->dev;
1260         int handled = 0;
1261         u32 count;
1262
1263         if ( (status & VID_BC_MSK_OPC_ERR) ||
1264              (status & VID_BC_MSK_BAD_PKT) ||
1265              (status & VID_BC_MSK_SYNC) ||
1266              (status & VID_BC_MSK_OF))
1267         {
1268                 if (status & VID_BC_MSK_OPC_ERR)
1269                         dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n", VID_BC_MSK_OPC_ERR);
1270                 if (status & VID_BC_MSK_BAD_PKT)
1271                         dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n", VID_BC_MSK_BAD_PKT);
1272                 if (status & VID_BC_MSK_SYNC)
1273                         dprintk(7, " (VID_BC_MSK_SYNC    0x%08x)\n", VID_BC_MSK_SYNC);
1274                 if (status & VID_BC_MSK_OF)
1275                         dprintk(7, " (VID_BC_MSK_OF      0x%08x)\n", VID_BC_MSK_OF);
1276
1277                 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1278
1279                 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1280                 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1281
1282         } else if (status & VID_BC_MSK_RISCI1) {
1283
1284                 dprintk(7, " (RISCI1            0x%08x)\n", VID_BC_MSK_RISCI1);
1285
1286                 spin_lock(&port->slock);
1287                 count = cx_read(port->reg_gpcnt);
1288                 cx23885_wakeup(port, &port->mpegq, count);
1289                 spin_unlock(&port->slock);
1290
1291         } else if (status & VID_BC_MSK_RISCI2) {
1292
1293                 dprintk(7, " (RISCI2            0x%08x)\n", VID_BC_MSK_RISCI2);
1294
1295                 spin_lock(&port->slock);
1296                 cx23885_restart_queue(port, &port->mpegq);
1297                 spin_unlock(&port->slock);
1298
1299         }
1300         if (status) {
1301                 cx_write(port->reg_ts_int_stat, status);
1302                 handled = 1;
1303         }
1304
1305         return handled;
1306 }
1307
1308 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1309 {
1310         struct cx23885_dev *dev = dev_id;
1311         struct cx23885_tsport *ts1 = &dev->ts1;
1312         struct cx23885_tsport *ts2 = &dev->ts2;
1313         u32 pci_status, pci_mask;
1314         u32 vida_status, vida_mask;
1315         u32 ts1_status, ts1_mask;
1316         u32 ts2_status, ts2_mask;
1317         int vida_count = 0, ts1_count = 0, ts2_count = 0, handled = 0;
1318
1319         pci_status = cx_read(PCI_INT_STAT);
1320         pci_mask = cx_read(PCI_INT_MSK);
1321         vida_status = cx_read(VID_A_INT_STAT);
1322         vida_mask = cx_read(VID_A_INT_MSK);
1323         ts1_status = cx_read(VID_B_INT_STAT);
1324         ts1_mask = cx_read(VID_B_INT_MSK);
1325         ts2_status = cx_read(VID_C_INT_STAT);
1326         ts2_mask = cx_read(VID_C_INT_MSK);
1327
1328         if ( (pci_status == 0) && (ts2_status == 0) && (ts1_status == 0) )
1329                 goto out;
1330
1331         vida_count = cx_read(VID_A_GPCNT);
1332         ts1_count = cx_read(ts1->reg_gpcnt);
1333         ts2_count = cx_read(ts2->reg_gpcnt);
1334         dprintk(7, "pci_status: 0x%08x  pci_mask: 0x%08x\n",
1335                 pci_status, pci_mask);
1336         dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
1337                 vida_status, vida_mask, vida_count);
1338         dprintk(7, "ts1_status: 0x%08x  ts1_mask: 0x%08x count: 0x%x\n",
1339                 ts1_status, ts1_mask, ts1_count);
1340         dprintk(7, "ts2_status: 0x%08x  ts2_mask: 0x%08x count: 0x%x\n",
1341                 ts2_status, ts2_mask, ts2_count);
1342
1343         if ( (pci_status & PCI_MSK_RISC_RD) ||
1344              (pci_status & PCI_MSK_RISC_WR) ||
1345              (pci_status & PCI_MSK_AL_RD) ||
1346              (pci_status & PCI_MSK_AL_WR) ||
1347              (pci_status & PCI_MSK_APB_DMA) ||
1348              (pci_status & PCI_MSK_VID_C) ||
1349              (pci_status & PCI_MSK_VID_B) ||
1350              (pci_status & PCI_MSK_VID_A) ||
1351              (pci_status & PCI_MSK_AUD_INT) ||
1352              (pci_status & PCI_MSK_AUD_EXT) )
1353         {
1354
1355                 if (pci_status & PCI_MSK_RISC_RD)
1356                         dprintk(7, " (PCI_MSK_RISC_RD   0x%08x)\n", PCI_MSK_RISC_RD);
1357                 if (pci_status & PCI_MSK_RISC_WR)
1358                         dprintk(7, " (PCI_MSK_RISC_WR   0x%08x)\n", PCI_MSK_RISC_WR);
1359                 if (pci_status & PCI_MSK_AL_RD)
1360                         dprintk(7, " (PCI_MSK_AL_RD     0x%08x)\n", PCI_MSK_AL_RD);
1361                 if (pci_status & PCI_MSK_AL_WR)
1362                         dprintk(7, " (PCI_MSK_AL_WR     0x%08x)\n", PCI_MSK_AL_WR);
1363                 if (pci_status & PCI_MSK_APB_DMA)
1364                         dprintk(7, " (PCI_MSK_APB_DMA   0x%08x)\n", PCI_MSK_APB_DMA);
1365                 if (pci_status & PCI_MSK_VID_C)
1366                         dprintk(7, " (PCI_MSK_VID_C     0x%08x)\n", PCI_MSK_VID_C);
1367                 if (pci_status & PCI_MSK_VID_B)
1368                         dprintk(7, " (PCI_MSK_VID_B     0x%08x)\n", PCI_MSK_VID_B);
1369                 if (pci_status & PCI_MSK_VID_A)
1370                         dprintk(7, " (PCI_MSK_VID_A     0x%08x)\n", PCI_MSK_VID_A);
1371                 if (pci_status & PCI_MSK_AUD_INT)
1372                         dprintk(7, " (PCI_MSK_AUD_INT   0x%08x)\n", PCI_MSK_AUD_INT);
1373                 if (pci_status & PCI_MSK_AUD_EXT)
1374                         dprintk(7, " (PCI_MSK_AUD_EXT   0x%08x)\n", PCI_MSK_AUD_EXT);
1375
1376         }
1377
1378         if (ts1_status) {
1379                 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1380                         handled += cx23885_irq_ts(ts1, ts1_status);
1381         }
1382
1383         if (ts2_status) {
1384                 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1385                         handled += cx23885_irq_ts(ts2, ts2_status);
1386         }
1387
1388         if (vida_status)
1389                 handled += cx23885_video_irq(dev, vida_status);
1390
1391         if (handled)
1392                 cx_write(PCI_INT_STAT, pci_status);
1393 out:
1394         return IRQ_RETVAL(handled);
1395 }
1396
1397 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1398                                      const struct pci_device_id *pci_id)
1399 {
1400         struct cx23885_dev *dev;
1401         int err;
1402
1403         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1404         if (NULL == dev)
1405                 return -ENOMEM;
1406
1407         /* pci init */
1408         dev->pci = pci_dev;
1409         if (pci_enable_device(pci_dev)) {
1410                 err = -EIO;
1411                 goto fail_free;
1412         }
1413
1414         if (cx23885_dev_setup(dev) < 0) {
1415                 err = -EINVAL;
1416                 goto fail_free;
1417         }
1418
1419         /* print pci info */
1420         pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1421         pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER,  &dev->pci_lat);
1422         printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1423                "latency: %d, mmio: 0x%llx\n", dev->name,
1424                pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1425                dev->pci_lat, (unsigned long long)pci_resource_start(pci_dev,0));
1426
1427         pci_set_master(pci_dev);
1428         if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1429                 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1430                 err = -EIO;
1431                 goto fail_irq;
1432         }
1433
1434         err = request_irq(pci_dev->irq, cx23885_irq,
1435                           IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
1436         if (err < 0) {
1437                 printk(KERN_ERR "%s: can't get IRQ %d\n",
1438                        dev->name, pci_dev->irq);
1439                 goto fail_irq;
1440         }
1441
1442         pci_set_drvdata(pci_dev, dev);
1443         return 0;
1444
1445 fail_irq:
1446         cx23885_dev_unregister(dev);
1447 fail_free:
1448         kfree(dev);
1449         return err;
1450 }
1451
1452 static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1453 {
1454         struct cx23885_dev *dev = pci_get_drvdata(pci_dev);
1455
1456         cx23885_shutdown(dev);
1457
1458         pci_disable_device(pci_dev);
1459
1460         /* unregister stuff */
1461         free_irq(pci_dev->irq, dev);
1462         pci_set_drvdata(pci_dev, NULL);
1463
1464         mutex_lock(&devlist);
1465         list_del(&dev->devlist);
1466         mutex_unlock(&devlist);
1467
1468         cx23885_dev_unregister(dev);
1469         kfree(dev);
1470 }
1471
1472 static struct pci_device_id cx23885_pci_tbl[] = {
1473         {
1474                 /* CX23885 */
1475                 .vendor       = 0x14f1,
1476                 .device       = 0x8852,
1477                 .subvendor    = PCI_ANY_ID,
1478                 .subdevice    = PCI_ANY_ID,
1479         },{
1480                 /* CX23887 Rev 2 */
1481                 .vendor       = 0x14f1,
1482                 .device       = 0x8880,
1483                 .subvendor    = PCI_ANY_ID,
1484                 .subdevice    = PCI_ANY_ID,
1485         },{
1486                 /* --- end of list --- */
1487         }
1488 };
1489 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1490
1491 static struct pci_driver cx23885_pci_driver = {
1492         .name     = "cx23885",
1493         .id_table = cx23885_pci_tbl,
1494         .probe    = cx23885_initdev,
1495         .remove   = __devexit_p(cx23885_finidev),
1496         /* TODO */
1497         .suspend  = NULL,
1498         .resume   = NULL,
1499 };
1500
1501 static int cx23885_init(void)
1502 {
1503         printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
1504                (CX23885_VERSION_CODE >> 16) & 0xff,
1505                (CX23885_VERSION_CODE >>  8) & 0xff,
1506                CX23885_VERSION_CODE & 0xff);
1507 #ifdef SNAPSHOT
1508         printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1509                SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1510 #endif
1511         return pci_register_driver(&cx23885_pci_driver);
1512 }
1513
1514 static void cx23885_fini(void)
1515 {
1516         pci_unregister_driver(&cx23885_pci_driver);
1517 }
1518
1519 module_init(cx23885_init);
1520 module_exit(cx23885_fini);
1521
1522 /* ----------------------------------------------------------- */
1523 /*
1524  * Local variables:
1525  * c-basic-offset: 8
1526  * End:
1527  * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
1528  */