SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/media/video/cx231xx/cx231xx-avcore.c

   1 /*
   2    cx231xx_avcore.c - driver for Conexant Cx23100/101/102
   3                       USB video capture devices
   4
   5    Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
   6
   7    This program contains the specific code to control the avdecoder chip and
   8    other related usb control functions for cx231xx based chipset.
   9
  10    This program is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 2 of the License, or
  13    (at your option) any later version.
  14
  15    This program is distributed in the hope that it will be useful,
  16    but WITHOUT ANY WARRANTY; without even the implied warranty of
  17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18    GNU General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this program; if not, write to the Free Software
  22    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/list.h>
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/bitmap.h>
  30 #include <linux/usb.h>
  31 #include <linux/i2c.h>
  32 #include <linux/version.h>
  33 #include <linux/mm.h>
  34 #include <linux/mutex.h>
  35
  36 #include <media/v4l2-common.h>
  37 #include <media/v4l2-ioctl.h>
  38 #include <media/v4l2-chip-ident.h>
  39
  40 #include "cx231xx.h"
  41
  42 /******************************************************************************
  43  *            C O L I B R I - B L O C K    C O N T R O L   functions          *
  44  ******************************************************************************/
  45 int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count)
  46 {
  47         int status = 0;
  48         u8 temp = 0;
  49         u32 colibri_power_status = 0;
  50         int i = 0;
  51
  52         /* super block initialize */
  53         temp = (u8) (ref_count & 0xff);
  54         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
  55                                         SUP_BLK_TUNE2, 2, temp, 1);
  56         if (status < 0)
  57                 return status;
  58
  59         status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
  60                                        SUP_BLK_TUNE2, 2,
  61                                        &colibri_power_status, 1);
  62         if (status < 0)
  63                 return status;
  64
  65         temp = (u8) ((ref_count & 0x300) >> 8);
  66         temp |= 0x40;
  67         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
  68                                         SUP_BLK_TUNE1, 2, temp, 1);
  69         if (status < 0)
  70                 return status;
  71
  72         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
  73                                         SUP_BLK_PLL2, 2, 0x0f, 1);
  74         if (status < 0)
  75                 return status;
  76
  77         /* enable pll     */
  78         while (colibri_power_status != 0x18) {
  79                 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
  80                                                 SUP_BLK_PWRDN, 2, 0x18, 1);
  81                 if (status < 0) {
  82                         cx231xx_info(
  83                         ": Init Super Block failed in send cmd\n");
  84                         break;
  85                 }
  86
  87                 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
  88                                                SUP_BLK_PWRDN, 2,
  89                                                &colibri_power_status, 1);
  90                 colibri_power_status &= 0xff;
  91                 if (status < 0) {
  92                         cx231xx_info(
  93                         ": Init Super Block failed in receive cmd\n");
  94                         break;
  95                 }
  96                 i++;
  97                 if (i == 10) {
  98                         cx231xx_info(
  99                         ": Init Super Block force break in loop !!!!\n");
 100                         status = -1;
 101                         break;
 102                 }
 103         }
 104
 105         if (status < 0)
 106                 return status;
 107
 108         /* start tuning filter */
 109         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 110                                         SUP_BLK_TUNE3, 2, 0x40, 1);
 111         if (status < 0)
 112                 return status;
 113
 114         msleep(5);
 115
 116         /* exit tuning */
 117         status =
 118             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE3,
 119                                    2, 0x00, 1);
 120
 121         return status;
 122 }
 123
 124 int cx231xx_colibri_init_channels(struct cx231xx *dev)
 125 {
 126         int status = 0;
 127
 128         /* power up all 3 channels, clear pd_buffer */
 129         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 130                                    ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1);
 131         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 132                                    ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1);
 133         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 134                                    ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1);
 135
 136         /* Enable quantizer calibration */
 137         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 138                                         ADC_COM_QUANT, 2, 0x02, 1);
 139
 140         /* channel initialize, force modulator (fb) reset */
 141         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 142                                    ADC_FB_FRCRST_CH1, 2, 0x17, 1);
 143         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 144                                    ADC_FB_FRCRST_CH2, 2, 0x17, 1);
 145         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 146                                    ADC_FB_FRCRST_CH3, 2, 0x17, 1);
 147
 148         /* start quantilizer calibration  */
 149         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 150                                    ADC_CAL_ATEST_CH1, 2, 0x10, 1);
 151         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 152                                    ADC_CAL_ATEST_CH2, 2, 0x10, 1);
 153         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 154                                    ADC_CAL_ATEST_CH3, 2, 0x10, 1);
 155         msleep(5);
 156
 157         /* exit modulator (fb) reset */
 158         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 159                                    ADC_FB_FRCRST_CH1, 2, 0x07, 1);
 160         status =  cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 161                                    ADC_FB_FRCRST_CH2, 2, 0x07, 1);
 162         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 163                                    ADC_FB_FRCRST_CH3, 2, 0x07, 1);
 164
 165         /* enable the pre_clamp in each channel for single-ended input */
 166         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 167                                    ADC_NTF_PRECLMP_EN_CH1, 2, 0xf0, 1);
 168         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 169                                    ADC_NTF_PRECLMP_EN_CH2, 2, 0xf0, 1);
 170         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 171                                    ADC_NTF_PRECLMP_EN_CH3, 2, 0xf0, 1);
 172
 173         /* use diode instead of resistor, so set term_en to 0, res_en to 0  */
 174         status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8,
 175                                    ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
 176         status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8,
 177                                    ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
 178         status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8,
 179                                    ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
 180
 181         /* dynamic element matching off */
 182         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 183                                    ADC_DCSERVO_DEM_CH1, 2, 0x03, 1);
 184         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 185                                    ADC_DCSERVO_DEM_CH2, 2, 0x03, 1);
 186         status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 187                                    ADC_DCSERVO_DEM_CH3, 2, 0x03, 1);
 188
 189         return status;
 190 }
 191
 192 int cx231xx_colibri_setup_AFE_for_baseband(struct cx231xx *dev)
 193 {
 194         u32 c_value = 0;
 195         int status = 0;
 196
 197         status =
 198             cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 199                                   ADC_PWRDN_CLAMP_CH2, 2, &c_value, 1);
 200         c_value &= (~(0x50));
 201         status =
 202             cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 203                                    ADC_PWRDN_CLAMP_CH2, 2, c_value, 1);
 204
 205         return status;
 206 }
 207
 208 /*
 209         The Analog Front End in Cx231xx has 3 channels. These
 210         channels are used to share between different inputs
 211         like tuner, s-video and composite inputs.
 212
 213         channel 1 ----- pin 1  to pin4(in reg is 1-4)
 214         channel 2 ----- pin 5  to pin8(in reg is 5-8)
 215         channel 3 ----- pin 9 to pin 12(in reg is 9-11)
 216 */
 217 int cx231xx_colibri_set_input_mux(struct cx231xx *dev, u32 input_mux)
 218 {
 219         u8 ch1_setting = (u8) input_mux;
 220         u8 ch2_setting = (u8) (input_mux >> 8);
 221         u8 ch3_setting = (u8) (input_mux >> 16);
 222         int status = 0;
 223         u32 value = 0;
 224
 225         if (ch1_setting != 0) {
 226                 status =
 227                     cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 228                                           ADC_INPUT_CH1, 2, &value, 1);
 229                 value &= (!INPUT_SEL_MASK);
 230                 value |= (ch1_setting - 1) << 4;
 231                 value &= 0xff;
 232                 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 233                                            ADC_INPUT_CH1, 2, value, 1);
 234         }
 235
 236         if (ch2_setting != 0) {
 237                 status =
 238                     cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 239                                           ADC_INPUT_CH2, 2, &value, 1);
 240                 value &= (!INPUT_SEL_MASK);
 241                 value |= (ch2_setting - 1) << 4;
 242                 value &= 0xff;
 243                 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 244                                            ADC_INPUT_CH2, 2, value, 1);
 245         }
 246
 247         /* For ch3_setting, the value to put in the register is
 248            7 less than the input number */
 249         if (ch3_setting != 0) {
 250                 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 251                                           ADC_INPUT_CH3, 2, &value, 1);
 252                 value &= (!INPUT_SEL_MASK);
 253                 value |= (ch3_setting - 1) << 4;
 254                 value &= 0xff;
 255                 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 256                                            ADC_INPUT_CH3, 2, value, 1);
 257         }
 258
 259         return status;
 260 }
 261
 262 int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
 263 {
 264         int status = 0;
 265
 266         /*
 267         * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
 268         * Currently, only baseband works.
 269         */
 270
 271         switch (mode) {
 272         case AFE_MODE_LOW_IF:
 273                 /* SetupAFEforLowIF();  */
 274                 break;
 275         case AFE_MODE_BASEBAND:
 276                 status = cx231xx_colibri_setup_AFE_for_baseband(dev);
 277                 break;
 278         case AFE_MODE_EU_HI_IF:
 279                 /* SetupAFEforEuHiIF(); */
 280                 break;
 281         case AFE_MODE_US_HI_IF:
 282                 /* SetupAFEforUsHiIF(); */
 283                 break;
 284         case AFE_MODE_JAPAN_HI_IF:
 285                 /* SetupAFEforJapanHiIF(); */
 286                 break;
 287         }
 288
 289         if ((mode != dev->colibri_mode) &&
 290                 (dev->video_input == CX231XX_VMUX_TELEVISION))
 291                 status = cx231xx_colibri_adjust_ref_count(dev,
 292                                                      CX231XX_VMUX_TELEVISION);
 293
 294         dev->colibri_mode = mode;
 295
 296         return status;
 297 }
 298
 299 int cx231xx_colibri_update_power_control(struct cx231xx *dev,
 300                                         enum AV_MODE avmode)
 301 {
 302         u32 colibri_power_status = 0;
 303         int status = 0;
 304
 305         switch (dev->model) {
 306         case CX231XX_BOARD_CNXT_RDE_250:
 307         case CX231XX_BOARD_CNXT_RDU_250:
 308                 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
 309                         while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS |
 310                                                 FLD_PWRDN_ENABLE_PLL)) {
 311                                 status = cx231xx_write_i2c_data(dev,
 312                                                         Colibri_DEVICE_ADDRESS,
 313                                                         SUP_BLK_PWRDN, 2,
 314                                                         FLD_PWRDN_TUNING_BIAS |
 315                                                         FLD_PWRDN_ENABLE_PLL,
 316                                                         1);
 317                                 status |= cx231xx_read_i2c_data(dev,
 318                                                         Colibri_DEVICE_ADDRESS,
 319                                                         SUP_BLK_PWRDN, 2,
 320                                                         &colibri_power_status,
 321                                                         1);
 322                                 if (status < 0)
 323                                         break;
 324                         }
 325
 326                         status = cx231xx_write_i2c_data(dev,
 327                                                    Colibri_DEVICE_ADDRESS,
 328                                                    ADC_PWRDN_CLAMP_CH1, 2, 0x00,
 329                                                    1);
 330                         status |= cx231xx_write_i2c_data(dev,
 331                                                    Colibri_DEVICE_ADDRESS,
 332                                                    ADC_PWRDN_CLAMP_CH2, 2, 0x00,
 333                                                    1);
 334                         status |= cx231xx_write_i2c_data(dev,
 335                                                    Colibri_DEVICE_ADDRESS,
 336                                                    ADC_PWRDN_CLAMP_CH3, 2, 0x00,
 337                                                    1);
 338                 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
 339                         status = cx231xx_write_i2c_data(dev,
 340                                                    Colibri_DEVICE_ADDRESS,
 341                                                    ADC_PWRDN_CLAMP_CH1, 2, 0x70,
 342                                                    1);
 343                         status |= cx231xx_write_i2c_data(dev,
 344                                                    Colibri_DEVICE_ADDRESS,
 345                                                    ADC_PWRDN_CLAMP_CH2, 2, 0x70,
 346                                                    1);
 347                         status |= cx231xx_write_i2c_data(dev,
 348                                                    Colibri_DEVICE_ADDRESS,
 349                                                    ADC_PWRDN_CLAMP_CH3, 2, 0x70,
 350                                                    1);
 351
 352                         status |= cx231xx_read_i2c_data(dev,
 353                                                   Colibri_DEVICE_ADDRESS,
 354                                                   SUP_BLK_PWRDN, 2,
 355                                                   &colibri_power_status, 1);
 356                         colibri_power_status |= FLD_PWRDN_PD_BANDGAP |
 357                                                 FLD_PWRDN_PD_BIAS |
 358                                                 FLD_PWRDN_PD_TUNECK;
 359                         status |= cx231xx_write_i2c_data(dev,
 360                                                    Colibri_DEVICE_ADDRESS,
 361                                                    SUP_BLK_PWRDN, 2,
 362                                                    colibri_power_status, 1);
 363                 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
 364                         while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS |
 365                                                 FLD_PWRDN_ENABLE_PLL)) {
 366                                 status = cx231xx_write_i2c_data(dev,
 367                                                         Colibri_DEVICE_ADDRESS,
 368                                                         SUP_BLK_PWRDN, 2,
 369                                                         FLD_PWRDN_TUNING_BIAS |
 370                                                         FLD_PWRDN_ENABLE_PLL,
 371                                                         1);
 372                                 status |= cx231xx_read_i2c_data(dev,
 373                                                         Colibri_DEVICE_ADDRESS,
 374                                                         SUP_BLK_PWRDN, 2,
 375                                                         &colibri_power_status,
 376                                                         1);
 377                                 if (status < 0)
 378                                         break;
 379                         }
 380
 381                         status |= cx231xx_write_i2c_data(dev,
 382                                                    Colibri_DEVICE_ADDRESS,
 383                                                    ADC_PWRDN_CLAMP_CH1, 2, 0x00,
 384                                                    1);
 385                         status |= cx231xx_write_i2c_data(dev,
 386                                                    Colibri_DEVICE_ADDRESS,
 387                                                    ADC_PWRDN_CLAMP_CH2, 2, 0x00,
 388                                                    1);
 389                         status |= cx231xx_write_i2c_data(dev,
 390                                                    Colibri_DEVICE_ADDRESS,
 391                                                    ADC_PWRDN_CLAMP_CH3, 2, 0x00,
 392                                                    1);
 393                 } else {
 394                         cx231xx_info("Invalid AV mode input\n");
 395                         status = -1;
 396                 }
 397                 break;
 398         default:
 399                 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
 400                         while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS |
 401                                                 FLD_PWRDN_ENABLE_PLL)) {
 402                                 status = cx231xx_write_i2c_data(dev,
 403                                                         Colibri_DEVICE_ADDRESS,
 404                                                         SUP_BLK_PWRDN, 2,
 405                                                         FLD_PWRDN_TUNING_BIAS |
 406                                                         FLD_PWRDN_ENABLE_PLL,
 407                                                         1);
 408                                 status |= cx231xx_read_i2c_data(dev,
 409                                                         Colibri_DEVICE_ADDRESS,
 410                                                         SUP_BLK_PWRDN, 2,
 411                                                         &colibri_power_status,
 412                                                         1);
 413                                 if (status < 0)
 414                                         break;
 415                         }
 416
 417                         status |= cx231xx_write_i2c_data(dev,
 418                                                         Colibri_DEVICE_ADDRESS,
 419                                                         ADC_PWRDN_CLAMP_CH1, 2,
 420                                                         0x40, 1);
 421                         status |= cx231xx_write_i2c_data(dev,
 422                                                         Colibri_DEVICE_ADDRESS,
 423                                                         ADC_PWRDN_CLAMP_CH2, 2,
 424                                                         0x40, 1);
 425                         status |= cx231xx_write_i2c_data(dev,
 426                                                         Colibri_DEVICE_ADDRESS,
 427                                                         ADC_PWRDN_CLAMP_CH3, 2,
 428                                                         0x00, 1);
 429                 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
 430                         status = cx231xx_write_i2c_data(dev,
 431                                                         Colibri_DEVICE_ADDRESS,
 432                                                         ADC_PWRDN_CLAMP_CH1, 2,
 433                                                         0x70, 1);
 434                         status |= cx231xx_write_i2c_data(dev,
 435                                                         Colibri_DEVICE_ADDRESS,
 436                                                         ADC_PWRDN_CLAMP_CH2, 2,
 437                                                         0x70, 1);
 438                         status |= cx231xx_write_i2c_data(dev,
 439                                                         Colibri_DEVICE_ADDRESS,
 440                                                         ADC_PWRDN_CLAMP_CH3, 2,
 441                                                         0x70, 1);
 442
 443                         status |= cx231xx_read_i2c_data(dev,
 444                                                        Colibri_DEVICE_ADDRESS,
 445                                                        SUP_BLK_PWRDN, 2,
 446                                                        &colibri_power_status,
 447                                                        1);
 448                         colibri_power_status |= FLD_PWRDN_PD_BANDGAP |
 449                                                 FLD_PWRDN_PD_BIAS |
 450                                                 FLD_PWRDN_PD_TUNECK;
 451                         status |= cx231xx_write_i2c_data(dev,
 452                                                         Colibri_DEVICE_ADDRESS,
 453                                                         SUP_BLK_PWRDN, 2,
 454                                                         colibri_power_status,
 455                                                         1);
 456                 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
 457                         while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS |
 458                                                 FLD_PWRDN_ENABLE_PLL)) {
 459                                 status = cx231xx_write_i2c_data(dev,
 460                                                         Colibri_DEVICE_ADDRESS,
 461                                                         SUP_BLK_PWRDN, 2,
 462                                                         FLD_PWRDN_TUNING_BIAS |
 463                                                         FLD_PWRDN_ENABLE_PLL,
 464                                                         1);
 465                                 status |= cx231xx_read_i2c_data(dev,
 466                                                         Colibri_DEVICE_ADDRESS,
 467                                                         SUP_BLK_PWRDN, 2,
 468                                                         &colibri_power_status,
 469                                                         1);
 470                                 if (status < 0)
 471                                         break;
 472                         }
 473
 474                         status |= cx231xx_write_i2c_data(dev,
 475                                                         Colibri_DEVICE_ADDRESS,
 476                                                         ADC_PWRDN_CLAMP_CH1, 2,
 477                                                         0x00, 1);
 478                         status |= cx231xx_write_i2c_data(dev,
 479                                                         Colibri_DEVICE_ADDRESS,
 480                                                         ADC_PWRDN_CLAMP_CH2, 2,
 481                                                         0x00, 1);
 482                         status |= cx231xx_write_i2c_data(dev,
 483                                                         Colibri_DEVICE_ADDRESS,
 484                                                         ADC_PWRDN_CLAMP_CH3, 2,
 485                                                         0x40, 1);
 486                 } else {
 487                         cx231xx_info("Invalid AV mode input\n");
 488                         status = -1;
 489                 }
 490         }                       /* switch  */
 491
 492         return status;
 493 }
 494
 495 int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input)
 496 {
 497         u32 input_mode = 0;
 498         u32 ntf_mode = 0;
 499         int status = 0;
 500
 501         dev->video_input = video_input;
 502
 503         if (video_input == CX231XX_VMUX_TELEVISION) {
 504                 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 505                                           ADC_INPUT_CH3, 2, &input_mode, 1);
 506                 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 507                                           ADC_NTF_PRECLMP_EN_CH3, 2, &ntf_mode,
 508                                           1);
 509         } else {
 510                 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 511                                           ADC_INPUT_CH1, 2, &input_mode, 1);
 512                 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
 513                                           ADC_NTF_PRECLMP_EN_CH1, 2, &ntf_mode,
 514                                           1);
 515         }
 516
 517         input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
 518
 519         switch (input_mode) {
 520         case SINGLE_ENDED:
 521                 dev->colibri_ref_count = 0x23C;
 522                 break;
 523         case LOW_IF:
 524                 dev->colibri_ref_count = 0x24C;
 525                 break;
 526         case EU_IF:
 527                 dev->colibri_ref_count = 0x258;
 528                 break;
 529         case US_IF:
 530                 dev->colibri_ref_count = 0x260;
 531                 break;
 532         default:
 533                 break;
 534         }
 535
 536         status = cx231xx_colibri_init_super_block(dev, dev->colibri_ref_count);
 537
 538         return status;
 539 }
 540
 541 /******************************************************************************
 542  *     V I D E O / A U D I O    D E C O D E R    C O N T R O L   functions    *
 543  ******************************************************************************/
 544 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
 545 {
 546         int status = 0;
 547
 548         switch (INPUT(input)->type) {
 549         case CX231XX_VMUX_COMPOSITE1:
 550         case CX231XX_VMUX_SVIDEO:
 551                 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
 552                     (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
 553                         /* External AV */
 554                         status = cx231xx_set_power_mode(dev,
 555                                         POLARIS_AVMODE_ENXTERNAL_AV);
 556                         if (status < 0) {
 557                                 cx231xx_errdev("%s: set_power_mode : Failed to"
 558                                                 " set Power - errCode [%d]!\n",
 559                                                 __func__, status);
 560                                 return status;
 561                         }
 562                 }
 563                 status = cx231xx_set_decoder_video_input(dev,
 564                                                          INPUT(input)->type,
 565                                                          INPUT(input)->vmux);
 566                 break;
 567         case CX231XX_VMUX_TELEVISION:
 568         case CX231XX_VMUX_CABLE:
 569                 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
 570                     (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
 571                         /* Tuner */
 572                         status = cx231xx_set_power_mode(dev,
 573                                                 POLARIS_AVMODE_ANALOGT_TV);
 574                         if (status < 0) {
 575                                 cx231xx_errdev("%s: set_power_mode:Failed"
 576                                         " to set Power - errCode [%d]!\n",
 577                                         __func__, status);
 578                                 return status;
 579                         }
 580                 }
 581                 status = cx231xx_set_decoder_video_input(dev,
 582                                                         CX231XX_VMUX_COMPOSITE1,
 583                                                         INPUT(input)->vmux);
 584                 break;
 585         default:
 586                 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n",
 587                      __func__, INPUT(input)->type);
 588                 break;
 589         }
 590
 591         /* save the selection */
 592         dev->video_input = input;
 593
 594         return status;
 595 }
 596
 597 int cx231xx_set_decoder_video_input(struct cx231xx *dev,
 598                                 u8 pin_type, u8 input)
 599 {
 600         int status = 0;
 601         u32 value = 0;
 602
 603         if (pin_type != dev->video_input) {
 604                 status = cx231xx_colibri_adjust_ref_count(dev, pin_type);
 605                 if (status < 0) {
 606                         cx231xx_errdev("%s: adjust_ref_count :Failed to set"
 607                                 "Colibri input mux - errCode [%d]!\n",
 608                                 __func__, status);
 609                         return status;
 610                 }
 611         }
 612
 613         /* call colibri block to set video inputs */
 614         status = cx231xx_colibri_set_input_mux(dev, input);
 615         if (status < 0) {
 616                 cx231xx_errdev("%s: set_input_mux :Failed to set"
 617                                 " Colibri input mux - errCode [%d]!\n",
 618                                 __func__, status);
 619                 return status;
 620         }
 621
 622         switch (pin_type) {
 623         case CX231XX_VMUX_COMPOSITE1:
 624                 status = cx231xx_read_i2c_data(dev,
 625                                                 HAMMERHEAD_I2C_ADDRESS,
 626                                                 AFE_CTRL, 2, &value, 4);
 627                 value |= (0 << 13) | (1 << 4);
 628                 value &= ~(1 << 5);
 629
 630                 /* set [24:23] [22:15] to 0  */
 631                 value &= (~(0x1ff8000));
 632                 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0  */
 633                 value |= 0x1000000;
 634                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
 635                                                 AFE_CTRL, 2, value, 4);
 636
 637                 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
 638                                                 OUT_CTRL1, 2, &value, 4);
 639                 value |= (1 << 7);
 640                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
 641                                                 OUT_CTRL1, 2, value, 4);
 642
 643                 /* Set vip 1.1 output mode */
 644                 status = cx231xx_read_modify_write_i2c_dword(dev,
 645                                                         HAMMERHEAD_I2C_ADDRESS,
 646                                                         OUT_CTRL1,
 647                                                         FLD_OUT_MODE,
 648                                                         OUT_MODE_VIP11);
 649
 650                 /* Tell DIF object to go to baseband mode  */
 651                 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
 652                 if (status < 0) {
 653                         cx231xx_errdev("%s: cx231xx_dif set to By pass"
 654                                                    " mode- errCode [%d]!\n",
 655                                 __func__, status);
 656                         return status;
 657                 }
 658
 659                 /* Read the DFE_CTRL1 register */
 660                 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
 661                                                 DFE_CTRL1, 2, &value, 4);
 662
 663                 /* enable the VBI_GATE_EN */
 664                 value |= FLD_VBI_GATE_EN;
 665
 666                 /* Enable the auto-VGA enable */
 667                 value |= FLD_VGA_AUTO_EN;
 668
 669                 /* Write it back */
 670                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
 671                                                 DFE_CTRL1, 2, value, 4);
 672
 673                 /* Disable auto config of registers */
 674                 status = cx231xx_read_modify_write_i2c_dword(dev,
 675                                         HAMMERHEAD_I2C_ADDRESS,
 676                                         MODE_CTRL, FLD_ACFG_DIS,
 677                                         cx231xx_set_field(FLD_ACFG_DIS, 1));
 678
 679                 /* Set CVBS input mode */
 680                 status = cx231xx_read_modify_write_i2c_dword(dev,
 681                         HAMMERHEAD_I2C_ADDRESS,
 682                         MODE_CTRL, FLD_INPUT_MODE,
 683                         cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
 684                 break;
 685         case CX231XX_VMUX_SVIDEO:
 686                 /* Disable the use of  DIF */
 687
 688                 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
 689                                                AFE_CTRL, 2, &value, 4);
 690
 691                 /* set [24:23] [22:15] to 0 */
 692                 value &= (~(0x1ff8000));
 693                 /* set FUNC_MODE[24:23] = 2
 694                 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
 695                 value |= 0x1000010;
 696                 status = cx231xx_write_i2c_data(dev,
 697                                                 HAMMERHEAD_I2C_ADDRESS,
 698                                                 AFE_CTRL, 2, value, 4);
 699
 700                 /* Tell DIF object to go to baseband mode */
 701                 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
 702                 if (status < 0) {
 703                         cx231xx_errdev("%s: cx231xx_dif set to By pass"
 704                                                    " mode- errCode [%d]!\n",
 705                                 __func__, status);
 706                         return status;
 707                 }
 708
 709                 /* Read the DFE_CTRL1 register */
 710                 status = cx231xx_read_i2c_data(dev,
 711                                                HAMMERHEAD_I2C_ADDRESS,
 712                                                DFE_CTRL1, 2, &value, 4);
 713
 714                 /* enable the VBI_GATE_EN */
 715                 value |= FLD_VBI_GATE_EN;
 716
 717                 /* Enable the auto-VGA enable */
 718                 value |= FLD_VGA_AUTO_EN;
 719
 720                 /* Write it back */
 721                 status = cx231xx_write_i2c_data(dev,
 722                                                 HAMMERHEAD_I2C_ADDRESS,
 723                                                 DFE_CTRL1, 2, value, 4);
 724
 725                 /* Disable auto config of registers  */
 726                 status =  cx231xx_read_modify_write_i2c_dword(dev,
 727                                         HAMMERHEAD_I2C_ADDRESS,
 728                                         MODE_CTRL, FLD_ACFG_DIS,
 729                                         cx231xx_set_field(FLD_ACFG_DIS, 1));
 730
 731                 /* Set YC input mode */
 732                 status = cx231xx_read_modify_write_i2c_dword(dev,
 733                         HAMMERHEAD_I2C_ADDRESS,
 734                         MODE_CTRL,
 735                         FLD_INPUT_MODE,
 736                         cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
 737
 738                 /* Chroma to ADC2 */
 739                 status = cx231xx_read_i2c_data(dev,
 740                                                 HAMMERHEAD_I2C_ADDRESS,
 741                                                 AFE_CTRL, 2, &value, 4);
 742                 value |= FLD_CHROMA_IN_SEL;     /* set the chroma in select */
 743
 744                 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
 745                    This sets them to use video
 746                    rather than audio.  Only one of the two will be in use. */
 747                 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
 748
 749                 status = cx231xx_write_i2c_data(dev,
 750                                                 HAMMERHEAD_I2C_ADDRESS,
 751                                                 AFE_CTRL, 2, value, 4);
 752
 753                 status = cx231xx_colibri_set_mode(dev, AFE_MODE_BASEBAND);
 754                 break;
 755         case CX231XX_VMUX_TELEVISION:
 756         case CX231XX_VMUX_CABLE:
 757         default:
 758                 switch (dev->model) {
 759                 case CX231XX_BOARD_CNXT_RDE_250:
 760                 case CX231XX_BOARD_CNXT_RDU_250:
 761                         /* Disable the use of  DIF   */
 762
 763                         status = cx231xx_read_i2c_data(dev,
 764                                                        HAMMERHEAD_I2C_ADDRESS,
 765                                                        AFE_CTRL, 2,
 766                                                        &value, 4);
 767                         value |= (0 << 13) | (1 << 4);
 768                         value &= ~(1 << 5);
 769
 770                         /* set [24:23] [22:15] to 0 */
 771                         value &= (~(0x1FF8000));
 772                         /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
 773                         value |= 0x1000000;
 774                         status = cx231xx_write_i2c_data(dev,
 775                                                         HAMMERHEAD_I2C_ADDRESS,
 776                                                         AFE_CTRL, 2,
 777                                                         value, 4);
 778
 779                         status = cx231xx_read_i2c_data(dev,
 780                                                        HAMMERHEAD_I2C_ADDRESS,
 781                                                        OUT_CTRL1, 2,
 782                                                        &value, 4);
 783                         value |= (1 << 7);
 784                         status = cx231xx_write_i2c_data(dev,
 785                                                         HAMMERHEAD_I2C_ADDRESS,
 786                                                         OUT_CTRL1, 2,
 787                                                         value, 4);
 788
 789                         /* Set vip 1.1 output mode */
 790                         status = cx231xx_read_modify_write_i2c_dword(dev,
 791                                                         HAMMERHEAD_I2C_ADDRESS,
 792                                                         OUT_CTRL1, FLD_OUT_MODE,
 793                                                         OUT_MODE_VIP11);
 794
 795                         /* Tell DIF object to go to baseband mode */
 796                         status = cx231xx_dif_set_standard(dev,
 797                                                           DIF_USE_BASEBAND);
 798                         if (status < 0) {
 799                                 cx231xx_errdev("%s: cx231xx_dif set to By pass"
 800                                                 " mode- errCode [%d]!\n",
 801                                                 __func__, status);
 802                                 return status;
 803                         }
 804
 805                         /* Read the DFE_CTRL1 register */
 806                         status = cx231xx_read_i2c_data(dev,
 807                                                        HAMMERHEAD_I2C_ADDRESS,
 808                                                        DFE_CTRL1, 2,
 809                                                        &value, 4);
 810
 811                         /* enable the VBI_GATE_EN */
 812                         value |= FLD_VBI_GATE_EN;
 813
 814                         /* Enable the auto-VGA enable */
 815                         value |= FLD_VGA_AUTO_EN;
 816
 817                         /* Write it back */
 818                         status = cx231xx_write_i2c_data(dev,
 819                                                         HAMMERHEAD_I2C_ADDRESS,
 820                                                         DFE_CTRL1, 2,
 821                                                         value, 4);
 822
 823                         /* Disable auto config of registers */
 824                         status = cx231xx_read_modify_write_i2c_dword(dev,
 825                                         HAMMERHEAD_I2C_ADDRESS,
 826                                         MODE_CTRL, FLD_ACFG_DIS,
 827                                         cx231xx_set_field(FLD_ACFG_DIS, 1));
 828
 829                         /* Set CVBS input mode */
 830                         status = cx231xx_read_modify_write_i2c_dword(dev,
 831                                 HAMMERHEAD_I2C_ADDRESS,
 832                                 MODE_CTRL, FLD_INPUT_MODE,
 833                                 cx231xx_set_field(FLD_INPUT_MODE,
 834                                                 INPUT_MODE_CVBS_0));
 835                         break;
 836                 default:
 837                         /* Enable the DIF for the tuner */
 838
 839                         /* Reinitialize the DIF */
 840                         status = cx231xx_dif_set_standard(dev, dev->norm);
 841                         if (status < 0) {
 842                                 cx231xx_errdev("%s: cx231xx_dif set to By pass"
 843                                                 " mode- errCode [%d]!\n",
 844                                                 __func__, status);
 845                                 return status;
 846                         }
 847
 848                         /* Make sure bypass is cleared */
 849                         status = cx231xx_read_i2c_data(dev,
 850                                                       HAMMERHEAD_I2C_ADDRESS,
 851                                                       DIF_MISC_CTRL,
 852                                                       2, &value, 4);
 853
 854                         /* Clear the bypass bit */
 855                         value &= ~FLD_DIF_DIF_BYPASS;
 856
 857                         /* Enable the use of the DIF block */
 858                         status = cx231xx_write_i2c_data(dev,
 859                                                         HAMMERHEAD_I2C_ADDRESS,
 860                                                         DIF_MISC_CTRL,
 861                                                         2, value, 4);
 862
 863                         /* Read the DFE_CTRL1 register */
 864                         status = cx231xx_read_i2c_data(dev,
 865                                                         HAMMERHEAD_I2C_ADDRESS,
 866                                                         DFE_CTRL1, 2,
 867                                                         &value, 4);
 868
 869                         /* Disable the VBI_GATE_EN */
 870                         value &= ~FLD_VBI_GATE_EN;
 871
 872                         /* Enable the auto-VGA enable, AGC, and
 873                            set the skip count to 2 */
 874                         value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
 875
 876                         /* Write it back */
 877                         status = cx231xx_write_i2c_data(dev,
 878                                                         HAMMERHEAD_I2C_ADDRESS,
 879                                                         DFE_CTRL1, 2,
 880                                                         value, 4);
 881
 882                         /* Wait until AGC locks up */
 883                         msleep(1);
 884
 885                         /* Disable the auto-VGA enable AGC */
 886                         value &= ~(FLD_VGA_AUTO_EN);
 887
 888                         /* Write it back */
 889                         status = cx231xx_write_i2c_data(dev,
 890                                                         HAMMERHEAD_I2C_ADDRESS,
 891                                                         DFE_CTRL1, 2,
 892                                                         value, 4);
 893
 894                         /* Enable Polaris B0 AGC output */
 895                         status = cx231xx_read_i2c_data(dev,
 896                                                         HAMMERHEAD_I2C_ADDRESS,
 897                                                         PIN_CTRL, 2,
 898                                                         &value, 4);
 899                         value |= (FLD_OEF_AGC_RF) |
 900                                  (FLD_OEF_AGC_IFVGA) |
 901                                  (FLD_OEF_AGC_IF);
 902                         status = cx231xx_write_i2c_data(dev,
 903                                                         HAMMERHEAD_I2C_ADDRESS,
 904                                                         PIN_CTRL, 2,
 905                                                         value, 4);
 906
 907                         /* Set vip 1.1 output mode */
 908                         status = cx231xx_read_modify_write_i2c_dword(dev,
 909                                                 HAMMERHEAD_I2C_ADDRESS,
 910                                                 OUT_CTRL1, FLD_OUT_MODE,
 911                                                 OUT_MODE_VIP11);
 912
 913                         /* Disable auto config of registers */
 914                         status = cx231xx_read_modify_write_i2c_dword(dev,
 915                                         HAMMERHEAD_I2C_ADDRESS,
 916                                         MODE_CTRL, FLD_ACFG_DIS,
 917                                         cx231xx_set_field(FLD_ACFG_DIS, 1));
 918
 919                         /* Set CVBS input mode */
 920                         status = cx231xx_read_modify_write_i2c_dword(dev,
 921                                 HAMMERHEAD_I2C_ADDRESS,
 922                                 MODE_CTRL, FLD_INPUT_MODE,
 923                                 cx231xx_set_field(FLD_INPUT_MODE,
 924                                                 INPUT_MODE_CVBS_0));
 925
 926                         /* Set some bits in AFE_CTRL so that channel 2 or 3
 927                          * is ready to receive audio */
 928                         /* Clear clamp for channels 2 and 3      (bit 16-17) */
 929                         /* Clear droop comp                      (bit 19-20) */
 930                         /* Set VGA_SEL (for audio control)       (bit 7-8) */
 931                         status = cx231xx_read_i2c_data(dev,
 932                                                         HAMMERHEAD_I2C_ADDRESS,
 933                                                         AFE_CTRL, 2,
 934                                                         &value, 4);
 935
 936                         value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
 937
 938                         status = cx231xx_write_i2c_data(dev,
 939                                                         HAMMERHEAD_I2C_ADDRESS,
 940                                                         AFE_CTRL, 2,
 941                                                         value, 4);
 942                         break;
 943
 944                 }
 945                 break;
 946         }
 947
 948         /* Set raw VBI mode */
 949         status = cx231xx_read_modify_write_i2c_dword(dev,
 950                                 HAMMERHEAD_I2C_ADDRESS,
 951                                 OUT_CTRL1, FLD_VBIHACTRAW_EN,
 952                                 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
 953
 954         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
 955                                        OUT_CTRL1, 2,
 956                                        &value, 4);
 957         if (value & 0x02) {
 958                 value |= (1 << 19);
 959                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
 960                                            OUT_CTRL1, 2, value, 4);
 961         }
 962
 963         return status;
 964 }
 965
 966 /*
 967  * Handle any video-mode specific overrides that are different
 968  * on a per video standards basis after touching the MODE_CTRL
 969  * register which resets many values for autodetect
 970  */
 971 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
 972 {
 973         int status = 0;
 974
 975         cx231xx_info("do_mode_ctrl_overrides : 0x%x\n",
 976                      (unsigned int)dev->norm);
 977
 978         /* Change the DFE_CTRL3 bp_percent to fix flagging */
 979         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
 980                                         DFE_CTRL3, 2,
 981                                         0xCD3F0280, 4);
 982
 983         if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
 984                 cx231xx_info("do_mode_ctrl_overrides NTSC\n");
 985
 986                 /* Move the close caption lines out of active video,
 987                    adjust the active video start point */
 988                 status = cx231xx_read_modify_write_i2c_dword(dev,
 989                                                         HAMMERHEAD_I2C_ADDRESS,
 990                                                         VERT_TIM_CTRL,
 991                                                         FLD_VBLANK_CNT, 0x18);
 992                 status = cx231xx_read_modify_write_i2c_dword(dev,
 993                                                         HAMMERHEAD_I2C_ADDRESS,
 994                                                         VERT_TIM_CTRL,
 995                                                         FLD_VACTIVE_CNT,
 996                                                         0x1E6000);
 997                 status = cx231xx_read_modify_write_i2c_dword(dev,
 998                                                         HAMMERHEAD_I2C_ADDRESS,
 999                                                         VERT_TIM_CTRL,
1000                                                         FLD_V656BLANK_CNT,
1001                                                         0x1E000000);
1002
1003                 status = cx231xx_read_modify_write_i2c_dword(dev,
1004                                                         HAMMERHEAD_I2C_ADDRESS,
1005                                                         HORIZ_TIM_CTRL,
1006                                                         FLD_HBLANK_CNT,
1007                                                         cx231xx_set_field
1008                                                         (FLD_HBLANK_CNT, 0x79));
1009         } else if (dev->norm & V4L2_STD_SECAM) {
1010                 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
1011                 status =  cx231xx_read_modify_write_i2c_dword(dev,
1012                                                         HAMMERHEAD_I2C_ADDRESS,
1013                                                         VERT_TIM_CTRL,
1014                                                         FLD_VBLANK_CNT, 0x24);
1015                 /* Adjust the active video horizontal start point */
1016                 status = cx231xx_read_modify_write_i2c_dword(dev,
1017                                                         HAMMERHEAD_I2C_ADDRESS,
1018                                                         HORIZ_TIM_CTRL,
1019                                                         FLD_HBLANK_CNT,
1020                                                         cx231xx_set_field
1021                                                         (FLD_HBLANK_CNT, 0x85));
1022         } else {
1023                 cx231xx_info("do_mode_ctrl_overrides PAL\n");
1024                 status = cx231xx_read_modify_write_i2c_dword(dev,
1025                                                         HAMMERHEAD_I2C_ADDRESS,
1026                                                         VERT_TIM_CTRL,
1027                                                         FLD_VBLANK_CNT, 0x24);
1028                 /* Adjust the active video horizontal start point */
1029                 status = cx231xx_read_modify_write_i2c_dword(dev,
1030                                                         HAMMERHEAD_I2C_ADDRESS,
1031                                                         HORIZ_TIM_CTRL,
1032                                                         FLD_HBLANK_CNT,
1033                                                         cx231xx_set_field
1034                                                         (FLD_HBLANK_CNT, 0x85));
1035         }
1036
1037         return status;
1038 }
1039
1040 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
1041 {
1042         int status = 0;
1043         enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
1044
1045         switch (INPUT(input)->amux) {
1046         case CX231XX_AMUX_VIDEO:
1047                 ainput = AUDIO_INPUT_TUNER_TV;
1048                 break;
1049         case CX231XX_AMUX_LINE_IN:
1050                 status = cx231xx_flatiron_set_audio_input(dev, input);
1051                 ainput = AUDIO_INPUT_LINE;
1052                 break;
1053         default:
1054                 break;
1055         }
1056
1057         status = cx231xx_set_audio_decoder_input(dev, ainput);
1058
1059         return status;
1060 }
1061
1062 int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1063                                     enum AUDIO_INPUT audio_input)
1064 {
1065         u32 dwval;
1066         int status;
1067         u32 gen_ctrl;
1068         u32 value = 0;
1069
1070         /* Put it in soft reset   */
1071         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1072                                        GENERAL_CTL, 2, &gen_ctrl, 1);
1073         gen_ctrl |= 1;
1074         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1075                                         GENERAL_CTL, 2, gen_ctrl, 1);
1076
1077         switch (audio_input) {
1078         case AUDIO_INPUT_LINE:
1079                 /* setup AUD_IO control from Merlin paralle output */
1080                 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
1081                                           AUD_CHAN_SRC_PARALLEL);
1082                 status = cx231xx_write_i2c_data(dev,
1083                                                 HAMMERHEAD_I2C_ADDRESS,
1084                                                 AUD_IO_CTRL, 2, value, 4);
1085
1086                 /* setup input to Merlin, SRC2 connect to AC97
1087                    bypass upsample-by-2, slave mode, sony mode, left justify
1088                    adr 091c, dat 01000000 */
1089                 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1090                                                AC97_CTL,
1091                                           2, &dwval, 4);
1092
1093                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1094                                            AC97_CTL, 2,
1095                                            (dwval | FLD_AC97_UP2X_BYPASS), 4);
1096
1097                 /* select the parallel1 and SRC3 */
1098                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1099                                 BAND_OUT_SEL, 2,
1100                                 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
1101                                 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
1102                                 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0),
1103                                 4);
1104
1105                 /* unmute all, AC97 in, independence mode
1106                    adr 08d0, data 0x00063073 */
1107                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1108                                            PATH1_CTL1, 2, 0x00063073, 4);
1109
1110                 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
1111                 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1112                                           PATH1_VOL_CTL, 2, &dwval, 4);
1113                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1114                                            PATH1_VOL_CTL, 2,
1115                                            (dwval | FLD_PATH1_AVC_THRESHOLD),
1116                                            4);
1117
1118                 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
1119                 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1120                                           PATH1_SC_CTL, 2, &dwval, 4);
1121                 status =  cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1122                                            PATH1_SC_CTL, 2,
1123                                            (dwval | FLD_PATH1_SC_THRESHOLD), 4);
1124                 break;
1125
1126         case AUDIO_INPUT_TUNER_TV:
1127         default:
1128
1129                 /* Setup SRC sources and clocks */
1130                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1131                         BAND_OUT_SEL, 2,
1132                         cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00)         |
1133                         cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01)        |
1134                         cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00)         |
1135                         cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02)        |
1136                         cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02)         |
1137                         cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03)        |
1138                         cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00)         |
1139                         cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00)        |
1140                         cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
1141                         cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03)        |
1142                         cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00)         |
1143                         cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02)   |
1144                         cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01), 4);
1145
1146                 /* Setup the AUD_IO control */
1147                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1148                         AUD_IO_CTRL, 2,
1149                         cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00)  |
1150                         cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00)   |
1151                         cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
1152                         cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
1153                         cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03), 4);
1154
1155                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1156                                            PATH1_CTL1, 2, 0x1F063870, 4);
1157
1158                 /* setAudioStandard(_audio_standard); */
1159
1160                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1161                                            PATH1_CTL1, 2, 0x00063870, 4);
1162                 switch (dev->model) {
1163                 case CX231XX_BOARD_CNXT_RDE_250:
1164                 case CX231XX_BOARD_CNXT_RDU_250:
1165                         status = cx231xx_read_modify_write_i2c_dword(dev,
1166                                         HAMMERHEAD_I2C_ADDRESS,
1167                                         CHIP_CTRL,
1168                                         FLD_SIF_EN,
1169                                         cx231xx_set_field(FLD_SIF_EN, 1));
1170                         break;
1171                 default:
1172                         break;
1173                 }
1174                 break;
1175
1176         case AUDIO_INPUT_TUNER_FM:
1177                 /*  use SIF for FM radio
1178                    setupFM();
1179                    setAudioStandard(_audio_standard);
1180                  */
1181                 break;
1182
1183         case AUDIO_INPUT_MUTE:
1184                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1185                                            PATH1_CTL1, 2, 0x1F011012, 4);
1186                 break;
1187         }
1188
1189         /* Take it out of soft reset */
1190         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1191                                        GENERAL_CTL, 2,  &gen_ctrl, 1);
1192         gen_ctrl &= ~1;
1193         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1194                                         GENERAL_CTL, 2, gen_ctrl, 1);
1195
1196         return status;
1197 }
1198
1199 /* Set resolution of the video */
1200 int cx231xx_resolution_set(struct cx231xx *dev)
1201 {
1202         int width, height;
1203         u32 hscale, vscale;
1204         int status = 0;
1205
1206         width = dev->width;
1207         height = dev->height;
1208
1209         get_scale(dev, width, height, &hscale, &vscale);
1210
1211         /* set horzontal scale */
1212         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1213                                         HSCALE_CTRL, 2, hscale, 4);
1214
1215         /* set vertical scale */
1216         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1217                                         VSCALE_CTRL, 2, vscale, 4);
1218
1219         return status;
1220 }
1221
1222 /******************************************************************************
1223  *                    C H I P Specific  C O N T R O L   functions             *
1224  ******************************************************************************/
1225 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1226 {
1227         u32 value;
1228         int status = 0;
1229
1230         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL,
1231                                        2, &value, 4);
1232         value |= (~dev->board.ctl_pin_status_mask);
1233         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL,
1234                                         2, value, 4);
1235
1236         return status;
1237 }
1238
1239 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1240                                               u8 analog_or_digital)
1241 {
1242         int status = 0;
1243
1244         /* first set the direction to output */
1245         status = cx231xx_set_gpio_direction(dev,
1246                                             dev->board.
1247                                             agc_analog_digital_select_gpio, 1);
1248
1249         /* 0 - demod ; 1 - Analog mode */
1250         status = cx231xx_set_gpio_value(dev,
1251                                    dev->board.agc_analog_digital_select_gpio,
1252                                    analog_or_digital);
1253
1254         return status;
1255 }
1256
1257 int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex)
1258 {
1259         u8 value[4] = { 0, 0, 0, 0 };
1260         int status = 0;
1261
1262         cx231xx_info("Changing the i2c port for tuner to %d\n", I2CIndex);
1263
1264         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1265                                        PWR_CTL_EN, value, 4);
1266         if (status < 0)
1267                 return status;
1268
1269         if (I2CIndex == I2C_1) {
1270                 if (value[0] & I2C_DEMOD_EN) {
1271                         value[0] &= ~I2C_DEMOD_EN;
1272                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1273                                                    PWR_CTL_EN, value, 4);
1274                 }
1275         } else {
1276                 if (!(value[0] & I2C_DEMOD_EN)) {
1277                         value[0] |= I2C_DEMOD_EN;
1278                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1279                                                    PWR_CTL_EN, value, 4);
1280                 }
1281         }
1282
1283         return status;
1284
1285 }
1286
1287 /******************************************************************************
1288  *                 D I F - B L O C K    C O N T R O L   functions             *
1289  ******************************************************************************/
1290 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1291                                           u32 function_mode, u32 standard)
1292 {
1293         int status = 0;
1294
1295         if (mode == V4L2_TUNER_RADIO) {
1296                 /* C2HH */
1297                 /* lo if big signal */
1298                 status = cx231xx_reg_mask_write(dev,
1299                                 HAMMERHEAD_I2C_ADDRESS, 32,
1300                                 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1301                 /* FUNC_MODE = DIF */
1302                 status = cx231xx_reg_mask_write(dev,
1303                                 HAMMERHEAD_I2C_ADDRESS, 32,
1304                                 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
1305                 /* IF_MODE */
1306                 status = cx231xx_reg_mask_write(dev,
1307                                 HAMMERHEAD_I2C_ADDRESS, 32,
1308                                 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
1309                 /* no inv */
1310                 status = cx231xx_reg_mask_write(dev,
1311                                 HAMMERHEAD_I2C_ADDRESS, 32,
1312                                 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1313         } else if (standard != DIF_USE_BASEBAND) {
1314                 if (standard & V4L2_STD_MN) {
1315                         /* lo if big signal */
1316                         status = cx231xx_reg_mask_write(dev,
1317                                         HAMMERHEAD_I2C_ADDRESS, 32,
1318                                         AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1319                         /* FUNC_MODE = DIF */
1320                         status = cx231xx_reg_mask_write(dev,
1321                                         HAMMERHEAD_I2C_ADDRESS, 32,
1322                                         AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1323                                         function_mode);
1324                         /* IF_MODE */
1325                         status = cx231xx_reg_mask_write(dev,
1326                                         HAMMERHEAD_I2C_ADDRESS, 32,
1327                                         AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
1328                         /* no inv */
1329                         status = cx231xx_reg_mask_write(dev,
1330                                         HAMMERHEAD_I2C_ADDRESS, 32,
1331                                         AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1332                         /* 0x124, AUD_CHAN1_SRC = 0x3 */
1333                         status = cx231xx_reg_mask_write(dev,
1334                                         HAMMERHEAD_I2C_ADDRESS, 32,
1335                                         AUD_IO_CTRL, 0, 31, 0x00000003);
1336                 } else if ((standard == V4L2_STD_PAL_I) |
1337                         (standard & V4L2_STD_SECAM)) {
1338                         /* C2HH setup */
1339                         /* lo if big signal */
1340                         status = cx231xx_reg_mask_write(dev,
1341                                         HAMMERHEAD_I2C_ADDRESS, 32,
1342                                         AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1343                         /* FUNC_MODE = DIF */
1344                         status = cx231xx_reg_mask_write(dev,
1345                                         HAMMERHEAD_I2C_ADDRESS, 32,
1346                                         AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1347                                         function_mode);
1348                         /* IF_MODE */
1349                         status = cx231xx_reg_mask_write(dev,
1350                                         HAMMERHEAD_I2C_ADDRESS, 32,
1351                                         AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
1352                         /* no inv */
1353                         status = cx231xx_reg_mask_write(dev,
1354                                         HAMMERHEAD_I2C_ADDRESS, 32,
1355                                         AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1356                 } else {
1357                         /* default PAL BG */
1358                         /* C2HH setup */
1359                         /* lo if big signal */
1360                         status = cx231xx_reg_mask_write(dev,
1361                                         HAMMERHEAD_I2C_ADDRESS, 32,
1362                                         AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1363                         /* FUNC_MODE = DIF */
1364                         status = cx231xx_reg_mask_write(dev,
1365                                         HAMMERHEAD_I2C_ADDRESS, 32,
1366                                         AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1367                                         function_mode);
1368                         /* IF_MODE */
1369                         status = cx231xx_reg_mask_write(dev,
1370                                         HAMMERHEAD_I2C_ADDRESS, 32,
1371                                         AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
1372                         /* no inv */
1373                         status = cx231xx_reg_mask_write(dev,
1374                                         HAMMERHEAD_I2C_ADDRESS, 32,
1375                                         AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1376                 }
1377         }
1378
1379         return status;
1380 }
1381
1382 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1383 {
1384         int status = 0;
1385         u32 dif_misc_ctrl_value = 0;
1386         u32 func_mode = 0;
1387
1388         cx231xx_info("%s: setStandard to %x\n", __func__, standard);
1389
1390         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1391                                        DIF_MISC_CTRL, 2, &dif_misc_ctrl_value,
1392                                        4);
1393         if (standard != DIF_USE_BASEBAND)
1394                 dev->norm = standard;
1395
1396         switch (dev->model) {
1397         case CX231XX_BOARD_CNXT_RDE_250:
1398         case CX231XX_BOARD_CNXT_RDU_250:
1399                 func_mode = 0x03;
1400                 break;
1401         default:
1402                 func_mode = 0x01;
1403         }
1404
1405         status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1406                                                   func_mode, standard);
1407
1408         if (standard == DIF_USE_BASEBAND) {     /* base band */
1409                 /* There is a different SRC_PHASE_INC value
1410                    for baseband vs. DIF */
1411                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1412                                                 DIF_SRC_PHASE_INC, 2, 0xDF7DF83,
1413                                                 4);
1414                 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1415                                                DIF_MISC_CTRL, 2,
1416                                                &dif_misc_ctrl_value, 4);
1417                 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
1418                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1419                                                 DIF_MISC_CTRL, 2,
1420                                                 dif_misc_ctrl_value, 4);
1421         } else if (standard & V4L2_STD_PAL_D) {
1422                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1423                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1424                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1425                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1426                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1427                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1428                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1429                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1430                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1431                                            DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1432                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1433                                            DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1434                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1435                                            DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1436                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1437                                            DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1438                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1439                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1440                                            0x26001700);
1441                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1442                                            DIF_AGC_RF_CURRENT, 0, 31,
1443                                            0x00002660);
1444                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1445                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1446                                            0x72500800);
1447                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1448                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1449                                            0x27000100);
1450                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1451                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
1452                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1453                                            DIF_COMP_FLT_CTRL, 0, 31,
1454                                            0x00000000);
1455                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1456                                            DIF_SRC_PHASE_INC, 0, 31,
1457                                            0x1befbf06);
1458                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1459                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1460                                            0x000035e8);
1461                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1462                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1463                 /* Save the Spec Inversion value */
1464                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1465                 dif_misc_ctrl_value |= 0x3a023F11;
1466         } else if (standard & V4L2_STD_PAL_I) {
1467                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1468                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1469                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1470                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1471                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1472                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1473                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1474                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1475                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1476                                            DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1477                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1478                                            DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1479                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1480                                            DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1481                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1482                                            DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1483                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1484                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1485                                            0x26001700);
1486                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1487                                            DIF_AGC_RF_CURRENT, 0, 31,
1488                                            0x00002660);
1489                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1490                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1491                                            0x72500800);
1492                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1493                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1494                                            0x27000100);
1495                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1496                                            DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
1497                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1498                                            DIF_COMP_FLT_CTRL, 0, 31,
1499                                            0x00000000);
1500                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1501                                            DIF_SRC_PHASE_INC, 0, 31,
1502                                            0x1befbf06);
1503                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1504                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1505                                            0x000035e8);
1506                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1507                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1508                 /* Save the Spec Inversion value */
1509                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1510                 dif_misc_ctrl_value |= 0x3a033F11;
1511         } else if (standard & V4L2_STD_PAL_M) {
1512                 /* improved Low Frequency Phase Noise */
1513                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1514                                                 DIF_PLL_CTRL, 2, 0xFF01FF0C, 4);
1515                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1516                                                 DIF_PLL_CTRL1, 2, 0xbd038c85,
1517                                                 4);
1518                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1519                                            DIF_PLL_CTRL2, 2, 0x1db4640a, 4);
1520                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1521                                            DIF_PLL_CTRL3, 2, 0x00008800, 4);
1522                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1523                                            DIF_AGC_IF_REF, 2, 0x444C1380, 4);
1524                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1525                                            DIF_AGC_IF_INT_CURRENT, 2,
1526                                            0x26001700, 4);
1527                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1528                                            DIF_AGC_RF_CURRENT, 2, 0x00002660,
1529                                            4);
1530                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1531                                            DIF_VIDEO_AGC_CTRL, 2, 0x72500800,
1532                                            4);
1533                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1534                                            DIF_VID_AUD_OVERRIDE, 2, 0x27000100,
1535                                            4);
1536                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1537                                            DIF_AV_SEP_CTRL, 2, 0x012c405d, 4);
1538                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1539                                            DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4);
1540                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1541                                            DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4);
1542                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1543                                            DIF_SRC_GAIN_CONTROL, 2, 0x000035e8,
1544                                            4);
1545                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1546                                            DIF_SOFT_RST_CTRL_REVB, 2,
1547                                            0x00000000, 4);
1548                 /* Save the Spec Inversion value */
1549                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1550                 dif_misc_ctrl_value |= 0x3A0A3F10;
1551         } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1552                 /* improved Low Frequency Phase Noise */
1553                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1554                                            DIF_PLL_CTRL, 2, 0xFF01FF0C, 4);
1555                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1556                                            DIF_PLL_CTRL1, 2, 0xbd038c85, 4);
1557                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1558                                            DIF_PLL_CTRL2, 2, 0x1db4640a, 4);
1559                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1560                                            DIF_PLL_CTRL3, 2, 0x00008800, 4);
1561                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1562                                            DIF_AGC_IF_REF, 2, 0x444C1380, 4);
1563                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1564                                            DIF_AGC_IF_INT_CURRENT, 2,
1565                                            0x26001700, 4);
1566                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1567                                            DIF_AGC_RF_CURRENT, 2, 0x00002660,
1568                                            4);
1569                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1570                                            DIF_VIDEO_AGC_CTRL, 2, 0x72500800,
1571                                            4);
1572                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1573                                            DIF_VID_AUD_OVERRIDE, 2, 0x27000100,
1574                                            4);
1575                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1576                                            DIF_AV_SEP_CTRL, 2, 0x012c405d, 4);
1577                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1578                                            DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4);
1579                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1580                                            DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4);
1581                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1582                                            DIF_SRC_GAIN_CONTROL, 2, 0x000035e8,
1583                                            4);
1584                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1585                                            DIF_SOFT_RST_CTRL_REVB, 2,
1586                                            0x00000000, 4);
1587                 /* Save the Spec Inversion value */
1588                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1589                 dif_misc_ctrl_value = 0x3A093F10;
1590         } else if (standard &
1591                   (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1592                    V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
1593
1594                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1595                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1596                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1597                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1598                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1599                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1600                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1601                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1602                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1603                                            DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1604                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1605                                            DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1606                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1607                                            DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1608                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1609                                            DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1610                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1611                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1612                                            0x26001700);
1613                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1614                                            DIF_AGC_RF_CURRENT, 0, 31,
1615                                            0x00002660);
1616                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1617                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1618                                            0x27000100);
1619                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1620                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1621                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1622                                            DIF_COMP_FLT_CTRL, 0, 31,
1623                                            0x00000000);
1624                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1625                                            DIF_SRC_PHASE_INC, 0, 31,
1626                                            0x1befbf06);
1627                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1628                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1629                                            0x000035e8);
1630                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1631                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1632                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1633                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1634                                            0xf4000000);
1635
1636                 /* Save the Spec Inversion value */
1637                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1638                 dif_misc_ctrl_value |= 0x3a023F11;
1639         } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
1640                 /* Is it SECAM_L1? */
1641                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1642                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1643                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1644                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1645                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1646                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1647                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1648                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1649                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1650                                            DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1651                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1652                                            DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1653                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1654                                            DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1655                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1656                                            DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1657                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1658                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1659                                            0x26001700);
1660                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1661                                            DIF_AGC_RF_CURRENT, 0, 31,
1662                                            0x00002660);
1663                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1664                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1665                                            0x27000100);
1666                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1667                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1668                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1669                                            DIF_COMP_FLT_CTRL, 0, 31,
1670                                            0x00000000);
1671                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1672                                            DIF_SRC_PHASE_INC, 0, 31,
1673                                            0x1befbf06);
1674                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1675                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1676                                            0x000035e8);
1677                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1678                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1679                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1680                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1681                                            0xf2560000);
1682
1683                 /* Save the Spec Inversion value */
1684                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1685                 dif_misc_ctrl_value |= 0x3a023F11;
1686
1687         } else if (standard & V4L2_STD_NTSC_M) {
1688                 /* V4L2_STD_NTSC_M (75 IRE Setup) Or
1689                    V4L2_STD_NTSC_M_JP (Japan,  0 IRE Setup) */
1690
1691                 /* For NTSC the centre frequency of video coming out of
1692                    sidewinder is around 7.1MHz or 3.6MHz depending on the
1693                    spectral inversion. so for a non spectrally inverted channel
1694                    the pll freq word is 0x03420c49
1695                  */
1696
1697                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1698                                            DIF_PLL_CTRL, 2, 0x6503BC0C, 4);
1699                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1700                                            DIF_PLL_CTRL1, 2, 0xBD038C85, 4);
1701                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1702                                            DIF_PLL_CTRL2, 2, 0x1DB4640A, 4);
1703                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1704                                            DIF_PLL_CTRL3, 2, 0x00008800, 4);
1705                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1706                                            DIF_AGC_IF_REF, 2, 0x444C0380, 4);
1707                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1708                                            DIF_AGC_IF_INT_CURRENT, 2,
1709                                            0x26001700, 4);
1710                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1711                                            DIF_AGC_RF_CURRENT, 2, 0x00002660,
1712                                            4);
1713                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1714                                            DIF_VIDEO_AGC_CTRL, 2, 0x04000800,
1715                                            4);
1716                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1717                                            DIF_VID_AUD_OVERRIDE, 2, 0x27000100,
1718                                            4);
1719                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1720                                            DIF_AV_SEP_CTRL, 2, 0x01296e1f, 4);
1721
1722                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1723                                            DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4);
1724                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1725                                            DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4);
1726                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1727                                            DIF_SRC_GAIN_CONTROL, 2, 0x000035e8,
1728                                            4);
1729
1730                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1731                                            DIF_AGC_CTRL_IF, 2, 0xC2262600, 4);
1732                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1733                                            DIF_AGC_CTRL_INT, 2, 0xC2262600, 4);
1734                 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1735                                            DIF_AGC_CTRL_RF, 2, 0xC2262600, 4);
1736
1737                 /* Save the Spec Inversion value */
1738                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1739                 dif_misc_ctrl_value |= 0x3a003F10;
1740         } else {
1741                 /* default PAL BG */
1742                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1743                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1744                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1745                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1746                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1747                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1748                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1749                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1750                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1751                                            DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1752                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1753                                            DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1754                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1755                                            DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1756                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1757                                            DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1758                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1759                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1760                                            0x26001700);
1761                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1762                                            DIF_AGC_RF_CURRENT, 0, 31,
1763                                            0x00002660);
1764                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1765                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1766                                            0x72500800);
1767                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1768                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1769                                            0x27000100);
1770                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1771                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
1772                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1773                                            DIF_COMP_FLT_CTRL, 0, 31,
1774                                            0x00A653A8);
1775                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1776                                            DIF_SRC_PHASE_INC, 0, 31,
1777                                            0x1befbf06);
1778                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1779                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1780                                            0x000035e8);
1781                 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1782                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1783                 /* Save the Spec Inversion value */
1784                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1785                 dif_misc_ctrl_value |= 0x3a013F11;
1786         }
1787
1788         /* The AGC values should be the same for all standards,
1789            AUD_SRC_SEL[19] should always be disabled    */
1790         dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
1791
1792         /* It is still possible to get Set Standard calls even when we
1793            are in FM mode.
1794            This is done to override the value for FM. */
1795         if (dev->active_mode == V4L2_TUNER_RADIO)
1796                 dif_misc_ctrl_value = 0x7a080000;
1797
1798         /* Write the calculated value for misc ontrol register      */
1799         status =
1800             cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_MISC_CTRL,
1801                                    2, dif_misc_ctrl_value, 4);
1802
1803         return status;
1804 }
1805
1806 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
1807 {
1808         int status = 0;
1809         u32 dwval;
1810
1811         /* Set the RF and IF k_agc values to 3 */
1812         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1813                                        DIF_AGC_IF_REF, 2, &dwval, 4);
1814         dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
1815         dwval |= 0x33000000;
1816
1817         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1818                                         DIF_AGC_IF_REF, 2, dwval, 4);
1819
1820         return status;
1821 }
1822
1823 int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
1824 {
1825         int status = 0;
1826         u32 dwval;
1827
1828         /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
1829          * SECAM L/B/D standards */
1830         status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1831                                        DIF_AGC_IF_REF, 2, &dwval, 4);
1832         dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
1833
1834         if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
1835                          V4L2_STD_SECAM_D))
1836                 dwval |= 0x88000000;
1837         else
1838                 dwval |= 0x44000000;
1839
1840         status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1841                                         DIF_AGC_IF_REF, 2, dwval, 4);
1842
1843         return status;
1844 }
1845
1846 /******************************************************************************
1847  *        F L A T I R O N - B L O C K    C O N T R O L   functions            *
1848  ******************************************************************************/
1849 int cx231xx_flatiron_initialize(struct cx231xx *dev)
1850 {
1851         int status = 0;
1852         u32 value;
1853
1854         status = cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
1855                                        CH_PWR_CTRL1, 1, &value, 1);
1856         /* enables clock to delta-sigma and decimation filter */
1857         value |= 0x80;
1858         status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
1859                                         CH_PWR_CTRL1, 1, value, 1);
1860         /* power up all channel */
1861         status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
1862                                         CH_PWR_CTRL2, 1, 0x00, 1);
1863
1864         return status;
1865 }
1866
1867 int cx231xx_flatiron_update_power_control(struct cx231xx *dev,
1868                                         enum AV_MODE avmode)
1869 {
1870         int status = 0;
1871         u32 value = 0;
1872
1873         if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
1874                 status = cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
1875                                           CH_PWR_CTRL2, 1, &value, 1);
1876                 value |= 0xfe;
1877                 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
1878                                                 CH_PWR_CTRL2, 1, value, 1);
1879         } else {
1880                 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
1881                                                 CH_PWR_CTRL2, 1, 0x00, 1);
1882         }
1883
1884         return status;
1885 }
1886
1887 /* set flatiron for audio input types */
1888 int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input)
1889 {
1890         int status = 0;
1891
1892         switch (audio_input) {
1893         case CX231XX_AMUX_LINE_IN:
1894                 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
1895                                                 CH_PWR_CTRL2, 1, 0x00, 1);
1896                 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS,
1897                                                 CH_PWR_CTRL1, 1, 0x80, 1);
1898                 break;
1899         case CX231XX_AMUX_VIDEO:
1900         default:
1901                 break;
1902         }
1903
1904         dev->ctl_ainput = audio_input;
1905
1906         return status;
1907 }
1908
1909 /******************************************************************************
1910  *                  P O W E R      C O N T R O L   functions                  *
1911  ******************************************************************************/
1912 int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
1913 {
1914         u8 value[4] = { 0, 0, 0, 0 };
1915         u32 tmp = 0;
1916         int status = 0;
1917
1918         if (dev->power_mode != mode)
1919                 dev->power_mode = mode;
1920         else {
1921                 cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",
1922                              mode);
1923                 return 0;
1924         }
1925
1926         cx231xx_info(" setPowerMode::mode = %d\n", mode);
1927
1928         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
1929                                        4);
1930         if (status < 0)
1931                 return status;
1932
1933         tmp = *((u32 *) value);
1934
1935         switch (mode) {
1936         case POLARIS_AVMODE_ENXTERNAL_AV:
1937
1938                 tmp &= (~PWR_MODE_MASK);
1939
1940                 tmp |= PWR_AV_EN;
1941                 value[0] = (u8) tmp;
1942                 value[1] = (u8) (tmp >> 8);
1943                 value[2] = (u8) (tmp >> 16);
1944                 value[3] = (u8) (tmp >> 24);
1945                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1946                                                 PWR_CTL_EN, value, 4);
1947                 msleep(PWR_SLEEP_INTERVAL);
1948
1949                 tmp |= PWR_ISO_EN;
1950                 value[0] = (u8) tmp;
1951                 value[1] = (u8) (tmp >> 8);
1952                 value[2] = (u8) (tmp >> 16);
1953                 value[3] = (u8) (tmp >> 24);
1954                 status =
1955                     cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
1956                                            value, 4);
1957                 msleep(PWR_SLEEP_INTERVAL);
1958
1959                 tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
1960                 value[0] = (u8) tmp;
1961                 value[1] = (u8) (tmp >> 8);
1962                 value[2] = (u8) (tmp >> 16);
1963                 value[3] = (u8) (tmp >> 24);
1964                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1965                                                 PWR_CTL_EN, value, 4);
1966
1967                 /* reset state of xceive tuner */
1968                 dev->xc_fw_load_done = 0;
1969                 break;
1970
1971         case POLARIS_AVMODE_ANALOGT_TV:
1972
1973                 tmp &= (~PWR_DEMOD_EN);
1974                 tmp |= (I2C_DEMOD_EN);
1975                 value[0] = (u8) tmp;
1976                 value[1] = (u8) (tmp >> 8);
1977                 value[2] = (u8) (tmp >> 16);
1978                 value[3] = (u8) (tmp >> 24);
1979                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1980                                                 PWR_CTL_EN, value, 4);
1981                 msleep(PWR_SLEEP_INTERVAL);
1982
1983                 if (!(tmp & PWR_TUNER_EN)) {
1984                         tmp |= (PWR_TUNER_EN);
1985                         value[0] = (u8) tmp;
1986                         value[1] = (u8) (tmp >> 8);
1987                         value[2] = (u8) (tmp >> 16);
1988                         value[3] = (u8) (tmp >> 24);
1989                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1990                                                         PWR_CTL_EN, value, 4);
1991                         msleep(PWR_SLEEP_INTERVAL);
1992                 }
1993
1994                 if (!(tmp & PWR_AV_EN)) {
1995                         tmp |= PWR_AV_EN;
1996                         value[0] = (u8) tmp;
1997                         value[1] = (u8) (tmp >> 8);
1998                         value[2] = (u8) (tmp >> 16);
1999                         value[3] = (u8) (tmp >> 24);
2000                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2001                                                         PWR_CTL_EN, value, 4);
2002                         msleep(PWR_SLEEP_INTERVAL);
2003                 }
2004                 if (!(tmp & PWR_ISO_EN)) {
2005                         tmp |= PWR_ISO_EN;
2006                         value[0] = (u8) tmp;
2007                         value[1] = (u8) (tmp >> 8);
2008                         value[2] = (u8) (tmp >> 16);
2009                         value[3] = (u8) (tmp >> 24);
2010                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2011                                                         PWR_CTL_EN, value, 4);
2012                         msleep(PWR_SLEEP_INTERVAL);
2013                 }
2014
2015                 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
2016                         tmp |= POLARIS_AVMODE_ANALOGT_TV;
2017                         value[0] = (u8) tmp;
2018                         value[1] = (u8) (tmp >> 8);
2019                         value[2] = (u8) (tmp >> 16);
2020                         value[3] = (u8) (tmp >> 24);
2021                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2022                                                         PWR_CTL_EN, value, 4);
2023                         msleep(PWR_SLEEP_INTERVAL);
2024                 }
2025
2026                 if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
2027                     (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
2028                         /* tuner path to channel 1 from port 3 */
2029                         cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2030
2031                         if (dev->cx231xx_reset_analog_tuner)
2032                                 dev->cx231xx_reset_analog_tuner(dev);
2033                 }
2034                 break;
2035
2036         case POLARIS_AVMODE_DIGITAL:
2037                 if (!(tmp & PWR_TUNER_EN)) {
2038                         tmp |= (PWR_TUNER_EN);
2039                         value[0] = (u8) tmp;
2040                         value[1] = (u8) (tmp >> 8);
2041                         value[2] = (u8) (tmp >> 16);
2042                         value[3] = (u8) (tmp >> 24);
2043                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2044                                                         PWR_CTL_EN, value, 4);
2045                         msleep(PWR_SLEEP_INTERVAL);
2046                 }
2047                 if (!(tmp & PWR_AV_EN)) {
2048                         tmp |= PWR_AV_EN;
2049                         value[0] = (u8) tmp;
2050                         value[1] = (u8) (tmp >> 8);
2051                         value[2] = (u8) (tmp >> 16);
2052                         value[3] = (u8) (tmp >> 24);
2053                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2054                                                         PWR_CTL_EN, value, 4);
2055                         msleep(PWR_SLEEP_INTERVAL);
2056                 }
2057                 if (!(tmp & PWR_ISO_EN)) {
2058                         tmp |= PWR_ISO_EN;
2059                         value[0] = (u8) tmp;
2060                         value[1] = (u8) (tmp >> 8);
2061                         value[2] = (u8) (tmp >> 16);
2062                         value[3] = (u8) (tmp >> 24);
2063                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2064                                                         PWR_CTL_EN, value, 4);
2065                         msleep(PWR_SLEEP_INTERVAL);
2066                 }
2067
2068                 tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN;
2069                 value[0] = (u8) tmp;
2070                 value[1] = (u8) (tmp >> 8);
2071                 value[2] = (u8) (tmp >> 16);
2072                 value[3] = (u8) (tmp >> 24);
2073                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2074                                                 PWR_CTL_EN, value, 4);
2075                 msleep(PWR_SLEEP_INTERVAL);
2076
2077                 if (!(tmp & PWR_DEMOD_EN)) {
2078                         tmp |= PWR_DEMOD_EN;
2079                         value[0] = (u8) tmp;
2080                         value[1] = (u8) (tmp >> 8);
2081                         value[2] = (u8) (tmp >> 16);
2082                         value[3] = (u8) (tmp >> 24);
2083                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2084                                                         PWR_CTL_EN, value, 4);
2085                         msleep(PWR_SLEEP_INTERVAL);
2086                 }
2087
2088                 if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
2089                     (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
2090                         /* tuner path to channel 1 from port 3 */
2091                         cx231xx_enable_i2c_for_tuner(dev, I2C_3);
2092
2093                         if (dev->cx231xx_reset_analog_tuner)
2094                                 dev->cx231xx_reset_analog_tuner(dev);
2095                 }
2096                 break;
2097
2098         default:
2099                 break;
2100         }
2101
2102         msleep(PWR_SLEEP_INTERVAL);
2103
2104         /* For power saving, only enable Pwr_resetout_n
2105            when digital TV is selected. */
2106         if (mode == POLARIS_AVMODE_DIGITAL) {
2107                 tmp |= PWR_RESETOUT_EN;
2108                 value[0] = (u8) tmp;
2109                 value[1] = (u8) (tmp >> 8);
2110                 value[2] = (u8) (tmp >> 16);
2111                 value[3] = (u8) (tmp >> 24);
2112                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
2113                                                 PWR_CTL_EN, value, 4);
2114                 msleep(PWR_SLEEP_INTERVAL);
2115         }
2116
2117         /* update power control for colibri */
2118         status = cx231xx_colibri_update_power_control(dev, mode);
2119
2120         /* update power control for flatiron */
2121         status = cx231xx_flatiron_update_power_control(dev, mode);
2122
2123         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2124                                        4);
2125         cx231xx_info(" The data of PWR_CTL_EN register 0x74"
2126                                  "=0x%0x,0x%0x,0x%0x,0x%0x\n",
2127                      value[0], value[1], value[2], value[3]);
2128
2129         return status;
2130 }
2131
2132 int cx231xx_power_suspend(struct cx231xx *dev)
2133 {
2134         u8 value[4] = { 0, 0, 0, 0 };
2135         u32 tmp = 0;
2136         int status = 0;
2137
2138         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
2139                                        value, 4);
2140         if (status > 0)
2141                 return status;
2142
2143         tmp = *((u32 *) value);
2144         tmp &= (~PWR_MODE_MASK);
2145
2146         value[0] = (u8) tmp;
2147         value[1] = (u8) (tmp >> 8);
2148         value[2] = (u8) (tmp >> 16);
2149         value[3] = (u8) (tmp >> 24);
2150         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
2151                                         value, 4);
2152
2153         return status;
2154 }
2155
2156 /******************************************************************************
2157  *                  S T R E A M    C O N T R O L   functions                  *
2158  ******************************************************************************/
2159 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
2160 {
2161         u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2162         u32 tmp = 0;
2163         int status = 0;
2164
2165         cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
2166         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
2167                                        value, 4);
2168         if (status < 0)
2169                 return status;
2170
2171         tmp = *((u32 *) value);
2172         tmp |= ep_mask;
2173         value[0] = (u8) tmp;
2174         value[1] = (u8) (tmp >> 8);
2175         value[2] = (u8) (tmp >> 16);
2176         value[3] = (u8) (tmp >> 24);
2177
2178         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2179                                         value, 4);
2180
2181         return status;
2182 }
2183
2184 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
2185 {
2186         u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
2187         u32 tmp = 0;
2188         int status = 0;
2189
2190         cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask);
2191         status =
2192             cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
2193         if (status < 0)
2194                 return status;
2195
2196         tmp = *((u32 *) value);
2197         tmp &= (~ep_mask);
2198         value[0] = (u8) tmp;
2199         value[1] = (u8) (tmp >> 8);
2200         value[2] = (u8) (tmp >> 16);
2201         value[3] = (u8) (tmp >> 24);
2202
2203         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2204                                         value, 4);
2205
2206         return status;
2207 }
2208
2209 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2210 {
2211         int status = 0;
2212
2213         if (dev->udev->speed == USB_SPEED_HIGH) {
2214                 switch (media_type) {
2215                 case 81: /* audio */
2216                         cx231xx_info("%s: Audio enter HANC\n", __func__);
2217                         status =
2218                             cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
2219                         break;
2220
2221                 case 2: /* vbi */
2222                         cx231xx_info("%s: set vanc registers\n", __func__);
2223                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2224                         break;
2225
2226                 case 3: /* sliced cc */
2227                         cx231xx_info("%s: set hanc registers\n", __func__);
2228                         status =
2229                             cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
2230                         break;
2231
2232                 case 0: /* video */
2233                         cx231xx_info("%s: set video registers\n", __func__);
2234                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2235                         break;
2236
2237                 case 4: /* ts1 */
2238                         cx231xx_info("%s: set ts1 registers\n", __func__);
2239                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2240                         status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2241                         break;
2242                 case 6: /* ts1 parallel mode */
2243                         cx231xx_info("%s: set ts1 parrallel mode registers\n",
2244                                      __func__);
2245                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2246                         status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2247                         break;
2248                 }
2249         } else {
2250                 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2251         }
2252
2253         return status;
2254 }
2255
2256 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2257 {
2258         int rc;
2259         u32 ep_mask = -1;
2260         struct pcb_config *pcb_config;
2261
2262         /* get EP for media type */
2263         pcb_config = (struct pcb_config *)&dev->current_pcb_config;
2264
2265         if (pcb_config->config_num == 1) {
2266                 switch (media_type) {
2267                 case 0: /* Video */
2268                         ep_mask = ENABLE_EP4;   /* ep4  [00:1000] */
2269                         break;
2270                 case 1: /* Audio */
2271                         ep_mask = ENABLE_EP3;   /* ep3  [00:0100] */
2272                         break;
2273                 case 2: /* Vbi */
2274                         ep_mask = ENABLE_EP5;   /* ep5 [01:0000] */
2275                         break;
2276                 case 3: /* Sliced_cc */
2277                         ep_mask = ENABLE_EP6;   /* ep6 [10:0000] */
2278                         break;
2279                 case 4: /* ts1 */
2280                 case 6: /* ts1 parallel mode */
2281                         ep_mask = ENABLE_EP1;   /* ep1 [00:0001] */
2282                         break;
2283                 case 5: /* ts2 */
2284                         ep_mask = ENABLE_EP2;   /* ep2 [00:0010] */
2285                         break;
2286                 }
2287
2288         } else if (pcb_config->config_num > 1) {
2289                 switch (media_type) {
2290                 case 0: /* Video */
2291                         ep_mask = ENABLE_EP4;   /* ep4  [00:1000] */
2292                         break;
2293                 case 1: /* Audio */
2294                         ep_mask = ENABLE_EP3;   /* ep3  [00:0100] */
2295                         break;
2296                 case 2: /* Vbi */
2297                         ep_mask = ENABLE_EP5;   /* ep5 [01:0000] */
2298                         break;
2299                 case 3: /* Sliced_cc */
2300                         ep_mask = ENABLE_EP6;   /* ep6 [10:0000] */
2301                         break;
2302                 case 4: /* ts1 */
2303                 case 6: /* ts1 parallel mode */
2304                         ep_mask = ENABLE_EP1;   /* ep1 [00:0001] */
2305                         break;
2306                 case 5: /* ts2 */
2307                         ep_mask = ENABLE_EP2;   /* ep2 [00:0010] */
2308                         break;
2309                 }
2310
2311         }
2312
2313         if (start) {
2314                 rc = cx231xx_initialize_stream_xfer(dev, media_type);
2315
2316                 if (rc < 0)
2317                         return rc;
2318
2319                 /* enable video capture */
2320                 if (ep_mask > 0)
2321                         rc = cx231xx_start_stream(dev, ep_mask);
2322         } else {
2323                 /* disable video capture */
2324                 if (ep_mask > 0)
2325                         rc = cx231xx_stop_stream(dev, ep_mask);
2326         }
2327
2328         if (dev->mode == CX231XX_ANALOG_MODE)
2329                 ;/* do any in Analog mode */
2330         else
2331                 ;/* do any in digital mode */
2332
2333         return rc;
2334 }
2335 EXPORT_SYMBOL_GPL(cx231xx_capture_start);
2336
2337 /*****************************************************************************
2338 *                   G P I O   B I T control functions                        *
2339 ******************************************************************************/
2340 int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val)
2341 {
2342         int status = 0;
2343
2344         status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0);
2345
2346         return status;
2347 }
2348
2349 int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val)
2350 {
2351         int status = 0;
2352
2353         status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1);
2354
2355         return status;
2356 }
2357
2358 /*
2359 * cx231xx_set_gpio_direction
2360 *      Sets the direction of the GPIO pin to input or output
2361 *
2362 * Parameters :
2363 *      pin_number : The GPIO Pin number to program the direction for
2364 *                   from 0 to 31
2365 *      pin_value : The Direction of the GPIO Pin under reference.
2366 *                      0 = Input direction
2367 *                      1 = Output direction
2368 */
2369 int cx231xx_set_gpio_direction(struct cx231xx *dev,
2370                                int pin_number, int pin_value)
2371 {
2372         int status = 0;
2373         u32 value = 0;
2374
2375         /* Check for valid pin_number - if 32 , bail out */
2376         if (pin_number >= 32)
2377                 return -EINVAL;
2378
2379         /* input */
2380         if (pin_value == 0)
2381                 value = dev->gpio_dir & (~(1 << pin_number));   /* clear */
2382         else
2383                 value = dev->gpio_dir | (1 << pin_number);
2384
2385         status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val);
2386
2387         /* cache the value for future */
2388         dev->gpio_dir = value;
2389
2390         return status;
2391 }
2392
2393 /*
2394 * cx231xx_set_gpio_value
2395 *      Sets the value of the GPIO pin to Logic high or low. The Pin under
2396 *      reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
2397 *
2398 * Parameters :
2399 *      pin_number : The GPIO Pin number to program the direction for
2400 *      pin_value : The value of the GPIO Pin under reference.
2401 *                      0 = set it to 0
2402 *                      1 = set it to 1
2403 */
2404 int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
2405 {
2406         int status = 0;
2407         u32 value = 0;
2408
2409         /* Check for valid pin_number - if 0xFF , bail out */
2410         if (pin_number >= 32)
2411                 return -EINVAL;
2412
2413         /* first do a sanity check - if the Pin is not output, make it output */
2414         if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
2415                 /* It was in input mode */
2416                 value = dev->gpio_dir | (1 << pin_number);
2417                 dev->gpio_dir = value;
2418                 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2419                                               (u8 *) &dev->gpio_val);
2420                 value = 0;
2421         }
2422
2423         if (pin_value == 0)
2424                 value = dev->gpio_val & (~(1 << pin_number));
2425         else
2426                 value = dev->gpio_val | (1 << pin_number);
2427
2428         /* store the value */
2429         dev->gpio_val = value;
2430
2431         /* toggle bit0 of GP_IO */
2432         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2433
2434         return status;
2435 }
2436
2437 /*****************************************************************************
2438 *                      G P I O I2C related functions                         *
2439 ******************************************************************************/
2440 int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2441 {
2442         int status = 0;
2443
2444         /* set SCL to output 1 ; set SDA to output 1 */
2445         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2446         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2447         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2448         dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2449
2450         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2451         if (status < 0)
2452                 return -EINVAL;
2453
2454         /* set SCL to output 1; set SDA to output 0 */
2455         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2456         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2457
2458         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2459         if (status < 0)
2460                 return -EINVAL;
2461
2462         /* set SCL to output 0; set SDA to output 0      */
2463         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2464         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2465
2466         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2467         if (status < 0)
2468                 return -EINVAL;
2469
2470         return status;
2471 }
2472
2473 int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2474 {
2475         int status = 0;
2476
2477         /* set SCL to output 0; set SDA to output 0      */
2478         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2479         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2480
2481         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2482         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2483
2484         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2485         if (status < 0)
2486                 return -EINVAL;
2487
2488         /* set SCL to output 1; set SDA to output 0      */
2489         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2490         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2491
2492         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2493         if (status < 0)
2494                 return -EINVAL;
2495
2496         /* set SCL to input ,release SCL cable control
2497            set SDA to input ,release SDA cable control */
2498         dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2499         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2500
2501         status =
2502             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2503         if (status < 0)
2504                 return -EINVAL;
2505
2506         return status;
2507 }
2508
2509 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2510 {
2511         int status = 0;
2512         u8 i;
2513
2514         /* set SCL to output ; set SDA to output */
2515         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2516         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2517
2518         for (i = 0; i < 8; i++) {
2519                 if (((data << i) & 0x80) == 0) {
2520                         /* set SCL to output 0; set SDA to output 0     */
2521                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2522                         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2523                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2524                                                       (u8 *)&dev->gpio_val);
2525
2526                         /* set SCL to output 1; set SDA to output 0     */
2527                         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2528                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2529                                                       (u8 *)&dev->gpio_val);
2530
2531                         /* set SCL to output 0; set SDA to output 0     */
2532                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2533                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2534                                                       (u8 *)&dev->gpio_val);
2535                 } else {
2536                         /* set SCL to output 0; set SDA to output 1     */
2537                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2538                         dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2539                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2540                                                       (u8 *)&dev->gpio_val);
2541
2542                         /* set SCL to output 1; set SDA to output 1     */
2543                         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2544                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2545                                                       (u8 *)&dev->gpio_val);
2546
2547                         /* set SCL to output 0; set SDA to output 1     */
2548                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2549                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2550                                                       (u8 *)&dev->gpio_val);
2551                 }
2552         }
2553         return status;
2554 }
2555
2556 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 * buf)
2557 {
2558         u8 value = 0;
2559         int status = 0;
2560         u32 gpio_logic_value = 0;
2561         u8 i;
2562
2563         /* read byte */
2564         for (i = 0; i < 8; i++) {       /* send write I2c addr */
2565
2566                 /* set SCL to output 0; set SDA to input */
2567                 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2568                 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2569                                               (u8 *)&dev->gpio_val);
2570
2571                 /* set SCL to output 1; set SDA to input */
2572                 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2573                 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2574                                               (u8 *)&dev->gpio_val);
2575
2576                 /* get SDA data bit */
2577                 gpio_logic_value = dev->gpio_val;
2578                 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2579                                               (u8 *)&dev->gpio_val);
2580                 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
2581                         value |= (1 << (8 - i - 1));
2582
2583                 dev->gpio_val = gpio_logic_value;
2584         }
2585
2586         /* set SCL to output 0,finish the read latest SCL signal.
2587            !!!set SDA to input, never to modify SDA direction at
2588            the same times */
2589         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2590         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2591
2592         /* store the value */
2593         *buf = value & 0xff;
2594
2595         return status;
2596 }
2597
2598 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2599 {
2600         int status = 0;
2601         u32 gpio_logic_value = 0;
2602         int nCnt = 10;
2603         int nInit = nCnt;
2604
2605         /* clock stretch; set SCL to input; set SDA to input;
2606            get SCL value till SCL = 1 */
2607         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2608         dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2609
2610         gpio_logic_value = dev->gpio_val;
2611         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2612
2613         do {
2614                 msleep(2);
2615                 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2616                                               (u8 *)&dev->gpio_val);
2617                 nCnt--;
2618         } while (((dev->gpio_val &
2619                           (1 << dev->board.tuner_scl_gpio)) == 0) &&
2620                          (nCnt > 0));
2621
2622         if (nCnt == 0)
2623                 cx231xx_info("No ACK after %d msec -GPIO I2C failed!",
2624                              nInit * 10);
2625
2626         /* readAck
2627            throuth clock stretch ,slave has given a SCL signal,
2628            so the SDA data can be directly read.  */
2629         status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2630
2631         if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
2632                 dev->gpio_val = gpio_logic_value;
2633                 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2634                 status = 0;
2635         } else {
2636                 dev->gpio_val = gpio_logic_value;
2637                 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
2638         }
2639
2640         /* read SDA end, set the SCL to output 0, after this operation,
2641            SDA direction can be changed. */
2642         dev->gpio_val = gpio_logic_value;
2643         dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
2644         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2645         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2646
2647         return status;
2648 }
2649
2650 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
2651 {
2652         int status = 0;
2653
2654         /* set SDA to ouput */
2655         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2656         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2657
2658         /* set SCL = 0 (output); set SDA = 0 (output) */
2659         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2660         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2661         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2662
2663         /* set SCL = 1 (output); set SDA = 0 (output) */
2664         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2665         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2666
2667         /* set SCL = 0 (output); set SDA = 0 (output) */
2668         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2669         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2670
2671         /* set SDA to input,and then the slave will read data from SDA. */
2672         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2673         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2674
2675         return status;
2676 }
2677
2678 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
2679 {
2680         int status = 0;
2681
2682         /* set scl to output ; set sda to input */
2683         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2684         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2685         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2686
2687         /* set scl to output 0; set sda to input */
2688         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2689         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2690
2691         /* set scl to output 1; set sda to input */
2692         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2693         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2694
2695         return status;
2696 }
2697
2698 /*****************************************************************************
2699 *                      G P I O I2C related functions                         *
2700 ******************************************************************************/
2701 /* cx231xx_gpio_i2c_read
2702  * Function to read data from gpio based I2C interface
2703  */
2704 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len)
2705 {
2706         int status = 0;
2707         int i = 0;
2708
2709         /* get the lock */
2710         mutex_lock(&dev->gpio_i2c_lock);
2711
2712         /* start */
2713         status = cx231xx_gpio_i2c_start(dev);
2714
2715         /* write dev_addr */
2716         status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
2717
2718         /* readAck */
2719         status = cx231xx_gpio_i2c_read_ack(dev);
2720
2721         /* read data */
2722         for (i = 0; i < len; i++) {
2723                 /* read data */
2724                 buf[i] = 0;
2725                 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
2726
2727                 if ((i + 1) != len) {
2728                         /* only do write ack if we more length */
2729                         status = cx231xx_gpio_i2c_write_ack(dev);
2730                 }
2731         }
2732
2733         /* write NAK - inform reads are complete */
2734         status = cx231xx_gpio_i2c_write_nak(dev);
2735
2736         /* write end */
2737         status = cx231xx_gpio_i2c_end(dev);
2738
2739         /* release the lock */
2740         mutex_unlock(&dev->gpio_i2c_lock);
2741
2742         return status;
2743 }
2744
2745 /* cx231xx_gpio_i2c_write
2746  * Function to write data to gpio based I2C interface
2747  */
2748 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len)
2749 {
2750         int status = 0;
2751         int i = 0;
2752
2753         /* get the lock */
2754         mutex_lock(&dev->gpio_i2c_lock);
2755
2756         /* start */
2757         status = cx231xx_gpio_i2c_start(dev);
2758
2759         /* write dev_addr */
2760         status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
2761
2762         /* read Ack */
2763         status = cx231xx_gpio_i2c_read_ack(dev);
2764
2765         for (i = 0; i < len; i++) {
2766                 /* Write data */
2767                 status = cx231xx_gpio_i2c_write_byte(dev, buf[i]);
2768
2769                 /* read Ack */
2770                 status = cx231xx_gpio_i2c_read_ack(dev);
2771         }
2772
2773         /* write End */
2774         status = cx231xx_gpio_i2c_end(dev);
2775
2776         /* release the lock */
2777         mutex_unlock(&dev->gpio_i2c_lock);
2778
2779         return 0;
2780 }