SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/media/dvb/ngene/ngene-core.c

   1 /*
   2  * ngene.c: nGene PCIe bridge driver
   3  *
   4  * Copyright (C) 2005-2007 Micronas
   5  *
   6  * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
   7  *                         Modifications for new nGene firmware,
   8  *                         support for EEPROM-copying,
   9  *                         support for new dual DVB-S2 card prototype
  10  *
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * version 2 only, as published by the Free Software Foundation.
  15  *
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  26  * 02110-1301, USA
  27  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  28  */
  29
  30 #include <linux/module.h>
  31 #include <linux/init.h>
  32 #include <linux/delay.h>
  33 #include <linux/slab.h>
  34 #include <linux/poll.h>
  35 #include <asm/io.h>
  36 #include <asm/div64.h>
  37 #include <linux/pci.h>
  38 #include <linux/pci_ids.h>
  39 #include <linux/smp_lock.h>
  40 #include <linux/timer.h>
  41 #include <linux/version.h>
  42 #include <linux/byteorder/generic.h>
  43 #include <linux/firmware.h>
  44
  45 #include "ngene.h"
  46
  47 #include "stv6110x.h"
  48 #include "stv090x.h"
  49 #include "lnbh24.h"
  50
  51 #ifdef NGENE_COMMAND_API
  52 #include "ngene-ioctls.h"
  53 #endif
  54
  55 static int copy_eeprom;
  56 module_param(copy_eeprom, int, 0444);
  57 MODULE_PARM_DESC(copy_eeprom, "Copy eeprom.");
  58
  59 static int debug;
  60 module_param(debug, int, 0444);
  61 MODULE_PARM_DESC(debug, "Print debugging information.");
  62
  63 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  64
  65 #define dprintk if (debug) printk
  66
  67 #define DEVICE_NAME "ngene"
  68
  69 #define ngwriteb(dat, adr)         writeb((dat), (char *)(dev->iomem + (adr)))
  70 #define ngwritel(dat, adr)         writel((dat), (char *)(dev->iomem + (adr)))
  71 #define ngwriteb(dat, adr)         writeb((dat), (char *)(dev->iomem + (adr)))
  72 #define ngreadl(adr)               readl(dev->iomem + (adr))
  73 #define ngreadb(adr)               readb(dev->iomem + (adr))
  74 #define ngcpyto(adr, src, count)   memcpy_toio((char *) \
  75                                    (dev->iomem + (adr)), (src), (count))
  76 #define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), (char *) \
  77                                    (dev->iomem + (adr)), (count))
  78
  79 /****************************************************************************/
  80 /* Functions with missing kernel exports ************************************/
  81 /****************************************************************************/
  82
  83 /* yeah, let's throw out all exports which are not used in kernel ... */
  84
  85 void my_dvb_ringbuffer_flush(struct dvb_ringbuffer *rbuf)
  86 {
  87         rbuf->pread = rbuf->pwrite;
  88         rbuf->error = 0;
  89 }
  90
  91 /****************************************************************************/
  92 /* nGene interrupt handler **************************************************/
  93 /****************************************************************************/
  94
  95 static void event_tasklet(unsigned long data)
  96 {
  97         struct ngene *dev = (struct ngene *)data;
  98
  99         while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) {
 100                 struct EVENT_BUFFER Event =
 101                         dev->EventQueue[dev->EventQueueReadIndex];
 102                 dev->EventQueueReadIndex =
 103                         (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1);
 104
 105                 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify))
 106                         dev->TxEventNotify(dev, Event.TimeStamp);
 107                 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify))
 108                         dev->RxEventNotify(dev, Event.TimeStamp,
 109                                            Event.RXCharacter);
 110         }
 111 }
 112
 113 static void demux_tasklet(unsigned long data)
 114 {
 115         struct ngene_channel *chan = (struct ngene_channel *)data;
 116         struct SBufferHeader *Cur = chan->nextBuffer;
 117
 118         spin_lock_irq(&chan->state_lock);
 119
 120         while (Cur->ngeneBuffer.SR.Flags & 0x80) {
 121                 if (chan->mode & NGENE_IO_TSOUT) {
 122                         u32 Flags = chan->DataFormatFlags;
 123                         if (Cur->ngeneBuffer.SR.Flags & 0x20)
 124                                 Flags |= BEF_OVERFLOW;
 125                         if (chan->pBufferExchange) {
 126                                 if (!chan->pBufferExchange(chan,
 127                                                            Cur->Buffer1,
 128                                                            chan->Capture1Length,
 129                                                            Cur->ngeneBuffer.SR.
 130                                                            Clock, Flags)) {
 131                                         /*
 132                                            We didn't get data
 133                                            Clear in service flag to make sure we
 134                                            get called on next interrupt again.
 135                                            leave fill/empty (0x80) flag alone
 136                                            to avoid hardware running out of
 137                                            buffers during startup, we hold only
 138                                            in run state ( the source may be late
 139                                            delivering data )
 140                                         */
 141
 142                                         if (chan->HWState == HWSTATE_RUN) {
 143                                                 Cur->ngeneBuffer.SR.Flags &=
 144                                                         ~0x40;
 145                                                 break;
 146                                                 /* Stop proccessing stream */
 147                                         }
 148                                 } else {
 149                                         /* We got a valid buffer,
 150                                            so switch to run state */
 151                                         chan->HWState = HWSTATE_RUN;
 152                                 }
 153                         } else {
 154                                 printk(KERN_ERR DEVICE_NAME ": OOPS\n");
 155                                 if (chan->HWState == HWSTATE_RUN) {
 156                                         Cur->ngeneBuffer.SR.Flags &= ~0x40;
 157                                         break;  /* Stop proccessing stream */
 158                                 }
 159                         }
 160                         if (chan->AudioDTOUpdated) {
 161                                 printk(KERN_INFO DEVICE_NAME
 162                                        ": Update AudioDTO = %d\n",
 163                                        chan->AudioDTOValue);
 164                                 Cur->ngeneBuffer.SR.DTOUpdate =
 165                                         chan->AudioDTOValue;
 166                                 chan->AudioDTOUpdated = 0;
 167                         }
 168                 } else {
 169                         if (chan->HWState == HWSTATE_RUN) {
 170                                 u32 Flags = 0;
 171                                 if (Cur->ngeneBuffer.SR.Flags & 0x01)
 172                                         Flags |= BEF_EVEN_FIELD;
 173                                 if (Cur->ngeneBuffer.SR.Flags & 0x20)
 174                                         Flags |= BEF_OVERFLOW;
 175                                 if (chan->pBufferExchange)
 176                                         chan->pBufferExchange(chan,
 177                                                               Cur->Buffer1,
 178                                                               chan->
 179                                                               Capture1Length,
 180                                                               Cur->ngeneBuffer.
 181                                                               SR.Clock, Flags);
 182                                 if (chan->pBufferExchange2)
 183                                         chan->pBufferExchange2(chan,
 184                                                                Cur->Buffer2,
 185                                                                chan->
 186                                                                Capture2Length,
 187                                                                Cur->ngeneBuffer.
 188                                                                SR.Clock, Flags);
 189                         } else if (chan->HWState != HWSTATE_STOP)
 190                                 chan->HWState = HWSTATE_RUN;
 191                 }
 192                 Cur->ngeneBuffer.SR.Flags = 0x00;
 193                 Cur = Cur->Next;
 194         }
 195         chan->nextBuffer = Cur;
 196
 197         spin_unlock_irq(&chan->state_lock);
 198 }
 199
 200 static irqreturn_t irq_handler(int irq, void *dev_id)
 201 {
 202         struct ngene *dev = (struct ngene *)dev_id;
 203         u32 icounts = 0;
 204         irqreturn_t rc = IRQ_NONE;
 205         u32 i = MAX_STREAM;
 206         u8 *tmpCmdDoneByte;
 207
 208         if (dev->BootFirmware) {
 209                 icounts = ngreadl(NGENE_INT_COUNTS);
 210                 if (icounts != dev->icounts) {
 211                         ngwritel(0, FORCE_NMI);
 212                         dev->cmd_done = 1;
 213                         wake_up(&dev->cmd_wq);
 214                         dev->icounts = icounts;
 215                         rc = IRQ_HANDLED;
 216                 }
 217                 return rc;
 218         }
 219
 220         ngwritel(0, FORCE_NMI);
 221
 222         spin_lock(&dev->cmd_lock);
 223         tmpCmdDoneByte = dev->CmdDoneByte;
 224         if (tmpCmdDoneByte &&
 225             (*tmpCmdDoneByte ||
 226             (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) {
 227                 dev->CmdDoneByte = NULL;
 228                 dev->cmd_done = 1;
 229                 wake_up(&dev->cmd_wq);
 230                 rc = IRQ_HANDLED;
 231         }
 232         spin_unlock(&dev->cmd_lock);
 233
 234         if (dev->EventBuffer->EventStatus & 0x80) {
 235                 u8 nextWriteIndex =
 236                         (dev->EventQueueWriteIndex + 1) &
 237                         (EVENT_QUEUE_SIZE - 1);
 238                 if (nextWriteIndex != dev->EventQueueReadIndex) {
 239                         dev->EventQueue[dev->EventQueueWriteIndex] =
 240                                 *(dev->EventBuffer);
 241                         dev->EventQueueWriteIndex = nextWriteIndex;
 242                 } else {
 243                         printk(KERN_ERR DEVICE_NAME ": event overflow\n");
 244                         dev->EventQueueOverflowCount += 1;
 245                         dev->EventQueueOverflowFlag = 1;
 246                 }
 247                 dev->EventBuffer->EventStatus &= ~0x80;
 248                 tasklet_schedule(&dev->event_tasklet);
 249                 rc = IRQ_HANDLED;
 250         }
 251
 252         while (i > 0) {
 253                 i--;
 254                 spin_lock(&dev->channel[i].state_lock);
 255                 /* if (dev->channel[i].State>=KSSTATE_RUN) { */
 256                 if (dev->channel[i].nextBuffer) {
 257                         if ((dev->channel[i].nextBuffer->
 258                              ngeneBuffer.SR.Flags & 0xC0) == 0x80) {
 259                                 dev->channel[i].nextBuffer->
 260                                         ngeneBuffer.SR.Flags |= 0x40;
 261                                 tasklet_schedule(
 262                                         &dev->channel[i].demux_tasklet);
 263                                 rc = IRQ_HANDLED;
 264                         }
 265                 }
 266                 spin_unlock(&dev->channel[i].state_lock);
 267         }
 268
 269         return rc;
 270 }
 271
 272 /****************************************************************************/
 273 /* nGene command interface **************************************************/
 274 /****************************************************************************/
 275
 276 static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com)
 277 {
 278         int ret;
 279         u8 *tmpCmdDoneByte;
 280
 281         dev->cmd_done = 0;
 282
 283         if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) {
 284                 dev->BootFirmware = 1;
 285                 dev->icounts = ngreadl(NGENE_INT_COUNTS);
 286                 ngwritel(0, NGENE_COMMAND);
 287                 ngwritel(0, NGENE_COMMAND_HI);
 288                 ngwritel(0, NGENE_STATUS);
 289                 ngwritel(0, NGENE_STATUS_HI);
 290                 ngwritel(0, NGENE_EVENT);
 291                 ngwritel(0, NGENE_EVENT_HI);
 292         } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) {
 293                 u64 fwio = dev->PAFWInterfaceBuffer;
 294
 295                 ngwritel(fwio & 0xffffffff, NGENE_COMMAND);
 296                 ngwritel(fwio >> 32, NGENE_COMMAND_HI);
 297                 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS);
 298                 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI);
 299                 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT);
 300                 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI);
 301         }
 302
 303         memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2);
 304
 305         if (dev->BootFirmware)
 306                 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2);
 307
 308         spin_lock_irq(&dev->cmd_lock);
 309         tmpCmdDoneByte = dev->ngenetohost + com->out_len;
 310         if (!com->out_len)
 311                 tmpCmdDoneByte++;
 312         *tmpCmdDoneByte = 0;
 313         dev->ngenetohost[0] = 0;
 314         dev->ngenetohost[1] = 0;
 315         dev->CmdDoneByte = tmpCmdDoneByte;
 316         spin_unlock_irq(&dev->cmd_lock);
 317
 318         /* Notify 8051. */
 319         ngwritel(1, FORCE_INT);
 320
 321         ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ);
 322         if (!ret) {
 323                 /*ngwritel(0, FORCE_NMI);*/
 324
 325                 printk(KERN_ERR DEVICE_NAME
 326                        ": Command timeout cmd=%02x prev=%02x\n",
 327                        com->cmd.hdr.Opcode, dev->prev_cmd);
 328                 return -1;
 329         }
 330         if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH)
 331                 dev->BootFirmware = 0;
 332
 333         dev->prev_cmd = com->cmd.hdr.Opcode;
 334         msleep(10);
 335
 336         if (!com->out_len)
 337                 return 0;
 338
 339         memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len);
 340
 341         return 0;
 342 }
 343
 344 static int ngene_command(struct ngene *dev, struct ngene_command *com)
 345 {
 346         int result;
 347
 348         down(&dev->cmd_mutex);
 349         result = ngene_command_mutex(dev, com);
 350         up(&dev->cmd_mutex);
 351         return result;
 352 }
 353
 354 int ngene_command_nop(struct ngene *dev)
 355 {
 356         struct ngene_command com;
 357
 358         com.cmd.hdr.Opcode = CMD_NOP;
 359         com.cmd.hdr.Length = 0;
 360         com.in_len = 0;
 361         com.out_len = 0;
 362
 363         return ngene_command(dev, &com);
 364 }
 365
 366 int ngene_command_i2c_read(struct ngene *dev, u8 adr,
 367                            u8 *out, u8 outlen, u8 *in, u8 inlen, int flag)
 368 {
 369         struct ngene_command com;
 370
 371         com.cmd.hdr.Opcode = CMD_I2C_READ;
 372         com.cmd.hdr.Length = outlen + 3;
 373         com.cmd.I2CRead.Device = adr << 1;
 374         memcpy(com.cmd.I2CRead.Data, out, outlen);
 375         com.cmd.I2CRead.Data[outlen] = inlen;
 376         com.cmd.I2CRead.Data[outlen + 1] = 0;
 377         com.in_len = outlen + 3;
 378         com.out_len = inlen + 1;
 379
 380         if (ngene_command(dev, &com) < 0)
 381                 return -EIO;
 382
 383         if ((com.cmd.raw8[0] >> 1) != adr)
 384                 return -EIO;
 385
 386         if (flag)
 387                 memcpy(in, com.cmd.raw8, inlen + 1);
 388         else
 389                 memcpy(in, com.cmd.raw8 + 1, inlen);
 390         return 0;
 391 }
 392
 393 int ngene_command_i2c_write(struct ngene *dev, u8 adr, u8 *out, u8 outlen)
 394 {
 395         struct ngene_command com;
 396
 397
 398         com.cmd.hdr.Opcode = CMD_I2C_WRITE;
 399         com.cmd.hdr.Length = outlen + 1;
 400         com.cmd.I2CRead.Device = adr << 1;
 401         memcpy(com.cmd.I2CRead.Data, out, outlen);
 402         com.in_len = outlen + 1;
 403         com.out_len = 1;
 404
 405         if (ngene_command(dev, &com) < 0)
 406                 return -EIO;
 407
 408         if (com.cmd.raw8[0] == 1)
 409                 return -EIO;
 410
 411         return 0;
 412 }
 413
 414 static int ngene_command_load_firmware(struct ngene *dev,
 415                                        u8 *ngene_fw, u32 size)
 416 {
 417 #define FIRSTCHUNK (1024)
 418         u32 cleft;
 419         struct ngene_command com;
 420
 421         com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE;
 422         com.cmd.hdr.Length = 0;
 423         com.in_len = 0;
 424         com.out_len = 0;
 425
 426         ngene_command(dev, &com);
 427
 428         cleft = (size + 3) & ~3;
 429         if (cleft > FIRSTCHUNK) {
 430                 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK,
 431                         cleft - FIRSTCHUNK);
 432                 cleft = FIRSTCHUNK;
 433         }
 434         ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft);
 435
 436         memset(&com, 0, sizeof(struct ngene_command));
 437         com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH;
 438         com.cmd.hdr.Length = 4;
 439         com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA;
 440         com.cmd.FWLoadFinish.Length = (unsigned short)cleft;
 441         com.in_len = 4;
 442         com.out_len = 0;
 443
 444         return ngene_command(dev, &com);
 445 }
 446
 447 int ngene_command_imem_read(struct ngene *dev, u8 adr, u8 *data, int type)
 448 {
 449         struct ngene_command com;
 450
 451         com.cmd.hdr.Opcode = type ? CMD_SFR_READ : CMD_IRAM_READ;
 452         com.cmd.hdr.Length = 1;
 453         com.cmd.SfrIramRead.address = adr;
 454         com.in_len = 1;
 455         com.out_len = 2;
 456
 457         if (ngene_command(dev, &com) < 0)
 458                 return -EIO;
 459
 460         *data = com.cmd.raw8[1];
 461         return 0;
 462 }
 463
 464 int ngene_command_imem_write(struct ngene *dev, u8 adr, u8 data, int type)
 465 {
 466         struct ngene_command com;
 467
 468         com.cmd.hdr.Opcode = type ? CMD_SFR_WRITE : CMD_IRAM_WRITE;
 469         com.cmd.hdr.Length = 2;
 470         com.cmd.SfrIramWrite.address = adr;
 471         com.cmd.SfrIramWrite.data = data;
 472         com.in_len = 2;
 473         com.out_len = 1;
 474
 475         if (ngene_command(dev, &com) < 0)
 476                 return -EIO;
 477
 478         return 0;
 479 }
 480
 481 static int ngene_command_config_uart(struct ngene *dev, u8 config,
 482                                      tx_cb_t *tx_cb, rx_cb_t *rx_cb)
 483 {
 484         struct ngene_command com;
 485
 486         com.cmd.hdr.Opcode = CMD_CONFIGURE_UART;
 487         com.cmd.hdr.Length = sizeof(struct FW_CONFIGURE_UART) - 2;
 488         com.cmd.ConfigureUart.UartControl = config;
 489         com.in_len = sizeof(struct FW_CONFIGURE_UART);
 490         com.out_len = 0;
 491
 492         if (ngene_command(dev, &com) < 0)
 493                 return -EIO;
 494
 495         dev->TxEventNotify = tx_cb;
 496         dev->RxEventNotify = rx_cb;
 497
 498         dprintk(KERN_DEBUG DEVICE_NAME ": Set UART config %02x.\n", config);
 499
 500         return 0;
 501 }
 502
 503 static void tx_cb(struct ngene *dev, u32 ts)
 504 {
 505         dev->tx_busy = 0;
 506         wake_up_interruptible(&dev->tx_wq);
 507 }
 508
 509 static void rx_cb(struct ngene *dev, u32 ts, u8 c)
 510 {
 511         int rp = dev->uart_rp;
 512         int nwp, wp = dev->uart_wp;
 513
 514         /* dprintk(KERN_DEBUG DEVICE_NAME ": %c\n", c); */
 515         nwp = (wp + 1) % (UART_RBUF_LEN);
 516         if (nwp == rp)
 517                 return;
 518         dev->uart_rbuf[wp] = c;
 519         dev->uart_wp = nwp;
 520         wake_up_interruptible(&dev->rx_wq);
 521 }
 522
 523 static int ngene_command_config_buf(struct ngene *dev, u8 config)
 524 {
 525         struct ngene_command com;
 526
 527         com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER;
 528         com.cmd.hdr.Length = 1;
 529         com.cmd.ConfigureBuffers.config = config;
 530         com.in_len = 1;
 531         com.out_len = 0;
 532
 533         if (ngene_command(dev, &com) < 0)
 534                 return -EIO;
 535         return 0;
 536 }
 537
 538 static int ngene_command_config_free_buf(struct ngene *dev, u8 *config)
 539 {
 540         struct ngene_command com;
 541
 542         com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
 543         com.cmd.hdr.Length = 6;
 544         memcpy(&com.cmd.ConfigureBuffers.config, config, 6);
 545         com.in_len = 6;
 546         com.out_len = 0;
 547
 548         if (ngene_command(dev, &com) < 0)
 549                 return -EIO;
 550
 551         return 0;
 552 }
 553
 554 static int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level)
 555 {
 556         struct ngene_command com;
 557
 558         com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN;
 559         com.cmd.hdr.Length = 1;
 560         com.cmd.SetGpioPin.select = select | (level << 7);
 561         com.in_len = 1;
 562         com.out_len = 0;
 563
 564         return ngene_command(dev, &com);
 565 }
 566
 567 /* The reset is only wired to GPIO4 on MicRacer Revision 1.10 !
 568    Also better set bootdelay to 1 in nvram or less. */
 569 static void ngene_reset_decypher(struct ngene *dev)
 570 {
 571         printk(KERN_INFO DEVICE_NAME ": Resetting Decypher.\n");
 572         ngene_command_gpio_set(dev, 4, 0);
 573         msleep(1);
 574         ngene_command_gpio_set(dev, 4, 1);
 575         msleep(2000);
 576 }
 577
 578 /*
 579  02000640 is sample on rising edge.
 580  02000740 is sample on falling edge.
 581  02000040 is ignore "valid" signal
 582
 583  0: FD_CTL1 Bit 7,6 must be 0,1
 584     7   disable(fw controlled)
 585     6   0-AUX,1-TS
 586     5   0-par,1-ser
 587     4   0-lsb/1-msb
 588     3,2 reserved
 589     1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
 590  1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
 591  2: FD_STA is read-only. 0-sync
 592  3: FD_INSYNC is number of 47s to trigger "in sync".
 593  4: FD_OUTSYNC is number of 47s to trigger "out of sync".
 594  5: FD_MAXBYTE1 is low-order of bytes per packet.
 595  6: FD_MAXBYTE2 is high-order of bytes per packet.
 596  7: Top byte is unused.
 597 */
 598
 599 /****************************************************************************/
 600
 601 static u8 TSFeatureDecoderSetup[8 * 4] = {
 602         0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
 603         0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
 604         0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
 605         0x72, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
 606 };
 607
 608 /* Set NGENE I2S Config to 16 bit packed */
 609 static u8 I2SConfiguration[] = {
 610         0x00, 0x10, 0x00, 0x00,
 611         0x80, 0x10, 0x00, 0x00,
 612 };
 613
 614 static u8 SPDIFConfiguration[10] = {
 615         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 616 };
 617
 618 /* Set NGENE I2S Config to transport stream compatible mode */
 619
 620 static u8 TS_I2SConfiguration[4] = { 0x3E, 0x1A, 0x00, 0x00 }; /*3e 18 00 00 ?*/
 621
 622 static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x20, 0x00, 0x00 };
 623
 624 static u8 ITUDecoderSetup[4][16] = {
 625         {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20,  /* SDTV */
 626          0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00},
 627         {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,
 628          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 629         {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00,  /* HDTV 1080i50 */
 630          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 631         {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,  /* HDTV 1080i60 */
 632          0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
 633 };
 634
 635 /*
 636  * 50 48 60 gleich
 637  * 27p50 9f 00 22 80 42 69 18 ...
 638  * 27p60 93 00 22 80 82 69 1c ...
 639  */
 640
 641 /* Maxbyte to 1144 (for raw data) */
 642 static u8 ITUFeatureDecoderSetup[8] = {
 643         0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00
 644 };
 645
 646 static void FillTSBuffer(void *Buffer, int Length, u32 Flags)
 647 {
 648         u32 *ptr = Buffer;
 649
 650         memset(Buffer, Length, 0xff);
 651         while (Length > 0) {
 652                 if (Flags & DF_SWAP32)
 653                         *ptr = 0x471FFF10;
 654                 else
 655                         *ptr = 0x10FF1F47;
 656                 ptr += (188 / 4);
 657                 Length -= 188;
 658         }
 659 }
 660
 661
 662 static void flush_buffers(struct ngene_channel *chan)
 663 {
 664         u8 val;
 665
 666         do {
 667                 msleep(1);
 668                 spin_lock_irq(&chan->state_lock);
 669                 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80;
 670                 spin_unlock_irq(&chan->state_lock);
 671         } while (val);
 672 }
 673
 674 static void clear_buffers(struct ngene_channel *chan)
 675 {
 676         struct SBufferHeader *Cur = chan->nextBuffer;
 677
 678         do {
 679                 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
 680                 if (chan->mode & NGENE_IO_TSOUT)
 681                         FillTSBuffer(Cur->Buffer1,
 682                                      chan->Capture1Length,
 683                                      chan->DataFormatFlags);
 684                 Cur = Cur->Next;
 685         } while (Cur != chan->nextBuffer);
 686
 687         if (chan->mode & NGENE_IO_TSOUT) {
 688                 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate =
 689                         chan->AudioDTOValue;
 690                 chan->AudioDTOUpdated = 0;
 691
 692                 Cur = chan->TSIdleBuffer.Head;
 693
 694                 do {
 695                         memset(&Cur->ngeneBuffer.SR, 0,
 696                                sizeof(Cur->ngeneBuffer.SR));
 697                         FillTSBuffer(Cur->Buffer1,
 698                                      chan->Capture1Length,
 699                                      chan->DataFormatFlags);
 700                         Cur = Cur->Next;
 701                 } while (Cur != chan->TSIdleBuffer.Head);
 702         }
 703 }
 704
 705 int ngene_command_stream_control(struct ngene *dev, u8 stream, u8 control,
 706                                  u8 mode, u8 flags)
 707 {
 708         struct ngene_channel *chan = &dev->channel[stream];
 709         struct ngene_command com;
 710         u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300);
 711         u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500);
 712         u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700);
 713         u16 BsSDO = 0x9B00;
 714
 715         /* down(&dev->stream_mutex); */
 716         while (down_trylock(&dev->stream_mutex)) {
 717                 printk(KERN_INFO DEVICE_NAME ": SC locked\n");
 718                 msleep(1);
 719         }
 720         memset(&com, 0, sizeof(com));
 721         com.cmd.hdr.Opcode = CMD_CONTROL;
 722         com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2;
 723         com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
 724         if (chan->mode & NGENE_IO_TSOUT)
 725                 com.cmd.StreamControl.Stream |= 0x07;
 726         com.cmd.StreamControl.Control = control |
 727                 (flags & SFLAG_ORDER_LUMA_CHROMA);
 728         com.cmd.StreamControl.Mode = mode;
 729         com.in_len = sizeof(struct FW_STREAM_CONTROL);
 730         com.out_len = 0;
 731
 732         printk(KERN_INFO DEVICE_NAME ": Stream=%02x, Control=%02x, Mode=%02x\n",
 733                com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control,
 734                com.cmd.StreamControl.Mode);
 735         chan->Mode = mode;
 736
 737         if (!(control & 0x80)) {
 738                 spin_lock_irq(&chan->state_lock);
 739                 if (chan->State == KSSTATE_RUN) {
 740                         chan->State = KSSTATE_ACQUIRE;
 741                         chan->HWState = HWSTATE_STOP;
 742                         spin_unlock_irq(&chan->state_lock);
 743                         if (ngene_command(dev, &com) < 0) {
 744                                 up(&dev->stream_mutex);
 745                                 return -1;
 746                         }
 747                         /* clear_buffers(chan); */
 748                         flush_buffers(chan);
 749                         up(&dev->stream_mutex);
 750                         return 0;
 751                 }
 752                 spin_unlock_irq(&chan->state_lock);
 753                 up(&dev->stream_mutex);
 754                 return 0;
 755         }
 756
 757         if (mode & SMODE_AUDIO_CAPTURE) {
 758                 com.cmd.StreamControl.CaptureBlockCount =
 759                         chan->Capture1Length / AUDIO_BLOCK_SIZE;
 760                 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
 761         } else if (mode & SMODE_TRANSPORT_STREAM) {
 762                 com.cmd.StreamControl.CaptureBlockCount =
 763                         chan->Capture1Length / TS_BLOCK_SIZE;
 764                 com.cmd.StreamControl.MaxLinesPerField =
 765                         chan->Capture1Length / TS_BLOCK_SIZE;
 766                 com.cmd.StreamControl.Buffer_Address =
 767                         chan->TSRingBuffer.PAHead;
 768                 if (chan->mode & NGENE_IO_TSOUT) {
 769                         com.cmd.StreamControl.BytesPerVBILine =
 770                                 chan->Capture1Length / TS_BLOCK_SIZE;
 771                         com.cmd.StreamControl.Stream |= 0x07;
 772                 }
 773         } else {
 774                 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine;
 775                 com.cmd.StreamControl.MaxLinesPerField = chan->nLines;
 776                 com.cmd.StreamControl.MinLinesPerField = 100;
 777                 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
 778
 779                 if (mode & SMODE_VBI_CAPTURE) {
 780                         com.cmd.StreamControl.MaxVBILinesPerField =
 781                                 chan->nVBILines;
 782                         com.cmd.StreamControl.MinVBILinesPerField = 0;
 783                         com.cmd.StreamControl.BytesPerVBILine =
 784                                 chan->nBytesPerVBILine;
 785                 }
 786                 if (flags & SFLAG_COLORBAR)
 787                         com.cmd.StreamControl.Stream |= 0x04;
 788         }
 789
 790         spin_lock_irq(&chan->state_lock);
 791         if (mode & SMODE_AUDIO_CAPTURE) {
 792                 chan->nextBuffer = chan->RingBuffer.Head;
 793                 if (mode & SMODE_AUDIO_SPDIF) {
 794                         com.cmd.StreamControl.SetupDataLen =
 795                                 sizeof(SPDIFConfiguration);
 796                         com.cmd.StreamControl.SetupDataAddr = BsSPI;
 797                         memcpy(com.cmd.StreamControl.SetupData,
 798                                SPDIFConfiguration, sizeof(SPDIFConfiguration));
 799                 } else {
 800                         com.cmd.StreamControl.SetupDataLen = 4;
 801                         com.cmd.StreamControl.SetupDataAddr = BsSDI;
 802                         memcpy(com.cmd.StreamControl.SetupData,
 803                                I2SConfiguration +
 804                                4 * dev->card_info->i2s[stream], 4);
 805                 }
 806         } else if (mode & SMODE_TRANSPORT_STREAM) {
 807                 chan->nextBuffer = chan->TSRingBuffer.Head;
 808                 if (stream >= STREAM_AUDIOIN1) {
 809                         if (chan->mode & NGENE_IO_TSOUT) {
 810                                 com.cmd.StreamControl.SetupDataLen =
 811                                         sizeof(TS_I2SOutConfiguration);
 812                                 com.cmd.StreamControl.SetupDataAddr = BsSDO;
 813                                 memcpy(com.cmd.StreamControl.SetupData,
 814                                        TS_I2SOutConfiguration,
 815                                        sizeof(TS_I2SOutConfiguration));
 816                         } else {
 817                                 com.cmd.StreamControl.SetupDataLen =
 818                                         sizeof(TS_I2SConfiguration);
 819                                 com.cmd.StreamControl.SetupDataAddr = BsSDI;
 820                                 memcpy(com.cmd.StreamControl.SetupData,
 821                                        TS_I2SConfiguration,
 822                                        sizeof(TS_I2SConfiguration));
 823                         }
 824                 } else {
 825                         com.cmd.StreamControl.SetupDataLen = 8;
 826                         com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10;
 827                         memcpy(com.cmd.StreamControl.SetupData,
 828                                TSFeatureDecoderSetup +
 829                                8 * dev->card_info->tsf[stream], 8);
 830                 }
 831         } else {
 832                 chan->nextBuffer = chan->RingBuffer.Head;
 833                 com.cmd.StreamControl.SetupDataLen =
 834                         16 + sizeof(ITUFeatureDecoderSetup);
 835                 com.cmd.StreamControl.SetupDataAddr = BsUVI;
 836                 memcpy(com.cmd.StreamControl.SetupData,
 837                        ITUDecoderSetup[chan->itumode], 16);
 838                 memcpy(com.cmd.StreamControl.SetupData + 16,
 839                        ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup));
 840         }
 841         clear_buffers(chan);
 842         chan->State = KSSTATE_RUN;
 843         if (mode & SMODE_TRANSPORT_STREAM)
 844                 chan->HWState = HWSTATE_RUN;
 845         else
 846                 chan->HWState = HWSTATE_STARTUP;
 847         spin_unlock_irq(&chan->state_lock);
 848
 849         if (ngene_command(dev, &com) < 0) {
 850                 up(&dev->stream_mutex);
 851                 return -1;
 852         }
 853         up(&dev->stream_mutex);
 854         return 0;
 855 }
 856
 857 int ngene_stream_control(struct ngene *dev, u8 stream, u8 control, u8 mode,
 858                          u16 lines, u16 bpl, u16 vblines, u16 vbibpl)
 859 {
 860         if (!(mode & SMODE_TRANSPORT_STREAM))
 861                 return -EINVAL;
 862
 863         if (lines * bpl > MAX_VIDEO_BUFFER_SIZE)
 864                 return -EINVAL;
 865
 866         if ((mode & SMODE_TRANSPORT_STREAM) && (((bpl * lines) & 0xff) != 0))
 867                 return -EINVAL;
 868
 869         if ((mode & SMODE_VIDEO_CAPTURE) && (bpl & 7) != 0)
 870                 return -EINVAL;
 871
 872         return ngene_command_stream_control(dev, stream, control, mode, 0);
 873 }
 874
 875 /****************************************************************************/
 876 /* I2C **********************************************************************/
 877 /****************************************************************************/
 878
 879 static void ngene_i2c_set_bus(struct ngene *dev, int bus)
 880 {
 881         if (!(dev->card_info->i2c_access & 2))
 882                 return;
 883         if (dev->i2c_current_bus == bus)
 884                 return;
 885
 886         switch (bus) {
 887         case 0:
 888                 ngene_command_gpio_set(dev, 3, 0);
 889                 ngene_command_gpio_set(dev, 2, 1);
 890                 break;
 891
 892         case 1:
 893                 ngene_command_gpio_set(dev, 2, 0);
 894                 ngene_command_gpio_set(dev, 3, 1);
 895                 break;
 896         }
 897         dev->i2c_current_bus = bus;
 898 }
 899
 900 static int ngene_i2c_master_xfer(struct i2c_adapter *adapter,
 901                                  struct i2c_msg msg[], int num)
 902 {
 903         struct ngene_channel *chan =
 904                 (struct ngene_channel *)i2c_get_adapdata(adapter);
 905         struct ngene *dev = chan->dev;
 906
 907         down(&dev->i2c_switch_mutex);
 908         ngene_i2c_set_bus(dev, chan->number);
 909
 910         if (num == 2 && msg[1].flags & I2C_M_RD && !(msg[0].flags & I2C_M_RD))
 911                 if (!ngene_command_i2c_read(dev, msg[0].addr,
 912                                             msg[0].buf, msg[0].len,
 913                                             msg[1].buf, msg[1].len, 0))
 914                         goto done;
 915
 916         if (num == 1 && !(msg[0].flags & I2C_M_RD))
 917                 if (!ngene_command_i2c_write(dev, msg[0].addr,
 918                                              msg[0].buf, msg[0].len))
 919                         goto done;
 920         if (num == 1 && (msg[0].flags & I2C_M_RD))
 921                 if (!ngene_command_i2c_read(dev, msg[0].addr, 0, 0,
 922                                             msg[0].buf, msg[0].len, 0))
 923                         goto done;
 924
 925         up(&dev->i2c_switch_mutex);
 926         return -EIO;
 927
 928 done:
 929         up(&dev->i2c_switch_mutex);
 930         return num;
 931 }
 932
 933
 934
 935 static u32 ngene_i2c_functionality(struct i2c_adapter *adap)
 936 {
 937         return I2C_FUNC_SMBUS_EMUL;
 938 }
 939
 940 struct i2c_algorithm ngene_i2c_algo = {
 941         .master_xfer = ngene_i2c_master_xfer,
 942         .functionality = ngene_i2c_functionality,
 943 };
 944
 945 static int ngene_i2c_init(struct ngene *dev, int dev_nr)
 946 {
 947         struct i2c_adapter *adap = &(dev->channel[dev_nr].i2c_adapter);
 948
 949         i2c_set_adapdata(adap, &(dev->channel[dev_nr]));
 950 #ifdef I2C_ADAP_CLASS_TV_DIGITAL
 951         adap->class = I2C_ADAP_CLASS_TV_DIGITAL | I2C_CLASS_TV_ANALOG;
 952 #else
 953         adap->class = I2C_CLASS_TV_ANALOG;
 954 #endif
 955
 956         strcpy(adap->name, "nGene");
 957
 958         adap->id = I2C_HW_SAA7146;
 959         adap->algo = &ngene_i2c_algo;
 960         adap->algo_data = (void *)&(dev->channel[dev_nr]);
 961
 962         mutex_init(&adap->bus_lock);
 963         return i2c_add_adapter(adap);
 964 }
 965
 966 int i2c_write(struct i2c_adapter *adapter, u8 adr, u8 data)
 967 {
 968         u8 m[1] = {data};
 969         struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 1};
 970
 971         if (i2c_transfer(adapter, &msg, 1) != 1) {
 972                 printk(KERN_ERR DEVICE_NAME
 973                        ": Failed to write to I2C adr %02x!\n", adr);
 974                 return -1;
 975         }
 976         return 0;
 977 }
 978
 979
 980 static int i2c_write_read(struct i2c_adapter *adapter,
 981                           u8 adr, u8 *w, u8 wlen, u8 *r, u8 rlen)
 982 {
 983         struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
 984                                    .buf = w, .len = wlen},
 985                                   {.addr = adr, .flags = I2C_M_RD,
 986                                    .buf = r, .len = rlen} };
 987
 988         if (i2c_transfer(adapter, msgs, 2) != 2) {
 989                 printk(KERN_ERR DEVICE_NAME ": error in i2c_write_read\n");
 990                 return -1;
 991         }
 992         return 0;
 993 }
 994
 995 static int test_dec_i2c(struct i2c_adapter *adapter, int reg)
 996 {
 997         u8 data[256] = { reg, 0x00, 0x93, 0x78, 0x43, 0x45 };
 998         u8 data2[256];
 999         int i;
1000
1001         memset(data2, 0, 256);
1002         i2c_write_read(adapter, 0x66, data, 2, data2, 4);
1003         for (i = 0; i < 4; i++)
1004                 printk("%02x ", data2[i]);
1005         printk("\n");
1006
1007         return 0;
1008 }
1009
1010
1011 /****************************************************************************/
1012 /* EEPROM TAGS **************************************************************/
1013 /****************************************************************************/
1014
1015 #define MICNG_EE_START      0x0100
1016 #define MICNG_EE_END        0x0FF0
1017
1018 #define MICNG_EETAG_END0    0x0000
1019 #define MICNG_EETAG_END1    0xFFFF
1020
1021 /* 0x0001 - 0x000F reserved for housekeeping */
1022 /* 0xFFFF - 0xFFFE reserved for housekeeping */
1023
1024 /* Micronas assigned tags
1025    EEProm tags for hardware support */
1026
1027 #define MICNG_EETAG_DRXD1_OSCDEVIATION  0x1000  /* 2 Bytes data */
1028 #define MICNG_EETAG_DRXD2_OSCDEVIATION  0x1001  /* 2 Bytes data */
1029
1030 #define MICNG_EETAG_MT2060_1_1STIF      0x1100  /* 2 Bytes data */
1031 #define MICNG_EETAG_MT2060_2_1STIF      0x1101  /* 2 Bytes data */
1032
1033 /* Tag range for OEMs */
1034
1035 #define MICNG_EETAG_OEM_FIRST  0xC000
1036 #define MICNG_EETAG_OEM_LAST   0xFFEF
1037
1038 static int i2c_write_eeprom(struct i2c_adapter *adapter,
1039                             u8 adr, u16 reg, u8 data)
1040 {
1041         u8 m[3] = {(reg >> 8), (reg & 0xff), data};
1042         struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m,
1043                               .len = sizeof(m)};
1044
1045         if (i2c_transfer(adapter, &msg, 1) != 1) {
1046                 dprintk(KERN_DEBUG DEVICE_NAME ": Error writing EEPROM!\n");
1047                 return -EIO;
1048         }
1049         return 0;
1050 }
1051
1052 static int i2c_read_eeprom(struct i2c_adapter *adapter,
1053                            u8 adr, u16 reg, u8 *data, int len)
1054 {
1055         u8 msg[2] = {(reg >> 8), (reg & 0xff)};
1056         struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
1057                                    .buf = msg, .len = 2 },
1058                                   {.addr = adr, .flags = I2C_M_RD,
1059                                    .buf = data, .len = len} };
1060
1061         if (i2c_transfer(adapter, msgs, 2) != 2) {
1062                 dprintk(KERN_DEBUG DEVICE_NAME ": Error reading EEPROM\n");
1063                 return -EIO;
1064         }
1065         return 0;
1066 }
1067
1068
1069 static int i2c_dump_eeprom(struct i2c_adapter *adapter, u8 adr)
1070 {
1071         u8 buf[64];
1072         int i;
1073
1074         if (i2c_read_eeprom(adapter, adr, 0x0000, buf, sizeof(buf))) {
1075                 printk(KERN_ERR DEVICE_NAME ": No EEPROM?\n");
1076                 return -1;
1077         }
1078         for (i = 0; i < sizeof(buf); i++) {
1079                 if (!(i & 15))
1080                         printk("\n");
1081                 printk("%02x ", buf[i]);
1082         }
1083         printk("\n");
1084
1085         return 0;
1086 }
1087
1088 static int i2c_copy_eeprom(struct i2c_adapter *adapter, u8 adr, u8 adr2)
1089 {
1090         u8 buf[64];
1091         int i;
1092
1093         if (i2c_read_eeprom(adapter, adr, 0x0000, buf, sizeof(buf))) {
1094                 printk(KERN_ERR DEVICE_NAME ": No EEPROM?\n");
1095                 return -1;
1096         }
1097         buf[36] = 0xc3;
1098         buf[39] = 0xab;
1099         for (i = 0; i < sizeof(buf); i++) {
1100                 i2c_write_eeprom(adapter, adr2, i, buf[i]);
1101                 msleep(10);
1102         }
1103         return 0;
1104 }
1105
1106
1107 /****************************************************************************/
1108 /* COMMAND API interface ****************************************************/
1109 /****************************************************************************/
1110
1111 #ifdef NGENE_COMMAND_API
1112
1113 static int command_do_ioctl(struct inode *inode, struct file *file,
1114                             unsigned int cmd, void *parg)
1115 {
1116         struct dvb_device *dvbdev = file->private_data;
1117         struct ngene_channel *chan = dvbdev->priv;
1118         struct ngene *dev = chan->dev;
1119         int err = 0;
1120
1121         switch (cmd) {
1122         case IOCTL_MIC_NO_OP:
1123                 err = ngene_command_nop(dev);
1124                 break;
1125
1126         case IOCTL_MIC_DOWNLOAD_FIRMWARE:
1127                 break;
1128
1129         case IOCTL_MIC_I2C_READ:
1130         {
1131                 MIC_I2C_READ *msg = parg;
1132
1133                 err = ngene_command_i2c_read(dev, msg->I2CAddress >> 1,
1134                                              msg->OutData, msg->OutLength,
1135                                              msg->OutData, msg->InLength, 1);
1136                 break;
1137         }
1138
1139         case IOCTL_MIC_I2C_WRITE:
1140         {
1141                 MIC_I2C_WRITE *msg = parg;
1142
1143                 err = ngene_command_i2c_write(dev, msg->I2CAddress >> 1,
1144                                               msg->Data, msg->Length);
1145                 break;
1146         }
1147
1148         case IOCTL_MIC_TEST_GETMEM:
1149         {
1150                 MIC_MEM *m = parg;
1151
1152                 if (m->Length > 64 * 1024 || m->Start + m->Length > 64 * 1024)
1153                         return -EINVAL;
1154
1155                 /* WARNING, only use this on x86,
1156                    other archs may not swallow this  */
1157                 err = copy_to_user(m->Data, dev->iomem + m->Start, m->Length);
1158                 break;
1159         }
1160
1161         case IOCTL_MIC_TEST_SETMEM:
1162         {
1163                 MIC_MEM *m = parg;
1164
1165                 if (m->Length > 64 * 1024 || m->Start + m->Length > 64 * 1024)
1166                         return -EINVAL;
1167
1168                 err = copy_from_user(dev->iomem + m->Start, m->Data, m->Length);
1169                 break;
1170         }
1171
1172         case IOCTL_MIC_SFR_READ:
1173         {
1174                 MIC_IMEM *m = parg;
1175
1176                 err = ngene_command_imem_read(dev, m->Address, &m->Data, 1);
1177                 break;
1178         }
1179
1180         case IOCTL_MIC_SFR_WRITE:
1181         {
1182                 MIC_IMEM *m = parg;
1183
1184                 err = ngene_command_imem_write(dev, m->Address, m->Data, 1);
1185                 break;
1186         }
1187
1188         case IOCTL_MIC_IRAM_READ:
1189         {
1190                 MIC_IMEM *m = parg;
1191
1192                 err = ngene_command_imem_read(dev, m->Address, &m->Data, 0);
1193                 break;
1194         }
1195
1196         case IOCTL_MIC_IRAM_WRITE:
1197         {
1198                 MIC_IMEM *m = parg;
1199
1200                 err = ngene_command_imem_write(dev, m->Address, m->Data, 0);
1201                 break;
1202         }
1203
1204         case IOCTL_MIC_STREAM_CONTROL:
1205         {
1206                 MIC_STREAM_CONTROL *m = parg;
1207
1208                 err = ngene_stream_control(dev, m->Stream, m->Control, m->Mode,
1209                                            m->nLines, m->nBytesPerLine,
1210                                            m->nVBILines, m->nBytesPerVBILine);
1211                 break;
1212         }
1213
1214         default:
1215                 err = -EINVAL;
1216                 break;
1217         }
1218         return err;
1219 }
1220
1221 static int command_ioctl(struct inode *inode, struct file *file,
1222                          unsigned int cmd, unsigned long arg)
1223 {
1224         void *parg = (void *)arg, *pbuf = NULL;
1225         char  buf[64];
1226         int   res = -EFAULT;
1227
1228         if (_IOC_DIR(cmd) & _IOC_WRITE) {
1229                 parg = buf;
1230                 if (_IOC_SIZE(cmd) > sizeof(buf)) {
1231                         pbuf = kmalloc(_IOC_SIZE(cmd), GFP_KERNEL);
1232                         if (!pbuf)
1233                                 return -ENOMEM;
1234                         parg = pbuf;
1235                 }
1236                 if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd)))
1237                         goto error;
1238         }
1239         res = command_do_ioctl(inode, file, cmd, parg);
1240         if (res < 0)
1241                 goto error;
1242         if (_IOC_DIR(cmd) & _IOC_READ)
1243                 if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd)))
1244                         res = -EFAULT;
1245 error:
1246         kfree(pbuf);
1247         return res;
1248 }
1249
1250 struct page *ngene_nopage(struct vm_area_struct *vma,
1251                           unsigned long address, int *type)
1252 {
1253         return 0;
1254 }
1255
1256 static int ngene_mmap(struct file *file, struct vm_area_struct *vma)
1257 {
1258         struct dvb_device *dvbdev = file->private_data;
1259         struct ngene_channel *chan = dvbdev->priv;
1260         struct ngene *dev = chan->dev;
1261
1262         unsigned long size = vma->vm_end - vma->vm_start;
1263         unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
1264         unsigned long padr = pci_resource_start(dev->pci_dev, 0) + off;
1265         unsigned long psize = pci_resource_len(dev->pci_dev, 0) - off;
1266
1267         if (size > psize)
1268                 return -EINVAL;
1269
1270         if (io_remap_pfn_range(vma, vma->vm_start, padr >> PAGE_SHIFT, size,
1271                                vma->vm_page_prot))
1272                 return -EAGAIN;
1273         return 0;
1274 }
1275
1276 static int write_uart(struct ngene *dev, u8 *data, int len)
1277 {
1278         struct ngene_command com;
1279
1280         com.cmd.hdr.Opcode = CMD_WRITE_UART;
1281         com.cmd.hdr.Length = len;
1282         memcpy(com.cmd.WriteUart.Data, data, len);
1283         com.cmd.WriteUart.Data[len] = 0;
1284         com.cmd.WriteUart.Data[len + 1] = 0;
1285         com.in_len = len;
1286         com.out_len = 0;
1287
1288         if (ngene_command(dev, &com) < 0)
1289                 return -EIO;
1290
1291         return 0;
1292 }
1293
1294 static int send_cli(struct ngene *dev, char *cmd)
1295 {
1296         /* printk(KERN_INFO DEVICE_NAME ": %s", cmd); */
1297         return write_uart(dev, cmd, strlen(cmd));
1298 }
1299
1300 static int send_cli_val(struct ngene *dev, char *cmd, u32 val)
1301 {
1302         char s[32];
1303
1304         snprintf(s, 32, "%s %d\n", cmd, val);
1305         /* printk(KERN_INFO DEVICE_NAME ": %s", s); */
1306         return write_uart(dev, s, strlen(s));
1307 }
1308
1309 static int ngene_command_write_uart_user(struct ngene *dev,
1310                                          const u8 *data, int len)
1311 {
1312         struct ngene_command com;
1313
1314         dev->tx_busy = 1;
1315         com.cmd.hdr.Opcode = CMD_WRITE_UART;
1316         com.cmd.hdr.Length = len;
1317
1318         if (copy_from_user(com.cmd.WriteUart.Data, data, len))
1319                 return -EFAULT;
1320         com.in_len = len;
1321         com.out_len = 0;
1322
1323         if (ngene_command(dev, &com) < 0)
1324                 return -EIO;
1325
1326         return 0;
1327 }
1328
1329 static ssize_t uart_write(struct file *file, const char *buf,
1330                           size_t count, loff_t *ppos)
1331 {
1332         struct dvb_device *dvbdev = file->private_data;
1333         struct ngene_channel *chan = dvbdev->priv;
1334         struct ngene *dev = chan->dev;
1335         int len, ret = 0;
1336         size_t left = count;
1337
1338         while (left) {
1339                 len = left;
1340                 if (len > 250)
1341                         len = 250;
1342                 ret = wait_event_interruptible(dev->tx_wq, dev->tx_busy == 0);
1343                 if (ret < 0)
1344                         return ret;
1345                 ngene_command_write_uart_user(dev, buf, len);
1346                 left -= len;
1347                 buf += len;
1348         }
1349         return count;
1350 }
1351
1352 static ssize_t ts_write(struct file *file, const char *buf,
1353                         size_t count, loff_t *ppos)
1354 {
1355         struct dvb_device *dvbdev = file->private_data;
1356         struct ngene_channel *chan = dvbdev->priv;
1357         struct ngene *dev = chan->dev;
1358
1359         if (wait_event_interruptible(dev->tsout_rbuf.queue,
1360                                      dvb_ringbuffer_free
1361                                      (&dev->tsout_rbuf) >= count) < 0)
1362                 return 0;
1363
1364         dvb_ringbuffer_write(&dev->tsout_rbuf, buf, count);
1365
1366         return count;
1367 }
1368
1369 static ssize_t uart_read(struct file *file, char *buf,
1370                          size_t count, loff_t *ppos)
1371 {
1372         struct dvb_device *dvbdev = file->private_data;
1373         struct ngene_channel *chan = dvbdev->priv;
1374         struct ngene *dev = chan->dev;
1375         int left;
1376         int wp, rp, avail, len;
1377
1378         if (!dev->uart_rbuf)
1379                 return -EINVAL;
1380         if (count > 128)
1381                 count = 128;
1382         left = count;
1383         while (left) {
1384                 if (wait_event_interruptible(dev->rx_wq,
1385                                              dev->uart_wp != dev->uart_rp) < 0)
1386                         return -EAGAIN;
1387                 wp = dev->uart_wp;
1388                 rp = dev->uart_rp;
1389                 avail = (wp - rp);
1390
1391                 if (avail < 0)
1392                         avail += UART_RBUF_LEN;
1393                 if (avail > left)
1394                         avail = left;
1395                 if (wp < rp) {
1396                         len = UART_RBUF_LEN - rp;
1397                         if (len > avail)
1398                                 len = avail;
1399                         if (copy_to_user(buf, dev->uart_rbuf + rp, len))
1400                                 return -EFAULT;
1401                         if (len < avail)
1402                                 if (copy_to_user(buf + len, dev->uart_rbuf,
1403                                                  avail - len))
1404                                         return -EFAULT;
1405                 } else {
1406                         if (copy_to_user(buf, dev->uart_rbuf + rp, avail))
1407                                 return -EFAULT;
1408                 }
1409                 dev->uart_rp = (rp + avail) % UART_RBUF_LEN;
1410                 left -= avail;
1411                 buf += avail;
1412         }
1413         return count;
1414 }
1415
1416 static const struct file_operations command_fops = {
1417         .owner   = THIS_MODULE,
1418         .read    = uart_read,
1419         .write   = ts_write,
1420         .ioctl   = command_ioctl,
1421         .open    = dvb_generic_open,
1422         .release = dvb_generic_release,
1423         .poll    = 0,
1424         .mmap    = ngene_mmap,
1425 };
1426
1427 static struct dvb_device dvbdev_command = {
1428         .priv    = 0,
1429         .readers = -1,
1430         .writers = -1,
1431         .users   = -1,
1432         .fops    = &command_fops,
1433 };
1434
1435 #endif
1436
1437 /****************************************************************************/
1438 /* DVB functions and API interface ******************************************/
1439 /****************************************************************************/
1440
1441 static void swap_buffer(u32 *p, u32 len)
1442 {
1443         while (len) {
1444                 *p = swab32(*p);
1445                 p++;
1446                 len -= 4;
1447         }
1448 }
1449
1450
1451 static void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags)
1452 {
1453         struct ngene_channel *chan = priv;
1454
1455
1456         dvb_dmx_swfilter(&chan->demux, buf, len);
1457         return 0;
1458 }
1459
1460 u8 fill_ts[188] = { 0x47, 0x1f, 0xff, 0x10 };
1461
1462 static void *tsout_exchange(void *priv, void *buf, u32 len,
1463                             u32 clock, u32 flags)
1464 {
1465         struct ngene_channel *chan = priv;
1466         struct ngene *dev = chan->dev;
1467         u32 alen;
1468
1469         alen = dvb_ringbuffer_avail(&dev->tsout_rbuf);
1470         alen -= alen % 188;
1471
1472         if (alen < len)
1473                 FillTSBuffer(buf + alen, len - alen, flags);
1474         else
1475                 alen = len;
1476         dvb_ringbuffer_read(&dev->tsout_rbuf, buf, alen);
1477         if (flags & DF_SWAP32)
1478                 swap_buffer((u32 *)buf, alen);
1479         wake_up_interruptible(&dev->tsout_rbuf.queue);
1480         return buf;
1481 }
1482
1483
1484 static void set_transfer(struct ngene_channel *chan, int state)
1485 {
1486         u8 control = 0, mode = 0, flags = 0;
1487         struct ngene *dev = chan->dev;
1488         int ret;
1489
1490         /*
1491         if (chan->running)
1492                 return;
1493         */
1494
1495         /*
1496         printk(KERN_INFO DEVICE_NAME ": st %d\n", state);
1497         msleep(100);
1498         */
1499
1500         if (state) {
1501                 if (chan->running) {
1502                         printk(KERN_INFO DEVICE_NAME ": already running\n");
1503                         return;
1504                 }
1505         } else {
1506                 if (!chan->running) {
1507                         printk(KERN_INFO DEVICE_NAME ": already stopped\n");
1508                         return;
1509                 }
1510         }
1511
1512         if (dev->card_info->switch_ctrl)
1513                 dev->card_info->switch_ctrl(chan, 1, state ^ 1);
1514
1515         if (state) {
1516                 spin_lock_irq(&chan->state_lock);
1517
1518                 /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
1519                           ngreadl(0x9310)); */
1520                 my_dvb_ringbuffer_flush(&dev->tsout_rbuf);
1521                 control = 0x80;
1522                 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1523                         chan->Capture1Length = 512 * 188;
1524                         mode = SMODE_TRANSPORT_STREAM;
1525                 }
1526                 if (chan->mode & NGENE_IO_TSOUT) {
1527                         chan->pBufferExchange = tsout_exchange;
1528                         /* 0x66666666 = 50MHz *2^33 /250MHz */
1529                         chan->AudioDTOValue = 0x66666666;
1530                         /* set_dto(chan, 38810700+1000); */
1531                         /* set_dto(chan, 19392658); */
1532                 }
1533                 if (chan->mode & NGENE_IO_TSIN)
1534                         chan->pBufferExchange = tsin_exchange;
1535                 /* ngwritel(0, 0x9310); */
1536                 spin_unlock_irq(&chan->state_lock);
1537         } else
1538                 ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
1539                            ngreadl(0x9310)); */
1540
1541         ret = ngene_command_stream_control(dev, chan->number,
1542                                            control, mode, flags);
1543         if (!ret)
1544                 chan->running = state;
1545         else
1546                 printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n",
1547                        state);
1548         if (!state) {
1549                 spin_lock_irq(&chan->state_lock);
1550                 chan->pBufferExchange = 0;
1551                 my_dvb_ringbuffer_flush(&dev->tsout_rbuf);
1552                 spin_unlock_irq(&chan->state_lock);
1553         }
1554 }
1555
1556 static int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed)
1557 {
1558         struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
1559         struct ngene_channel *chan = dvbdmx->priv;
1560 #ifdef NGENE_COMMAND_API
1561         struct ngene *dev = chan->dev;
1562
1563         if (dev->card_info->io_type[chan->number] & NGENE_IO_TSOUT) {
1564                 switch (dvbdmxfeed->pes_type) {
1565                 case DMX_TS_PES_VIDEO:
1566                         send_cli_val(dev, "vpid", dvbdmxfeed->pid);
1567                         send_cli(dev, "res 1080i50\n");
1568                         /* send_cli(dev, "vdec mpeg2\n"); */
1569                         break;
1570
1571                 case DMX_TS_PES_AUDIO:
1572                         send_cli_val(dev, "apid", dvbdmxfeed->pid);
1573                         send_cli(dev, "start\n");
1574                         break;
1575
1576                 case DMX_TS_PES_PCR:
1577                         send_cli_val(dev, "pcrpid", dvbdmxfeed->pid);
1578                         break;
1579
1580                 default:
1581                         break;
1582                 }
1583
1584         }
1585 #endif
1586
1587         if (chan->users == 0) {
1588                 set_transfer(chan, 1);
1589                 /* msleep(10); */
1590         }
1591
1592         return ++chan->users;
1593 }
1594
1595 static int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
1596 {
1597         struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
1598         struct ngene_channel *chan = dvbdmx->priv;
1599 #ifdef NGENE_COMMAND_API
1600         struct ngene *dev = chan->dev;
1601
1602         if (dev->card_info->io_type[chan->number] & NGENE_IO_TSOUT) {
1603                 switch (dvbdmxfeed->pes_type) {
1604                 case DMX_TS_PES_VIDEO:
1605                         send_cli(dev, "stop\n");
1606                         break;
1607
1608                 case DMX_TS_PES_AUDIO:
1609                         break;
1610
1611                 case DMX_TS_PES_PCR:
1612                         break;
1613
1614                 default:
1615                         break;
1616                 }
1617
1618         }
1619 #endif
1620
1621         if (--chan->users)
1622                 return chan->users;
1623
1624         set_transfer(chan, 0);
1625
1626         return 0;
1627 }
1628
1629
1630
1631 static int write_to_decoder(struct dvb_demux_feed *feed,
1632                             const u8 *buf, size_t len)
1633 {
1634         struct dvb_demux *dvbdmx = feed->demux;
1635         struct ngene_channel *chan = dvbdmx->priv;
1636         struct ngene *dev = chan->dev;
1637
1638         if (wait_event_interruptible(dev->tsout_rbuf.queue,
1639                                      dvb_ringbuffer_free
1640                                      (&dev->tsout_rbuf) >= len) < 0)
1641                 return 0;
1642
1643         dvb_ringbuffer_write(&dev->tsout_rbuf, buf, len);
1644
1645         return len;
1646 }
1647
1648 static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
1649                                    int (*start_feed)(struct dvb_demux_feed *),
1650                                    int (*stop_feed)(struct dvb_demux_feed *),
1651                                    void *priv)
1652 {
1653         dvbdemux->priv = priv;
1654
1655         dvbdemux->filternum = 256;
1656         dvbdemux->feednum = 256;
1657         dvbdemux->start_feed = start_feed;
1658         dvbdemux->stop_feed = stop_feed;
1659         dvbdemux->write_to_decoder = 0;
1660         dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
1661                                       DMX_SECTION_FILTERING |
1662                                       DMX_MEMORY_BASED_FILTERING);
1663         return dvb_dmx_init(dvbdemux);
1664 }
1665
1666 static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
1667                                       struct dvb_demux *dvbdemux,
1668                                       struct dmx_frontend *hw_frontend,
1669                                       struct dmx_frontend *mem_frontend,
1670                                       struct dvb_adapter *dvb_adapter)
1671 {
1672         int ret;
1673
1674         dmxdev->filternum = 256;
1675         dmxdev->demux = &dvbdemux->dmx;
1676         dmxdev->capabilities = 0;
1677         ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
1678         if (ret < 0)
1679                 return ret;
1680
1681         hw_frontend->source = DMX_FRONTEND_0;
1682         dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
1683         mem_frontend->source = DMX_MEMORY_FE;
1684         dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
1685         return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
1686 }
1687
1688 /****************************************************************************/
1689 /* Decypher firmware loading ************************************************/
1690 /****************************************************************************/
1691
1692 #define DECYPHER_FW "decypher.fw"
1693
1694 static int dec_ts_send(struct ngene *dev, u8 *buf, u32 len)
1695 {
1696         while (dvb_ringbuffer_free(&dev->tsout_rbuf) < len)
1697                 msleep(1);
1698
1699
1700         dvb_ringbuffer_write(&dev->tsout_rbuf, buf, len);
1701
1702         return len;
1703 }
1704
1705 u8 dec_fw_fill_ts[188] = { 0x47, 0x09, 0x0e, 0x10, 0xff, 0xff, 0x00, 0x00 };
1706
1707 int dec_fw_send(struct ngene *dev, u8 *fw, u32 size)
1708 {
1709         struct ngene_channel *chan = &dev->channel[4];
1710         u32 len = 180, cc = 0;
1711         u8 buf[8] = { 0x47, 0x09, 0x0e, 0x10, 0x00, 0x00, 0x00, 0x00 };
1712
1713         set_transfer(chan, 1);
1714         msleep(100);
1715         while (size) {
1716                 len = 180;
1717                 if (len > size)
1718                         len = size;
1719                 buf[3] = 0x10 | (cc & 0x0f);
1720                 buf[4] = (cc >> 8);
1721                 buf[5] = cc & 0xff;
1722                 buf[6] = len;
1723
1724                 dec_ts_send(dev, buf, 8);
1725                 dec_ts_send(dev, fw, len);
1726                 if (len < 180)
1727                         dec_ts_send(dev, dec_fw_fill_ts + len + 8, 180 - len);
1728                 cc++;
1729                 size -= len;
1730                 fw += len;
1731         }
1732         for (len = 0; len < 512; len++)
1733                 dec_ts_send(dev, dec_fw_fill_ts, 188);
1734         while (dvb_ringbuffer_avail(&dev->tsout_rbuf))
1735                 msleep(10);
1736         msleep(100);
1737         set_transfer(chan, 0);
1738         return 0;
1739 }
1740
1741 int dec_fw_boot(struct ngene *dev)
1742 {
1743         u32 size;
1744         const struct firmware *fw = NULL;
1745         u8 *dec_fw;
1746
1747         if (request_firmware(&fw, DECYPHER_FW, &dev->pci_dev->dev) < 0) {
1748                 printk(KERN_ERR DEVICE_NAME
1749                        ": %s not found. Check hotplug directory.\n",
1750                        DECYPHER_FW);
1751                 return -1;
1752         }
1753         printk(KERN_INFO DEVICE_NAME ": Booting decypher firmware file %s\n",
1754                DECYPHER_FW);
1755
1756         size = fw->size;
1757         dec_fw = (u8 *)fw->data;
1758         dec_fw_send(dev, dec_fw, size);
1759         release_firmware(fw);
1760         return 0;
1761 }
1762
1763 /****************************************************************************/
1764 /* nGene hardware init and release functions ********************************/
1765 /****************************************************************************/
1766
1767 void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb)
1768 {
1769         struct SBufferHeader *Cur = rb->Head;
1770         u32 j;
1771
1772         if (!Cur)
1773                 return;
1774
1775         for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) {
1776                 if (Cur->Buffer1)
1777                         pci_free_consistent(dev->pci_dev,
1778                                             rb->Buffer1Length,
1779                                             Cur->Buffer1,
1780                                             Cur->scList1->Address);
1781
1782                 if (Cur->Buffer2)
1783                         pci_free_consistent(dev->pci_dev,
1784                                             rb->Buffer2Length,
1785                                             Cur->Buffer2,
1786                                             Cur->scList2->Address);
1787         }
1788
1789         if (rb->SCListMem)
1790                 pci_free_consistent(dev->pci_dev, rb->SCListMemSize,
1791                                     rb->SCListMem, rb->PASCListMem);
1792
1793         pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead);
1794 }
1795
1796 void free_idlebuffer(struct ngene *dev,
1797                      struct SRingBufferDescriptor *rb,
1798                      struct SRingBufferDescriptor *tb)
1799 {
1800         int j;
1801         struct SBufferHeader *Cur = tb->Head;
1802
1803         if (!rb->Head)
1804                 return;
1805         free_ringbuffer(dev, rb);
1806         for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) {
1807                 Cur->Buffer2 = 0;
1808                 Cur->scList2 = 0;
1809                 Cur->ngeneBuffer.Address_of_first_entry_2 = 0;
1810                 Cur->ngeneBuffer.Number_of_entries_2 = 0;
1811         }
1812 }
1813
1814 void free_common_buffers(struct ngene *dev)
1815 {
1816         u32 i;
1817         struct ngene_channel *chan;
1818
1819         for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1820                 chan = &dev->channel[i];
1821                 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer);
1822                 free_ringbuffer(dev, &chan->RingBuffer);
1823                 free_ringbuffer(dev, &chan->TSRingBuffer);
1824         }
1825
1826         if (dev->OverflowBuffer)
1827                 pci_free_consistent(dev->pci_dev,
1828                                     OVERFLOW_BUFFER_SIZE,
1829                                     dev->OverflowBuffer, dev->PAOverflowBuffer);
1830
1831         if (dev->FWInterfaceBuffer)
1832                 pci_free_consistent(dev->pci_dev,
1833                                     4096,
1834                                     dev->FWInterfaceBuffer,
1835                                     dev->PAFWInterfaceBuffer);
1836 }
1837
1838 /****************************************************************************/
1839 /* Ring buffer handling *****************************************************/
1840 /****************************************************************************/
1841
1842 int create_ring_buffer(struct pci_dev *pci_dev,
1843                        struct SRingBufferDescriptor *descr, u32 NumBuffers)
1844 {
1845         dma_addr_t tmp;
1846         struct SBufferHeader *Head;
1847         u32 i;
1848         u32 MemSize = SIZEOF_SBufferHeader * NumBuffers;
1849         u64 PARingBufferHead;
1850         u64 PARingBufferCur;
1851         u64 PARingBufferNext;
1852         struct SBufferHeader *Cur, *Next;
1853
1854         descr->Head = 0;
1855         descr->MemSize = 0;
1856         descr->PAHead = 0;
1857         descr->NumBuffers = 0;
1858
1859         if (MemSize < 4096)
1860                 MemSize = 4096;
1861
1862         Head = pci_alloc_consistent(pci_dev, MemSize, &tmp);
1863         PARingBufferHead = tmp;
1864
1865         if (!Head)
1866                 return -ENOMEM;
1867
1868         memset(Head, 0, MemSize);
1869
1870         PARingBufferCur = PARingBufferHead;
1871         Cur = Head;
1872
1873         for (i = 0; i < NumBuffers - 1; i++) {
1874                 Next = (struct SBufferHeader *)
1875                         (((u8 *) Cur) + SIZEOF_SBufferHeader);
1876                 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader;
1877                 Cur->Next = Next;
1878                 Cur->ngeneBuffer.Next = PARingBufferNext;
1879                 Cur = Next;
1880                 PARingBufferCur = PARingBufferNext;
1881         }
1882         /* Last Buffer points back to first one */
1883         Cur->Next = Head;
1884         Cur->ngeneBuffer.Next = PARingBufferHead;
1885
1886         descr->Head       = Head;
1887         descr->MemSize    = MemSize;
1888         descr->PAHead     = PARingBufferHead;
1889         descr->NumBuffers = NumBuffers;
1890
1891         return 0;
1892 }
1893
1894 static int AllocateRingBuffers(struct pci_dev *pci_dev,
1895                                dma_addr_t of,
1896                                struct SRingBufferDescriptor *pRingBuffer,
1897                                u32 Buffer1Length, u32 Buffer2Length)
1898 {
1899         dma_addr_t tmp;
1900         u32 i, j;
1901         int status = 0;
1902         u32 SCListMemSize = pRingBuffer->NumBuffers
1903                 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) :
1904                     NUM_SCATTER_GATHER_ENTRIES)
1905                 * sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1906
1907         u64 PASCListMem;
1908         PHW_SCATTER_GATHER_ELEMENT SCListEntry;
1909         u64 PASCListEntry;
1910         struct SBufferHeader *Cur;
1911         void *SCListMem;
1912
1913         if (SCListMemSize < 4096)
1914                 SCListMemSize = 4096;
1915
1916         SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp);
1917
1918         PASCListMem = tmp;
1919         if (SCListMem == NULL)
1920                 return -ENOMEM;
1921
1922         memset(SCListMem, 0, SCListMemSize);
1923
1924         pRingBuffer->SCListMem = SCListMem;
1925         pRingBuffer->PASCListMem = PASCListMem;
1926         pRingBuffer->SCListMemSize = SCListMemSize;
1927         pRingBuffer->Buffer1Length = Buffer1Length;
1928         pRingBuffer->Buffer2Length = Buffer2Length;
1929
1930         SCListEntry = (PHW_SCATTER_GATHER_ELEMENT) SCListMem;
1931         PASCListEntry = PASCListMem;
1932         Cur = pRingBuffer->Head;
1933
1934         for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) {
1935                 u64 PABuffer;
1936
1937                 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length,
1938                                                     &tmp);
1939                 PABuffer = tmp;
1940
1941                 if (Buffer == NULL)
1942                         return -ENOMEM;
1943
1944                 Cur->Buffer1 = Buffer;
1945
1946                 SCListEntry->Address = PABuffer;
1947                 SCListEntry->Length  = Buffer1Length;
1948
1949                 Cur->scList1 = SCListEntry;
1950                 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry;
1951                 Cur->ngeneBuffer.Number_of_entries_1 =
1952                         NUM_SCATTER_GATHER_ENTRIES;
1953
1954                 SCListEntry += 1;
1955                 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1956
1957 #if NUM_SCATTER_GATHER_ENTRIES > 1
1958                 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) {
1959                         SCListEntry->Address = of;
1960                         SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1961                         SCListEntry += 1;
1962                         PASCListEntry +=
1963                                 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1964                 }
1965 #endif
1966
1967                 if (!Buffer2Length)
1968                         continue;
1969
1970                 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp);
1971                 PABuffer = tmp;
1972
1973                 if (Buffer == NULL)
1974                         return -ENOMEM;
1975
1976                 Cur->Buffer2 = Buffer;
1977
1978                 SCListEntry->Address = PABuffer;
1979                 SCListEntry->Length  = Buffer2Length;
1980
1981                 Cur->scList2 = SCListEntry;
1982                 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry;
1983                 Cur->ngeneBuffer.Number_of_entries_2 =
1984                         NUM_SCATTER_GATHER_ENTRIES;
1985
1986                 SCListEntry   += 1;
1987                 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1988
1989 #if NUM_SCATTER_GATHER_ENTRIES > 1
1990                 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) {
1991                         SCListEntry->Address = of;
1992                         SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1993                         SCListEntry += 1;
1994                         PASCListEntry +=
1995                                 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1996                 }
1997 #endif
1998
1999         }
2000
2001         return status;
2002 }
2003
2004 static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer,
2005                             struct SRingBufferDescriptor *pRingBuffer)
2006 {
2007         int status = 0;
2008
2009         /* Copy pointer to scatter gather list in TSRingbuffer
2010            structure for buffer 2
2011            Load number of buffer
2012         */
2013         u32 n = pRingBuffer->NumBuffers;
2014
2015         /* Point to first buffer entry */
2016         struct SBufferHeader *Cur = pRingBuffer->Head;
2017         int i;
2018         /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */
2019         for (i = 0; i < n; i++) {
2020                 Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
2021                 Cur->scList2 = pIdleBuffer->Head->scList1;
2022                 Cur->ngeneBuffer.Address_of_first_entry_2 =
2023                         pIdleBuffer->Head->ngeneBuffer.
2024                         Address_of_first_entry_1;
2025                 Cur->ngeneBuffer.Number_of_entries_2 =
2026                         pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1;
2027                 Cur = Cur->Next;
2028         }
2029         return status;
2030 }
2031
2032 static u32 RingBufferSizes[MAX_STREAM] = {
2033         RING_SIZE_VIDEO,
2034         RING_SIZE_VIDEO,
2035         RING_SIZE_AUDIO,
2036         RING_SIZE_AUDIO,
2037         RING_SIZE_AUDIO,
2038 };
2039
2040 static u32 Buffer1Sizes[MAX_STREAM] = {
2041         MAX_VIDEO_BUFFER_SIZE,
2042         MAX_VIDEO_BUFFER_SIZE,
2043         MAX_AUDIO_BUFFER_SIZE,
2044         MAX_AUDIO_BUFFER_SIZE,
2045         MAX_AUDIO_BUFFER_SIZE
2046 };
2047
2048 static u32 Buffer2Sizes[MAX_STREAM] = {
2049         MAX_VBI_BUFFER_SIZE,
2050         MAX_VBI_BUFFER_SIZE,
2051         0,
2052         0,
2053         0
2054 };
2055
2056
2057 static int AllocCommonBuffers(struct ngene *dev)
2058 {
2059         int status = 0, i;
2060
2061         dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096,
2062                                                      &dev->PAFWInterfaceBuffer);
2063         if (!dev->FWInterfaceBuffer)
2064                 return -ENOMEM;
2065         dev->hosttongene = dev->FWInterfaceBuffer;
2066         dev->ngenetohost = dev->FWInterfaceBuffer + 256;
2067         dev->EventBuffer = dev->FWInterfaceBuffer + 512;
2068
2069         dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev,
2070                                                    OVERFLOW_BUFFER_SIZE,
2071                                                    &dev->PAOverflowBuffer);
2072         if (!dev->OverflowBuffer)
2073                 return -ENOMEM;
2074         memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE);
2075
2076         for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
2077                 int type = dev->card_info->io_type[i];
2078
2079                 dev->channel[i].State = KSSTATE_STOP;
2080
2081                 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
2082                         status = create_ring_buffer(dev->pci_dev,
2083                                                     &dev->channel[i].RingBuffer,
2084                                                     RingBufferSizes[i]);
2085                         if (status < 0)
2086                                 break;
2087
2088                         if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
2089                                 status = AllocateRingBuffers(dev->pci_dev,
2090                                                              dev->
2091                                                              PAOverflowBuffer,
2092                                                              &dev->channel[i].
2093                                                              RingBuffer,
2094                                                              Buffer1Sizes[i],
2095                                                              Buffer2Sizes[i]);
2096                                 if (status < 0)
2097                                         break;
2098                         } else if (type & NGENE_IO_HDTV) {
2099                                 status = AllocateRingBuffers(dev->pci_dev,
2100                                                              dev->
2101                                                              PAOverflowBuffer,
2102                                                              &dev->channel[i].
2103                                                              RingBuffer,
2104                                                            MAX_HDTV_BUFFER_SIZE,
2105                                                              0);
2106                                 if (status < 0)
2107                                         break;
2108                         }
2109                 }
2110
2111                 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
2112
2113                         status = create_ring_buffer(dev->pci_dev,
2114                                                     &dev->channel[i].
2115                                                     TSRingBuffer, RING_SIZE_TS);
2116                         if (status < 0)
2117                                 break;
2118
2119                         status = AllocateRingBuffers(dev->pci_dev,
2120                                                      dev->PAOverflowBuffer,
2121                                                      &dev->channel[i].
2122                                                      TSRingBuffer,
2123                                                      MAX_TS_BUFFER_SIZE, 0);
2124                         if (status)
2125                                 break;
2126                 }
2127
2128                 if (type & NGENE_IO_TSOUT) {
2129                         status = create_ring_buffer(dev->pci_dev,
2130                                                     &dev->channel[i].
2131                                                     TSIdleBuffer, 1);
2132                         if (status < 0)
2133                                 break;
2134                         status = AllocateRingBuffers(dev->pci_dev,
2135                                                      dev->PAOverflowBuffer,
2136                                                      &dev->channel[i].
2137                                                      TSIdleBuffer,
2138                                                      MAX_TS_BUFFER_SIZE, 0);
2139                         if (status)
2140                                 break;
2141                         FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer,
2142                                          &dev->channel[i].TSRingBuffer);
2143                 }
2144         }
2145         return status;
2146 }
2147
2148 static void ngene_release_buffers(struct ngene *dev)
2149 {
2150         if (dev->iomem)
2151                 iounmap(dev->iomem);
2152         free_common_buffers(dev);
2153         vfree(dev->tsout_buf);
2154         vfree(dev->ain_buf);
2155         vfree(dev->vin_buf);
2156         vfree(dev);
2157 }
2158
2159 static int ngene_get_buffers(struct ngene *dev)
2160 {
2161         if (AllocCommonBuffers(dev))
2162                 return -ENOMEM;
2163         if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) {
2164                 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE);
2165                 if (!dev->tsout_buf)
2166                         return -ENOMEM;
2167                 dvb_ringbuffer_init(&dev->tsout_rbuf,
2168                                     dev->tsout_buf, TSOUT_BUF_SIZE);
2169         }
2170         if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
2171                 dev->ain_buf = vmalloc(AIN_BUF_SIZE);
2172                 if (!dev->ain_buf)
2173                         return -ENOMEM;
2174                 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE);
2175         }
2176         if (dev->card_info->io_type[0] & NGENE_IO_HDTV) {
2177                 dev->vin_buf = vmalloc(VIN_BUF_SIZE);
2178                 if (!dev->vin_buf)
2179                         return -ENOMEM;
2180                 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE);
2181         }
2182         dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0),
2183                              pci_resource_len(dev->pci_dev, 0));
2184         if (!dev->iomem)
2185                 return -ENOMEM;
2186
2187         return 0;
2188 }
2189
2190 static void ngene_init(struct ngene *dev)
2191 {
2192         int i;
2193
2194         tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev);
2195
2196         memset_io(dev->iomem + 0xc000, 0x00, 0x220);
2197         memset_io(dev->iomem + 0xc400, 0x00, 0x100);
2198
2199         for (i = 0; i < MAX_STREAM; i++) {
2200                 dev->channel[i].dev = dev;
2201                 dev->channel[i].number = i;
2202         }
2203
2204         dev->fw_interface_version = 0;
2205
2206         ngwritel(0, NGENE_INT_ENABLE);
2207
2208         dev->icounts = ngreadl(NGENE_INT_COUNTS);
2209
2210         dev->device_version = ngreadl(DEV_VER) & 0x0f;
2211         printk(KERN_INFO DEVICE_NAME ": Device version %d\n",
2212                dev->device_version);
2213 }
2214
2215 static int ngene_load_firm(struct ngene *dev)
2216 {
2217         u32 size;
2218         const struct firmware *fw = NULL;
2219         u8 *ngene_fw;
2220         char *fw_name;
2221         int err, version;
2222
2223         version = dev->card_info->fw_version;
2224
2225         switch (version) {
2226         default:
2227         case 15:
2228                 version = 15;
2229                 size = 23466;
2230                 fw_name = "ngene_15.fw";
2231                 break;
2232         case 16:
2233                 size = 23498;
2234                 fw_name = "ngene_16.fw";
2235                 break;
2236         case 17:
2237                 size = 24446;
2238                 fw_name = "ngene_17.fw";
2239                 break;
2240         }
2241
2242         if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
2243                 printk(KERN_ERR DEVICE_NAME
2244                         ": Could not load firmware file %s.\n", fw_name);
2245                 printk(KERN_INFO DEVICE_NAME
2246                         ": Copy %s to your hotplug directory!\n", fw_name);
2247                 return -1;
2248         }
2249         if (size != fw->size) {
2250                 printk(KERN_ERR DEVICE_NAME
2251                         ": Firmware %s has invalid size!", fw_name);
2252                 err = -1;
2253         } else {
2254                 printk(KERN_INFO DEVICE_NAME
2255                         ": Loading firmware file %s.\n", fw_name);
2256                 ngene_fw = (u8 *) fw->data;
2257                 err = ngene_command_load_firmware(dev, ngene_fw, size);
2258         }
2259
2260         release_firmware(fw);
2261
2262         return err;
2263 }
2264
2265 static void ngene_stop(struct ngene *dev)
2266 {
2267         down(&dev->cmd_mutex);
2268         i2c_del_adapter(&(dev->channel[0].i2c_adapter));
2269         i2c_del_adapter(&(dev->channel[1].i2c_adapter));
2270         ngwritel(0, NGENE_INT_ENABLE);
2271         ngwritel(0, NGENE_COMMAND);
2272         ngwritel(0, NGENE_COMMAND_HI);
2273         ngwritel(0, NGENE_STATUS);
2274         ngwritel(0, NGENE_STATUS_HI);
2275         ngwritel(0, NGENE_EVENT);
2276         ngwritel(0, NGENE_EVENT_HI);
2277         free_irq(dev->pci_dev->irq, dev);
2278 }
2279
2280 static int ngene_start(struct ngene *dev)
2281 {
2282         int stat;
2283         int i;
2284
2285         pci_set_master(dev->pci_dev);
2286         ngene_init(dev);
2287
2288         stat = request_irq(dev->pci_dev->irq, irq_handler,
2289                            IRQF_SHARED, "nGene",
2290                            (void *)dev);
2291         if (stat < 0)
2292                 return stat;
2293
2294         init_waitqueue_head(&dev->cmd_wq);
2295         init_waitqueue_head(&dev->tx_wq);
2296         init_waitqueue_head(&dev->rx_wq);
2297         sema_init(&dev->cmd_mutex, 1);
2298         sema_init(&dev->stream_mutex, 1);
2299         sema_init(&dev->pll_mutex, 1);
2300         sema_init(&dev->i2c_switch_mutex, 1);
2301         spin_lock_init(&dev->cmd_lock);
2302         for (i = 0; i < MAX_STREAM; i++)
2303                 spin_lock_init(&dev->channel[i].state_lock);
2304         ngwritel(1, TIMESTAMPS);
2305
2306         ngwritel(1, NGENE_INT_ENABLE);
2307
2308         stat = ngene_load_firm(dev);
2309         if (stat < 0)
2310                 goto fail;
2311
2312         stat = ngene_i2c_init(dev, 0);
2313         if (stat < 0)
2314                 goto fail;
2315
2316         stat = ngene_i2c_init(dev, 1);
2317         if (stat < 0)
2318                 goto fail;
2319
2320         if (dev->card_info->fw_version == 17) {
2321                 u8 hdtv_config[6] =
2322                         {6144 / 64, 0, 0, 2048 / 64, 2048 / 64, 2048 / 64};
2323                 u8 tsin4_config[6] =
2324                         {3072 / 64, 3072 / 64, 0, 3072 / 64, 3072 / 64, 0};
2325                 u8 default_config[6] =
2326                         {4096 / 64, 4096 / 64, 0, 2048 / 64, 2048 / 64, 0};
2327                 u8 *bconf = default_config;
2328
2329                 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
2330                         bconf = tsin4_config;
2331                 if (dev->card_info->io_type[0] == NGENE_IO_HDTV) {
2332                         bconf = hdtv_config;
2333                         ngene_reset_decypher(dev);
2334                 }
2335                 printk(KERN_INFO DEVICE_NAME ": FW 17 buffer config\n");
2336                 stat = ngene_command_config_free_buf(dev, bconf);
2337         } else {
2338                 int bconf = BUFFER_CONFIG_4422;
2339
2340                 if (dev->card_info->io_type[0] == NGENE_IO_HDTV) {
2341                         bconf = BUFFER_CONFIG_8022;
2342                         ngene_reset_decypher(dev);
2343                 }
2344                 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
2345                         bconf = BUFFER_CONFIG_3333;
2346                 stat = ngene_command_config_buf(dev, bconf);
2347         }
2348
2349         if (dev->card_info->io_type[0] == NGENE_IO_HDTV) {
2350                 ngene_command_config_uart(dev, 0xc1, tx_cb, rx_cb);
2351                 test_dec_i2c(&dev->channel[0].i2c_adapter, 0);
2352                 test_dec_i2c(&dev->channel[0].i2c_adapter, 1);
2353         }
2354
2355         return stat;
2356 fail:
2357         ngwritel(0, NGENE_INT_ENABLE);
2358         free_irq(dev->pci_dev->irq, dev);
2359         return stat;
2360 }
2361
2362
2363
2364 /****************************************************************************/
2365 /* Switch control (I2C gates, etc.) *****************************************/
2366 /****************************************************************************/
2367
2368
2369 /****************************************************************************/
2370 /* Demod/tuner attachment ***************************************************/
2371 /****************************************************************************/
2372
2373 static int tuner_attach_stv6110(struct ngene_channel *chan)
2374 {
2375         struct stv090x_config *feconf = (struct stv090x_config *)
2376                 chan->dev->card_info->fe_config[chan->number];
2377         struct stv6110x_config *tunerconf = (struct stv6110x_config *)
2378                 chan->dev->card_info->tuner_config[chan->number];
2379         struct stv6110x_devctl *ctl;
2380
2381         ctl = dvb_attach(stv6110x_attach, chan->fe, tunerconf,
2382                          &chan->i2c_adapter);
2383         if (ctl == NULL) {
2384                 printk(KERN_ERR DEVICE_NAME ": No STV6110X found!\n");
2385                 return -ENODEV;
2386         }
2387
2388         feconf->tuner_init          = ctl->tuner_init;
2389         feconf->tuner_set_mode      = ctl->tuner_set_mode;
2390         feconf->tuner_set_frequency = ctl->tuner_set_frequency;
2391         feconf->tuner_get_frequency = ctl->tuner_get_frequency;
2392         feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
2393         feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth;
2394         feconf->tuner_set_bbgain    = ctl->tuner_set_bbgain;
2395         feconf->tuner_get_bbgain    = ctl->tuner_get_bbgain;
2396         feconf->tuner_set_refclk    = ctl->tuner_set_refclk;
2397         feconf->tuner_get_status    = ctl->tuner_get_status;
2398
2399         return 0;
2400 }
2401
2402
2403 static int demod_attach_stv0900(struct ngene_channel *chan)
2404 {
2405         struct stv090x_config *feconf = (struct stv090x_config *)
2406                 chan->dev->card_info->fe_config[chan->number];
2407
2408         chan->fe = dvb_attach(stv090x_attach,
2409                         feconf,
2410                         &chan->i2c_adapter,
2411                         chan->number == 0 ? STV090x_DEMODULATOR_0 :
2412                                             STV090x_DEMODULATOR_1);
2413         if (chan->fe == NULL) {
2414                 printk(KERN_ERR DEVICE_NAME ": No STV0900 found!\n");
2415                 return -ENODEV;
2416         }
2417
2418         if (!dvb_attach(lnbh24_attach, chan->fe, &chan->i2c_adapter, 0,
2419                         0, chan->dev->card_info->lnb[chan->number])) {
2420                 printk(KERN_ERR DEVICE_NAME ": No LNBH24 found!\n");
2421                 dvb_frontend_detach(chan->fe);
2422                 return -ENODEV;
2423         }
2424
2425         return 0;
2426 }
2427
2428 /****************************************************************************/
2429 /****************************************************************************/
2430 /****************************************************************************/
2431
2432 static void release_channel(struct ngene_channel *chan)
2433 {
2434         struct dvb_demux *dvbdemux = &chan->demux;
2435         struct ngene *dev = chan->dev;
2436         struct ngene_info *ni = dev->card_info;
2437         int io = ni->io_type[chan->number];
2438
2439         tasklet_kill(&chan->demux_tasklet);
2440
2441         if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
2442 #ifdef NGENE_COMMAND_API
2443                 if (chan->command_dev)
2444                         dvb_unregister_device(chan->command_dev);
2445 #endif
2446                 if (chan->fe) {
2447                         dvb_unregister_frontend(chan->fe);
2448                         /*dvb_frontend_detach(chan->fe); */
2449                         chan->fe = 0;
2450                 }
2451                 dvbdemux->dmx.close(&dvbdemux->dmx);
2452                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
2453                                               &chan->hw_frontend);
2454                 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
2455                                               &chan->mem_frontend);
2456                 dvb_dmxdev_release(&chan->dmxdev);
2457                 dvb_dmx_release(&chan->demux);
2458 #ifndef ONE_ADAPTER
2459                 dvb_unregister_adapter(&chan->dvb_adapter);
2460 #endif
2461         }
2462
2463 }
2464
2465 static int init_channel(struct ngene_channel *chan)
2466 {
2467         int ret = 0, nr = chan->number;
2468         struct dvb_adapter *adapter = 0;
2469         struct dvb_demux *dvbdemux = &chan->demux;
2470         struct ngene *dev = chan->dev;
2471         struct ngene_info *ni = dev->card_info;
2472         int io = ni->io_type[nr];
2473
2474         tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan);
2475         chan->users = 0;
2476         chan->type = io;
2477         chan->mode = chan->type;        /* for now only one mode */
2478
2479         if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
2480                 if (nr >= STREAM_AUDIOIN1)
2481                         chan->DataFormatFlags = DF_SWAP32;
2482
2483                 if (io & NGENE_IO_TSOUT)
2484                         dec_fw_boot(dev);
2485
2486 #ifdef ONE_ADAPTER
2487                 adapter = &chan->dev->dvb_adapter;
2488 #else
2489                 ret = dvb_register_adapter(&chan->dvb_adapter, "nGene",
2490                                            THIS_MODULE,
2491                                            &chan->dev->pci_dev->dev,
2492                                            adapter_nr);
2493                 if (ret < 0)
2494                         return ret;
2495                 adapter = &chan->dvb_adapter;
2496 #endif
2497                 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
2498                                               ngene_start_feed,
2499                                               ngene_stop_feed, chan);
2500                 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
2501                                                  &chan->hw_frontend,
2502                                                  &chan->mem_frontend, adapter);
2503                 if (io & NGENE_IO_TSOUT) {
2504                         dvbdemux->write_to_decoder = write_to_decoder;
2505                 }
2506 #ifdef NGENE_COMMAND_API
2507                 dvb_register_device(adapter, &chan->command_dev,
2508                                     &dvbdev_command, (void *)chan,
2509                                     DVB_DEVICE_SEC);
2510 #endif
2511         }
2512
2513         if (io & NGENE_IO_TSIN) {
2514                 chan->fe = NULL;
2515                 if (ni->demod_attach[nr])
2516                         ni->demod_attach[nr](chan);
2517                 if (chan->fe) {
2518                         if (dvb_register_frontend(adapter, chan->fe) < 0) {
2519                                 if (chan->fe->ops.release)
2520                                         chan->fe->ops.release(chan->fe);
2521                                 chan->fe = NULL;
2522                         }
2523                 }
2524                 if (chan->fe && ni->tuner_attach[nr])
2525                         if (ni->tuner_attach[nr] (chan) < 0) {
2526                                 printk(KERN_ERR DEVICE_NAME
2527                                        ": Tuner attach failed on channel %d!\n",
2528                                        nr);
2529                         }
2530         }
2531
2532         return ret;
2533 }
2534
2535 static int init_channels(struct ngene *dev)
2536 {
2537         int i, j;
2538
2539         for (i = 0; i < MAX_STREAM; i++) {
2540                 if (init_channel(&dev->channel[i]) < 0) {
2541                         for (j = 0; j < i; j++)
2542                                 release_channel(&dev->channel[j]);
2543                         return -1;
2544                 }
2545         }
2546         return 0;
2547 }
2548
2549 /****************************************************************************/
2550 /* device probe/remove calls ************************************************/
2551 /****************************************************************************/
2552
2553 static void __devexit ngene_remove(struct pci_dev *pdev)
2554 {
2555         struct ngene *dev = (struct ngene *)pci_get_drvdata(pdev);
2556         int i;
2557
2558         tasklet_kill(&dev->event_tasklet);
2559         for (i = 0; i < MAX_STREAM; i++)
2560                 release_channel(&dev->channel[i]);
2561 #ifdef ONE_ADAPTER
2562         dvb_unregister_adapter(&dev->dvb_adapter);
2563 #endif
2564         ngene_stop(dev);
2565         ngene_release_buffers(dev);
2566         pci_set_drvdata(pdev, 0);
2567         pci_disable_device(pdev);
2568 }
2569
2570 static int __devinit ngene_probe(struct pci_dev *pci_dev,
2571                                  const struct pci_device_id *id)
2572 {
2573         struct ngene *dev;
2574         int stat = 0;
2575
2576         if (pci_enable_device(pci_dev) < 0)
2577                 return -ENODEV;
2578
2579         dev = vmalloc(sizeof(struct ngene));
2580         if (dev == NULL)
2581                 return -ENOMEM;
2582         memset(dev, 0, sizeof(struct ngene));
2583
2584         dev->pci_dev = pci_dev;
2585         dev->card_info = (struct ngene_info *)id->driver_data;
2586         printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name);
2587
2588         pci_set_drvdata(pci_dev, dev);
2589
2590         /* Alloc buffers and start nGene */
2591         stat = ngene_get_buffers(dev);
2592         if (stat < 0)
2593                 goto fail1;
2594         stat = ngene_start(dev);
2595         if (stat < 0)
2596                 goto fail1;
2597
2598         dev->i2c_current_bus = -1;
2599         /* Disable analog TV decoder chips if present */
2600         if (copy_eeprom) {
2601                 i2c_copy_eeprom(&dev->channel[0].i2c_adapter, 0x50, 0x52);
2602                 i2c_dump_eeprom(&dev->channel[0].i2c_adapter, 0x52);
2603         }
2604         /*i2c_check_eeprom(&dev->i2c_adapter);*/
2605
2606         /* Register DVB adapters and devices for both channels */
2607 #ifdef ONE_ADAPTER
2608         if (dvb_register_adapter(&dev->dvb_adapter, "nGene", THIS_MODULE,
2609                                  &dev->pci_dev->dev, adapter_nr) < 0)
2610                 goto fail2;
2611 #endif
2612         if (init_channels(dev) < 0)
2613                 goto fail2;
2614
2615         return 0;
2616
2617 fail2:
2618         ngene_stop(dev);
2619 fail1:
2620         ngene_release_buffers(dev);
2621         pci_set_drvdata(pci_dev, 0);
2622         return stat;
2623 }
2624
2625 /****************************************************************************/
2626 /* Card configs *************************************************************/
2627 /****************************************************************************/
2628
2629 static struct stv090x_config fe_mps2 = {
2630         .device         = STV0900,
2631         .demod_mode     = STV090x_DUAL,
2632         .clk_mode       = STV090x_CLK_EXT,
2633
2634         .xtal           = 27000000,
2635         .address        = 0x68,
2636 //      .ref_clk        = 27000000,
2637
2638         .ts1_mode       = STV090x_TSMODE_SERIAL_PUNCTURED,
2639         .ts2_mode       = STV090x_TSMODE_SERIAL_PUNCTURED,
2640
2641         .repeater_level = STV090x_RPTLEVEL_16,
2642
2643         .diseqc_envelope_mode = true,
2644
2645         .tuner_init           = NULL,
2646         .tuner_set_mode       = NULL,
2647         .tuner_set_frequency  = NULL,
2648         .tuner_get_frequency  = NULL,
2649         .tuner_set_bandwidth  = NULL,
2650         .tuner_get_bandwidth  = NULL,
2651         .tuner_set_bbgain     = NULL,
2652         .tuner_get_bbgain     = NULL,
2653         .tuner_set_refclk     = NULL,
2654         .tuner_get_status     = NULL,
2655 };
2656
2657 static struct stv6110x_config tuner_mps2_0 = {
2658         .addr   = 0x60,
2659         .refclk = 27000000,
2660 };
2661
2662 static struct stv6110x_config tuner_mps2_1 = {
2663         .addr   = 0x63,
2664         .refclk = 27000000,
2665 };
2666
2667 static struct ngene_info ngene_info_mps2 = {
2668         .type           = NGENE_SIDEWINDER,
2669         .name           = "Media-Pointer MP-S2/CineS2 DVB-S2 Twin Tuner",
2670         .io_type        = {NGENE_IO_TSIN, NGENE_IO_TSIN},
2671         .demod_attach   = {demod_attach_stv0900, demod_attach_stv0900},
2672         .tuner_attach   = {tuner_attach_stv6110, tuner_attach_stv6110},
2673         .fe_config      = {&fe_mps2, &fe_mps2},
2674         .tuner_config   = {&tuner_mps2_0, &tuner_mps2_1},
2675         .lnb            = {0x0b, 0x08},
2676         .tsf            = {3, 3},
2677         .fw_version     = 17,
2678 };
2679
2680 /****************************************************************************/
2681
2682
2683
2684 /****************************************************************************/
2685 /****************************************************************************/
2686 /****************************************************************************/
2687
2688 #define NGENE_ID(_subvend, _subdev, _driverdata) { \
2689         .vendor = NGENE_VID, .device = NGENE_PID, \
2690         .subvendor = _subvend, .subdevice = _subdev, \
2691         .driver_data = (unsigned long) &_driverdata }
2692
2693 /****************************************************************************/
2694
2695 static const struct pci_device_id ngene_id_tbl[] __devinitdata = {
2696         NGENE_ID(0x18c3, 0xabc3, ngene_info_mps2),
2697         NGENE_ID(0x18c3, 0xabc4, ngene_info_mps2),
2698         NGENE_ID(0x18c3, 0xdb01, ngene_info_mps2),
2699         {0}
2700 };
2701 MODULE_DEVICE_TABLE(pci, ngene_id_tbl);
2702
2703 /****************************************************************************/
2704 /* Init/Exit ****************************************************************/
2705 /****************************************************************************/
2706
2707 static pci_ers_result_t ngene_error_detected(struct pci_dev *dev,
2708                                              enum pci_channel_state state)
2709 {
2710         printk(KERN_ERR DEVICE_NAME ": PCI error\n");
2711         if (state == pci_channel_io_perm_failure)
2712                 return PCI_ERS_RESULT_DISCONNECT;
2713         if (state == pci_channel_io_frozen)
2714                 return PCI_ERS_RESULT_NEED_RESET;
2715         return PCI_ERS_RESULT_CAN_RECOVER;
2716 }
2717
2718 static pci_ers_result_t ngene_link_reset(struct pci_dev *dev)
2719 {
2720         printk(KERN_INFO DEVICE_NAME ": link reset\n");
2721         return 0;
2722 }
2723
2724 static pci_ers_result_t ngene_slot_reset(struct pci_dev *dev)
2725 {
2726         printk(KERN_INFO DEVICE_NAME ": slot reset\n");
2727         return 0;
2728 }
2729
2730 static void ngene_resume(struct pci_dev *dev)
2731 {
2732         printk(KERN_INFO DEVICE_NAME ": resume\n");
2733 }
2734
2735 static struct pci_error_handlers ngene_errors = {
2736         .error_detected = ngene_error_detected,
2737         .link_reset = ngene_link_reset,
2738         .slot_reset = ngene_slot_reset,
2739         .resume = ngene_resume,
2740 };
2741
2742 static struct pci_driver ngene_pci_driver = {
2743         .name        = "ngene",
2744         .id_table    = ngene_id_tbl,
2745         .probe       = ngene_probe,
2746         .remove      = ngene_remove,
2747         .err_handler = &ngene_errors,
2748 };
2749
2750 static __init int module_init_ngene(void)
2751 {
2752         printk(KERN_INFO
2753                "nGene PCIE bridge driver, Copyright (C) 2005-2007 Micronas\n");
2754         return pci_register_driver(&ngene_pci_driver);
2755 }
2756
2757 static __exit void module_exit_ngene(void)
2758 {
2759         pci_unregister_driver(&ngene_pci_driver);
2760 }
2761
2762 module_init(module_init_ngene);
2763 module_exit(module_exit_ngene);
2764
2765 MODULE_DESCRIPTION("nGene");
2766 MODULE_AUTHOR("Micronas, Ralph Metzler, Manfred Voelkel");
2767 MODULE_LICENSE("GPL");