2 * ngene.c: nGene PCIe bridge driver
4 * Copyright (C) 2005-2007 Micronas
6 * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
7 * Modifications for new nGene firmware,
8 * support for EEPROM-copying,
9 * support for new dual DVB-S2 card prototype
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2 only, as published by the Free Software Foundation.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
27 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
30 #include <linux/module.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/slab.h>
34 #include <linux/poll.h>
36 #include <asm/div64.h>
37 #include <linux/pci.h>
38 #include <linux/pci_ids.h>
39 #include <linux/smp_lock.h>
40 #include <linux/timer.h>
41 #include <linux/version.h>
42 #include <linux/byteorder/generic.h>
43 #include <linux/firmware.h>
51 #ifdef NGENE_COMMAND_API
52 #include "ngene-ioctls.h"
55 static int copy_eeprom;
56 module_param(copy_eeprom, int, 0444);
57 MODULE_PARM_DESC(copy_eeprom, "Copy eeprom.");
59 static int ngene_fw_debug;
60 module_param(ngene_fw_debug, int, 0444);
61 MODULE_PARM_DESC(ngene_fw_debug, "Debug firmware.");
64 module_param(debug, int, 0444);
65 MODULE_PARM_DESC(debug, "Print debugging information.");
67 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
69 #define dprintk if (debug) printk
71 #define DEVICE_NAME "ngene"
73 #define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr)))
74 #define ngwritel(dat, adr) writel((dat), (char *)(dev->iomem + (adr)))
75 #define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr)))
76 #define ngreadl(adr) readl(dev->iomem + (adr))
77 #define ngreadb(adr) readb(dev->iomem + (adr))
78 #define ngcpyto(adr, src, count) memcpy_toio((char *) \
79 (dev->iomem + (adr)), (src), (count))
80 #define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), (char *) \
81 (dev->iomem + (adr)), (count))
83 /****************************************************************************/
84 /* Functions with missing kernel exports ************************************/
85 /****************************************************************************/
87 /* yeah, let's throw out all exports which are not used in kernel ... */
89 void my_dvb_ringbuffer_flush(struct dvb_ringbuffer *rbuf)
91 rbuf->pread = rbuf->pwrite;
95 /****************************************************************************/
96 /* nGene interrupt handler **************************************************/
97 /****************************************************************************/
99 static void event_tasklet(unsigned long data)
101 struct ngene *dev = (struct ngene *)data;
103 while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) {
104 struct EVENT_BUFFER Event =
105 dev->EventQueue[dev->EventQueueReadIndex];
106 dev->EventQueueReadIndex =
107 (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1);
109 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify))
110 dev->TxEventNotify(dev, Event.TimeStamp);
111 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify))
112 dev->RxEventNotify(dev, Event.TimeStamp,
117 static void demux_tasklet(unsigned long data)
119 struct ngene_channel *chan = (struct ngene_channel *)data;
120 struct SBufferHeader *Cur = chan->nextBuffer;
122 spin_lock_irq(&chan->state_lock);
124 while (Cur->ngeneBuffer.SR.Flags & 0x80) {
125 if (chan->mode & NGENE_IO_TSOUT) {
126 u32 Flags = chan->DataFormatFlags;
127 if (Cur->ngeneBuffer.SR.Flags & 0x20)
128 Flags |= BEF_OVERFLOW;
129 if (chan->pBufferExchange) {
130 if (!chan->pBufferExchange(chan,
132 chan->Capture1Length,
137 Clear in service flag to make sure we
138 get called on next interrupt again.
139 leave fill/empty (0x80) flag alone
140 to avoid hardware running out of
141 buffers during startup, we hold only
142 in run state ( the source may be late
146 if (chan->HWState == HWSTATE_RUN) {
147 Cur->ngeneBuffer.SR.Flags &=
150 /* Stop proccessing stream */
153 /* We got a valid buffer,
154 so switch to run state */
155 chan->HWState = HWSTATE_RUN;
158 printk(KERN_ERR DEVICE_NAME ": OOPS\n");
159 if (chan->HWState == HWSTATE_RUN) {
160 Cur->ngeneBuffer.SR.Flags &= ~0x40;
161 break; /* Stop proccessing stream */
164 if (chan->AudioDTOUpdated) {
165 printk(KERN_INFO DEVICE_NAME
166 ": Update AudioDTO = %d\n",
167 chan->AudioDTOValue);
168 Cur->ngeneBuffer.SR.DTOUpdate =
170 chan->AudioDTOUpdated = 0;
173 if (chan->HWState == HWSTATE_RUN) {
175 if (Cur->ngeneBuffer.SR.Flags & 0x01)
176 Flags |= BEF_EVEN_FIELD;
177 if (Cur->ngeneBuffer.SR.Flags & 0x20)
178 Flags |= BEF_OVERFLOW;
179 if (chan->pBufferExchange)
180 chan->pBufferExchange(chan,
186 if (chan->pBufferExchange2)
187 chan->pBufferExchange2(chan,
193 } else if (chan->HWState != HWSTATE_STOP)
194 chan->HWState = HWSTATE_RUN;
196 Cur->ngeneBuffer.SR.Flags = 0x00;
199 chan->nextBuffer = Cur;
201 spin_unlock_irq(&chan->state_lock);
204 static irqreturn_t irq_handler(int irq, void *dev_id)
206 struct ngene *dev = (struct ngene *)dev_id;
208 irqreturn_t rc = IRQ_NONE;
212 if (dev->BootFirmware) {
213 icounts = ngreadl(NGENE_INT_COUNTS);
214 if (icounts != dev->icounts) {
215 ngwritel(0, FORCE_NMI);
217 wake_up(&dev->cmd_wq);
218 dev->icounts = icounts;
224 ngwritel(0, FORCE_NMI);
226 spin_lock(&dev->cmd_lock);
227 tmpCmdDoneByte = dev->CmdDoneByte;
228 if (tmpCmdDoneByte &&
230 (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) {
231 dev->CmdDoneByte = NULL;
233 wake_up(&dev->cmd_wq);
236 spin_unlock(&dev->cmd_lock);
238 if (dev->EventBuffer->EventStatus & 0x80) {
240 (dev->EventQueueWriteIndex + 1) &
241 (EVENT_QUEUE_SIZE - 1);
242 if (nextWriteIndex != dev->EventQueueReadIndex) {
243 dev->EventQueue[dev->EventQueueWriteIndex] =
245 dev->EventQueueWriteIndex = nextWriteIndex;
247 printk(KERN_ERR DEVICE_NAME ": event overflow\n");
248 dev->EventQueueOverflowCount += 1;
249 dev->EventQueueOverflowFlag = 1;
251 dev->EventBuffer->EventStatus &= ~0x80;
252 tasklet_schedule(&dev->event_tasklet);
258 spin_lock(&dev->channel[i].state_lock);
259 /* if (dev->channel[i].State>=KSSTATE_RUN) { */
260 if (dev->channel[i].nextBuffer) {
261 if ((dev->channel[i].nextBuffer->
262 ngeneBuffer.SR.Flags & 0xC0) == 0x80) {
263 dev->channel[i].nextBuffer->
264 ngeneBuffer.SR.Flags |= 0x40;
266 &dev->channel[i].demux_tasklet);
270 spin_unlock(&dev->channel[i].state_lock);
276 /****************************************************************************/
277 /* nGene command interface **************************************************/
278 /****************************************************************************/
280 static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com)
287 if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) {
288 dev->BootFirmware = 1;
289 dev->icounts = ngreadl(NGENE_INT_COUNTS);
290 ngwritel(0, NGENE_COMMAND);
291 ngwritel(0, NGENE_COMMAND_HI);
292 ngwritel(0, NGENE_STATUS);
293 ngwritel(0, NGENE_STATUS_HI);
294 ngwritel(0, NGENE_EVENT);
295 ngwritel(0, NGENE_EVENT_HI);
296 } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) {
297 u64 fwio = dev->PAFWInterfaceBuffer;
299 ngwritel(fwio & 0xffffffff, NGENE_COMMAND);
300 ngwritel(fwio >> 32, NGENE_COMMAND_HI);
301 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS);
302 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI);
303 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT);
304 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI);
307 memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2);
309 if (dev->BootFirmware)
310 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2);
312 spin_lock_irq(&dev->cmd_lock);
313 tmpCmdDoneByte = dev->ngenetohost + com->out_len;
317 dev->ngenetohost[0] = 0;
318 dev->ngenetohost[1] = 0;
319 dev->CmdDoneByte = tmpCmdDoneByte;
320 spin_unlock_irq(&dev->cmd_lock);
323 ngwritel(1, FORCE_INT);
325 ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ);
327 /*ngwritel(0, FORCE_NMI);*/
329 printk(KERN_ERR DEVICE_NAME
330 ": Command timeout cmd=%02x prev=%02x\n",
331 com->cmd.hdr.Opcode, dev->prev_cmd);
334 if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH)
335 dev->BootFirmware = 0;
337 dev->prev_cmd = com->cmd.hdr.Opcode;
343 memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len);
348 static int ngene_command(struct ngene *dev, struct ngene_command *com)
352 down(&dev->cmd_mutex);
353 result = ngene_command_mutex(dev, com);
358 int ngene_command_nop(struct ngene *dev)
360 struct ngene_command com;
362 com.cmd.hdr.Opcode = CMD_NOP;
363 com.cmd.hdr.Length = 0;
367 return ngene_command(dev, &com);
370 int ngene_command_i2c_read(struct ngene *dev, u8 adr,
371 u8 *out, u8 outlen, u8 *in, u8 inlen, int flag)
373 struct ngene_command com;
375 com.cmd.hdr.Opcode = CMD_I2C_READ;
376 com.cmd.hdr.Length = outlen + 3;
377 com.cmd.I2CRead.Device = adr << 1;
378 memcpy(com.cmd.I2CRead.Data, out, outlen);
379 com.cmd.I2CRead.Data[outlen] = inlen;
380 com.cmd.I2CRead.Data[outlen + 1] = 0;
381 com.in_len = outlen + 3;
382 com.out_len = inlen + 1;
384 if (ngene_command(dev, &com) < 0)
387 if ((com.cmd.raw8[0] >> 1) != adr)
391 memcpy(in, com.cmd.raw8, inlen + 1);
393 memcpy(in, com.cmd.raw8 + 1, inlen);
397 int ngene_command_i2c_write(struct ngene *dev, u8 adr, u8 *out, u8 outlen)
399 struct ngene_command com;
402 com.cmd.hdr.Opcode = CMD_I2C_WRITE;
403 com.cmd.hdr.Length = outlen + 1;
404 com.cmd.I2CRead.Device = adr << 1;
405 memcpy(com.cmd.I2CRead.Data, out, outlen);
406 com.in_len = outlen + 1;
409 if (ngene_command(dev, &com) < 0)
412 if (com.cmd.raw8[0] == 1)
418 static int ngene_command_load_firmware(struct ngene *dev,
419 u8 *ngene_fw, u32 size)
421 #define FIRSTCHUNK (1024)
423 struct ngene_command com;
425 com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE;
426 com.cmd.hdr.Length = 0;
430 ngene_command(dev, &com);
432 cleft = (size + 3) & ~3;
433 if (cleft > FIRSTCHUNK) {
434 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK,
438 ngene_fw[FW_DEBUG_DEFAULT - PROGRAM_SRAM] = ngene_fw_debug;
439 ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft);
441 memset(&com, 0, sizeof(struct ngene_command));
442 com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH;
443 com.cmd.hdr.Length = 4;
444 com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA;
445 com.cmd.FWLoadFinish.Length = (unsigned short)cleft;
449 return ngene_command(dev, &com);
452 int ngene_command_imem_read(struct ngene *dev, u8 adr, u8 *data, int type)
454 struct ngene_command com;
456 com.cmd.hdr.Opcode = type ? CMD_SFR_READ : CMD_IRAM_READ;
457 com.cmd.hdr.Length = 1;
458 com.cmd.SfrIramRead.address = adr;
462 if (ngene_command(dev, &com) < 0)
465 *data = com.cmd.raw8[1];
469 int ngene_command_imem_write(struct ngene *dev, u8 adr, u8 data, int type)
471 struct ngene_command com;
473 com.cmd.hdr.Opcode = type ? CMD_SFR_WRITE : CMD_IRAM_WRITE;
474 com.cmd.hdr.Length = 2;
475 com.cmd.SfrIramWrite.address = adr;
476 com.cmd.SfrIramWrite.data = data;
480 if (ngene_command(dev, &com) < 0)
486 static int ngene_command_config_uart(struct ngene *dev, u8 config,
487 tx_cb_t *tx_cb, rx_cb_t *rx_cb)
489 struct ngene_command com;
491 com.cmd.hdr.Opcode = CMD_CONFIGURE_UART;
492 com.cmd.hdr.Length = sizeof(struct FW_CONFIGURE_UART) - 2;
493 com.cmd.ConfigureUart.UartControl = config;
494 com.in_len = sizeof(struct FW_CONFIGURE_UART);
497 if (ngene_command(dev, &com) < 0)
500 dev->TxEventNotify = tx_cb;
501 dev->RxEventNotify = rx_cb;
503 dprintk(KERN_DEBUG DEVICE_NAME ": Set UART config %02x.\n", config);
508 static void tx_cb(struct ngene *dev, u32 ts)
511 wake_up_interruptible(&dev->tx_wq);
514 static void rx_cb(struct ngene *dev, u32 ts, u8 c)
516 int rp = dev->uart_rp;
517 int nwp, wp = dev->uart_wp;
519 /* dprintk(KERN_DEBUG DEVICE_NAME ": %c\n", c); */
520 nwp = (wp + 1) % (UART_RBUF_LEN);
523 dev->uart_rbuf[wp] = c;
525 wake_up_interruptible(&dev->rx_wq);
528 static int ngene_command_config_buf(struct ngene *dev, u8 config)
530 struct ngene_command com;
532 com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER;
533 com.cmd.hdr.Length = 1;
534 com.cmd.ConfigureBuffers.config = config;
538 if (ngene_command(dev, &com) < 0)
543 static int ngene_command_config_free_buf(struct ngene *dev, u8 *config)
545 struct ngene_command com;
547 com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
548 com.cmd.hdr.Length = 6;
549 memcpy(&com.cmd.ConfigureBuffers.config, config, 6);
553 if (ngene_command(dev, &com) < 0)
559 static int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level)
561 struct ngene_command com;
563 com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN;
564 com.cmd.hdr.Length = 1;
565 com.cmd.SetGpioPin.select = select | (level << 7);
569 return ngene_command(dev, &com);
572 /* The reset is only wired to GPIO4 on MicRacer Revision 1.10 !
573 Also better set bootdelay to 1 in nvram or less. */
574 static void ngene_reset_decypher(struct ngene *dev)
576 printk(KERN_INFO DEVICE_NAME ": Resetting Decypher.\n");
577 ngene_command_gpio_set(dev, 4, 0);
579 ngene_command_gpio_set(dev, 4, 1);
584 02000640 is sample on rising edge.
585 02000740 is sample on falling edge.
586 02000040 is ignore "valid" signal
588 0: FD_CTL1 Bit 7,6 must be 0,1
589 7 disable(fw controlled)
594 1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
595 1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
596 2: FD_STA is read-only. 0-sync
597 3: FD_INSYNC is number of 47s to trigger "in sync".
598 4: FD_OUTSYNC is number of 47s to trigger "out of sync".
599 5: FD_MAXBYTE1 is low-order of bytes per packet.
600 6: FD_MAXBYTE2 is high-order of bytes per packet.
601 7: Top byte is unused.
604 /****************************************************************************/
606 static u8 TSFeatureDecoderSetup[8 * 4] = {
607 0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
608 0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
609 0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
610 0x72, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
613 /* Set NGENE I2S Config to 16 bit packed */
614 static u8 I2SConfiguration[] = {
615 0x00, 0x10, 0x00, 0x00,
616 0x80, 0x10, 0x00, 0x00,
619 static u8 SPDIFConfiguration[10] = {
620 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
623 /* Set NGENE I2S Config to transport stream compatible mode */
625 static u8 TS_I2SConfiguration[4] = { 0x3E, 0x1A, 0x00, 0x00 }; /*3e 18 00 00 ?*/
627 static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x20, 0x00, 0x00 };
629 static u8 ITUDecoderSetup[4][16] = {
630 {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20, /* SDTV */
631 0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00},
632 {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,
633 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
634 {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00, /* HDTV 1080i50 */
635 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
636 {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00, /* HDTV 1080i60 */
637 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
642 * 27p50 9f 00 22 80 42 69 18 ...
643 * 27p60 93 00 22 80 82 69 1c ...
646 /* Maxbyte to 1144 (for raw data) */
647 static u8 ITUFeatureDecoderSetup[8] = {
648 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00
651 static void FillTSBuffer(void *Buffer, int Length, u32 Flags)
655 memset(Buffer, Length, 0xff);
657 if (Flags & DF_SWAP32)
667 static void flush_buffers(struct ngene_channel *chan)
673 spin_lock_irq(&chan->state_lock);
674 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80;
675 spin_unlock_irq(&chan->state_lock);
679 static void clear_buffers(struct ngene_channel *chan)
681 struct SBufferHeader *Cur = chan->nextBuffer;
684 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
685 if (chan->mode & NGENE_IO_TSOUT)
686 FillTSBuffer(Cur->Buffer1,
687 chan->Capture1Length,
688 chan->DataFormatFlags);
690 } while (Cur != chan->nextBuffer);
692 if (chan->mode & NGENE_IO_TSOUT) {
693 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate =
695 chan->AudioDTOUpdated = 0;
697 Cur = chan->TSIdleBuffer.Head;
700 memset(&Cur->ngeneBuffer.SR, 0,
701 sizeof(Cur->ngeneBuffer.SR));
702 FillTSBuffer(Cur->Buffer1,
703 chan->Capture1Length,
704 chan->DataFormatFlags);
706 } while (Cur != chan->TSIdleBuffer.Head);
710 int ngene_command_stream_control(struct ngene *dev, u8 stream, u8 control,
713 struct ngene_channel *chan = &dev->channel[stream];
714 struct ngene_command com;
715 u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300);
716 u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500);
717 u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700);
720 /* down(&dev->stream_mutex); */
721 while (down_trylock(&dev->stream_mutex)) {
722 printk(KERN_INFO DEVICE_NAME ": SC locked\n");
725 memset(&com, 0, sizeof(com));
726 com.cmd.hdr.Opcode = CMD_CONTROL;
727 com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2;
728 com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
729 if (chan->mode & NGENE_IO_TSOUT)
730 com.cmd.StreamControl.Stream |= 0x07;
731 com.cmd.StreamControl.Control = control |
732 (flags & SFLAG_ORDER_LUMA_CHROMA);
733 com.cmd.StreamControl.Mode = mode;
734 com.in_len = sizeof(struct FW_STREAM_CONTROL);
737 printk(KERN_INFO DEVICE_NAME ": Stream=%02x, Control=%02x, Mode=%02x\n",
738 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control,
739 com.cmd.StreamControl.Mode);
742 if (!(control & 0x80)) {
743 spin_lock_irq(&chan->state_lock);
744 if (chan->State == KSSTATE_RUN) {
745 chan->State = KSSTATE_ACQUIRE;
746 chan->HWState = HWSTATE_STOP;
747 spin_unlock_irq(&chan->state_lock);
748 if (ngene_command(dev, &com) < 0) {
749 up(&dev->stream_mutex);
752 /* clear_buffers(chan); */
754 up(&dev->stream_mutex);
757 spin_unlock_irq(&chan->state_lock);
758 up(&dev->stream_mutex);
762 if (mode & SMODE_AUDIO_CAPTURE) {
763 com.cmd.StreamControl.CaptureBlockCount =
764 chan->Capture1Length / AUDIO_BLOCK_SIZE;
765 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
766 } else if (mode & SMODE_TRANSPORT_STREAM) {
767 com.cmd.StreamControl.CaptureBlockCount =
768 chan->Capture1Length / TS_BLOCK_SIZE;
769 com.cmd.StreamControl.MaxLinesPerField =
770 chan->Capture1Length / TS_BLOCK_SIZE;
771 com.cmd.StreamControl.Buffer_Address =
772 chan->TSRingBuffer.PAHead;
773 if (chan->mode & NGENE_IO_TSOUT) {
774 com.cmd.StreamControl.BytesPerVBILine =
775 chan->Capture1Length / TS_BLOCK_SIZE;
776 com.cmd.StreamControl.Stream |= 0x07;
779 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine;
780 com.cmd.StreamControl.MaxLinesPerField = chan->nLines;
781 com.cmd.StreamControl.MinLinesPerField = 100;
782 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
784 if (mode & SMODE_VBI_CAPTURE) {
785 com.cmd.StreamControl.MaxVBILinesPerField =
787 com.cmd.StreamControl.MinVBILinesPerField = 0;
788 com.cmd.StreamControl.BytesPerVBILine =
789 chan->nBytesPerVBILine;
791 if (flags & SFLAG_COLORBAR)
792 com.cmd.StreamControl.Stream |= 0x04;
795 spin_lock_irq(&chan->state_lock);
796 if (mode & SMODE_AUDIO_CAPTURE) {
797 chan->nextBuffer = chan->RingBuffer.Head;
798 if (mode & SMODE_AUDIO_SPDIF) {
799 com.cmd.StreamControl.SetupDataLen =
800 sizeof(SPDIFConfiguration);
801 com.cmd.StreamControl.SetupDataAddr = BsSPI;
802 memcpy(com.cmd.StreamControl.SetupData,
803 SPDIFConfiguration, sizeof(SPDIFConfiguration));
805 com.cmd.StreamControl.SetupDataLen = 4;
806 com.cmd.StreamControl.SetupDataAddr = BsSDI;
807 memcpy(com.cmd.StreamControl.SetupData,
809 4 * dev->card_info->i2s[stream], 4);
811 } else if (mode & SMODE_TRANSPORT_STREAM) {
812 chan->nextBuffer = chan->TSRingBuffer.Head;
813 if (stream >= STREAM_AUDIOIN1) {
814 if (chan->mode & NGENE_IO_TSOUT) {
815 com.cmd.StreamControl.SetupDataLen =
816 sizeof(TS_I2SOutConfiguration);
817 com.cmd.StreamControl.SetupDataAddr = BsSDO;
818 memcpy(com.cmd.StreamControl.SetupData,
819 TS_I2SOutConfiguration,
820 sizeof(TS_I2SOutConfiguration));
822 com.cmd.StreamControl.SetupDataLen =
823 sizeof(TS_I2SConfiguration);
824 com.cmd.StreamControl.SetupDataAddr = BsSDI;
825 memcpy(com.cmd.StreamControl.SetupData,
827 sizeof(TS_I2SConfiguration));
830 com.cmd.StreamControl.SetupDataLen = 8;
831 com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10;
832 memcpy(com.cmd.StreamControl.SetupData,
833 TSFeatureDecoderSetup +
834 8 * dev->card_info->tsf[stream], 8);
837 chan->nextBuffer = chan->RingBuffer.Head;
838 com.cmd.StreamControl.SetupDataLen =
839 16 + sizeof(ITUFeatureDecoderSetup);
840 com.cmd.StreamControl.SetupDataAddr = BsUVI;
841 memcpy(com.cmd.StreamControl.SetupData,
842 ITUDecoderSetup[chan->itumode], 16);
843 memcpy(com.cmd.StreamControl.SetupData + 16,
844 ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup));
847 chan->State = KSSTATE_RUN;
848 if (mode & SMODE_TRANSPORT_STREAM)
849 chan->HWState = HWSTATE_RUN;
851 chan->HWState = HWSTATE_STARTUP;
852 spin_unlock_irq(&chan->state_lock);
854 if (ngene_command(dev, &com) < 0) {
855 up(&dev->stream_mutex);
858 up(&dev->stream_mutex);
862 int ngene_stream_control(struct ngene *dev, u8 stream, u8 control, u8 mode,
863 u16 lines, u16 bpl, u16 vblines, u16 vbibpl)
865 if (!(mode & SMODE_TRANSPORT_STREAM))
868 if (lines * bpl > MAX_VIDEO_BUFFER_SIZE)
871 if ((mode & SMODE_TRANSPORT_STREAM) && (((bpl * lines) & 0xff) != 0))
874 if ((mode & SMODE_VIDEO_CAPTURE) && (bpl & 7) != 0)
877 return ngene_command_stream_control(dev, stream, control, mode, 0);
880 /****************************************************************************/
881 /* I2C **********************************************************************/
882 /****************************************************************************/
884 static void ngene_i2c_set_bus(struct ngene *dev, int bus)
886 if (!(dev->card_info->i2c_access & 2))
888 if (dev->i2c_current_bus == bus)
893 ngene_command_gpio_set(dev, 3, 0);
894 ngene_command_gpio_set(dev, 2, 1);
898 ngene_command_gpio_set(dev, 2, 0);
899 ngene_command_gpio_set(dev, 3, 1);
902 dev->i2c_current_bus = bus;
905 static int ngene_i2c_master_xfer(struct i2c_adapter *adapter,
906 struct i2c_msg msg[], int num)
908 struct ngene_channel *chan =
909 (struct ngene_channel *)i2c_get_adapdata(adapter);
910 struct ngene *dev = chan->dev;
912 down(&dev->i2c_switch_mutex);
913 ngene_i2c_set_bus(dev, chan->number);
915 if (num == 2 && msg[1].flags & I2C_M_RD && !(msg[0].flags & I2C_M_RD))
916 if (!ngene_command_i2c_read(dev, msg[0].addr,
917 msg[0].buf, msg[0].len,
918 msg[1].buf, msg[1].len, 0))
921 if (num == 1 && !(msg[0].flags & I2C_M_RD))
922 if (!ngene_command_i2c_write(dev, msg[0].addr,
923 msg[0].buf, msg[0].len))
925 if (num == 1 && (msg[0].flags & I2C_M_RD))
926 if (!ngene_command_i2c_read(dev, msg[0].addr, 0, 0,
927 msg[0].buf, msg[0].len, 0))
930 up(&dev->i2c_switch_mutex);
934 up(&dev->i2c_switch_mutex);
940 static u32 ngene_i2c_functionality(struct i2c_adapter *adap)
942 return I2C_FUNC_SMBUS_EMUL;
945 struct i2c_algorithm ngene_i2c_algo = {
946 .master_xfer = ngene_i2c_master_xfer,
947 .functionality = ngene_i2c_functionality,
950 static int ngene_i2c_init(struct ngene *dev, int dev_nr)
952 struct i2c_adapter *adap = &(dev->channel[dev_nr].i2c_adapter);
954 i2c_set_adapdata(adap, &(dev->channel[dev_nr]));
955 #ifdef I2C_ADAP_CLASS_TV_DIGITAL
956 adap->class = I2C_ADAP_CLASS_TV_DIGITAL | I2C_CLASS_TV_ANALOG;
958 adap->class = I2C_CLASS_TV_ANALOG;
961 strcpy(adap->name, "nGene");
963 adap->id = I2C_HW_SAA7146;
964 adap->algo = &ngene_i2c_algo;
965 adap->algo_data = (void *)&(dev->channel[dev_nr]);
967 mutex_init(&adap->bus_lock);
968 return i2c_add_adapter(adap);
971 int i2c_write(struct i2c_adapter *adapter, u8 adr, u8 data)
974 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 1};
976 if (i2c_transfer(adapter, &msg, 1) != 1) {
977 printk(KERN_ERR DEVICE_NAME
978 ": Failed to write to I2C adr %02x!\n", adr);
985 static int i2c_write_read(struct i2c_adapter *adapter,
986 u8 adr, u8 *w, u8 wlen, u8 *r, u8 rlen)
988 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
989 .buf = w, .len = wlen},
990 {.addr = adr, .flags = I2C_M_RD,
991 .buf = r, .len = rlen} };
993 if (i2c_transfer(adapter, msgs, 2) != 2) {
994 printk(KERN_ERR DEVICE_NAME ": error in i2c_write_read\n");
1000 static int test_dec_i2c(struct i2c_adapter *adapter, int reg)
1002 u8 data[256] = { reg, 0x00, 0x93, 0x78, 0x43, 0x45 };
1006 memset(data2, 0, 256);
1007 i2c_write_read(adapter, 0x66, data, 2, data2, 4);
1008 for (i = 0; i < 4; i++)
1009 printk("%02x ", data2[i]);
1016 /****************************************************************************/
1017 /* EEPROM TAGS **************************************************************/
1018 /****************************************************************************/
1020 #define MICNG_EE_START 0x0100
1021 #define MICNG_EE_END 0x0FF0
1023 #define MICNG_EETAG_END0 0x0000
1024 #define MICNG_EETAG_END1 0xFFFF
1026 /* 0x0001 - 0x000F reserved for housekeeping */
1027 /* 0xFFFF - 0xFFFE reserved for housekeeping */
1029 /* Micronas assigned tags
1030 EEProm tags for hardware support */
1032 #define MICNG_EETAG_DRXD1_OSCDEVIATION 0x1000 /* 2 Bytes data */
1033 #define MICNG_EETAG_DRXD2_OSCDEVIATION 0x1001 /* 2 Bytes data */
1035 #define MICNG_EETAG_MT2060_1_1STIF 0x1100 /* 2 Bytes data */
1036 #define MICNG_EETAG_MT2060_2_1STIF 0x1101 /* 2 Bytes data */
1038 /* Tag range for OEMs */
1040 #define MICNG_EETAG_OEM_FIRST 0xC000
1041 #define MICNG_EETAG_OEM_LAST 0xFFEF
1043 static int i2c_write_eeprom(struct i2c_adapter *adapter,
1044 u8 adr, u16 reg, u8 data)
1046 u8 m[3] = {(reg >> 8), (reg & 0xff), data};
1047 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m,
1050 if (i2c_transfer(adapter, &msg, 1) != 1) {
1051 dprintk(KERN_DEBUG DEVICE_NAME ": Error writing EEPROM!\n");
1057 static int i2c_read_eeprom(struct i2c_adapter *adapter,
1058 u8 adr, u16 reg, u8 *data, int len)
1060 u8 msg[2] = {(reg >> 8), (reg & 0xff)};
1061 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
1062 .buf = msg, .len = 2 },
1063 {.addr = adr, .flags = I2C_M_RD,
1064 .buf = data, .len = len} };
1066 if (i2c_transfer(adapter, msgs, 2) != 2) {
1067 dprintk(KERN_DEBUG DEVICE_NAME ": Error reading EEPROM\n");
1074 static int i2c_dump_eeprom(struct i2c_adapter *adapter, u8 adr)
1079 if (i2c_read_eeprom(adapter, adr, 0x0000, buf, sizeof(buf))) {
1080 printk(KERN_ERR DEVICE_NAME ": No EEPROM?\n");
1083 for (i = 0; i < sizeof(buf); i++) {
1086 printk("%02x ", buf[i]);
1093 static int i2c_copy_eeprom(struct i2c_adapter *adapter, u8 adr, u8 adr2)
1098 if (i2c_read_eeprom(adapter, adr, 0x0000, buf, sizeof(buf))) {
1099 printk(KERN_ERR DEVICE_NAME ": No EEPROM?\n");
1104 for (i = 0; i < sizeof(buf); i++) {
1105 i2c_write_eeprom(adapter, adr2, i, buf[i]);
1112 /****************************************************************************/
1113 /* COMMAND API interface ****************************************************/
1114 /****************************************************************************/
1116 #ifdef NGENE_COMMAND_API
1118 static int command_do_ioctl(struct inode *inode, struct file *file,
1119 unsigned int cmd, void *parg)
1121 struct dvb_device *dvbdev = file->private_data;
1122 struct ngene_channel *chan = dvbdev->priv;
1123 struct ngene *dev = chan->dev;
1127 case IOCTL_MIC_NO_OP:
1128 err = ngene_command_nop(dev);
1131 case IOCTL_MIC_DOWNLOAD_FIRMWARE:
1134 case IOCTL_MIC_I2C_READ:
1136 MIC_I2C_READ *msg = parg;
1138 err = ngene_command_i2c_read(dev, msg->I2CAddress >> 1,
1139 msg->OutData, msg->OutLength,
1140 msg->OutData, msg->InLength, 1);
1144 case IOCTL_MIC_I2C_WRITE:
1146 MIC_I2C_WRITE *msg = parg;
1148 err = ngene_command_i2c_write(dev, msg->I2CAddress >> 1,
1149 msg->Data, msg->Length);
1153 case IOCTL_MIC_TEST_GETMEM:
1157 if (m->Length > 64 * 1024 || m->Start + m->Length > 64 * 1024)
1160 /* WARNING, only use this on x86,
1161 other archs may not swallow this */
1162 err = copy_to_user(m->Data, dev->iomem + m->Start, m->Length);
1166 case IOCTL_MIC_TEST_SETMEM:
1170 if (m->Length > 64 * 1024 || m->Start + m->Length > 64 * 1024)
1173 err = copy_from_user(dev->iomem + m->Start, m->Data, m->Length);
1177 case IOCTL_MIC_SFR_READ:
1181 err = ngene_command_imem_read(dev, m->Address, &m->Data, 1);
1185 case IOCTL_MIC_SFR_WRITE:
1189 err = ngene_command_imem_write(dev, m->Address, m->Data, 1);
1193 case IOCTL_MIC_IRAM_READ:
1197 err = ngene_command_imem_read(dev, m->Address, &m->Data, 0);
1201 case IOCTL_MIC_IRAM_WRITE:
1205 err = ngene_command_imem_write(dev, m->Address, m->Data, 0);
1209 case IOCTL_MIC_STREAM_CONTROL:
1211 MIC_STREAM_CONTROL *m = parg;
1213 err = ngene_stream_control(dev, m->Stream, m->Control, m->Mode,
1214 m->nLines, m->nBytesPerLine,
1215 m->nVBILines, m->nBytesPerVBILine);
1226 static int command_ioctl(struct inode *inode, struct file *file,
1227 unsigned int cmd, unsigned long arg)
1229 void *parg = (void *)arg, *pbuf = NULL;
1233 if (_IOC_DIR(cmd) & _IOC_WRITE) {
1235 if (_IOC_SIZE(cmd) > sizeof(buf)) {
1236 pbuf = kmalloc(_IOC_SIZE(cmd), GFP_KERNEL);
1241 if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd)))
1244 res = command_do_ioctl(inode, file, cmd, parg);
1247 if (_IOC_DIR(cmd) & _IOC_READ)
1248 if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd)))
1255 struct page *ngene_nopage(struct vm_area_struct *vma,
1256 unsigned long address, int *type)
1261 static int ngene_mmap(struct file *file, struct vm_area_struct *vma)
1263 struct dvb_device *dvbdev = file->private_data;
1264 struct ngene_channel *chan = dvbdev->priv;
1265 struct ngene *dev = chan->dev;
1267 unsigned long size = vma->vm_end - vma->vm_start;
1268 unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
1269 unsigned long padr = pci_resource_start(dev->pci_dev, 0) + off;
1270 unsigned long psize = pci_resource_len(dev->pci_dev, 0) - off;
1275 if (io_remap_pfn_range(vma, vma->vm_start, padr >> PAGE_SHIFT, size,
1281 static int write_uart(struct ngene *dev, u8 *data, int len)
1283 struct ngene_command com;
1285 com.cmd.hdr.Opcode = CMD_WRITE_UART;
1286 com.cmd.hdr.Length = len;
1287 memcpy(com.cmd.WriteUart.Data, data, len);
1288 com.cmd.WriteUart.Data[len] = 0;
1289 com.cmd.WriteUart.Data[len + 1] = 0;
1293 if (ngene_command(dev, &com) < 0)
1299 static int send_cli(struct ngene *dev, char *cmd)
1301 /* printk(KERN_INFO DEVICE_NAME ": %s", cmd); */
1302 return write_uart(dev, cmd, strlen(cmd));
1305 static int send_cli_val(struct ngene *dev, char *cmd, u32 val)
1309 snprintf(s, 32, "%s %d\n", cmd, val);
1310 /* printk(KERN_INFO DEVICE_NAME ": %s", s); */
1311 return write_uart(dev, s, strlen(s));
1314 static int ngene_command_write_uart_user(struct ngene *dev,
1315 const u8 *data, int len)
1317 struct ngene_command com;
1320 com.cmd.hdr.Opcode = CMD_WRITE_UART;
1321 com.cmd.hdr.Length = len;
1323 if (copy_from_user(com.cmd.WriteUart.Data, data, len))
1328 if (ngene_command(dev, &com) < 0)
1334 static ssize_t uart_write(struct file *file, const char *buf,
1335 size_t count, loff_t *ppos)
1337 struct dvb_device *dvbdev = file->private_data;
1338 struct ngene_channel *chan = dvbdev->priv;
1339 struct ngene *dev = chan->dev;
1341 size_t left = count;
1347 ret = wait_event_interruptible(dev->tx_wq, dev->tx_busy == 0);
1350 ngene_command_write_uart_user(dev, buf, len);
1357 static ssize_t ts_write(struct file *file, const char *buf,
1358 size_t count, loff_t *ppos)
1360 struct dvb_device *dvbdev = file->private_data;
1361 struct ngene_channel *chan = dvbdev->priv;
1362 struct ngene *dev = chan->dev;
1364 if (wait_event_interruptible(dev->tsout_rbuf.queue,
1366 (&dev->tsout_rbuf) >= count) < 0)
1369 dvb_ringbuffer_write(&dev->tsout_rbuf, buf, count);
1374 static ssize_t uart_read(struct file *file, char *buf,
1375 size_t count, loff_t *ppos)
1377 struct dvb_device *dvbdev = file->private_data;
1378 struct ngene_channel *chan = dvbdev->priv;
1379 struct ngene *dev = chan->dev;
1381 int wp, rp, avail, len;
1383 if (!dev->uart_rbuf)
1389 if (wait_event_interruptible(dev->rx_wq,
1390 dev->uart_wp != dev->uart_rp) < 0)
1397 avail += UART_RBUF_LEN;
1401 len = UART_RBUF_LEN - rp;
1404 if (copy_to_user(buf, dev->uart_rbuf + rp, len))
1407 if (copy_to_user(buf + len, dev->uart_rbuf,
1411 if (copy_to_user(buf, dev->uart_rbuf + rp, avail))
1414 dev->uart_rp = (rp + avail) % UART_RBUF_LEN;
1421 static const struct file_operations command_fops = {
1422 .owner = THIS_MODULE,
1425 .ioctl = command_ioctl,
1426 .open = dvb_generic_open,
1427 .release = dvb_generic_release,
1432 static struct dvb_device dvbdev_command = {
1437 .fops = &command_fops,
1442 /****************************************************************************/
1443 /* DVB functions and API interface ******************************************/
1444 /****************************************************************************/
1446 static void swap_buffer(u32 *p, u32 len)
1456 static void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags)
1458 struct ngene_channel *chan = priv;
1461 dvb_dmx_swfilter(&chan->demux, buf, len);
1465 u8 fill_ts[188] = { 0x47, 0x1f, 0xff, 0x10 };
1467 static void *tsout_exchange(void *priv, void *buf, u32 len,
1468 u32 clock, u32 flags)
1470 struct ngene_channel *chan = priv;
1471 struct ngene *dev = chan->dev;
1474 alen = dvb_ringbuffer_avail(&dev->tsout_rbuf);
1478 FillTSBuffer(buf + alen, len - alen, flags);
1481 dvb_ringbuffer_read(&dev->tsout_rbuf, buf, alen);
1482 if (flags & DF_SWAP32)
1483 swap_buffer((u32 *)buf, alen);
1484 wake_up_interruptible(&dev->tsout_rbuf.queue);
1489 static void set_transfer(struct ngene_channel *chan, int state)
1491 u8 control = 0, mode = 0, flags = 0;
1492 struct ngene *dev = chan->dev;
1501 printk(KERN_INFO DEVICE_NAME ": st %d\n", state);
1506 if (chan->running) {
1507 printk(KERN_INFO DEVICE_NAME ": already running\n");
1511 if (!chan->running) {
1512 printk(KERN_INFO DEVICE_NAME ": already stopped\n");
1517 if (dev->card_info->switch_ctrl)
1518 dev->card_info->switch_ctrl(chan, 1, state ^ 1);
1521 spin_lock_irq(&chan->state_lock);
1523 /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
1524 ngreadl(0x9310)); */
1525 my_dvb_ringbuffer_flush(&dev->tsout_rbuf);
1527 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1528 chan->Capture1Length = 512 * 188;
1529 mode = SMODE_TRANSPORT_STREAM;
1531 if (chan->mode & NGENE_IO_TSOUT) {
1532 chan->pBufferExchange = tsout_exchange;
1533 /* 0x66666666 = 50MHz *2^33 /250MHz */
1534 chan->AudioDTOValue = 0x66666666;
1535 /* set_dto(chan, 38810700+1000); */
1536 /* set_dto(chan, 19392658); */
1538 if (chan->mode & NGENE_IO_TSIN)
1539 chan->pBufferExchange = tsin_exchange;
1540 /* ngwritel(0, 0x9310); */
1541 spin_unlock_irq(&chan->state_lock);
1543 ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n",
1544 ngreadl(0x9310)); */
1546 ret = ngene_command_stream_control(dev, chan->number,
1547 control, mode, flags);
1549 chan->running = state;
1551 printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n",
1554 spin_lock_irq(&chan->state_lock);
1555 chan->pBufferExchange = 0;
1556 my_dvb_ringbuffer_flush(&dev->tsout_rbuf);
1557 spin_unlock_irq(&chan->state_lock);
1561 static int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed)
1563 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
1564 struct ngene_channel *chan = dvbdmx->priv;
1565 #ifdef NGENE_COMMAND_API
1566 struct ngene *dev = chan->dev;
1568 if (dev->card_info->io_type[chan->number] & NGENE_IO_TSOUT) {
1569 switch (dvbdmxfeed->pes_type) {
1570 case DMX_TS_PES_VIDEO:
1571 send_cli_val(dev, "vpid", dvbdmxfeed->pid);
1572 send_cli(dev, "res 1080i50\n");
1573 /* send_cli(dev, "vdec mpeg2\n"); */
1576 case DMX_TS_PES_AUDIO:
1577 send_cli_val(dev, "apid", dvbdmxfeed->pid);
1578 send_cli(dev, "start\n");
1581 case DMX_TS_PES_PCR:
1582 send_cli_val(dev, "pcrpid", dvbdmxfeed->pid);
1592 if (chan->users == 0) {
1593 set_transfer(chan, 1);
1597 return ++chan->users;
1600 static int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
1602 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
1603 struct ngene_channel *chan = dvbdmx->priv;
1604 #ifdef NGENE_COMMAND_API
1605 struct ngene *dev = chan->dev;
1607 if (dev->card_info->io_type[chan->number] & NGENE_IO_TSOUT) {
1608 switch (dvbdmxfeed->pes_type) {
1609 case DMX_TS_PES_VIDEO:
1610 send_cli(dev, "stop\n");
1613 case DMX_TS_PES_AUDIO:
1616 case DMX_TS_PES_PCR:
1629 set_transfer(chan, 0);
1636 static int write_to_decoder(struct dvb_demux_feed *feed,
1637 const u8 *buf, size_t len)
1639 struct dvb_demux *dvbdmx = feed->demux;
1640 struct ngene_channel *chan = dvbdmx->priv;
1641 struct ngene *dev = chan->dev;
1643 if (wait_event_interruptible(dev->tsout_rbuf.queue,
1645 (&dev->tsout_rbuf) >= len) < 0)
1648 dvb_ringbuffer_write(&dev->tsout_rbuf, buf, len);
1653 static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
1654 int (*start_feed)(struct dvb_demux_feed *),
1655 int (*stop_feed)(struct dvb_demux_feed *),
1658 dvbdemux->priv = priv;
1660 dvbdemux->filternum = 256;
1661 dvbdemux->feednum = 256;
1662 dvbdemux->start_feed = start_feed;
1663 dvbdemux->stop_feed = stop_feed;
1664 dvbdemux->write_to_decoder = 0;
1665 dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
1666 DMX_SECTION_FILTERING |
1667 DMX_MEMORY_BASED_FILTERING);
1668 return dvb_dmx_init(dvbdemux);
1671 static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
1672 struct dvb_demux *dvbdemux,
1673 struct dmx_frontend *hw_frontend,
1674 struct dmx_frontend *mem_frontend,
1675 struct dvb_adapter *dvb_adapter)
1679 dmxdev->filternum = 256;
1680 dmxdev->demux = &dvbdemux->dmx;
1681 dmxdev->capabilities = 0;
1682 ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
1686 hw_frontend->source = DMX_FRONTEND_0;
1687 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
1688 mem_frontend->source = DMX_MEMORY_FE;
1689 dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
1690 return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
1693 /****************************************************************************/
1694 /* Decypher firmware loading ************************************************/
1695 /****************************************************************************/
1697 #define DECYPHER_FW "decypher.fw"
1699 static int dec_ts_send(struct ngene *dev, u8 *buf, u32 len)
1701 while (dvb_ringbuffer_free(&dev->tsout_rbuf) < len)
1705 dvb_ringbuffer_write(&dev->tsout_rbuf, buf, len);
1710 u8 dec_fw_fill_ts[188] = { 0x47, 0x09, 0x0e, 0x10, 0xff, 0xff, 0x00, 0x00 };
1712 int dec_fw_send(struct ngene *dev, u8 *fw, u32 size)
1714 struct ngene_channel *chan = &dev->channel[4];
1715 u32 len = 180, cc = 0;
1716 u8 buf[8] = { 0x47, 0x09, 0x0e, 0x10, 0x00, 0x00, 0x00, 0x00 };
1718 set_transfer(chan, 1);
1724 buf[3] = 0x10 | (cc & 0x0f);
1729 dec_ts_send(dev, buf, 8);
1730 dec_ts_send(dev, fw, len);
1732 dec_ts_send(dev, dec_fw_fill_ts + len + 8, 180 - len);
1737 for (len = 0; len < 512; len++)
1738 dec_ts_send(dev, dec_fw_fill_ts, 188);
1739 while (dvb_ringbuffer_avail(&dev->tsout_rbuf))
1742 set_transfer(chan, 0);
1746 int dec_fw_boot(struct ngene *dev)
1749 const struct firmware *fw = NULL;
1752 if (request_firmware(&fw, DECYPHER_FW, &dev->pci_dev->dev) < 0) {
1753 printk(KERN_ERR DEVICE_NAME
1754 ": %s not found. Check hotplug directory.\n",
1758 printk(KERN_INFO DEVICE_NAME ": Booting decypher firmware file %s\n",
1762 dec_fw = (u8 *)fw->data;
1763 dec_fw_send(dev, dec_fw, size);
1764 release_firmware(fw);
1768 /****************************************************************************/
1769 /* nGene hardware init and release functions ********************************/
1770 /****************************************************************************/
1772 void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb)
1774 struct SBufferHeader *Cur = rb->Head;
1780 for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) {
1782 pci_free_consistent(dev->pci_dev,
1785 Cur->scList1->Address);
1788 pci_free_consistent(dev->pci_dev,
1791 Cur->scList2->Address);
1795 pci_free_consistent(dev->pci_dev, rb->SCListMemSize,
1796 rb->SCListMem, rb->PASCListMem);
1798 pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead);
1801 void free_idlebuffer(struct ngene *dev,
1802 struct SRingBufferDescriptor *rb,
1803 struct SRingBufferDescriptor *tb)
1806 struct SBufferHeader *Cur = tb->Head;
1810 free_ringbuffer(dev, rb);
1811 for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) {
1814 Cur->ngeneBuffer.Address_of_first_entry_2 = 0;
1815 Cur->ngeneBuffer.Number_of_entries_2 = 0;
1819 void free_common_buffers(struct ngene *dev)
1822 struct ngene_channel *chan;
1824 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1825 chan = &dev->channel[i];
1826 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer);
1827 free_ringbuffer(dev, &chan->RingBuffer);
1828 free_ringbuffer(dev, &chan->TSRingBuffer);
1831 if (dev->OverflowBuffer)
1832 pci_free_consistent(dev->pci_dev,
1833 OVERFLOW_BUFFER_SIZE,
1834 dev->OverflowBuffer, dev->PAOverflowBuffer);
1836 if (dev->FWInterfaceBuffer)
1837 pci_free_consistent(dev->pci_dev,
1839 dev->FWInterfaceBuffer,
1840 dev->PAFWInterfaceBuffer);
1843 /****************************************************************************/
1844 /* Ring buffer handling *****************************************************/
1845 /****************************************************************************/
1847 int create_ring_buffer(struct pci_dev *pci_dev,
1848 struct SRingBufferDescriptor *descr, u32 NumBuffers)
1851 struct SBufferHeader *Head;
1853 u32 MemSize = SIZEOF_SBufferHeader * NumBuffers;
1854 u64 PARingBufferHead;
1855 u64 PARingBufferCur;
1856 u64 PARingBufferNext;
1857 struct SBufferHeader *Cur, *Next;
1862 descr->NumBuffers = 0;
1867 Head = pci_alloc_consistent(pci_dev, MemSize, &tmp);
1868 PARingBufferHead = tmp;
1873 memset(Head, 0, MemSize);
1875 PARingBufferCur = PARingBufferHead;
1878 for (i = 0; i < NumBuffers - 1; i++) {
1879 Next = (struct SBufferHeader *)
1880 (((u8 *) Cur) + SIZEOF_SBufferHeader);
1881 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader;
1883 Cur->ngeneBuffer.Next = PARingBufferNext;
1885 PARingBufferCur = PARingBufferNext;
1887 /* Last Buffer points back to first one */
1889 Cur->ngeneBuffer.Next = PARingBufferHead;
1892 descr->MemSize = MemSize;
1893 descr->PAHead = PARingBufferHead;
1894 descr->NumBuffers = NumBuffers;
1899 static int AllocateRingBuffers(struct pci_dev *pci_dev,
1901 struct SRingBufferDescriptor *pRingBuffer,
1902 u32 Buffer1Length, u32 Buffer2Length)
1907 u32 SCListMemSize = pRingBuffer->NumBuffers
1908 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) :
1909 NUM_SCATTER_GATHER_ENTRIES)
1910 * sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1913 PHW_SCATTER_GATHER_ELEMENT SCListEntry;
1915 struct SBufferHeader *Cur;
1918 if (SCListMemSize < 4096)
1919 SCListMemSize = 4096;
1921 SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp);
1924 if (SCListMem == NULL)
1927 memset(SCListMem, 0, SCListMemSize);
1929 pRingBuffer->SCListMem = SCListMem;
1930 pRingBuffer->PASCListMem = PASCListMem;
1931 pRingBuffer->SCListMemSize = SCListMemSize;
1932 pRingBuffer->Buffer1Length = Buffer1Length;
1933 pRingBuffer->Buffer2Length = Buffer2Length;
1935 SCListEntry = (PHW_SCATTER_GATHER_ELEMENT) SCListMem;
1936 PASCListEntry = PASCListMem;
1937 Cur = pRingBuffer->Head;
1939 for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) {
1942 void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length,
1949 Cur->Buffer1 = Buffer;
1951 SCListEntry->Address = PABuffer;
1952 SCListEntry->Length = Buffer1Length;
1954 Cur->scList1 = SCListEntry;
1955 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry;
1956 Cur->ngeneBuffer.Number_of_entries_1 =
1957 NUM_SCATTER_GATHER_ENTRIES;
1960 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1962 #if NUM_SCATTER_GATHER_ENTRIES > 1
1963 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) {
1964 SCListEntry->Address = of;
1965 SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
1968 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1975 Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp);
1981 Cur->Buffer2 = Buffer;
1983 SCListEntry->Address = PABuffer;
1984 SCListEntry->Length = Buffer2Length;
1986 Cur->scList2 = SCListEntry;
1987 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry;
1988 Cur->ngeneBuffer.Number_of_entries_2 =
1989 NUM_SCATTER_GATHER_ENTRIES;
1992 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
1994 #if NUM_SCATTER_GATHER_ENTRIES > 1
1995 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) {
1996 SCListEntry->Address = of;
1997 SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
2000 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
2009 static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer,
2010 struct SRingBufferDescriptor *pRingBuffer)
2014 /* Copy pointer to scatter gather list in TSRingbuffer
2015 structure for buffer 2
2016 Load number of buffer
2018 u32 n = pRingBuffer->NumBuffers;
2020 /* Point to first buffer entry */
2021 struct SBufferHeader *Cur = pRingBuffer->Head;
2023 /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */
2024 for (i = 0; i < n; i++) {
2025 Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
2026 Cur->scList2 = pIdleBuffer->Head->scList1;
2027 Cur->ngeneBuffer.Address_of_first_entry_2 =
2028 pIdleBuffer->Head->ngeneBuffer.
2029 Address_of_first_entry_1;
2030 Cur->ngeneBuffer.Number_of_entries_2 =
2031 pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1;
2037 static u32 RingBufferSizes[MAX_STREAM] = {
2045 static u32 Buffer1Sizes[MAX_STREAM] = {
2046 MAX_VIDEO_BUFFER_SIZE,
2047 MAX_VIDEO_BUFFER_SIZE,
2048 MAX_AUDIO_BUFFER_SIZE,
2049 MAX_AUDIO_BUFFER_SIZE,
2050 MAX_AUDIO_BUFFER_SIZE
2053 static u32 Buffer2Sizes[MAX_STREAM] = {
2054 MAX_VBI_BUFFER_SIZE,
2055 MAX_VBI_BUFFER_SIZE,
2062 static int AllocCommonBuffers(struct ngene *dev)
2066 dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096,
2067 &dev->PAFWInterfaceBuffer);
2068 if (!dev->FWInterfaceBuffer)
2070 dev->hosttongene = dev->FWInterfaceBuffer;
2071 dev->ngenetohost = dev->FWInterfaceBuffer + 256;
2072 dev->EventBuffer = dev->FWInterfaceBuffer + 512;
2074 dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev,
2075 OVERFLOW_BUFFER_SIZE,
2076 &dev->PAOverflowBuffer);
2077 if (!dev->OverflowBuffer)
2079 memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE);
2081 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
2082 int type = dev->card_info->io_type[i];
2084 dev->channel[i].State = KSSTATE_STOP;
2086 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
2087 status = create_ring_buffer(dev->pci_dev,
2088 &dev->channel[i].RingBuffer,
2089 RingBufferSizes[i]);
2093 if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
2094 status = AllocateRingBuffers(dev->pci_dev,
2103 } else if (type & NGENE_IO_HDTV) {
2104 status = AllocateRingBuffers(dev->pci_dev,
2109 MAX_HDTV_BUFFER_SIZE,
2116 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
2118 status = create_ring_buffer(dev->pci_dev,
2120 TSRingBuffer, RING_SIZE_TS);
2124 status = AllocateRingBuffers(dev->pci_dev,
2125 dev->PAOverflowBuffer,
2128 MAX_TS_BUFFER_SIZE, 0);
2133 if (type & NGENE_IO_TSOUT) {
2134 status = create_ring_buffer(dev->pci_dev,
2139 status = AllocateRingBuffers(dev->pci_dev,
2140 dev->PAOverflowBuffer,
2143 MAX_TS_BUFFER_SIZE, 0);
2146 FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer,
2147 &dev->channel[i].TSRingBuffer);
2153 static void ngene_release_buffers(struct ngene *dev)
2156 iounmap(dev->iomem);
2157 free_common_buffers(dev);
2158 vfree(dev->tsout_buf);
2159 vfree(dev->ain_buf);
2160 vfree(dev->vin_buf);
2164 static int ngene_get_buffers(struct ngene *dev)
2166 if (AllocCommonBuffers(dev))
2168 if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) {
2169 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE);
2170 if (!dev->tsout_buf)
2172 dvb_ringbuffer_init(&dev->tsout_rbuf,
2173 dev->tsout_buf, TSOUT_BUF_SIZE);
2175 if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
2176 dev->ain_buf = vmalloc(AIN_BUF_SIZE);
2179 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE);
2181 if (dev->card_info->io_type[0] & NGENE_IO_HDTV) {
2182 dev->vin_buf = vmalloc(VIN_BUF_SIZE);
2185 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE);
2187 dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0),
2188 pci_resource_len(dev->pci_dev, 0));
2195 static void ngene_init(struct ngene *dev)
2199 tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev);
2201 memset_io(dev->iomem + 0xc000, 0x00, 0x220);
2202 memset_io(dev->iomem + 0xc400, 0x00, 0x100);
2204 for (i = 0; i < MAX_STREAM; i++) {
2205 dev->channel[i].dev = dev;
2206 dev->channel[i].number = i;
2209 dev->fw_interface_version = 0;
2211 ngwritel(0, NGENE_INT_ENABLE);
2213 dev->icounts = ngreadl(NGENE_INT_COUNTS);
2215 dev->device_version = ngreadl(DEV_VER) & 0x0f;
2216 printk(KERN_INFO DEVICE_NAME ": Device version %d\n",
2217 dev->device_version);
2220 static int ngene_load_firm(struct ngene *dev)
2223 const struct firmware *fw = NULL;
2228 version = dev->card_info->fw_version;
2235 fw_name = "ngene_15.fw";
2239 fw_name = "ngene_16.fw";
2243 fw_name = "ngene_17.fw";
2247 if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
2248 printk(KERN_ERR DEVICE_NAME
2249 ": Could not load firmware file %s.\n", fw_name);
2250 printk(KERN_INFO DEVICE_NAME
2251 ": Copy %s to your hotplug directory!\n", fw_name);
2254 if (size != fw->size) {
2255 printk(KERN_ERR DEVICE_NAME
2256 ": Firmware %s has invalid size!", fw_name);
2259 printk(KERN_INFO DEVICE_NAME
2260 ": Loading firmware file %s.\n", fw_name);
2261 ngene_fw = (u8 *) fw->data;
2262 err = ngene_command_load_firmware(dev, ngene_fw, size);
2265 release_firmware(fw);
2270 static void ngene_stop(struct ngene *dev)
2272 down(&dev->cmd_mutex);
2273 i2c_del_adapter(&(dev->channel[0].i2c_adapter));
2274 i2c_del_adapter(&(dev->channel[1].i2c_adapter));
2275 ngwritel(0, NGENE_INT_ENABLE);
2276 ngwritel(0, NGENE_COMMAND);
2277 ngwritel(0, NGENE_COMMAND_HI);
2278 ngwritel(0, NGENE_STATUS);
2279 ngwritel(0, NGENE_STATUS_HI);
2280 ngwritel(0, NGENE_EVENT);
2281 ngwritel(0, NGENE_EVENT_HI);
2282 free_irq(dev->pci_dev->irq, dev);
2285 static int ngene_start(struct ngene *dev)
2290 pci_set_master(dev->pci_dev);
2293 stat = request_irq(dev->pci_dev->irq, irq_handler,
2294 IRQF_SHARED, "nGene",
2299 init_waitqueue_head(&dev->cmd_wq);
2300 init_waitqueue_head(&dev->tx_wq);
2301 init_waitqueue_head(&dev->rx_wq);
2302 sema_init(&dev->cmd_mutex, 1);
2303 sema_init(&dev->stream_mutex, 1);
2304 sema_init(&dev->pll_mutex, 1);
2305 sema_init(&dev->i2c_switch_mutex, 1);
2306 spin_lock_init(&dev->cmd_lock);
2307 for (i = 0; i < MAX_STREAM; i++)
2308 spin_lock_init(&dev->channel[i].state_lock);
2309 ngwritel(1, TIMESTAMPS);
2311 ngwritel(1, NGENE_INT_ENABLE);
2313 stat = ngene_load_firm(dev);
2317 stat = ngene_i2c_init(dev, 0);
2321 stat = ngene_i2c_init(dev, 1);
2325 if (dev->card_info->fw_version == 17) {
2327 {6144 / 64, 0, 0, 2048 / 64, 2048 / 64, 2048 / 64};
2328 u8 tsin4_config[6] =
2329 {3072 / 64, 3072 / 64, 0, 3072 / 64, 3072 / 64, 0};
2330 u8 default_config[6] =
2331 {4096 / 64, 4096 / 64, 0, 2048 / 64, 2048 / 64, 0};
2332 u8 *bconf = default_config;
2334 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
2335 bconf = tsin4_config;
2336 if (dev->card_info->io_type[0] == NGENE_IO_HDTV) {
2337 bconf = hdtv_config;
2338 ngene_reset_decypher(dev);
2340 printk(KERN_INFO DEVICE_NAME ": FW 17 buffer config\n");
2341 stat = ngene_command_config_free_buf(dev, bconf);
2343 int bconf = BUFFER_CONFIG_4422;
2345 if (dev->card_info->io_type[0] == NGENE_IO_HDTV) {
2346 bconf = BUFFER_CONFIG_8022;
2347 ngene_reset_decypher(dev);
2349 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
2350 bconf = BUFFER_CONFIG_3333;
2351 stat = ngene_command_config_buf(dev, bconf);
2354 if (dev->card_info->io_type[0] == NGENE_IO_HDTV) {
2355 ngene_command_config_uart(dev, 0xc1, tx_cb, rx_cb);
2356 test_dec_i2c(&dev->channel[0].i2c_adapter, 0);
2357 test_dec_i2c(&dev->channel[0].i2c_adapter, 1);
2362 ngwritel(0, NGENE_INT_ENABLE);
2363 free_irq(dev->pci_dev->irq, dev);
2369 /****************************************************************************/
2370 /* Switch control (I2C gates, etc.) *****************************************/
2371 /****************************************************************************/
2374 /****************************************************************************/
2375 /* Demod/tuner attachment ***************************************************/
2376 /****************************************************************************/
2378 static int tuner_attach_stv6110(struct ngene_channel *chan)
2380 struct stv090x_config *feconf = (struct stv090x_config *)
2381 chan->dev->card_info->fe_config[chan->number];
2382 struct stv6110x_config *tunerconf = (struct stv6110x_config *)
2383 chan->dev->card_info->tuner_config[chan->number];
2384 struct stv6110x_devctl *ctl;
2386 ctl = dvb_attach(stv6110x_attach, chan->fe, tunerconf,
2387 &chan->i2c_adapter);
2389 printk(KERN_ERR DEVICE_NAME ": No STV6110X found!\n");
2393 feconf->tuner_init = ctl->tuner_init;
2394 feconf->tuner_set_mode = ctl->tuner_set_mode;
2395 feconf->tuner_set_frequency = ctl->tuner_set_frequency;
2396 feconf->tuner_get_frequency = ctl->tuner_get_frequency;
2397 feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
2398 feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth;
2399 feconf->tuner_set_bbgain = ctl->tuner_set_bbgain;
2400 feconf->tuner_get_bbgain = ctl->tuner_get_bbgain;
2401 feconf->tuner_set_refclk = ctl->tuner_set_refclk;
2402 feconf->tuner_get_status = ctl->tuner_get_status;
2408 static int demod_attach_stv0900(struct ngene_channel *chan)
2410 struct stv090x_config *feconf = (struct stv090x_config *)
2411 chan->dev->card_info->fe_config[chan->number];
2413 chan->fe = dvb_attach(stv090x_attach,
2416 chan->number == 0 ? STV090x_DEMODULATOR_0 :
2417 STV090x_DEMODULATOR_1);
2418 if (chan->fe == NULL) {
2419 printk(KERN_ERR DEVICE_NAME ": No STV0900 found!\n");
2423 if (!dvb_attach(lnbh24_attach, chan->fe, &chan->i2c_adapter, 0,
2424 0, chan->dev->card_info->lnb[chan->number])) {
2425 printk(KERN_ERR DEVICE_NAME ": No LNBH24 found!\n");
2426 dvb_frontend_detach(chan->fe);
2433 /****************************************************************************/
2434 /****************************************************************************/
2435 /****************************************************************************/
2437 static void release_channel(struct ngene_channel *chan)
2439 struct dvb_demux *dvbdemux = &chan->demux;
2440 struct ngene *dev = chan->dev;
2441 struct ngene_info *ni = dev->card_info;
2442 int io = ni->io_type[chan->number];
2444 tasklet_kill(&chan->demux_tasklet);
2446 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
2447 #ifdef NGENE_COMMAND_API
2448 if (chan->command_dev)
2449 dvb_unregister_device(chan->command_dev);
2452 dvb_unregister_frontend(chan->fe);
2453 /*dvb_frontend_detach(chan->fe); */
2456 dvbdemux->dmx.close(&dvbdemux->dmx);
2457 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
2458 &chan->hw_frontend);
2459 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
2460 &chan->mem_frontend);
2461 dvb_dmxdev_release(&chan->dmxdev);
2462 dvb_dmx_release(&chan->demux);
2464 dvb_unregister_adapter(&chan->dvb_adapter);
2470 static int init_channel(struct ngene_channel *chan)
2472 int ret = 0, nr = chan->number;
2473 struct dvb_adapter *adapter = 0;
2474 struct dvb_demux *dvbdemux = &chan->demux;
2475 struct ngene *dev = chan->dev;
2476 struct ngene_info *ni = dev->card_info;
2477 int io = ni->io_type[nr];
2479 tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan);
2482 chan->mode = chan->type; /* for now only one mode */
2484 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
2485 if (nr >= STREAM_AUDIOIN1)
2486 chan->DataFormatFlags = DF_SWAP32;
2488 if (io & NGENE_IO_TSOUT)
2492 adapter = &chan->dev->dvb_adapter;
2494 ret = dvb_register_adapter(&chan->dvb_adapter, "nGene",
2496 &chan->dev->pci_dev->dev,
2500 adapter = &chan->dvb_adapter;
2502 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
2504 ngene_stop_feed, chan);
2505 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
2507 &chan->mem_frontend, adapter);
2508 if (io & NGENE_IO_TSOUT) {
2509 dvbdemux->write_to_decoder = write_to_decoder;
2511 #ifdef NGENE_COMMAND_API
2512 dvb_register_device(adapter, &chan->command_dev,
2513 &dvbdev_command, (void *)chan,
2518 if (io & NGENE_IO_TSIN) {
2520 if (ni->demod_attach[nr])
2521 ni->demod_attach[nr](chan);
2523 if (dvb_register_frontend(adapter, chan->fe) < 0) {
2524 if (chan->fe->ops.release)
2525 chan->fe->ops.release(chan->fe);
2529 if (chan->fe && ni->tuner_attach[nr])
2530 if (ni->tuner_attach[nr] (chan) < 0) {
2531 printk(KERN_ERR DEVICE_NAME
2532 ": Tuner attach failed on channel %d!\n",
2540 static int init_channels(struct ngene *dev)
2544 for (i = 0; i < MAX_STREAM; i++) {
2545 if (init_channel(&dev->channel[i]) < 0) {
2546 for (j = 0; j < i; j++)
2547 release_channel(&dev->channel[j]);
2554 /****************************************************************************/
2555 /* device probe/remove calls ************************************************/
2556 /****************************************************************************/
2558 static void __devexit ngene_remove(struct pci_dev *pdev)
2560 struct ngene *dev = (struct ngene *)pci_get_drvdata(pdev);
2563 tasklet_kill(&dev->event_tasklet);
2564 for (i = 0; i < MAX_STREAM; i++)
2565 release_channel(&dev->channel[i]);
2567 dvb_unregister_adapter(&dev->dvb_adapter);
2570 ngene_release_buffers(dev);
2571 pci_set_drvdata(pdev, 0);
2572 pci_disable_device(pdev);
2575 static int __devinit ngene_probe(struct pci_dev *pci_dev,
2576 const struct pci_device_id *id)
2581 if (pci_enable_device(pci_dev) < 0)
2584 dev = vmalloc(sizeof(struct ngene));
2587 memset(dev, 0, sizeof(struct ngene));
2589 dev->pci_dev = pci_dev;
2590 dev->card_info = (struct ngene_info *)id->driver_data;
2591 printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name);
2593 pci_set_drvdata(pci_dev, dev);
2595 /* Alloc buffers and start nGene */
2596 stat = ngene_get_buffers(dev);
2599 stat = ngene_start(dev);
2603 dev->i2c_current_bus = -1;
2604 /* Disable analog TV decoder chips if present */
2606 i2c_copy_eeprom(&dev->channel[0].i2c_adapter, 0x50, 0x52);
2607 i2c_dump_eeprom(&dev->channel[0].i2c_adapter, 0x52);
2609 /*i2c_check_eeprom(&dev->i2c_adapter);*/
2611 /* Register DVB adapters and devices for both channels */
2613 if (dvb_register_adapter(&dev->dvb_adapter, "nGene", THIS_MODULE,
2614 &dev->pci_dev->dev, adapter_nr) < 0)
2617 if (init_channels(dev) < 0)
2625 ngene_release_buffers(dev);
2626 pci_set_drvdata(pci_dev, 0);
2630 /****************************************************************************/
2631 /* Card configs *************************************************************/
2632 /****************************************************************************/
2634 static struct stv090x_config fe_mps2 = {
2636 .demod_mode = STV090x_DUAL,
2637 .clk_mode = STV090x_CLK_EXT,
2641 // .ref_clk = 27000000,
2643 .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
2644 .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
2646 .repeater_level = STV090x_RPTLEVEL_16,
2648 .diseqc_envelope_mode = true,
2651 .tuner_set_mode = NULL,
2652 .tuner_set_frequency = NULL,
2653 .tuner_get_frequency = NULL,
2654 .tuner_set_bandwidth = NULL,
2655 .tuner_get_bandwidth = NULL,
2656 .tuner_set_bbgain = NULL,
2657 .tuner_get_bbgain = NULL,
2658 .tuner_set_refclk = NULL,
2659 .tuner_get_status = NULL,
2662 static struct stv6110x_config tuner_mps2_0 = {
2667 static struct stv6110x_config tuner_mps2_1 = {
2672 static struct ngene_info ngene_info_mps2 = {
2673 .type = NGENE_SIDEWINDER,
2674 .name = "Media-Pointer MP-S2/CineS2 DVB-S2 Twin Tuner",
2675 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN},
2676 .demod_attach = {demod_attach_stv0900, demod_attach_stv0900},
2677 .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110},
2678 .fe_config = {&fe_mps2, &fe_mps2},
2679 .tuner_config = {&tuner_mps2_0, &tuner_mps2_1},
2680 .lnb = {0x0b, 0x08},
2685 /****************************************************************************/
2689 /****************************************************************************/
2690 /****************************************************************************/
2691 /****************************************************************************/
2693 #define NGENE_ID(_subvend, _subdev, _driverdata) { \
2694 .vendor = NGENE_VID, .device = NGENE_PID, \
2695 .subvendor = _subvend, .subdevice = _subdev, \
2696 .driver_data = (unsigned long) &_driverdata }
2698 /****************************************************************************/
2700 static const struct pci_device_id ngene_id_tbl[] __devinitdata = {
2701 NGENE_ID(0x18c3, 0xabc3, ngene_info_mps2),
2702 NGENE_ID(0x18c3, 0xabc4, ngene_info_mps2),
2703 NGENE_ID(0x18c3, 0xdb01, ngene_info_mps2),
2706 MODULE_DEVICE_TABLE(pci, ngene_id_tbl);
2708 /****************************************************************************/
2709 /* Init/Exit ****************************************************************/
2710 /****************************************************************************/
2712 static pci_ers_result_t ngene_error_detected(struct pci_dev *dev,
2713 enum pci_channel_state state)
2715 printk(KERN_ERR DEVICE_NAME ": PCI error\n");
2716 if (state == pci_channel_io_perm_failure)
2717 return PCI_ERS_RESULT_DISCONNECT;
2718 if (state == pci_channel_io_frozen)
2719 return PCI_ERS_RESULT_NEED_RESET;
2720 return PCI_ERS_RESULT_CAN_RECOVER;
2723 static pci_ers_result_t ngene_link_reset(struct pci_dev *dev)
2725 printk(KERN_INFO DEVICE_NAME ": link reset\n");
2729 static pci_ers_result_t ngene_slot_reset(struct pci_dev *dev)
2731 printk(KERN_INFO DEVICE_NAME ": slot reset\n");
2735 static void ngene_resume(struct pci_dev *dev)
2737 printk(KERN_INFO DEVICE_NAME ": resume\n");
2740 static struct pci_error_handlers ngene_errors = {
2741 .error_detected = ngene_error_detected,
2742 .link_reset = ngene_link_reset,
2743 .slot_reset = ngene_slot_reset,
2744 .resume = ngene_resume,
2747 static struct pci_driver ngene_pci_driver = {
2749 .id_table = ngene_id_tbl,
2750 .probe = ngene_probe,
2751 .remove = ngene_remove,
2752 .err_handler = &ngene_errors,
2755 static __init int module_init_ngene(void)
2758 "nGene PCIE bridge driver, Copyright (C) 2005-2007 Micronas\n");
2759 return pci_register_driver(&ngene_pci_driver);
2762 static __exit void module_exit_ngene(void)
2764 pci_unregister_driver(&ngene_pci_driver);
2767 module_init(module_init_ngene);
2768 module_exit(module_exit_ngene);
2770 MODULE_DESCRIPTION("nGene");
2771 MODULE_AUTHOR("Micronas, Ralph Metzler, Manfred Voelkel");
2772 MODULE_LICENSE("GPL");