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   1 /*
   2     tda18271-fe.c - driver for the Philips / NXP TDA18271 silicon tuner
   3
   4     Copyright (C) 2007 Michael Krufky (mkrufky@linuxtv.org)
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14     GNU General Public License for more details.
  15
  16     You should have received a copy of the GNU General Public License
  17     along with this program; if not, write to the Free Software
  18     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19 */
  20
  21 #include <linux/delay.h>
  22 #include <linux/videodev2.h>
  23 #include "tda18271-priv.h"
  24
  25 int tda18271_debug;
  26 module_param_named(debug, tda18271_debug, int, 0644);
  27 MODULE_PARM_DESC(debug, "set debug level (info=1, map=2, reg=4 (or-able))");
  28
  29 /*---------------------------------------------------------------------*/
  30
  31 static int tda18271_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
  32 {
  33         struct tda18271_priv *priv = fe->tuner_priv;
  34         enum tda18271_i2c_gate gate;
  35         int ret = 0;
  36
  37         switch (priv->gate) {
  38         case TDA18271_GATE_DIGITAL:
  39         case TDA18271_GATE_ANALOG:
  40                 gate = priv->gate;
  41                 break;
  42         case TDA18271_GATE_AUTO:
  43         default:
  44                 switch (priv->mode) {
  45                 case TDA18271_DIGITAL:
  46                         gate = TDA18271_GATE_DIGITAL;
  47                         break;
  48                 case TDA18271_ANALOG:
  49                 default:
  50                         gate = TDA18271_GATE_ANALOG;
  51                         break;
  52                 }
  53         }
  54
  55         switch (gate) {
  56         case TDA18271_GATE_ANALOG:
  57                 if (fe->ops.analog_ops.i2c_gate_ctrl)
  58                         ret = fe->ops.analog_ops.i2c_gate_ctrl(fe, enable);
  59                 break;
  60         case TDA18271_GATE_DIGITAL:
  61                 if (fe->ops.i2c_gate_ctrl)
  62                         ret = fe->ops.i2c_gate_ctrl(fe, enable);
  63                 break;
  64         default:
  65                 ret = -EINVAL;
  66                 break;
  67         }
  68
  69         return ret;
  70 };
  71
  72 /*---------------------------------------------------------------------*/
  73
  74 static void tda18271_dump_regs(struct dvb_frontend *fe)
  75 {
  76         struct tda18271_priv *priv = fe->tuner_priv;
  77         unsigned char *regs = priv->tda18271_regs;
  78
  79         tda_reg("=== TDA18271 REG DUMP ===\n");
  80         tda_reg("ID_BYTE            = 0x%02x\n", 0xff & regs[R_ID]);
  81         tda_reg("THERMO_BYTE        = 0x%02x\n", 0xff & regs[R_TM]);
  82         tda_reg("POWER_LEVEL_BYTE   = 0x%02x\n", 0xff & regs[R_PL]);
  83         tda_reg("EASY_PROG_BYTE_1   = 0x%02x\n", 0xff & regs[R_EP1]);
  84         tda_reg("EASY_PROG_BYTE_2   = 0x%02x\n", 0xff & regs[R_EP2]);
  85         tda_reg("EASY_PROG_BYTE_3   = 0x%02x\n", 0xff & regs[R_EP3]);
  86         tda_reg("EASY_PROG_BYTE_4   = 0x%02x\n", 0xff & regs[R_EP4]);
  87         tda_reg("EASY_PROG_BYTE_5   = 0x%02x\n", 0xff & regs[R_EP5]);
  88         tda_reg("CAL_POST_DIV_BYTE  = 0x%02x\n", 0xff & regs[R_CPD]);
  89         tda_reg("CAL_DIV_BYTE_1     = 0x%02x\n", 0xff & regs[R_CD1]);
  90         tda_reg("CAL_DIV_BYTE_2     = 0x%02x\n", 0xff & regs[R_CD2]);
  91         tda_reg("CAL_DIV_BYTE_3     = 0x%02x\n", 0xff & regs[R_CD3]);
  92         tda_reg("MAIN_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_MPD]);
  93         tda_reg("MAIN_DIV_BYTE_1    = 0x%02x\n", 0xff & regs[R_MD1]);
  94         tda_reg("MAIN_DIV_BYTE_2    = 0x%02x\n", 0xff & regs[R_MD2]);
  95         tda_reg("MAIN_DIV_BYTE_3    = 0x%02x\n", 0xff & regs[R_MD3]);
  96 }
  97
  98 static void tda18271_read_regs(struct dvb_frontend *fe)
  99 {
 100         struct tda18271_priv *priv = fe->tuner_priv;
 101         unsigned char *regs = priv->tda18271_regs;
 102         unsigned char buf = 0x00;
 103         int ret;
 104         struct i2c_msg msg[] = {
 105                 { .addr = priv->i2c_addr, .flags = 0,
 106                   .buf = &buf, .len = 1 },
 107                 { .addr = priv->i2c_addr, .flags = I2C_M_RD,
 108                   .buf = regs, .len = 16 }
 109         };
 110
 111         tda18271_i2c_gate_ctrl(fe, 1);
 112
 113         /* read all registers */
 114         ret = i2c_transfer(priv->i2c_adap, msg, 2);
 115
 116         tda18271_i2c_gate_ctrl(fe, 0);
 117
 118         if (ret != 2)
 119                 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
 120
 121         if (tda18271_debug & DBG_REG)
 122                 tda18271_dump_regs(fe);
 123 }
 124
 125 static void tda18271_write_regs(struct dvb_frontend *fe, int idx, int len)
 126 {
 127         struct tda18271_priv *priv = fe->tuner_priv;
 128         unsigned char *regs = priv->tda18271_regs;
 129         unsigned char buf[TDA18271_NUM_REGS+1];
 130         struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
 131                                .buf = buf, .len = len+1 };
 132         int i, ret;
 133
 134         BUG_ON((len == 0) || (idx+len > sizeof(buf)));
 135
 136         buf[0] = idx;
 137         for (i = 1; i <= len; i++) {
 138                 buf[i] = regs[idx-1+i];
 139         }
 140
 141         tda18271_i2c_gate_ctrl(fe, 1);
 142
 143         /* write registers */
 144         ret = i2c_transfer(priv->i2c_adap, &msg, 1);
 145
 146         tda18271_i2c_gate_ctrl(fe, 0);
 147
 148         if (ret != 1)
 149                 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
 150 }
 151
 152 /*---------------------------------------------------------------------*/
 153
 154 static int tda18271_init_regs(struct dvb_frontend *fe)
 155 {
 156         struct tda18271_priv *priv = fe->tuner_priv;
 157         unsigned char *regs = priv->tda18271_regs;
 158
 159         tda_dbg("initializing registers for device @ %d-%04x\n",
 160                 i2c_adapter_id(priv->i2c_adap), priv->i2c_addr);
 161
 162         /* initialize registers */
 163         regs[R_ID]   = 0x83;
 164         regs[R_TM]   = 0x08;
 165         regs[R_PL]   = 0x80;
 166         regs[R_EP1]  = 0xc6;
 167         regs[R_EP2]  = 0xdf;
 168         regs[R_EP3]  = 0x16;
 169         regs[R_EP4]  = 0x60;
 170         regs[R_EP5]  = 0x80;
 171         regs[R_CPD]  = 0x80;
 172         regs[R_CD1]  = 0x00;
 173         regs[R_CD2]  = 0x00;
 174         regs[R_CD3]  = 0x00;
 175         regs[R_MPD]  = 0x00;
 176         regs[R_MD1]  = 0x00;
 177         regs[R_MD2]  = 0x00;
 178         regs[R_MD3]  = 0x00;
 179         regs[R_EB1]  = 0xff;
 180         regs[R_EB2]  = 0x01;
 181         regs[R_EB3]  = 0x84;
 182         regs[R_EB4]  = 0x41;
 183         regs[R_EB5]  = 0x01;
 184         regs[R_EB6]  = 0x84;
 185         regs[R_EB7]  = 0x40;
 186         regs[R_EB8]  = 0x07;
 187         regs[R_EB9]  = 0x00;
 188         regs[R_EB10] = 0x00;
 189         regs[R_EB11] = 0x96;
 190         regs[R_EB12] = 0x0f;
 191         regs[R_EB13] = 0xc1;
 192         regs[R_EB14] = 0x00;
 193         regs[R_EB15] = 0x8f;
 194         regs[R_EB16] = 0x00;
 195         regs[R_EB17] = 0x00;
 196         regs[R_EB18] = 0x00;
 197         regs[R_EB19] = 0x00;
 198         regs[R_EB20] = 0x20;
 199         regs[R_EB21] = 0x33;
 200         regs[R_EB22] = 0x48;
 201         regs[R_EB23] = 0xb0;
 202
 203         tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS);
 204         /* setup AGC1 & AGC2 */
 205         regs[R_EB17] = 0x00;
 206         tda18271_write_regs(fe, R_EB17, 1);
 207         regs[R_EB17] = 0x03;
 208         tda18271_write_regs(fe, R_EB17, 1);
 209         regs[R_EB17] = 0x43;
 210         tda18271_write_regs(fe, R_EB17, 1);
 211         regs[R_EB17] = 0x4c;
 212         tda18271_write_regs(fe, R_EB17, 1);
 213
 214         regs[R_EB20] = 0xa0;
 215         tda18271_write_regs(fe, R_EB20, 1);
 216         regs[R_EB20] = 0xa7;
 217         tda18271_write_regs(fe, R_EB20, 1);
 218         regs[R_EB20] = 0xe7;
 219         tda18271_write_regs(fe, R_EB20, 1);
 220         regs[R_EB20] = 0xec;
 221         tda18271_write_regs(fe, R_EB20, 1);
 222
 223         /* image rejection calibration */
 224
 225         /* low-band */
 226         regs[R_EP3] = 0x1f;
 227         regs[R_EP4] = 0x66;
 228         regs[R_EP5] = 0x81;
 229         regs[R_CPD] = 0xcc;
 230         regs[R_CD1] = 0x6c;
 231         regs[R_CD2] = 0x00;
 232         regs[R_CD3] = 0x00;
 233         regs[R_MPD] = 0xcd;
 234         regs[R_MD1] = 0x77;
 235         regs[R_MD2] = 0x08;
 236         regs[R_MD3] = 0x00;
 237
 238         tda18271_write_regs(fe, R_EP3, 11);
 239         msleep(5); /* pll locking */
 240
 241         regs[R_EP1] = 0xc6;
 242         tda18271_write_regs(fe, R_EP1, 1);
 243         msleep(5); /* wanted low measurement */
 244
 245         regs[R_EP3] = 0x1f;
 246         regs[R_EP4] = 0x66;
 247         regs[R_EP5] = 0x85;
 248         regs[R_CPD] = 0xcb;
 249         regs[R_CD1] = 0x66;
 250         regs[R_CD2] = 0x70;
 251         regs[R_CD3] = 0x00;
 252
 253         tda18271_write_regs(fe, R_EP3, 7);
 254         msleep(5); /* pll locking */
 255
 256         regs[R_EP2] = 0xdf;
 257         tda18271_write_regs(fe, R_EP2, 1);
 258         msleep(30); /* image low optimization completion */
 259
 260         /* mid-band */
 261         regs[R_EP3] = 0x1f;
 262         regs[R_EP4] = 0x66;
 263         regs[R_EP5] = 0x82;
 264         regs[R_CPD] = 0xa8;
 265         regs[R_CD1] = 0x66;
 266         regs[R_CD2] = 0x00;
 267         regs[R_CD3] = 0x00;
 268         regs[R_MPD] = 0xa9;
 269         regs[R_MD1] = 0x73;
 270         regs[R_MD2] = 0x1a;
 271         regs[R_MD3] = 0x00;
 272
 273         tda18271_write_regs(fe, R_EP3, 11);
 274         msleep(5); /* pll locking */
 275
 276         regs[R_EP1] = 0xc6;
 277         tda18271_write_regs(fe, R_EP1, 1);
 278         msleep(5); /* wanted mid measurement */
 279
 280         regs[R_EP3] = 0x1f;
 281         regs[R_EP4] = 0x66;
 282         regs[R_EP5] = 0x86;
 283         regs[R_CPD] = 0xa8;
 284         regs[R_CD1] = 0x66;
 285         regs[R_CD2] = 0xa0;
 286         regs[R_CD3] = 0x00;
 287
 288         tda18271_write_regs(fe, R_EP3, 7);
 289         msleep(5); /* pll locking */
 290
 291         regs[R_EP2] = 0xdf;
 292         tda18271_write_regs(fe, R_EP2, 1);
 293         msleep(30); /* image mid optimization completion */
 294
 295         /* high-band */
 296         regs[R_EP3] = 0x1f;
 297         regs[R_EP4] = 0x66;
 298         regs[R_EP5] = 0x83;
 299         regs[R_CPD] = 0x98;
 300         regs[R_CD1] = 0x65;
 301         regs[R_CD2] = 0x00;
 302         regs[R_CD3] = 0x00;
 303         regs[R_MPD] = 0x99;
 304         regs[R_MD1] = 0x71;
 305         regs[R_MD2] = 0xcd;
 306         regs[R_MD3] = 0x00;
 307
 308         tda18271_write_regs(fe, R_EP3, 11);
 309         msleep(5); /* pll locking */
 310
 311         regs[R_EP1] = 0xc6;
 312         tda18271_write_regs(fe, R_EP1, 1);
 313         msleep(5); /* wanted high measurement */
 314
 315         regs[R_EP3] = 0x1f;
 316         regs[R_EP4] = 0x66;
 317         regs[R_EP5] = 0x87;
 318         regs[R_CPD] = 0x98;
 319         regs[R_CD1] = 0x65;
 320         regs[R_CD2] = 0x50;
 321         regs[R_CD3] = 0x00;
 322
 323         tda18271_write_regs(fe, R_EP3, 7);
 324         msleep(5); /* pll locking */
 325
 326         regs[R_EP2] = 0xdf;
 327
 328         tda18271_write_regs(fe, R_EP2, 1);
 329         msleep(30); /* image high optimization completion */
 330
 331         regs[R_EP4] = 0x64;
 332         tda18271_write_regs(fe, R_EP4, 1);
 333
 334         regs[R_EP1] = 0xc6;
 335         tda18271_write_regs(fe, R_EP1, 1);
 336
 337         return 0;
 338 }
 339
 340 static int tda18271_init(struct dvb_frontend *fe)
 341 {
 342         struct tda18271_priv *priv = fe->tuner_priv;
 343         unsigned char *regs = priv->tda18271_regs;
 344
 345         tda18271_read_regs(fe);
 346
 347         /* test IR_CAL_OK to see if we need init */
 348         if ((regs[R_EP1] & 0x08) == 0)
 349                 tda18271_init_regs(fe);
 350
 351         return 0;
 352 }
 353
 354 static int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq)
 355 {
 356         /* Sets Main Post-Divider & Divider bytes, but does not write them */
 357         struct tda18271_priv *priv = fe->tuner_priv;
 358         unsigned char *regs = priv->tda18271_regs;
 359         u8 d, pd;
 360         u32 div;
 361
 362         int ret = tda18271_lookup_pll_map(MAIN_PLL, &freq, &pd, &d);
 363         if (ret < 0)
 364                 goto fail;
 365
 366         regs[R_MPD]   = (0x77 & pd);
 367
 368         switch (priv->mode) {
 369         case TDA18271_ANALOG:
 370                 regs[R_MPD]  &= ~0x08;
 371                 break;
 372         case TDA18271_DIGITAL:
 373                 regs[R_MPD]  |=  0x08;
 374                 break;
 375         }
 376
 377         div =  ((d * (freq / 1000)) << 7) / 125;
 378
 379         regs[R_MD1]   = 0x7f & (div >> 16);
 380         regs[R_MD2]   = 0xff & (div >> 8);
 381         regs[R_MD3]   = 0xff & div;
 382 fail:
 383         return ret;
 384 }
 385
 386 static int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq)
 387 {
 388         /* Sets Cal Post-Divider & Divider bytes, but does not write them */
 389         struct tda18271_priv *priv = fe->tuner_priv;
 390         unsigned char *regs = priv->tda18271_regs;
 391         u8 d, pd;
 392         u32 div;
 393
 394         int ret = tda18271_lookup_pll_map(CAL_PLL, &freq, &pd, &d);
 395         if (ret < 0)
 396                 goto fail;
 397
 398         regs[R_CPD]   = pd;
 399
 400         div =  ((d * (freq / 1000)) << 7) / 125;
 401
 402         regs[R_CD1]   = 0x7f & (div >> 16);
 403         regs[R_CD2]   = 0xff & (div >> 8);
 404         regs[R_CD3]   = 0xff & div;
 405 fail:
 406         return ret;
 407 }
 408
 409 static int tda18271_calc_bp_filter(struct dvb_frontend *fe, u32 *freq)
 410 {
 411         /* Sets BP filter bits, but does not write them */
 412         struct tda18271_priv *priv = fe->tuner_priv;
 413         unsigned char *regs = priv->tda18271_regs;
 414         u8 val;
 415
 416         int ret = tda18271_lookup_map(BP_FILTER, freq, &val);
 417         if (ret < 0)
 418                 goto fail;
 419
 420         regs[R_EP1]  &= ~0x07; /* clear bp filter bits */
 421         regs[R_EP1]  |= (0x07 & val);
 422 fail:
 423         return ret;
 424 }
 425
 426 static int tda18271_calc_km(struct dvb_frontend *fe, u32 *freq)
 427 {
 428         /* Sets K & M bits, but does not write them */
 429         struct tda18271_priv *priv = fe->tuner_priv;
 430         unsigned char *regs = priv->tda18271_regs;
 431         u8 val;
 432
 433         int ret = tda18271_lookup_map(RF_CAL_KMCO, freq, &val);
 434         if (ret < 0)
 435                 goto fail;
 436
 437         regs[R_EB13] &= ~0x7c; /* clear k & m bits */
 438         regs[R_EB13] |= (0x7c & val);
 439 fail:
 440         return ret;
 441 }
 442
 443 static int tda18271_calc_rf_band(struct dvb_frontend *fe, u32 *freq)
 444 {
 445         /* Sets RF Band bits, but does not write them */
 446         struct tda18271_priv *priv = fe->tuner_priv;
 447         unsigned char *regs = priv->tda18271_regs;
 448         u8 val;
 449
 450         int ret = tda18271_lookup_map(RF_BAND, freq, &val);
 451         if (ret < 0)
 452                 goto fail;
 453
 454         regs[R_EP2]  &= ~0xe0; /* clear rf band bits */
 455         regs[R_EP2]  |= (0xe0 & (val << 5));
 456 fail:
 457         return ret;
 458 }
 459
 460 static int tda18271_calc_gain_taper(struct dvb_frontend *fe, u32 *freq)
 461 {
 462         /* Sets Gain Taper bits, but does not write them */
 463         struct tda18271_priv *priv = fe->tuner_priv;
 464         unsigned char *regs = priv->tda18271_regs;
 465         u8 val;
 466
 467         int ret = tda18271_lookup_map(GAIN_TAPER, freq, &val);
 468         if (ret < 0)
 469                 goto fail;
 470
 471         regs[R_EP2]  &= ~0x1f; /* clear gain taper bits */
 472         regs[R_EP2]  |= (0x1f & val);
 473 fail:
 474         return ret;
 475 }
 476
 477 static int tda18271_calc_ir_measure(struct dvb_frontend *fe, u32 *freq)
 478 {
 479         /* Sets IR Meas bits, but does not write them */
 480         struct tda18271_priv *priv = fe->tuner_priv;
 481         unsigned char *regs = priv->tda18271_regs;
 482         u8 val;
 483
 484         int ret = tda18271_lookup_map(IR_MEASURE, freq, &val);
 485         if (ret < 0)
 486                 goto fail;
 487
 488         regs[R_EP5] &= ~0x07;
 489         regs[R_EP5] |= (0x07 & val);
 490 fail:
 491         return ret;
 492 }
 493
 494 static int tda18271_calc_rf_cal(struct dvb_frontend *fe, u32 *freq)
 495 {
 496         /* Sets RF Cal bits, but does not write them */
 497         struct tda18271_priv *priv = fe->tuner_priv;
 498         unsigned char *regs = priv->tda18271_regs;
 499         u8 val;
 500
 501         int ret = tda18271_lookup_map(RF_CAL, freq, &val);
 502         if (ret < 0)
 503                 goto fail;
 504
 505         /* VHF_Low band only */
 506         if (0 == val) {
 507                 ret = -ERANGE;
 508                 goto fail;
 509         }
 510         regs[R_EB14] = val;
 511 fail:
 512         return ret;
 513 }
 514
 515 static int tda18271_tune(struct dvb_frontend *fe,
 516                          u32 ifc, u32 freq, u32 bw, u8 std)
 517 {
 518         struct tda18271_priv *priv = fe->tuner_priv;
 519         unsigned char *regs = priv->tda18271_regs;
 520         u32 N = 0;
 521
 522         tda18271_init(fe);
 523
 524         tda_dbg("freq = %d, ifc = %d\n", freq, ifc);
 525
 526         /* RF tracking filter calibration */
 527
 528         /* calculate BP_Filter */
 529         tda18271_calc_bp_filter(fe, &freq);
 530         tda18271_write_regs(fe, R_EP1, 1);
 531
 532         regs[R_EB4]  &= 0x07;
 533         regs[R_EB4]  |= 0x60;
 534         tda18271_write_regs(fe, R_EB4, 1);
 535
 536         regs[R_EB7]   = 0x60;
 537         tda18271_write_regs(fe, R_EB7, 1);
 538
 539         regs[R_EB14]  = 0x00;
 540         tda18271_write_regs(fe, R_EB14, 1);
 541
 542         regs[R_EB20]  = 0xcc;
 543         tda18271_write_regs(fe, R_EB20, 1);
 544
 545         /* set CAL mode to RF tracking filter calibration */
 546         regs[R_EP4]  |= 0x03;
 547
 548         /* calculate CAL PLL */
 549
 550         switch (priv->mode) {
 551         case TDA18271_ANALOG:
 552                 N = freq - 1250000;
 553                 break;
 554         case TDA18271_DIGITAL:
 555                 N = freq + bw / 2;
 556                 break;
 557         }
 558
 559         tda18271_calc_cal_pll(fe, N);
 560
 561         /* calculate MAIN PLL */
 562
 563         switch (priv->mode) {
 564         case TDA18271_ANALOG:
 565                 N = freq - 250000;
 566                 break;
 567         case TDA18271_DIGITAL:
 568                 N = freq + bw / 2 + 1000000;
 569                 break;
 570         }
 571
 572         tda18271_calc_main_pll(fe, N);
 573
 574         tda18271_write_regs(fe, R_EP3, 11);
 575         msleep(5); /* RF tracking filter calibration initialization */
 576
 577         /* search for K,M,CO for RF Calibration */
 578         tda18271_calc_km(fe, &freq);
 579         tda18271_write_regs(fe, R_EB13, 1);
 580
 581         /* search for RF_BAND */
 582         tda18271_calc_rf_band(fe, &freq);
 583
 584         /* search for Gain_Taper */
 585         tda18271_calc_gain_taper(fe, &freq);
 586
 587         tda18271_write_regs(fe, R_EP2, 1);
 588         tda18271_write_regs(fe, R_EP1, 1);
 589         tda18271_write_regs(fe, R_EP2, 1);
 590         tda18271_write_regs(fe, R_EP1, 1);
 591
 592         regs[R_EB4]  &= 0x07;
 593         regs[R_EB4]  |= 0x40;
 594         tda18271_write_regs(fe, R_EB4, 1);
 595
 596         regs[R_EB7]   = 0x40;
 597         tda18271_write_regs(fe, R_EB7, 1);
 598         msleep(10);
 599
 600         regs[R_EB20]  = 0xec;
 601         tda18271_write_regs(fe, R_EB20, 1);
 602         msleep(60); /* RF tracking filter calibration completion */
 603
 604         regs[R_EP4]  &= ~0x03; /* set cal mode to normal */
 605         tda18271_write_regs(fe, R_EP4, 1);
 606
 607         tda18271_write_regs(fe, R_EP1, 1);
 608
 609         /* RF tracking filter correction for VHF_Low band */
 610         if (0 == tda18271_calc_rf_cal(fe, &freq))
 611                 tda18271_write_regs(fe, R_EB14, 1);
 612
 613         /* Channel Configuration */
 614
 615         switch (priv->mode) {
 616         case TDA18271_ANALOG:
 617                 regs[R_EB22]  = 0x2c;
 618                 break;
 619         case TDA18271_DIGITAL:
 620                 regs[R_EB22]  = 0x37;
 621                 break;
 622         }
 623         tda18271_write_regs(fe, R_EB22, 1);
 624
 625         regs[R_EP1]  |= 0x40; /* set dis power level on */
 626
 627         /* set standard */
 628         regs[R_EP3]  &= ~0x1f; /* clear std bits */
 629
 630         /* see table 22 */
 631         regs[R_EP3]  |= std;
 632
 633         regs[R_EP4]  &= ~0x03; /* set cal mode to normal */
 634
 635         regs[R_EP4]  &= ~0x1c; /* clear if level bits */
 636         switch (priv->mode) {
 637         case TDA18271_ANALOG:
 638                 regs[R_MPD]  &= ~0x80; /* IF notch = 0 */
 639                 break;
 640         case TDA18271_DIGITAL:
 641                 regs[R_EP4]  |= 0x04;
 642                 regs[R_MPD]  |= 0x80;
 643                 break;
 644         }
 645
 646         regs[R_EP4]  &= ~0x80; /* turn this bit on only for fm */
 647
 648         /* image rejection validity */
 649         tda18271_calc_ir_measure(fe, &freq);
 650
 651         /* calculate MAIN PLL */
 652         N = freq + ifc;
 653
 654         tda18271_calc_main_pll(fe, N);
 655
 656         tda18271_write_regs(fe, R_TM, 15);
 657         msleep(5);
 658
 659         return 0;
 660 }
 661
 662 /* ------------------------------------------------------------------ */
 663
 664 static int tda18271_set_params(struct dvb_frontend *fe,
 665                                struct dvb_frontend_parameters *params)
 666 {
 667         struct tda18271_priv *priv = fe->tuner_priv;
 668         u8 std;
 669         u32 bw, sgIF = 0;
 670
 671         u32 freq = params->frequency;
 672
 673         priv->mode = TDA18271_DIGITAL;
 674
 675         /* see table 22 */
 676         if (fe->ops.info.type == FE_ATSC) {
 677                 switch (params->u.vsb.modulation) {
 678                 case VSB_8:
 679                 case VSB_16:
 680                         std = 0x1b; /* device-specific (spec says 0x1c) */
 681                         sgIF = 5380000;
 682                         break;
 683                 case QAM_64:
 684                 case QAM_256:
 685                         std = 0x18; /* device-specific (spec says 0x1d) */
 686                         sgIF = 4000000;
 687                         break;
 688                 default:
 689                         tda_warn("modulation not set!\n");
 690                         return -EINVAL;
 691                 }
 692 #if 0
 693                 /* userspace request is already center adjusted */
 694                 freq += 1750000; /* Adjust to center (+1.75MHZ) */
 695 #endif
 696                 bw = 6000000;
 697         } else if (fe->ops.info.type == FE_OFDM) {
 698                 switch (params->u.ofdm.bandwidth) {
 699                 case BANDWIDTH_6_MHZ:
 700                         std = 0x1b; /* device-specific (spec says 0x1c) */
 701                         bw = 6000000;
 702                         sgIF = 3300000;
 703                         break;
 704                 case BANDWIDTH_7_MHZ:
 705                         std = 0x19; /* device-specific (spec says 0x1d) */
 706                         bw = 7000000;
 707                         sgIF = 3800000;
 708                         break;
 709                 case BANDWIDTH_8_MHZ:
 710                         std = 0x1a; /* device-specific (spec says 0x1e) */
 711                         bw = 8000000;
 712                         sgIF = 4300000;
 713                         break;
 714                 default:
 715                         tda_warn("bandwidth not set!\n");
 716                         return -EINVAL;
 717                 }
 718         } else {
 719                 tda_warn("modulation type not supported!\n");
 720                 return -EINVAL;
 721         }
 722
 723         return tda18271_tune(fe, sgIF, freq, bw, std);
 724 }
 725
 726 static int tda18271_set_analog_params(struct dvb_frontend *fe,
 727                                       struct analog_parameters *params)
 728 {
 729         struct tda18271_priv *priv = fe->tuner_priv;
 730         u8 std;
 731         unsigned int sgIF;
 732         char *mode;
 733
 734         priv->mode = TDA18271_ANALOG;
 735
 736         /* see table 22 */
 737         if (params->std & V4L2_STD_MN) {
 738                 std = 0x0d;
 739                 sgIF =  92;
 740                 mode = "MN";
 741         } else if (params->std & V4L2_STD_B) {
 742                 std = 0x0e;
 743                 sgIF =  108;
 744                 mode = "B";
 745         } else if (params->std & V4L2_STD_GH) {
 746                 std = 0x0f;
 747                 sgIF =  124;
 748                 mode = "GH";
 749         } else if (params->std & V4L2_STD_PAL_I) {
 750                 std = 0x0f;
 751                 sgIF =  124;
 752                 mode = "I";
 753         } else if (params->std & V4L2_STD_DK) {
 754                 std = 0x0f;
 755                 sgIF =  124;
 756                 mode = "DK";
 757         } else if (params->std & V4L2_STD_SECAM_L) {
 758                 std = 0x0f;
 759                 sgIF =  124;
 760                 mode = "L";
 761         } else if (params->std & V4L2_STD_SECAM_LC) {
 762                 std = 0x0f;
 763                 sgIF =  20;
 764                 mode = "LC";
 765         } else {
 766                 std = 0x0f;
 767                 sgIF =  124;
 768                 mode = "xx";
 769         }
 770
 771         if (params->mode == V4L2_TUNER_RADIO)
 772                 sgIF =  88; /* if frequency is 5.5 MHz */
 773
 774         tda_dbg("setting tda18271 to system %s\n", mode);
 775
 776         return tda18271_tune(fe, sgIF * 62500, params->frequency * 62500,
 777                              0, std);
 778 }
 779
 780 static int tda18271_release(struct dvb_frontend *fe)
 781 {
 782         kfree(fe->tuner_priv);
 783         fe->tuner_priv = NULL;
 784         return 0;
 785 }
 786
 787 static int tda18271_get_frequency(struct dvb_frontend *fe, u32 *frequency)
 788 {
 789         struct tda18271_priv *priv = fe->tuner_priv;
 790         *frequency = priv->frequency;
 791         return 0;
 792 }
 793
 794 static int tda18271_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
 795 {
 796         struct tda18271_priv *priv = fe->tuner_priv;
 797         *bandwidth = priv->bandwidth;
 798         return 0;
 799 }
 800
 801 static int tda18271_get_id(struct dvb_frontend *fe)
 802 {
 803         struct tda18271_priv *priv = fe->tuner_priv;
 804         unsigned char *regs = priv->tda18271_regs;
 805         char *name;
 806         int ret = 0;
 807
 808         tda18271_read_regs(fe);
 809
 810         switch (regs[R_ID] & 0x7f) {
 811         case 3:
 812                 name = "TDA18271HD/C1";
 813                 break;
 814         case 4:
 815                 name = "TDA18271HD/C2";
 816                 ret = -EPROTONOSUPPORT;
 817                 break;
 818         default:
 819                 name = "Unknown device";
 820                 ret = -EINVAL;
 821                 break;
 822         }
 823
 824         tda_info("%s detected @ %d-%04x%s\n", name,
 825                  i2c_adapter_id(priv->i2c_adap), priv->i2c_addr,
 826                  (0 == ret) ? "" : ", device not supported.");
 827
 828         return ret;
 829 }
 830
 831 static struct dvb_tuner_ops tda18271_tuner_ops = {
 832         .info = {
 833                 .name = "NXP TDA18271HD",
 834                 .frequency_min  =  45000000,
 835                 .frequency_max  = 864000000,
 836                 .frequency_step =     62500
 837         },
 838         .init              = tda18271_init,
 839         .set_params        = tda18271_set_params,
 840         .set_analog_params = tda18271_set_analog_params,
 841         .release           = tda18271_release,
 842         .get_frequency     = tda18271_get_frequency,
 843         .get_bandwidth     = tda18271_get_bandwidth,
 844 };
 845
 846 struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr,
 847                                      struct i2c_adapter *i2c,
 848                                      enum tda18271_i2c_gate gate)
 849 {
 850         struct tda18271_priv *priv = NULL;
 851
 852         priv = kzalloc(sizeof(struct tda18271_priv), GFP_KERNEL);
 853         if (priv == NULL)
 854                 return NULL;
 855
 856         priv->i2c_addr = addr;
 857         priv->i2c_adap = i2c;
 858         priv->gate = gate;
 859
 860         fe->tuner_priv = priv;
 861
 862         if (tda18271_get_id(fe) < 0)
 863                 goto fail;
 864
 865         memcpy(&fe->ops.tuner_ops, &tda18271_tuner_ops,
 866                sizeof(struct dvb_tuner_ops));
 867
 868         tda18271_init_regs(fe);
 869
 870         return fe;
 871 fail:
 872         tda18271_release(fe);
 873         return NULL;
 874 }
 875 EXPORT_SYMBOL_GPL(tda18271_attach);
 876 MODULE_DESCRIPTION("NXP TDA18271HD analog / digital tuner driver");
 877 MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
 878 MODULE_LICENSE("GPL");
 879
 880 /*
 881  * Overrides for Emacs so that we follow Linus's tabbing style.
 882  * ---------------------------------------------------------------------------
 883  * Local variables:
 884  * c-basic-offset: 8
 885  * End:
 886  */