2 STV0900/0903 Multistandard Broadcast Frontend driver
3 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
5 Copyright (C) ST Microelectronics
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/init.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/mutex.h>
28 #include <linux/dvb/frontend.h>
29 #include "dvb_frontend.h"
31 #include "stv6110x.h" /* for demodulator internal modes */
33 #include "stv090x_reg.h"
35 #include "stv090x_priv.h"
37 static unsigned int verbose;
38 module_param(verbose, int, 0644);
40 struct mutex demod_lock;
42 /* DVBS1 and DSS C/N Lookup table */
43 static const struct stv090x_tab stv090x_s1cn_tab[] = {
44 { 0, 8917 }, /* 0.0dB */
45 { 5, 8801 }, /* 0.5dB */
46 { 10, 8667 }, /* 1.0dB */
47 { 15, 8522 }, /* 1.5dB */
48 { 20, 8355 }, /* 2.0dB */
49 { 25, 8175 }, /* 2.5dB */
50 { 30, 7979 }, /* 3.0dB */
51 { 35, 7763 }, /* 3.5dB */
52 { 40, 7530 }, /* 4.0dB */
53 { 45, 7282 }, /* 4.5dB */
54 { 50, 7026 }, /* 5.0dB */
55 { 55, 6781 }, /* 5.5dB */
56 { 60, 6514 }, /* 6.0dB */
57 { 65, 6241 }, /* 6.5dB */
58 { 70, 5965 }, /* 7.0dB */
59 { 75, 5690 }, /* 7.5dB */
60 { 80, 5424 }, /* 8.0dB */
61 { 85, 5161 }, /* 8.5dB */
62 { 90, 4902 }, /* 9.0dB */
63 { 95, 4654 }, /* 9.5dB */
64 { 100, 4417 }, /* 10.0dB */
65 { 105, 4186 }, /* 10.5dB */
66 { 110, 3968 }, /* 11.0dB */
67 { 115, 3757 }, /* 11.5dB */
68 { 120, 3558 }, /* 12.0dB */
69 { 125, 3366 }, /* 12.5dB */
70 { 130, 3185 }, /* 13.0dB */
71 { 135, 3012 }, /* 13.5dB */
72 { 140, 2850 }, /* 14.0dB */
73 { 145, 2698 }, /* 14.5dB */
74 { 150, 2550 }, /* 15.0dB */
75 { 160, 2283 }, /* 16.0dB */
76 { 170, 2042 }, /* 17.0dB */
77 { 180, 1827 }, /* 18.0dB */
78 { 190, 1636 }, /* 19.0dB */
79 { 200, 1466 }, /* 20.0dB */
80 { 210, 1315 }, /* 21.0dB */
81 { 220, 1181 }, /* 22.0dB */
82 { 230, 1064 }, /* 23.0dB */
83 { 240, 960 }, /* 24.0dB */
84 { 250, 869 }, /* 25.0dB */
85 { 260, 792 }, /* 26.0dB */
86 { 270, 724 }, /* 27.0dB */
87 { 280, 665 }, /* 28.0dB */
88 { 290, 616 }, /* 29.0dB */
89 { 300, 573 }, /* 30.0dB */
90 { 310, 537 }, /* 31.0dB */
91 { 320, 507 }, /* 32.0dB */
92 { 330, 483 }, /* 33.0dB */
93 { 400, 398 }, /* 40.0dB */
94 { 450, 381 }, /* 45.0dB */
95 { 500, 377 } /* 50.0dB */
98 /* DVBS2 C/N Lookup table */
99 static const struct stv090x_tab stv090x_s2cn_tab[] = {
100 { -30, 13348 }, /* -3.0dB */
101 { -20, 12640 }, /* -2d.0B */
102 { -10, 11883 }, /* -1.0dB */
103 { 0, 11101 }, /* -0.0dB */
104 { 5, 10718 }, /* 0.5dB */
105 { 10, 10339 }, /* 1.0dB */
106 { 15, 9947 }, /* 1.5dB */
107 { 20, 9552 }, /* 2.0dB */
108 { 25, 9183 }, /* 2.5dB */
109 { 30, 8799 }, /* 3.0dB */
110 { 35, 8422 }, /* 3.5dB */
111 { 40, 8062 }, /* 4.0dB */
112 { 45, 7707 }, /* 4.5dB */
113 { 50, 7353 }, /* 5.0dB */
114 { 55, 7025 }, /* 5.5dB */
115 { 60, 6684 }, /* 6.0dB */
116 { 65, 6331 }, /* 6.5dB */
117 { 70, 6036 }, /* 7.0dB */
118 { 75, 5727 }, /* 7.5dB */
119 { 80, 5437 }, /* 8.0dB */
120 { 85, 5164 }, /* 8.5dB */
121 { 90, 4902 }, /* 9.0dB */
122 { 95, 4653 }, /* 9.5dB */
123 { 100, 4408 }, /* 10.0dB */
124 { 105, 4187 }, /* 10.5dB */
125 { 110, 3961 }, /* 11.0dB */
126 { 115, 3751 }, /* 11.5dB */
127 { 120, 3558 }, /* 12.0dB */
128 { 125, 3368 }, /* 12.5dB */
129 { 130, 3191 }, /* 13.0dB */
130 { 135, 3017 }, /* 13.5dB */
131 { 140, 2862 }, /* 14.0dB */
132 { 145, 2710 }, /* 14.5dB */
133 { 150, 2565 }, /* 15.0dB */
134 { 160, 2300 }, /* 16.0dB */
135 { 170, 2058 }, /* 17.0dB */
136 { 180, 1849 }, /* 18.0dB */
137 { 190, 1663 }, /* 19.0dB */
138 { 200, 1495 }, /* 20.0dB */
139 { 210, 1349 }, /* 21.0dB */
140 { 220, 1222 }, /* 22.0dB */
141 { 230, 1110 }, /* 23.0dB */
142 { 240, 1011 }, /* 24.0dB */
143 { 250, 925 }, /* 25.0dB */
144 { 260, 853 }, /* 26.0dB */
145 { 270, 789 }, /* 27.0dB */
146 { 280, 734 }, /* 28.0dB */
147 { 290, 690 }, /* 29.0dB */
148 { 300, 650 }, /* 30.0dB */
149 { 310, 619 }, /* 31.0dB */
150 { 320, 593 }, /* 32.0dB */
151 { 330, 571 }, /* 33.0dB */
152 { 400, 498 }, /* 40.0dB */
153 { 450, 484 }, /* 45.0dB */
154 { 500, 481 } /* 50.0dB */
157 /* RF level C/N lookup table */
158 static const struct stv090x_tab stv090x_rf_tab[] = {
159 { -5, 0xcaa1 }, /* -5dBm */
160 { -10, 0xc229 }, /* -10dBm */
161 { -15, 0xbb08 }, /* -15dBm */
162 { -20, 0xb4bc }, /* -20dBm */
163 { -25, 0xad5a }, /* -25dBm */
164 { -30, 0xa298 }, /* -30dBm */
165 { -35, 0x98a8 }, /* -35dBm */
166 { -40, 0x8389 }, /* -40dBm */
167 { -45, 0x59be }, /* -45dBm */
168 { -50, 0x3a14 }, /* -50dBm */
169 { -55, 0x2d11 }, /* -55dBm */
170 { -60, 0x210d }, /* -60dBm */
171 { -65, 0xa14f }, /* -65dBm */
172 { -70, 0x07aa } /* -70dBm */
176 static struct stv090x_reg stv0900_initval[] = {
178 { STV090x_OUTCFG, 0x00 },
179 { STV090x_MODECFG, 0xff },
180 { STV090x_AGCRF1CFG, 0x11 },
181 { STV090x_AGCRF2CFG, 0x13 },
182 { STV090x_TSGENERAL1X, 0x14 },
183 { STV090x_TSTTNR2, 0x21 },
184 { STV090x_TSTTNR4, 0x21 },
185 { STV090x_P2_DISTXCTL, 0x22 },
186 { STV090x_P2_F22TX, 0xc0 },
187 { STV090x_P2_F22RX, 0xc0 },
188 { STV090x_P2_DISRXCTL, 0x00 },
189 { STV090x_P2_DMDCFGMD, 0xF9 },
190 { STV090x_P2_DEMOD, 0x08 },
191 { STV090x_P2_DMDCFG3, 0xc4 },
192 { STV090x_P2_CARFREQ, 0xed },
193 { STV090x_P2_LDT, 0xd0 },
194 { STV090x_P2_LDT2, 0xb8 },
195 { STV090x_P2_TMGCFG, 0xd2 },
196 { STV090x_P2_TMGTHRISE, 0x20 },
197 { STV090x_P1_TMGCFG, 0xd2 },
199 { STV090x_P2_TMGTHFALL, 0x00 },
200 { STV090x_P2_FECSPY, 0x88 },
201 { STV090x_P2_FSPYDATA, 0x3a },
202 { STV090x_P2_FBERCPT4, 0x00 },
203 { STV090x_P2_FSPYBER, 0x10 },
204 { STV090x_P2_ERRCTRL1, 0x35 },
205 { STV090x_P2_ERRCTRL2, 0xc1 },
206 { STV090x_P2_CFRICFG, 0xf8 },
207 { STV090x_P2_NOSCFG, 0x1c },
208 { STV090x_P2_DMDTOM, 0x20 },
209 { STV090x_P2_CORRELMANT, 0x70 },
210 { STV090x_P2_CORRELABS, 0x88 },
211 { STV090x_P2_AGC2O, 0x5b },
212 { STV090x_P2_AGC2REF, 0x38 },
213 { STV090x_P2_CARCFG, 0xe4 },
214 { STV090x_P2_ACLC, 0x1A },
215 { STV090x_P2_BCLC, 0x09 },
216 { STV090x_P2_CARHDR, 0x08 },
217 { STV090x_P2_KREFTMG, 0xc1 },
218 { STV090x_P2_SFRUPRATIO, 0xf0 },
219 { STV090x_P2_SFRLOWRATIO, 0x70 },
220 { STV090x_P2_SFRSTEP, 0x58 },
221 { STV090x_P2_TMGCFG2, 0x01 },
222 { STV090x_P2_CAR2CFG, 0x26 },
223 { STV090x_P2_BCLC2S2Q, 0x86 },
224 { STV090x_P2_BCLC2S28, 0x86 },
225 { STV090x_P2_SMAPCOEF7, 0x77 },
226 { STV090x_P2_SMAPCOEF6, 0x85 },
227 { STV090x_P2_SMAPCOEF5, 0x77 },
228 { STV090x_P2_TSCFGL, 0x20 },
229 { STV090x_P2_DMDCFG2, 0x3b },
230 { STV090x_P2_MODCODLST0, 0xff },
231 { STV090x_P2_MODCODLST1, 0xff },
232 { STV090x_P2_MODCODLST2, 0xff },
233 { STV090x_P2_MODCODLST3, 0xff },
234 { STV090x_P2_MODCODLST4, 0xff },
235 { STV090x_P2_MODCODLST5, 0xff },
236 { STV090x_P2_MODCODLST6, 0xff },
237 { STV090x_P2_MODCODLST7, 0xcc },
238 { STV090x_P2_MODCODLST8, 0xcc },
239 { STV090x_P2_MODCODLST9, 0xcc },
240 { STV090x_P2_MODCODLSTA, 0xcc },
241 { STV090x_P2_MODCODLSTB, 0xcc },
242 { STV090x_P2_MODCODLSTC, 0xcc },
243 { STV090x_P2_MODCODLSTD, 0xcc },
244 { STV090x_P2_MODCODLSTE, 0xcc },
245 { STV090x_P2_MODCODLSTF, 0xcf },
246 { STV090x_P1_DISTXCTL, 0x22 },
247 { STV090x_P1_F22TX, 0xc0 },
248 { STV090x_P1_F22RX, 0xc0 },
249 { STV090x_P1_DISRXCTL, 0x00 },
250 { STV090x_P1_DMDCFGMD, 0xf9 },
251 { STV090x_P1_DEMOD, 0x08 },
252 { STV090x_P1_DMDCFG3, 0xc4 },
253 { STV090x_P1_DMDTOM, 0x20 },
254 { STV090x_P1_CARFREQ, 0xed },
255 { STV090x_P1_LDT, 0xd0 },
256 { STV090x_P1_LDT2, 0xb8 },
257 { STV090x_P1_TMGCFG, 0xd2 },
258 { STV090x_P1_TMGTHRISE, 0x20 },
259 { STV090x_P1_TMGTHFALL, 0x00 },
260 { STV090x_P1_SFRUPRATIO, 0xf0 },
261 { STV090x_P1_SFRLOWRATIO, 0x70 },
262 { STV090x_P1_TSCFGL, 0x20 },
263 { STV090x_P1_FECSPY, 0x88 },
264 { STV090x_P1_FSPYDATA, 0x3a },
265 { STV090x_P1_FBERCPT4, 0x00 },
266 { STV090x_P1_FSPYBER, 0x10 },
267 { STV090x_P1_ERRCTRL1, 0x35 },
268 { STV090x_P1_ERRCTRL2, 0xc1 },
269 { STV090x_P1_CFRICFG, 0xf8 },
270 { STV090x_P1_NOSCFG, 0x1c },
271 { STV090x_P1_CORRELMANT, 0x70 },
272 { STV090x_P1_CORRELABS, 0x88 },
273 { STV090x_P1_AGC2O, 0x5b },
274 { STV090x_P1_AGC2REF, 0x38 },
275 { STV090x_P1_CARCFG, 0xe4 },
276 { STV090x_P1_ACLC, 0x1A },
277 { STV090x_P1_BCLC, 0x09 },
278 { STV090x_P1_CARHDR, 0x08 },
279 { STV090x_P1_KREFTMG, 0xc1 },
280 { STV090x_P1_SFRSTEP, 0x58 },
281 { STV090x_P1_TMGCFG2, 0x01 },
282 { STV090x_P1_CAR2CFG, 0x26 },
283 { STV090x_P1_BCLC2S2Q, 0x86 },
284 { STV090x_P1_BCLC2S28, 0x86 },
285 { STV090x_P1_SMAPCOEF7, 0x77 },
286 { STV090x_P1_SMAPCOEF6, 0x85 },
287 { STV090x_P1_SMAPCOEF5, 0x77 },
288 { STV090x_P1_DMDCFG2, 0x3b },
289 { STV090x_P1_MODCODLST0, 0xff },
290 { STV090x_P1_MODCODLST1, 0xff },
291 { STV090x_P1_MODCODLST2, 0xff },
292 { STV090x_P1_MODCODLST3, 0xff },
293 { STV090x_P1_MODCODLST4, 0xff },
294 { STV090x_P1_MODCODLST5, 0xff },
295 { STV090x_P1_MODCODLST6, 0xff },
296 { STV090x_P1_MODCODLST7, 0xcc },
297 { STV090x_P1_MODCODLST8, 0xcc },
298 { STV090x_P1_MODCODLST9, 0xcc },
299 { STV090x_P1_MODCODLSTA, 0xcc },
300 { STV090x_P1_MODCODLSTB, 0xcc },
301 { STV090x_P1_MODCODLSTC, 0xcc },
302 { STV090x_P1_MODCODLSTD, 0xcc },
303 { STV090x_P1_MODCODLSTE, 0xcc },
304 { STV090x_P1_MODCODLSTF, 0xcf },
305 { STV090x_GENCFG, 0x1d },
306 { STV090x_NBITER_NF4, 0x37 },
307 { STV090x_NBITER_NF5, 0x29 },
308 { STV090x_NBITER_NF6, 0x37 },
309 { STV090x_NBITER_NF7, 0x33 },
310 { STV090x_NBITER_NF8, 0x31 },
311 { STV090x_NBITER_NF9, 0x2f },
312 { STV090x_NBITER_NF10, 0x39 },
313 { STV090x_NBITER_NF11, 0x3a },
314 { STV090x_NBITER_NF12, 0x29 },
315 { STV090x_NBITER_NF13, 0x37 },
316 { STV090x_NBITER_NF14, 0x33 },
317 { STV090x_NBITER_NF15, 0x2f },
318 { STV090x_NBITER_NF16, 0x39 },
319 { STV090x_NBITER_NF17, 0x3a },
320 { STV090x_NBITERNOERR, 0x04 },
321 { STV090x_GAINLLR_NF4, 0x0C },
322 { STV090x_GAINLLR_NF5, 0x0F },
323 { STV090x_GAINLLR_NF6, 0x11 },
324 { STV090x_GAINLLR_NF7, 0x14 },
325 { STV090x_GAINLLR_NF8, 0x17 },
326 { STV090x_GAINLLR_NF9, 0x19 },
327 { STV090x_GAINLLR_NF10, 0x20 },
328 { STV090x_GAINLLR_NF11, 0x21 },
329 { STV090x_GAINLLR_NF12, 0x0D },
330 { STV090x_GAINLLR_NF13, 0x0F },
331 { STV090x_GAINLLR_NF14, 0x13 },
332 { STV090x_GAINLLR_NF15, 0x1A },
333 { STV090x_GAINLLR_NF16, 0x1F },
334 { STV090x_GAINLLR_NF17, 0x21 },
335 { STV090x_RCCFGH, 0x20 },
336 { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
337 { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
338 { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
339 { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
342 static struct stv090x_reg stv0903_initval[] = {
343 { STV090x_OUTCFG, 0x00 },
344 { STV090x_AGCRF1CFG, 0x11 },
345 { STV090x_STOPCLK1, 0x48 },
346 { STV090x_STOPCLK2, 0x14 },
347 { STV090x_TSTTNR1, 0x27 },
348 { STV090x_TSTTNR2, 0x21 },
349 { STV090x_P1_DISTXCTL, 0x22 },
350 { STV090x_P1_F22TX, 0xc0 },
351 { STV090x_P1_F22RX, 0xc0 },
352 { STV090x_P1_DISRXCTL, 0x00 },
353 { STV090x_P1_DMDCFGMD, 0xF9 },
354 { STV090x_P1_DEMOD, 0x08 },
355 { STV090x_P1_DMDCFG3, 0xc4 },
356 { STV090x_P1_CARFREQ, 0xed },
357 { STV090x_P1_TNRCFG2, 0x82 },
358 { STV090x_P1_LDT, 0xd0 },
359 { STV090x_P1_LDT2, 0xb8 },
360 { STV090x_P1_TMGCFG, 0xd2 },
361 { STV090x_P1_TMGTHRISE, 0x20 },
362 { STV090x_P1_TMGTHFALL, 0x00 },
363 { STV090x_P1_SFRUPRATIO, 0xf0 },
364 { STV090x_P1_SFRLOWRATIO, 0x70 },
365 { STV090x_P1_TSCFGL, 0x20 },
366 { STV090x_P1_FECSPY, 0x88 },
367 { STV090x_P1_FSPYDATA, 0x3a },
368 { STV090x_P1_FBERCPT4, 0x00 },
369 { STV090x_P1_FSPYBER, 0x10 },
370 { STV090x_P1_ERRCTRL1, 0x35 },
371 { STV090x_P1_ERRCTRL2, 0xc1 },
372 { STV090x_P1_CFRICFG, 0xf8 },
373 { STV090x_P1_NOSCFG, 0x1c },
374 { STV090x_P1_DMDTOM, 0x20 },
375 { STV090x_P1_CORRELMANT, 0x70 },
376 { STV090x_P1_CORRELABS, 0x88 },
377 { STV090x_P1_AGC2O, 0x5b },
378 { STV090x_P1_AGC2REF, 0x38 },
379 { STV090x_P1_CARCFG, 0xe4 },
380 { STV090x_P1_ACLC, 0x1A },
381 { STV090x_P1_BCLC, 0x09 },
382 { STV090x_P1_CARHDR, 0x08 },
383 { STV090x_P1_KREFTMG, 0xc1 },
384 { STV090x_P1_SFRSTEP, 0x58 },
385 { STV090x_P1_TMGCFG2, 0x01 },
386 { STV090x_P1_CAR2CFG, 0x26 },
387 { STV090x_P1_BCLC2S2Q, 0x86 },
388 { STV090x_P1_BCLC2S28, 0x86 },
389 { STV090x_P1_SMAPCOEF7, 0x77 },
390 { STV090x_P1_SMAPCOEF6, 0x85 },
391 { STV090x_P1_SMAPCOEF5, 0x77 },
392 { STV090x_P1_DMDCFG2, 0x3b },
393 { STV090x_P1_MODCODLST0, 0xff },
394 { STV090x_P1_MODCODLST1, 0xff },
395 { STV090x_P1_MODCODLST2, 0xff },
396 { STV090x_P1_MODCODLST3, 0xff },
397 { STV090x_P1_MODCODLST4, 0xff },
398 { STV090x_P1_MODCODLST5, 0xff },
399 { STV090x_P1_MODCODLST6, 0xff },
400 { STV090x_P1_MODCODLST7, 0xcc },
401 { STV090x_P1_MODCODLST8, 0xcc },
402 { STV090x_P1_MODCODLST9, 0xcc },
403 { STV090x_P1_MODCODLSTA, 0xcc },
404 { STV090x_P1_MODCODLSTB, 0xcc },
405 { STV090x_P1_MODCODLSTC, 0xcc },
406 { STV090x_P1_MODCODLSTD, 0xcc },
407 { STV090x_P1_MODCODLSTE, 0xcc },
408 { STV090x_P1_MODCODLSTF, 0xcf },
409 { STV090x_GENCFG, 0x1c },
410 { STV090x_NBITER_NF4, 0x37 },
411 { STV090x_NBITER_NF5, 0x29 },
412 { STV090x_NBITER_NF6, 0x37 },
413 { STV090x_NBITER_NF7, 0x33 },
414 { STV090x_NBITER_NF8, 0x31 },
415 { STV090x_NBITER_NF9, 0x2f },
416 { STV090x_NBITER_NF10, 0x39 },
417 { STV090x_NBITER_NF11, 0x3a },
418 { STV090x_NBITER_NF12, 0x29 },
419 { STV090x_NBITER_NF13, 0x37 },
420 { STV090x_NBITER_NF14, 0x33 },
421 { STV090x_NBITER_NF15, 0x2f },
422 { STV090x_NBITER_NF16, 0x39 },
423 { STV090x_NBITER_NF17, 0x3a },
424 { STV090x_NBITERNOERR, 0x04 },
425 { STV090x_GAINLLR_NF4, 0x0C },
426 { STV090x_GAINLLR_NF5, 0x0F },
427 { STV090x_GAINLLR_NF6, 0x11 },
428 { STV090x_GAINLLR_NF7, 0x14 },
429 { STV090x_GAINLLR_NF8, 0x17 },
430 { STV090x_GAINLLR_NF9, 0x19 },
431 { STV090x_GAINLLR_NF10, 0x20 },
432 { STV090x_GAINLLR_NF11, 0x21 },
433 { STV090x_GAINLLR_NF12, 0x0D },
434 { STV090x_GAINLLR_NF13, 0x0F },
435 { STV090x_GAINLLR_NF14, 0x13 },
436 { STV090x_GAINLLR_NF15, 0x1A },
437 { STV090x_GAINLLR_NF16, 0x1F },
438 { STV090x_GAINLLR_NF17, 0x21 },
439 { STV090x_RCCFGH, 0x20 },
440 { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
441 { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
444 static struct stv090x_reg stv0900_cut20_val[] = {
446 { STV090x_P2_DMDCFG3, 0xe8 },
447 { STV090x_P2_DMDCFG4, 0x10 },
448 { STV090x_P2_CARFREQ, 0x38 },
449 { STV090x_P2_CARHDR, 0x20 },
450 { STV090x_P2_KREFTMG, 0x5a },
451 { STV090x_P2_SMAPCOEF7, 0x06 },
452 { STV090x_P2_SMAPCOEF6, 0x00 },
453 { STV090x_P2_SMAPCOEF5, 0x04 },
454 { STV090x_P2_NOSCFG, 0x0c },
455 { STV090x_P1_DMDCFG3, 0xe8 },
456 { STV090x_P1_DMDCFG4, 0x10 },
457 { STV090x_P1_CARFREQ, 0x38 },
458 { STV090x_P1_CARHDR, 0x20 },
459 { STV090x_P1_KREFTMG, 0x5a },
460 { STV090x_P1_SMAPCOEF7, 0x06 },
461 { STV090x_P1_SMAPCOEF6, 0x00 },
462 { STV090x_P1_SMAPCOEF5, 0x04 },
463 { STV090x_P1_NOSCFG, 0x0c },
464 { STV090x_GAINLLR_NF4, 0x21 },
465 { STV090x_GAINLLR_NF5, 0x21 },
466 { STV090x_GAINLLR_NF6, 0x20 },
467 { STV090x_GAINLLR_NF7, 0x1F },
468 { STV090x_GAINLLR_NF8, 0x1E },
469 { STV090x_GAINLLR_NF9, 0x1E },
470 { STV090x_GAINLLR_NF10, 0x1D },
471 { STV090x_GAINLLR_NF11, 0x1B },
472 { STV090x_GAINLLR_NF12, 0x20 },
473 { STV090x_GAINLLR_NF13, 0x20 },
474 { STV090x_GAINLLR_NF14, 0x20 },
475 { STV090x_GAINLLR_NF15, 0x20 },
476 { STV090x_GAINLLR_NF16, 0x20 },
477 { STV090x_GAINLLR_NF17, 0x21 },
480 static struct stv090x_reg stv0903_cut20_val[] = {
481 { STV090x_P1_DMDCFG3, 0xe8 },
482 { STV090x_P1_DMDCFG4, 0x10 },
483 { STV090x_P1_CARFREQ, 0x38 },
484 { STV090x_P1_CARHDR, 0x20 },
485 { STV090x_P1_KREFTMG, 0x5a },
486 { STV090x_P1_SMAPCOEF7, 0x06 },
487 { STV090x_P1_SMAPCOEF6, 0x00 },
488 { STV090x_P1_SMAPCOEF5, 0x04 },
489 { STV090x_P1_NOSCFG, 0x0c },
490 { STV090x_GAINLLR_NF4, 0x21 },
491 { STV090x_GAINLLR_NF5, 0x21 },
492 { STV090x_GAINLLR_NF6, 0x20 },
493 { STV090x_GAINLLR_NF7, 0x1F },
494 { STV090x_GAINLLR_NF8, 0x1E },
495 { STV090x_GAINLLR_NF9, 0x1E },
496 { STV090x_GAINLLR_NF10, 0x1D },
497 { STV090x_GAINLLR_NF11, 0x1B },
498 { STV090x_GAINLLR_NF12, 0x20 },
499 { STV090x_GAINLLR_NF13, 0x20 },
500 { STV090x_GAINLLR_NF14, 0x20 },
501 { STV090x_GAINLLR_NF15, 0x20 },
502 { STV090x_GAINLLR_NF16, 0x20 },
503 { STV090x_GAINLLR_NF17, 0x21 }
506 /* Cut 2.0 Long Frame Tracking CR loop */
507 static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
508 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
509 { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
510 { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
511 { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
512 { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
513 { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
514 { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
515 { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
516 { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
517 { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
518 { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
519 { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
520 { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
521 { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
522 { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
525 /* Cut 3.0 Long Frame Tracking CR loop */
526 static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = {
527 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
528 { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b },
529 { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
530 { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
531 { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
532 { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
533 { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
534 { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
535 { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
536 { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 },
537 { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a },
538 { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a },
539 { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b },
540 { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b },
541 { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b }
544 /* Cut 2.0 Long Frame Tracking CR Loop */
545 static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
546 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
547 { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
548 { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
549 { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
550 { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
551 { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
552 { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
553 { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
554 { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
555 { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
556 { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
557 { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
560 /* Cut 3.0 Long Frame Tracking CR Loop */
561 static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = {
562 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
563 { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a },
564 { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a },
565 { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
566 { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
567 { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
568 { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
569 { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
570 { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
571 { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
572 { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
573 { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }
576 static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
577 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
578 { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
579 { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
580 { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
583 static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = {
584 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
585 { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b },
586 { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b },
587 { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b }
590 /* Cut 2.0 Short Frame Tracking CR Loop */
591 static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = {
592 /* MODCOD 2M 5M 10M 20M 30M */
593 { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d },
594 { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c },
595 { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d },
596 { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }
599 /* Cut 3.0 Short Frame Tracking CR Loop */
600 static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = {
601 /* MODCOD 2M 5M 10M 20M 30M */
602 { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A },
603 { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 },
604 { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
605 { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }
608 static inline s32 comp2(s32 __x, s32 __width)
613 return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
616 static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
618 const struct stv090x_config *config = state->config;
621 u8 b0[] = { reg >> 8, reg & 0xff };
624 struct i2c_msg msg[] = {
625 { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
626 { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
629 ret = i2c_transfer(state->i2c, msg, 2);
631 if (ret != -ERESTARTSYS)
633 "Read error, Reg=[0x%02x], Status=%d",
636 return ret < 0 ? ret : -EREMOTEIO;
638 if (unlikely(*state->verbose >= FE_DEBUGREG))
639 dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
642 return (unsigned int) buf;
645 static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
647 const struct stv090x_config *config = state->config;
650 struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
654 memcpy(&buf[2], data, count);
656 if (unlikely(*state->verbose >= FE_DEBUGREG)) {
659 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
660 for (i = 0; i < count; i++)
661 printk(" %02x", data[i]);
665 ret = i2c_transfer(state->i2c, &i2c_msg, 1);
667 if (ret != -ERESTARTSYS)
668 dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
669 reg, data[0], count, ret);
670 return ret < 0 ? ret : -EREMOTEIO;
676 static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
678 return stv090x_write_regs(state, reg, &data, 1);
681 static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
683 struct stv090x_state *state = fe->demodulator_priv;
686 reg = STV090x_READ_DEMOD(state, I2CRPT);
688 dprintk(FE_DEBUG, 1, "Enable Gate");
689 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
690 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
694 dprintk(FE_DEBUG, 1, "Disable Gate");
695 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
696 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
701 dprintk(FE_ERROR, 1, "I/O error");
705 static void stv090x_get_lock_tmg(struct stv090x_state *state)
707 switch (state->algo) {
708 case STV090x_BLIND_SEARCH:
709 dprintk(FE_DEBUG, 1, "Blind Search");
710 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
711 state->DemodTimeout = 1500;
712 state->FecTimeout = 400;
713 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
714 state->DemodTimeout = 1000;
715 state->FecTimeout = 300;
716 } else { /*SR >20Msps*/
717 state->DemodTimeout = 700;
718 state->FecTimeout = 100;
722 case STV090x_COLD_SEARCH:
723 case STV090x_WARM_SEARCH:
725 dprintk(FE_DEBUG, 1, "Normal Search");
726 if (state->srate <= 1000000) { /*SR <=1Msps*/
727 state->DemodTimeout = 4500;
728 state->FecTimeout = 1700;
729 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
730 state->DemodTimeout = 2500;
731 state->FecTimeout = 1100;
732 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
733 state->DemodTimeout = 1000;
734 state->FecTimeout = 550;
735 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
736 state->DemodTimeout = 700;
737 state->FecTimeout = 250;
738 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
739 state->DemodTimeout = 400;
740 state->FecTimeout = 130;
741 } else { /*SR >20Msps*/
742 state->DemodTimeout = 300;
743 state->FecTimeout = 100;
748 if (state->algo == STV090x_WARM_SEARCH)
749 state->DemodTimeout /= 2;
752 static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
756 if (srate > 60000000) {
757 sym = (srate << 4); /* SR * 2^16 / master_clk */
758 sym /= (state->mclk >> 12);
759 } else if (srate > 6000000) {
761 sym /= (state->mclk >> 10);
764 sym /= (state->mclk >> 7);
767 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
769 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
774 dprintk(FE_ERROR, 1, "I/O error");
778 static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
782 srate = 105 * (srate / 100);
783 if (srate > 60000000) {
784 sym = (srate << 4); /* SR * 2^16 / master_clk */
785 sym /= (state->mclk >> 12);
786 } else if (srate > 6000000) {
788 sym /= (state->mclk >> 10);
791 sym /= (state->mclk >> 7);
795 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
797 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
800 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
802 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
808 dprintk(FE_ERROR, 1, "I/O error");
812 static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
816 srate = 95 * (srate / 100);
817 if (srate > 60000000) {
818 sym = (srate << 4); /* SR * 2^16 / master_clk */
819 sym /= (state->mclk >> 12);
820 } else if (srate > 6000000) {
822 sym /= (state->mclk >> 10);
825 sym /= (state->mclk >> 7);
828 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */
830 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
834 dprintk(FE_ERROR, 1, "I/O error");
838 static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff)
855 return srate + (srate * ro) / 100;
858 static int stv090x_set_vit_thacq(struct stv090x_state *state)
860 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
862 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
864 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
866 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
868 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
870 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
874 dprintk(FE_ERROR, 1, "I/O error");
878 static int stv090x_set_vit_thtracq(struct stv090x_state *state)
880 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
882 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
884 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
886 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
888 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
890 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
894 dprintk(FE_ERROR, 1, "I/O error");
898 static int stv090x_set_viterbi(struct stv090x_state *state)
900 switch (state->search_mode) {
901 case STV090x_SEARCH_AUTO:
902 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
904 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
907 case STV090x_SEARCH_DVBS1:
908 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
910 switch (state->fec) {
912 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
917 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
922 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
927 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
932 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
937 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
942 case STV090x_SEARCH_DSS:
943 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
945 switch (state->fec) {
947 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
952 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
957 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
962 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
972 dprintk(FE_ERROR, 1, "I/O error");
976 static int stv090x_stop_modcod(struct stv090x_state *state)
978 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
980 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
982 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
984 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
986 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
988 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
990 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
992 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
994 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
996 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
998 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
1000 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
1002 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
1004 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
1006 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
1008 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
1012 dprintk(FE_ERROR, 1, "I/O error");
1016 static int stv090x_activate_modcod(struct stv090x_state *state)
1018 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1020 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
1022 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
1024 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
1026 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
1028 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
1030 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
1032 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
1034 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
1036 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
1038 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
1040 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
1042 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
1044 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
1046 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
1048 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
1053 dprintk(FE_ERROR, 1, "I/O error");
1057 static int stv090x_activate_modcod_single(struct stv090x_state *state)
1060 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1062 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0)
1064 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0)
1066 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0)
1068 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0)
1070 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0)
1072 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0)
1074 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0)
1076 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0)
1078 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0)
1080 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0)
1082 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0)
1084 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0)
1086 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0)
1088 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0)
1090 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0)
1096 dprintk(FE_ERROR, 1, "I/O error");
1100 static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
1104 switch (state->demod) {
1105 case STV090x_DEMODULATOR_0:
1106 mutex_lock(&demod_lock);
1107 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1108 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
1109 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1111 mutex_unlock(&demod_lock);
1114 case STV090x_DEMODULATOR_1:
1115 mutex_lock(&demod_lock);
1116 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1117 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
1118 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1120 mutex_unlock(&demod_lock);
1124 dprintk(FE_ERROR, 1, "Wrong demodulator!");
1129 mutex_unlock(&demod_lock);
1130 dprintk(FE_ERROR, 1, "I/O error");
1134 static int stv090x_dvbs_track_crl(struct stv090x_state *state)
1136 if (state->dev_ver >= 0x30) {
1137 /* Set ACLC BCLC optimised value vs SR */
1138 if (state->srate >= 15000000) {
1139 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0)
1141 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0)
1143 } else if ((state->srate >= 7000000) && (15000000 > state->srate)) {
1144 if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0)
1146 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0)
1148 } else if (state->srate < 7000000) {
1149 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0)
1151 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0)
1157 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1159 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1164 dprintk(FE_ERROR, 1, "I/O error");
1168 static int stv090x_delivery_search(struct stv090x_state *state)
1172 switch (state->search_mode) {
1173 case STV090x_SEARCH_DVBS1:
1174 case STV090x_SEARCH_DSS:
1175 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1176 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1177 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1178 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1181 /* Activate Viterbi decoder in legacy search,
1182 * do not use FRESVIT1, might impact VITERBI2
1184 if (stv090x_vitclk_ctl(state, 0) < 0)
1187 if (stv090x_dvbs_track_crl(state) < 0)
1190 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
1193 if (stv090x_set_vit_thacq(state) < 0)
1195 if (stv090x_set_viterbi(state) < 0)
1199 case STV090x_SEARCH_DVBS2:
1200 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1201 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1202 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1203 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1205 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1206 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1207 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1210 if (stv090x_vitclk_ctl(state, 1) < 0)
1213 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
1215 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1218 if (state->dev_ver <= 0x20) {
1219 /* enable S2 carrier loop */
1220 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1223 /* > Cut 3: Stop carrier 3 */
1224 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1228 if (state->demod_mode != STV090x_SINGLE) {
1229 /* Cut 2: enable link during search */
1230 if (stv090x_activate_modcod(state) < 0)
1233 /* Single demodulator
1234 * Authorize SHORT and LONG frames,
1235 * QPSK, 8PSK, 16APSK and 32APSK
1237 if (stv090x_activate_modcod_single(state) < 0)
1243 case STV090x_SEARCH_AUTO:
1245 /* enable DVB-S2 and DVB-S2 in Auto MODE */
1246 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1247 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1248 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1249 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1252 if (stv090x_vitclk_ctl(state, 0) < 0)
1255 if (stv090x_dvbs_track_crl(state) < 0)
1258 if (state->dev_ver <= 0x20) {
1259 /* enable S2 carrier loop */
1260 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1263 /* > Cut 3: Stop carrier 3 */
1264 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1268 if (state->demod_mode != STV090x_SINGLE) {
1269 /* Cut 2: enable link during search */
1270 if (stv090x_activate_modcod(state) < 0)
1273 /* Single demodulator
1274 * Authorize SHORT and LONG frames,
1275 * QPSK, 8PSK, 16APSK and 32APSK
1277 if (stv090x_activate_modcod_single(state) < 0)
1281 if (state->srate >= 2000000) {
1282 /* Srate >= 2MSPS, Viterbi threshold to acquire */
1283 if (stv090x_set_vit_thacq(state) < 0)
1286 /* Srate < 2MSPS, Reset Viterbi thresholdto track
1287 * and then re-acquire
1289 if (stv090x_set_vit_thtracq(state) < 0)
1293 if (stv090x_set_viterbi(state) < 0)
1299 dprintk(FE_ERROR, 1, "I/O error");
1303 static int stv090x_start_search(struct stv090x_state *state)
1308 /* Reset demodulator */
1309 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1310 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
1311 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1314 if (state->dev_ver <= 0x20) {
1315 if (state->srate <= 5000000) {
1316 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
1318 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
1320 if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0)
1322 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
1324 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
1327 /*enlarge the timing bandwith for Low SR*/
1328 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
1331 /* If the symbol rate is >5 Msps
1332 Set The carrier search up and low to auto mode */
1333 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1335 /*reduce the timing bandwith for high SR*/
1336 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1341 if (state->srate <= 5000000) {
1342 /* enlarge the timing bandwith for Low SR */
1343 STV090x_WRITE_DEMOD(state, RTCS2, 0x68);
1345 /* reduce timing bandwith for high SR */
1346 STV090x_WRITE_DEMOD(state, RTCS2, 0x44);
1349 /* Set CFR min and max to manual mode */
1350 STV090x_WRITE_DEMOD(state, CARCFG, 0x46);
1352 if (state->algo == STV090x_WARM_SEARCH) {
1357 freq_abs = 1000 << 16;
1358 freq_abs /= (state->mclk / 1000);
1359 freq = (s16) freq_abs;
1362 * CFR min =- (SearchRange / 2 + 600KHz)
1363 * CFR max = +(SearchRange / 2 + 600KHz)
1364 * (600KHz for the tuner step size)
1366 freq_abs = (state->search_range / 2000) + 600;
1367 freq_abs = freq_abs << 16;
1368 freq_abs /= (state->mclk / 1000);
1369 freq = (s16) freq_abs;
1372 if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
1374 if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0)
1379 if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0)
1381 if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0)
1386 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
1388 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
1391 if (state->dev_ver >= 0x20) {
1392 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1394 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1397 if ((state->search_mode == STV090x_DVBS1) ||
1398 (state->search_mode == STV090x_DSS) ||
1399 (state->search_mode == STV090x_SEARCH_AUTO)) {
1401 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1403 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
1408 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
1410 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
1412 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
1415 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1416 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1417 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1418 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1420 reg = STV090x_READ_DEMOD(state, DMDCFG2);
1421 STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
1422 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
1425 if (state->dev_ver >= 0x20) {
1426 /*Frequency offset detector setting*/
1427 if (state->srate < 2000000) {
1428 if (state->dev_ver <= 0x20) {
1430 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
1434 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
1437 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
1441 if (state->srate < 10000000) {
1442 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
1445 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
1449 if (state->srate < 10000000) {
1450 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
1453 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1458 switch (state->algo) {
1459 case STV090x_WARM_SEARCH:
1460 /* The symbol rate and the exact
1461 * carrier Frequency are known
1463 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1465 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
1469 case STV090x_COLD_SEARCH:
1470 /* The symbol rate is known */
1471 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1473 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1482 dprintk(FE_ERROR, 1, "I/O error");
1486 static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1488 u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg;
1489 s32 i, j, steps, dir;
1491 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1493 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1494 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1495 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
1496 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1499 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
1501 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1503 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
1505 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1507 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
1509 if (stv090x_set_srate(state, 1000000) < 0)
1512 steps = -1 + state->search_range / 1000000;
1514 steps = (2 * steps) + 1;
1519 freq_step = (1000000 * 256) / (state->mclk / 256);
1522 for (i = 0; i < steps; i++) {
1524 freq_init = freq_init + (freq_step * i);
1526 freq_init = freq_init - (freq_step * i);
1530 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
1532 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
1534 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
1536 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
1541 for (j = 0; j < 10; j++) {
1542 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1543 STV090x_READ_DEMOD(state, AGC2I0);
1546 if (agc2 < agc2_min)
1552 dprintk(FE_ERROR, 1, "I/O error");
1556 static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
1559 s32 srate, int_1, int_2, tmp_1, tmp_2;
1561 r3 = STV090x_READ_DEMOD(state, SFR3);
1562 r2 = STV090x_READ_DEMOD(state, SFR2);
1563 r1 = STV090x_READ_DEMOD(state, SFR1);
1564 r0 = STV090x_READ_DEMOD(state, SFR0);
1566 srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
1569 int_2 = srate >> 16;
1571 tmp_1 = clk % 0x10000;
1572 tmp_2 = srate % 0x10000;
1574 srate = (int_1 * int_2) +
1575 ((int_1 * tmp_2) >> 16) +
1576 ((int_2 * tmp_1) >> 16);
1581 static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1583 struct dvb_frontend *fe = &state->frontend;
1585 int tmg_lock = 0, i;
1586 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
1587 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
1590 if (state->dev_ver >= 0x30)
1595 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1596 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
1597 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1599 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
1601 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
1603 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
1605 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1606 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1607 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
1608 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1611 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
1613 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1615 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
1617 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1619 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
1621 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0)
1624 if (state->dev_ver >= 0x30) {
1625 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
1627 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
1630 } else if (state->dev_ver >= 0x20) {
1631 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
1633 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
1637 if (state->srate <= 2000000)
1639 else if (state->srate <= 5000000)
1641 else if (state->srate <= 12000000)
1646 steps = -1 + ((state->search_range / 1000) / car_step);
1648 steps = (2 * steps) + 1;
1651 else if (steps > 10) {
1653 car_step = (state->search_range / 1000) / 10;
1657 freq = state->frequency;
1659 while ((!tmg_lock) && (cur_step < steps)) {
1660 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
1662 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1663 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x00); /* trigger acquisition */
1664 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1667 for (i = 0; i < 10; i++) {
1668 reg = STV090x_READ_DEMOD(state, DSTATUS);
1669 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1671 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1672 STV090x_READ_DEMOD(state, AGC2I0);
1675 srate_coarse = stv090x_get_srate(state, state->mclk);
1678 if ((tmg_cpt >= 5) && (agc2 < agc2th) &&
1679 (srate_coarse < 50000000) && (srate_coarse > 850000))
1681 else if (cur_step < steps) {
1683 freq += cur_step * car_step;
1685 freq -= cur_step * car_step;
1688 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
1691 if (state->config->tuner_set_frequency) {
1692 if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
1696 if (state->config->tuner_set_bandwidth) {
1697 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
1701 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
1706 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
1709 if (state->config->tuner_get_status) {
1710 if (state->config->tuner_get_status(fe, ®) < 0)
1715 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1717 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1719 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
1727 srate_coarse = stv090x_get_srate(state, state->mclk);
1729 return srate_coarse;
1731 dprintk(FE_ERROR, 1, "I/O error");
1735 static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
1737 u32 srate_coarse, freq_coarse, sym, reg;
1739 srate_coarse = stv090x_get_srate(state, state->mclk);
1740 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
1741 freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
1742 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1744 if (sym < state->srate)
1747 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
1749 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0)
1751 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1753 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1755 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
1757 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1758 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
1759 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1762 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1765 if (state->dev_ver >= 0x30) {
1766 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
1768 } else if (state->dev_ver >= 0x20) {
1769 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
1773 if (srate_coarse > 3000000) {
1774 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1775 sym = (sym / 1000) * 65536;
1776 sym /= (state->mclk / 1000);
1777 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1779 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1781 sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
1782 sym = (sym / 1000) * 65536;
1783 sym /= (state->mclk / 1000);
1784 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1786 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1788 sym = (srate_coarse / 1000) * 65536;
1789 sym /= (state->mclk / 1000);
1790 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1792 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1795 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1796 sym = (sym / 100) * 65536;
1797 sym /= (state->mclk / 100);
1798 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1800 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1802 sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
1803 sym = (sym / 100) * 65536;
1804 sym /= (state->mclk / 100);
1805 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1807 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1809 sym = (srate_coarse / 100) * 65536;
1810 sym /= (state->mclk / 100);
1811 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1813 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1816 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
1818 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
1820 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
1822 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
1826 return srate_coarse;
1829 dprintk(FE_ERROR, 1, "I/O error");
1833 static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
1835 s32 timer = 0, lock = 0;
1839 while ((timer < timeout) && (!lock)) {
1840 reg = STV090x_READ_DEMOD(state, DMDSTATE);
1841 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
1844 case 0: /* searching */
1845 case 1: /* first PLH detected */
1847 dprintk(FE_DEBUG, 1, "Demodulator searching ..");
1850 case 2: /* DVB-S2 mode */
1851 case 3: /* DVB-S1/legacy mode */
1852 reg = STV090x_READ_DEMOD(state, DSTATUS);
1853 lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
1860 dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
1867 static int stv090x_blind_search(struct stv090x_state *state)
1869 u32 agc2, reg, srate_coarse;
1870 s32 timeout_dmd = 500, cpt_fail, agc2_ovflw, i;
1871 u8 k_ref, k_max, k_min;
1872 int coarse_fail, lock;
1877 agc2 = stv090x_get_agc2_min_level(state);
1879 if (agc2 > STV090x_SEARCH_AGC2_TH(state->dev_ver)) {
1883 if (state->dev_ver <= 0x20) {
1884 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1888 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0)
1892 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1895 if (state->dev_ver >= 0x20) {
1896 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1898 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1900 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1902 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
1908 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
1910 if (stv090x_srate_srch_coarse(state) != 0) {
1911 srate_coarse = stv090x_srate_srch_fine(state);
1912 if (srate_coarse != 0) {
1913 stv090x_get_lock_tmg(state);
1914 lock = stv090x_get_dmdlock(state, timeout_dmd);
1921 for (i = 0; i < 10; i++) {
1922 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1923 STV090x_READ_DEMOD(state, AGC2I0);
1926 reg = STV090x_READ_DEMOD(state, DSTATUS2);
1927 if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
1928 (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
1932 if ((cpt_fail > 7) || (agc2_ovflw > 7))
1938 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
1944 dprintk(FE_ERROR, 1, "I/O error");
1948 static int stv090x_chk_tmg(struct stv090x_state *state)
1952 u8 freq, tmg_thh, tmg_thl;
1955 freq = STV090x_READ_DEMOD(state, CARFREQ);
1956 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
1957 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
1958 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1960 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1963 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1964 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
1965 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1967 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
1970 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
1972 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
1975 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
1977 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1979 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
1982 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
1986 for (i = 0; i < 10; i++) {
1987 reg = STV090x_READ_DEMOD(state, DSTATUS);
1988 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1995 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1997 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
1999 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
2002 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
2004 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
2006 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
2012 dprintk(FE_ERROR, 1, "I/O error");
2016 static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
2018 struct dvb_frontend *fe = &state->frontend;
2021 s32 car_step, steps, cur_step, dir, freq, timeout_lock;
2024 if (state->srate >= 10000000)
2025 timeout_lock = timeout_dmd / 3;
2027 timeout_lock = timeout_dmd / 2;
2029 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
2031 if (state->srate >= 10000000) {
2032 if (stv090x_chk_tmg(state)) {
2033 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2035 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2037 lock = stv090x_get_dmdlock(state, timeout_dmd);
2042 if (state->srate <= 4000000)
2044 else if (state->srate <= 7000000)
2046 else if (state->srate <= 10000000)
2051 steps = (state->search_range / 1000) / car_step;
2053 steps = 2 * (steps + 1);
2056 else if (steps > 12)
2063 freq = state->frequency;
2064 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
2065 while ((cur_step <= steps) && (!lock)) {
2067 freq += cur_step * car_step;
2069 freq -= cur_step * car_step;
2072 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2075 if (state->config->tuner_set_frequency) {
2076 if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
2080 if (state->config->tuner_set_bandwidth) {
2081 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
2085 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2090 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2093 if (state->config->tuner_get_status) {
2094 if (state->config->tuner_get_status(fe, ®) < 0)
2099 dprintk(FE_DEBUG, 1, "Tuner phase locked");
2101 dprintk(FE_DEBUG, 1, "Tuner unlocked");
2103 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2106 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
2107 if (state->delsys == STV090x_DVBS2) {
2108 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2109 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
2110 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2111 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2113 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2114 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2115 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2118 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
2120 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
2122 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2124 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2126 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
2138 dprintk(FE_ERROR, 1, "I/O error");
2142 static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
2144 s32 timeout, inc, steps_max, srate, car_max;
2146 srate = state->srate;
2147 car_max = state->search_range / 1000;
2148 car_max += car_max / 10;
2149 car_max = 65536 * (car_max / 2);
2150 car_max /= (state->mclk / 1000);
2152 if (car_max > 0x4000)
2153 car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
2156 inc /= state->mclk / 1000;
2161 switch (state->search_mode) {
2162 case STV090x_SEARCH_DVBS1:
2163 case STV090x_SEARCH_DSS:
2164 inc *= 3; /* freq step = 3% of srate */
2168 case STV090x_SEARCH_DVBS2:
2173 case STV090x_SEARCH_AUTO:
2180 if ((inc > car_max) || (inc < 0))
2181 inc = car_max / 2; /* increment <= 1/8 Mclk */
2183 timeout *= 27500; /* 27.5 Msps reference */
2185 timeout /= (srate / 1000);
2187 if ((timeout > 100) || (timeout < 0))
2190 steps_max = (car_max / inc) + 1; /* min steps = 3 */
2191 if ((steps_max > 100) || (steps_max < 0)) {
2192 steps_max = 100; /* max steps <= 100 */
2193 inc = car_max / steps_max;
2196 *timeout_sw = timeout;
2202 static int stv090x_chk_signal(struct stv090x_state *state)
2204 s32 offst_car, agc2, car_max;
2207 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
2208 offst_car |= STV090x_READ_DEMOD(state, CFR1);
2209 offst_car = comp2(offst_car, 16);
2211 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
2212 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
2213 car_max = state->search_range / 1000;
2215 car_max += (car_max / 10); /* 10% margin */
2216 car_max = (65536 * car_max / 2);
2217 car_max /= state->mclk / 1000;
2219 if (car_max > 0x4000)
2222 if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
2224 dprintk(FE_DEBUG, 1, "No Signal");
2227 dprintk(FE_DEBUG, 1, "Found Signal");
2233 static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
2235 int no_signal, lock = 0;
2236 s32 cpt_step = 0, offst_freq, car_max;
2239 car_max = state->search_range / 1000;
2240 car_max += (car_max / 10);
2241 car_max = (65536 * car_max / 2);
2242 car_max /= (state->mclk / 1000);
2243 if (car_max > 0x4000)
2249 offst_freq = -car_max + inc;
2252 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2254 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
2256 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
2258 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2261 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2262 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
2263 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2267 if (offst_freq >= 0)
2268 offst_freq = -offst_freq - 2 * inc;
2270 offst_freq = -offst_freq;
2272 offst_freq += 2 * inc;
2277 lock = stv090x_get_dmdlock(state, timeout);
2278 no_signal = stv090x_chk_signal(state);
2282 ((offst_freq - inc) < car_max) &&
2283 ((offst_freq + inc) > -car_max) &&
2284 (cpt_step < steps_max));
2286 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2287 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
2288 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2293 dprintk(FE_ERROR, 1, "I/O error");
2297 static int stv090x_sw_algo(struct stv090x_state *state)
2299 int no_signal, zigzag, lock = 0;
2302 s32 dvbs2_fly_wheel;
2303 s32 inc, timeout_step, trials, steps_max;
2306 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max);
2308 switch (state->search_mode) {
2309 case STV090x_SEARCH_DVBS1:
2310 case STV090x_SEARCH_DSS:
2311 /* accelerate the frequency detector */
2312 if (state->dev_ver >= 0x20) {
2313 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
2317 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
2322 case STV090x_SEARCH_DVBS2:
2323 if (state->dev_ver >= 0x20) {
2324 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2328 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2333 case STV090x_SEARCH_AUTO:
2335 /* accelerate the frequency detector */
2336 if (state->dev_ver >= 0x20) {
2337 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
2339 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2343 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0)
2351 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
2352 no_signal = stv090x_chk_signal(state);
2355 /*run the SW search 2 times maximum*/
2356 if (lock || no_signal || (trials == 2)) {
2357 /*Check if the demod is not losing lock in DVBS2*/
2358 if (state->dev_ver >= 0x20) {
2359 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2361 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
2365 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2366 if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
2367 /*Check if the demod is not losing lock in DVBS2*/
2368 msleep(timeout_step);
2369 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2370 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2371 if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
2372 msleep(timeout_step);
2373 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2374 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2376 if (dvbs2_fly_wheel < 0xd) {
2377 /*FALSE lock, The demod is loosing lock */
2380 if (state->dev_ver >= 0x20) {
2381 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2385 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2391 } while ((!lock) && (trials < 2) && (!no_signal));
2395 dprintk(FE_ERROR, 1, "I/O error");
2399 static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
2402 enum stv090x_delsys delsys;
2404 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2405 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
2406 delsys = STV090x_DVBS2;
2407 else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
2408 reg = STV090x_READ_DEMOD(state, FECM);
2409 if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
2410 delsys = STV090x_DSS;
2412 delsys = STV090x_DVBS1;
2414 delsys = STV090x_ERROR;
2421 static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
2423 s32 derot, int_1, int_2, tmp_1, tmp_2;
2425 derot = STV090x_READ_DEMOD(state, CFR2) << 16;
2426 derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
2427 derot |= STV090x_READ_DEMOD(state, CFR0);
2429 derot = comp2(derot, 24);
2430 int_1 = state->mclk >> 12;
2431 int_2 = derot >> 12;
2433 /* carrier_frequency = MasterClock * Reg / 2^24 */
2434 tmp_1 = state->mclk % 0x1000;
2435 tmp_2 = derot % 0x1000;
2437 derot = (int_1 * int_2) +
2438 ((int_1 * tmp_2) >> 12) +
2439 ((int_2 * tmp_1) >> 12);
2444 static int stv090x_get_viterbi(struct stv090x_state *state)
2448 reg = STV090x_READ_DEMOD(state, VITCURPUN);
2449 rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
2453 state->fec = STV090x_PR12;
2457 state->fec = STV090x_PR23;
2461 state->fec = STV090x_PR34;
2465 state->fec = STV090x_PR56;
2469 state->fec = STV090x_PR67;
2473 state->fec = STV090x_PR78;
2477 state->fec = STV090x_PRERR;
2484 static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
2486 struct dvb_frontend *fe = &state->frontend;
2490 s32 i = 0, offst_freq;
2494 if (state->algo == STV090x_BLIND_SEARCH) {
2495 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2496 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
2497 while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) {
2498 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2503 state->delsys = stv090x_get_std(state);
2505 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2508 if (state->config->tuner_get_frequency) {
2509 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2513 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2516 offst_freq = stv090x_get_car_freq(state, state->mclk) / 1000;
2517 state->frequency += offst_freq;
2519 if (stv090x_get_viterbi(state) < 0)
2522 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2523 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2524 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2525 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
2526 reg = STV090x_READ_DEMOD(state, TMGOBS);
2527 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2528 reg = STV090x_READ_DEMOD(state, FECM);
2529 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
2531 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
2533 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2536 if (state->config->tuner_get_frequency) {
2537 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2541 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2544 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2545 return STV090x_RANGEOK;
2546 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
2547 return STV090x_RANGEOK;
2549 return STV090x_OUTOFRANGE; /* Out of Range */
2551 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2552 return STV090x_RANGEOK;
2554 return STV090x_OUTOFRANGE;
2557 return STV090x_OUTOFRANGE;
2559 dprintk(FE_ERROR, 1, "I/O error");
2563 static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
2567 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
2568 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
2569 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
2571 offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
2575 offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg);
2581 static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
2585 struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low;
2587 if (state->dev_ver == 0x20) {
2588 car_loop = stv090x_s2_crl_cut20;
2589 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20;
2590 car_loop_apsk_low = stv090x_s2_apsk_crl_cut20;
2593 car_loop = stv090x_s2_crl_cut30;
2594 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30;
2595 car_loop_apsk_low = stv090x_s2_apsk_crl_cut30;
2598 if (modcod < STV090x_QPSK_12) {
2600 while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod))
2608 while ((i < 14) && (modcod != car_loop[i].modcod))
2613 while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod))
2621 if (modcod <= STV090x_QPSK_25) {
2623 if (state->srate <= 3000000)
2624 aclc = car_loop_qpsk_low[i].crl_pilots_on_2;
2625 else if (state->srate <= 7000000)
2626 aclc = car_loop_qpsk_low[i].crl_pilots_on_5;
2627 else if (state->srate <= 15000000)
2628 aclc = car_loop_qpsk_low[i].crl_pilots_on_10;
2629 else if (state->srate <= 25000000)
2630 aclc = car_loop_qpsk_low[i].crl_pilots_on_20;
2632 aclc = car_loop_qpsk_low[i].crl_pilots_on_30;
2634 if (state->srate <= 3000000)
2635 aclc = car_loop_qpsk_low[i].crl_pilots_off_2;
2636 else if (state->srate <= 7000000)
2637 aclc = car_loop_qpsk_low[i].crl_pilots_off_5;
2638 else if (state->srate <= 15000000)
2639 aclc = car_loop_qpsk_low[i].crl_pilots_off_10;
2640 else if (state->srate <= 25000000)
2641 aclc = car_loop_qpsk_low[i].crl_pilots_off_20;
2643 aclc = car_loop_qpsk_low[i].crl_pilots_off_30;
2646 } else if (modcod <= STV090x_8PSK_910) {
2648 if (state->srate <= 3000000)
2649 aclc = car_loop[i].crl_pilots_on_2;
2650 else if (state->srate <= 7000000)
2651 aclc = car_loop[i].crl_pilots_on_5;
2652 else if (state->srate <= 15000000)
2653 aclc = car_loop[i].crl_pilots_on_10;
2654 else if (state->srate <= 25000000)
2655 aclc = car_loop[i].crl_pilots_on_20;
2657 aclc = car_loop[i].crl_pilots_on_30;
2659 if (state->srate <= 3000000)
2660 aclc = car_loop[i].crl_pilots_off_2;
2661 else if (state->srate <= 7000000)
2662 aclc = car_loop[i].crl_pilots_off_5;
2663 else if (state->srate <= 15000000)
2664 aclc = car_loop[i].crl_pilots_off_10;
2665 else if (state->srate <= 25000000)
2666 aclc = car_loop[i].crl_pilots_off_20;
2668 aclc = car_loop[i].crl_pilots_off_30;
2670 } else { /* 16APSK and 32APSK */
2671 if (state->srate <= 3000000)
2672 aclc = car_loop_apsk_low[i].crl_pilots_on_2;
2673 else if (state->srate <= 7000000)
2674 aclc = car_loop_apsk_low[i].crl_pilots_on_5;
2675 else if (state->srate <= 15000000)
2676 aclc = car_loop_apsk_low[i].crl_pilots_on_10;
2677 else if (state->srate <= 25000000)
2678 aclc = car_loop_apsk_low[i].crl_pilots_on_20;
2680 aclc = car_loop_apsk_low[i].crl_pilots_on_30;
2686 static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
2688 struct stv090x_short_frame_crloop *short_crl = NULL;
2692 switch (state->modulation) {
2700 case STV090x_16APSK:
2703 case STV090x_32APSK:
2708 if (state->dev_ver >= 0x30) {
2709 /* Cut 3.0 and up */
2710 short_crl = stv090x_s2_short_crl_cut30;
2712 /* Cut 2.0 and up: we don't support cuts older than 2.0 */
2713 short_crl = stv090x_s2_short_crl_cut20;
2716 if (state->srate <= 3000000)
2717 aclc = short_crl[index].crl_2;
2718 else if (state->srate <= 7000000)
2719 aclc = short_crl[index].crl_5;
2720 else if (state->srate <= 15000000)
2721 aclc = short_crl[index].crl_10;
2722 else if (state->srate <= 25000000)
2723 aclc = short_crl[index].crl_20;
2725 aclc = short_crl[index].crl_30;
2730 static int stv090x_optimize_track(struct stv090x_state *state)
2732 struct dvb_frontend *fe = &state->frontend;
2734 enum stv090x_rolloff rolloff;
2735 enum stv090x_modcod modcod;
2737 s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
2740 srate = stv090x_get_srate(state, state->mclk);
2741 srate += stv090x_get_tmgoffst(state, srate);
2743 switch (state->delsys) {
2746 if (state->search_mode == STV090x_SEARCH_AUTO) {
2747 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2748 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2749 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2750 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2753 reg = STV090x_READ_DEMOD(state, DEMOD);
2754 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
2755 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01);
2756 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2759 if (state->dev_ver >= 0x30) {
2760 if (stv090x_get_viterbi(state) < 0)
2763 if (state->fec == STV090x_PR12) {
2764 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0)
2766 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2769 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0)
2771 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2776 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
2781 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2782 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
2783 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2784 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2786 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
2788 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
2790 if (state->frame_len == STV090x_LONG_FRAME) {
2791 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2792 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2793 pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2794 aclc = stv090x_optimize_carloop(state, modcod, pilots);
2795 if (modcod <= STV090x_QPSK_910) {
2796 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
2797 } else if (modcod <= STV090x_8PSK_910) {
2798 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2800 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2803 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
2804 if (modcod <= STV090x_16APSK_910) {
2805 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2807 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2810 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2812 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2817 /*Carrier loop setting for short frame*/
2818 aclc = stv090x_optimize_carloop_short(state);
2819 if (state->modulation == STV090x_QPSK) {
2820 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
2822 } else if (state->modulation == STV090x_8PSK) {
2823 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2825 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2827 } else if (state->modulation == STV090x_16APSK) {
2828 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2830 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2832 } else if (state->modulation == STV090x_32APSK) {
2833 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2835 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2840 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
2843 case STV090x_UNKNOWN:
2845 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2846 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2847 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2848 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2853 f_1 = STV090x_READ_DEMOD(state, CFR2);
2854 f_0 = STV090x_READ_DEMOD(state, CFR1);
2855 reg = STV090x_READ_DEMOD(state, TMGOBS);
2856 rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2858 if (state->algo == STV090x_BLIND_SEARCH) {
2859 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
2860 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2861 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
2862 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
2863 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2865 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
2868 if (stv090x_set_srate(state, srate) < 0)
2873 if (state->dev_ver >= 0x20) {
2874 if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
2875 (state->search_mode == STV090x_SEARCH_DSS) ||
2876 (state->search_mode == STV090x_SEARCH_AUTO)) {
2878 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
2880 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
2885 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2888 /* AUTO tracking MODE */
2889 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0)
2891 /* AUTO tracking MODE */
2892 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0)
2895 if ((state->dev_ver >= 0x20) || (blind_tune == 1) || (state->srate < 10000000)) {
2896 /* update initial carrier freq with the found freq offset */
2897 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2899 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2901 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
2903 if ((state->dev_ver >= 0x20) || (blind_tune == 1)) {
2905 if (state->algo != STV090x_WARM_SEARCH) {
2907 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
2910 if (state->config->tuner_set_bandwidth) {
2911 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
2915 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
2920 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
2921 msleep(50); /* blind search: wait 50ms for SR stabilization */
2925 stv090x_get_lock_tmg(state);
2927 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
2928 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2930 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2932 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2934 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2939 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
2941 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2943 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2945 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2947 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2955 if (state->dev_ver >= 0x20) {
2956 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2960 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
2961 stv090x_set_vit_thtracq(state);
2965 dprintk(FE_ERROR, 1, "I/O error");
2969 static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
2971 s32 timer = 0, lock = 0, stat;
2974 while ((timer < timeout) && (!lock)) {
2975 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2976 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
2979 case 0: /* searching */
2980 case 1: /* first PLH detected */
2985 case 2: /* DVB-S2 mode */
2986 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
2987 lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
2990 case 3: /* DVB-S1/legacy mode */
2991 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
2992 lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
3003 static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
3009 lock = stv090x_get_dmdlock(state, timeout_dmd);
3011 lock = stv090x_get_feclock(state, timeout_fec);
3016 while ((timer < timeout_fec) && (!lock)) {
3017 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3018 lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
3027 static int stv090x_set_s2rolloff(struct stv090x_state *state)
3031 if (state->dev_ver <= 0x20) {
3032 /* rolloff to auto mode if DVBS2 */
3033 reg = STV090x_READ_DEMOD(state, DEMOD);
3034 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00);
3035 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3038 /* DVB-S2 rolloff to auto mode if DVBS2 */
3039 reg = STV090x_READ_DEMOD(state, DEMOD);
3040 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00);
3041 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3046 dprintk(FE_ERROR, 1, "I/O error");
3051 static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
3053 struct dvb_frontend *fe = &state->frontend;
3054 enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
3056 s32 timeout_dmd = 500, timeout_fec = 50, agc1_power, power_iq = 0, i;
3057 int lock = 0, low_sr = 0, no_signal = 0;
3059 reg = STV090x_READ_DEMOD(state, TSCFGH);
3060 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
3061 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3064 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
3067 if (state->dev_ver >= 0x20) {
3068 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) /* cut 2.0 */
3072 stv090x_get_lock_tmg(state);
3074 if (state->algo == STV090x_BLIND_SEARCH) {
3075 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
3076 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */
3078 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
3080 if (stv090x_set_srate(state, 1000000) < 0) /* inital srate = 1Msps */
3084 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
3086 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
3089 if (state->srate < 2000000) {
3091 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0)
3095 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
3099 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
3102 if (state->dev_ver >= 0x20) {
3103 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
3105 if (state->algo == STV090x_COLD_SEARCH)
3106 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
3107 else if (state->algo == STV090x_WARM_SEARCH)
3108 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
3111 /* if cold start or warm (Symbolrate is known)
3112 * use a Narrow symbol rate scan range
3114 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */
3117 if (stv090x_set_srate(state, state->srate) < 0)
3120 if (stv090x_set_max_srate(state, state->mclk, state->srate) < 0)
3122 if (stv090x_set_min_srate(state, state->mclk, state->srate) < 0)
3125 if (state->srate >= 10000000)
3132 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
3135 if (state->config->tuner_set_bbgain) {
3136 if (state->config->tuner_set_bbgain(fe, 10) < 0) /* 10dB */
3140 if (state->config->tuner_set_frequency) {
3141 if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
3145 if (state->config->tuner_set_bandwidth) {
3146 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
3150 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
3155 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
3158 if (state->config->tuner_get_status) {
3159 if (state->config->tuner_get_status(fe, ®) < 0)
3164 dprintk(FE_DEBUG, 1, "Tuner phase locked");
3166 dprintk(FE_DEBUG, 1, "Tuner unlocked");
3168 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
3172 agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1),
3173 STV090x_READ_DEMOD(state, AGCIQIN0));
3175 if (agc1_power == 0) {
3176 /* If AGC1 integrator value is 0
3177 * then read POWERI, POWERQ
3179 for (i = 0; i < 5; i++) {
3180 power_iq += (STV090x_READ_DEMOD(state, POWERI) +
3181 STV090x_READ_DEMOD(state, POWERQ)) >> 1;
3186 if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) {
3187 dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq);
3191 reg = STV090x_READ_DEMOD(state, DEMOD);
3192 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
3194 if (state->dev_ver <= 0x20) {
3195 /* rolloff to auto mode if DVBS2 */
3196 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1);
3198 /* DVB-S2 rolloff to auto mode if DVBS2 */
3199 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1);
3201 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3204 if (stv090x_delivery_search(state) < 0)
3207 if (state->algo != STV090x_BLIND_SEARCH) {
3208 if (stv090x_start_search(state) < 0)
3213 /* need to check for AGC1 state */
3217 if (state->algo == STV090x_BLIND_SEARCH)
3218 lock = stv090x_blind_search(state);
3220 else if (state->algo == STV090x_COLD_SEARCH)
3221 lock = stv090x_get_coldlock(state, timeout_dmd);
3223 else if (state->algo == STV090x_WARM_SEARCH)
3224 lock = stv090x_get_dmdlock(state, timeout_dmd);
3226 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
3228 if (stv090x_chk_tmg(state))
3229 lock = stv090x_sw_algo(state);
3234 signal_state = stv090x_get_sig_params(state);
3236 if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
3237 stv090x_optimize_track(state);
3239 if (state->dev_ver >= 0x20) {
3240 /* >= Cut 2.0 :release TS reset after
3241 * demod lock and optimized Tracking
3243 reg = STV090x_READ_DEMOD(state, TSCFGH);
3244 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3245 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3250 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3251 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3254 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3255 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3259 if (stv090x_get_lock(state, timeout_fec, timeout_fec)) {
3261 if (state->delsys == STV090x_DVBS2) {
3262 stv090x_set_s2rolloff(state);
3264 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3265 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1);
3266 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
3268 /* Reset DVBS2 packet delinator error counter */
3269 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3270 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0);
3271 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
3274 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
3277 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
3280 /* Reset the Total packet counter */
3281 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
3283 /* Reset the packet Error counter2 */
3284 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3288 signal_state = STV090x_NODATA;
3289 no_signal = stv090x_chk_signal(state);
3292 return signal_state;
3295 dprintk(FE_ERROR, 1, "I/O error");
3299 static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
3301 struct stv090x_state *state = fe->demodulator_priv;
3302 struct dtv_frontend_properties *props = &fe->dtv_property_cache;
3304 state->delsys = props->delivery_system;
3305 state->frequency = p->frequency;
3306 state->srate = p->u.qpsk.symbol_rate;
3307 state->search_mode = STV090x_SEARCH_AUTO;
3308 state->algo = STV090x_COLD_SEARCH;
3309 state->fec = STV090x_PRERR;
3310 if (state->srate > 10000000) {
3311 dprintk(FE_DEBUG, 1, "Search range: 10 MHz");
3312 state->search_range = 10000000;
3314 dprintk(FE_DEBUG, 1, "Search range: 5 MHz");
3315 state->search_range = 5000000;
3318 if (stv090x_algo(state) == STV090x_RANGEOK) {
3319 dprintk(FE_DEBUG, 1, "Search success!");
3320 return DVBFE_ALGO_SEARCH_SUCCESS;
3322 dprintk(FE_DEBUG, 1, "Search failed!");
3323 return DVBFE_ALGO_SEARCH_FAILED;
3326 return DVBFE_ALGO_SEARCH_ERROR;
3330 static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
3332 struct stv090x_state *state = fe->demodulator_priv;
3336 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3337 search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3339 switch (search_state) {
3340 case 0: /* searching */
3341 case 1: /* first PLH detected */
3343 dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
3347 case 2: /* DVB-S2 mode */
3348 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
3349 reg = STV090x_READ_DEMOD(state, DSTATUS);
3350 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3351 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3352 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3353 *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
3358 case 3: /* DVB-S1/legacy mode */
3359 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
3360 reg = STV090x_READ_DEMOD(state, DSTATUS);
3361 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3362 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3363 if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
3364 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3365 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3366 *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
3376 static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
3378 struct stv090x_state *state = fe->demodulator_priv;
3380 s32 count_4, count_3, count_2, count_1, count_0, count;
3382 enum fe_status status;
3384 stv090x_read_status(fe, &status);
3385 if (!(status & FE_HAS_LOCK)) {
3386 *per = 1 << 23; /* Max PER */
3389 reg = STV090x_READ_DEMOD(state, ERRCNT22);
3390 h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
3392 reg = STV090x_READ_DEMOD(state, ERRCNT21);
3393 m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
3395 reg = STV090x_READ_DEMOD(state, ERRCNT20);
3396 l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
3398 *per = ((h << 16) | (m << 8) | l);
3400 count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
3401 count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
3402 count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
3403 count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
3404 count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
3406 if ((!count_4) && (!count_3)) {
3407 count = (count_2 & 0xff) << 16;
3408 count |= (count_1 & 0xff) << 8;
3409 count |= count_0 & 0xff;
3416 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
3418 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3423 dprintk(FE_ERROR, 1, "I/O error");
3427 static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
3432 if ((val >= tab[min].read && val < tab[max].read) ||
3433 (val >= tab[max].read && val < tab[min].read)) {
3434 while ((max - min) > 1) {
3435 med = (max + min) / 2;
3436 if ((val >= tab[min].read && val < tab[med].read) ||
3437 (val >= tab[med].read && val < tab[min].read))
3442 res = ((val - tab[min].read) *
3443 (tab[max].real - tab[min].real) /
3444 (tab[max].read - tab[min].read)) +
3447 if (tab[min].read < tab[max].read) {
3448 if (val < tab[min].read)
3449 res = tab[min].real;
3450 else if (val >= tab[max].read)
3451 res = tab[max].real;
3453 if (val >= tab[min].read)
3454 res = tab[min].real;
3455 else if (val < tab[max].read)
3456 res = tab[max].real;
3463 static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
3465 struct stv090x_state *state = fe->demodulator_priv;
3467 s32 agc_0, agc_1, agc;
3470 reg = STV090x_READ_DEMOD(state, AGCIQIN1);
3471 agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3472 reg = STV090x_READ_DEMOD(state, AGCIQIN0);
3473 agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3474 agc = MAKEWORD16(agc_1, agc_0);
3476 str = stv090x_table_lookup(stv090x_rf_tab,
3477 ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
3478 if (agc > stv090x_rf_tab[0].read)
3480 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
3482 *strength = (str + 100) * 0xFFFF / 100;
3487 static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
3489 struct stv090x_state *state = fe->demodulator_priv;
3490 u32 reg_0, reg_1, reg, i;
3491 s32 val_0, val_1, val = 0;
3496 switch (state->delsys) {
3498 reg = STV090x_READ_DEMOD(state, DSTATUS);
3499 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3502 for (i = 0; i < 16; i++) {
3503 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
3504 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3505 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
3506 val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD);
3507 val += MAKEWORD16(val_1, val_0);
3511 last = ARRAY_SIZE(stv090x_s2cn_tab) - 1;
3512 div = stv090x_s2cn_tab[0].read -
3513 stv090x_s2cn_tab[last].read;
3514 *cnr = 0xFFFF - ((val * 0xFFFF) / div);
3520 reg = STV090x_READ_DEMOD(state, DSTATUS);
3521 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3524 for (i = 0; i < 16; i++) {
3525 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
3526 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3527 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
3528 val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD);
3529 val += MAKEWORD16(val_1, val_0);
3533 last = ARRAY_SIZE(stv090x_s1cn_tab) - 1;
3534 div = stv090x_s1cn_tab[0].read -
3535 stv090x_s1cn_tab[last].read;
3536 *cnr = 0xFFFF - ((val * 0xFFFF) / div);
3546 static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
3548 struct stv090x_state *state = fe->demodulator_priv;
3551 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3554 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3555 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3556 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3558 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3559 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3564 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3565 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3566 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3575 dprintk(FE_ERROR, 1, "I/O error");
3580 static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
3582 return DVBFE_ALGO_CUSTOM;
3585 static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
3587 struct stv090x_state *state = fe->demodulator_priv;
3588 u32 reg, idle = 0, fifo_full = 1;
3591 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3593 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 2);
3594 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3595 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3597 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3598 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3601 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3602 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3605 for (i = 0; i < cmd->msg_len; i++) {
3608 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3609 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3612 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
3615 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3616 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3617 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3622 while ((!idle) && (i < 10)) {
3623 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3624 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3631 dprintk(FE_ERROR, 1, "I/O error");
3635 static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
3637 struct stv090x_state *state = fe->demodulator_priv;
3638 u32 reg, idle = 0, fifo_full = 1;
3642 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3644 if (burst == SEC_MINI_A) {
3652 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
3653 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3654 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3656 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3657 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3660 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3661 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3665 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3666 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3669 if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
3672 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3673 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3674 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3679 while ((!idle) && (i < 10)) {
3680 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3681 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3688 dprintk(FE_ERROR, 1, "I/O error");
3692 static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
3694 struct stv090x_state *state = fe->demodulator_priv;
3695 u32 reg = 0, i = 0, rx_end = 0;
3697 while ((rx_end != 1) && (i < 10)) {
3700 reg = STV090x_READ_DEMOD(state, DISRX_ST0);
3701 rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
3705 reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
3706 for (i = 0; i < reply->msg_len; i++)
3707 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
3713 static int stv090x_sleep(struct dvb_frontend *fe)
3715 struct stv090x_state *state = fe->demodulator_priv;
3718 dprintk(FE_DEBUG, 1, "Set %s to sleep",
3719 state->device == STV0900 ? "STV0900" : "STV0903");
3721 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3722 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
3723 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3726 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3727 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
3728 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3733 dprintk(FE_ERROR, 1, "I/O error");
3737 static int stv090x_wakeup(struct dvb_frontend *fe)
3739 struct stv090x_state *state = fe->demodulator_priv;
3742 dprintk(FE_DEBUG, 1, "Wake %s from standby",
3743 state->device == STV0900 ? "STV0900" : "STV0903");
3745 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3746 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
3747 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3750 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3751 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
3752 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3757 dprintk(FE_ERROR, 1, "I/O error");
3761 static void stv090x_release(struct dvb_frontend *fe)
3763 struct stv090x_state *state = fe->demodulator_priv;
3768 static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
3772 switch (ldpc_mode) {
3775 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
3776 /* set LDPC to dual mode */
3777 if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0)
3780 state->demod_mode = STV090x_DUAL;
3782 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3783 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3784 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3786 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3787 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3790 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
3792 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
3794 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
3796 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
3798 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
3800 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
3802 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
3805 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
3807 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
3809 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
3811 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
3813 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
3815 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
3817 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
3820 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
3822 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
3827 case STV090x_SINGLE:
3828 if (stv090x_stop_modcod(state) < 0)
3830 if (stv090x_activate_modcod_single(state) < 0)
3833 if (state->demod == STV090x_DEMODULATOR_1) {
3834 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
3837 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
3841 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3842 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3843 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3845 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3846 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3849 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3850 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
3851 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3853 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
3854 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3861 dprintk(FE_ERROR, 1, "I/O error");
3865 /* return (Hz), clk in Hz*/
3866 static u32 stv090x_get_mclk(struct stv090x_state *state)
3868 const struct stv090x_config *config = state->config;
3872 div = stv090x_read_reg(state, STV090x_NCOARSE);
3873 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3874 ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
3876 return (div + 1) * config->xtal / ratio; /* kHz */
3879 static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
3881 const struct stv090x_config *config = state->config;
3882 u32 reg, div, clk_sel;
3884 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3885 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
3887 div = ((clk_sel * mclk) / config->xtal) - 1;
3889 reg = stv090x_read_reg(state, STV090x_NCOARSE);
3890 STV090x_SETFIELD(reg, M_DIV_FIELD, div);
3891 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
3894 state->mclk = stv090x_get_mclk(state);
3896 /*Set the DiseqC frequency to 22KHz */
3897 div = state->mclk / 704000;
3898 if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
3900 if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
3905 dprintk(FE_ERROR, 1, "I/O error");
3909 static int stv090x_set_tspath(struct stv090x_state *state)
3913 if (state->dev_ver >= 0x20) {
3914 switch (state->config->ts1_mode) {
3915 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3916 case STV090x_TSMODE_DVBCI:
3917 switch (state->config->ts2_mode) {
3918 case STV090x_TSMODE_SERIAL_PUNCTURED:
3919 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3921 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
3924 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3925 case STV090x_TSMODE_DVBCI:
3926 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
3928 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3929 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3930 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3932 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
3933 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3934 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
3936 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
3938 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
3944 case STV090x_TSMODE_SERIAL_PUNCTURED:
3945 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3947 switch (state->config->ts2_mode) {
3948 case STV090x_TSMODE_SERIAL_PUNCTURED:
3949 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3951 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
3955 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3956 case STV090x_TSMODE_DVBCI:
3957 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
3964 switch (state->config->ts1_mode) {
3965 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3966 case STV090x_TSMODE_DVBCI:
3967 switch (state->config->ts2_mode) {
3968 case STV090x_TSMODE_SERIAL_PUNCTURED:
3969 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3971 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
3974 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3975 case STV090x_TSMODE_DVBCI:
3976 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
3977 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3978 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3979 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3981 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3982 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
3983 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3985 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
3987 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
3993 case STV090x_TSMODE_SERIAL_PUNCTURED:
3994 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3996 switch (state->config->ts2_mode) {
3997 case STV090x_TSMODE_SERIAL_PUNCTURED:
3998 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4000 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
4003 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4004 case STV090x_TSMODE_DVBCI:
4005 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
4012 switch (state->config->ts1_mode) {
4013 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4014 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4015 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4016 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4017 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4021 case STV090x_TSMODE_DVBCI:
4022 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4023 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4024 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4025 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4029 case STV090x_TSMODE_SERIAL_PUNCTURED:
4030 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4031 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4032 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4033 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4037 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4038 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4039 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4040 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4041 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4049 switch (state->config->ts2_mode) {
4050 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4051 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4052 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4053 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4054 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4058 case STV090x_TSMODE_DVBCI:
4059 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4060 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4061 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4062 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4066 case STV090x_TSMODE_SERIAL_PUNCTURED:
4067 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4068 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4069 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4070 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4074 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4075 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4076 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4077 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4078 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4085 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4086 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4087 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4089 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4090 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4093 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4094 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4095 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4097 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4098 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4103 dprintk(FE_ERROR, 1, "I/O error");
4107 static int stv090x_init(struct dvb_frontend *fe)
4109 struct stv090x_state *state = fe->demodulator_priv;
4110 const struct stv090x_config *config = state->config;
4113 if (stv090x_wakeup(fe) < 0) {
4114 dprintk(FE_ERROR, 1, "Error waking device");
4118 if (stv090x_ldpc_mode(state, state->demod_mode) < 0)
4121 reg = STV090x_READ_DEMOD(state, TNRCFG2);
4122 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
4123 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
4125 reg = STV090x_READ_DEMOD(state, DEMOD);
4126 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
4127 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
4130 if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
4133 if (config->tuner_set_mode) {
4134 if (config->tuner_set_mode(fe, TUNER_WAKE) < 0)
4138 if (config->tuner_init) {
4139 if (config->tuner_init(fe) < 0)
4143 if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
4146 if (stv090x_set_tspath(state) < 0)
4151 dprintk(FE_ERROR, 1, "I/O error");
4155 static int stv090x_setup(struct dvb_frontend *fe)
4157 struct stv090x_state *state = fe->demodulator_priv;
4158 const struct stv090x_config *config = state->config;
4159 const struct stv090x_reg *stv090x_initval = NULL;
4160 const struct stv090x_reg *stv090x_cut20_val = NULL;
4161 unsigned long t1_size = 0, t2_size = 0;
4166 if (state->device == STV0900) {
4167 dprintk(FE_DEBUG, 1, "Initializing STV0900");
4168 stv090x_initval = stv0900_initval;
4169 t1_size = ARRAY_SIZE(stv0900_initval);
4170 stv090x_cut20_val = stv0900_cut20_val;
4171 t2_size = ARRAY_SIZE(stv0900_cut20_val);
4172 } else if (state->device == STV0903) {
4173 dprintk(FE_DEBUG, 1, "Initializing STV0903");
4174 stv090x_initval = stv0903_initval;
4175 t1_size = ARRAY_SIZE(stv0903_initval);
4176 stv090x_cut20_val = stv0903_cut20_val;
4177 t2_size = ARRAY_SIZE(stv0903_cut20_val);
4181 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Stop Demod */
4186 if (STV090x_WRITE_DEMOD(state, TNRCFG, 0x6c) < 0) /* check register ! (No Tuner Mode) */
4189 STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
4190 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0) /* repeater OFF */
4193 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
4196 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
4198 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
4203 dprintk(FE_DEBUG, 1, "Setting up initial values");
4204 for (i = 0; i < t1_size; i++) {
4205 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
4209 state->dev_ver = stv090x_read_reg(state, STV090x_MID);
4210 if (state->dev_ver >= 0x20) {
4211 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4214 /* write cut20_val*/
4215 dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
4216 for (i = 0; i < t2_size; i++) {
4217 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
4221 } else if (state->dev_ver < 0x20) {
4222 dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!",
4226 } else if (state->dev_ver > 0x30) {
4227 /* we shouldn't bail out from here */
4228 dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!",
4232 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
4234 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
4237 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
4239 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0)
4241 stv090x_get_mclk(state);
4245 dprintk(FE_ERROR, 1, "I/O error");
4249 static struct dvb_frontend_ops stv090x_ops = {
4252 .name = "STV090x Multistandard",
4254 .frequency_min = 950000,
4255 .frequency_max = 2150000,
4256 .frequency_stepsize = 0,
4257 .frequency_tolerance = 0,
4258 .symbol_rate_min = 1000000,
4259 .symbol_rate_max = 45000000,
4260 .caps = FE_CAN_INVERSION_AUTO |
4263 FE_CAN_2G_MODULATION
4266 .release = stv090x_release,
4267 .init = stv090x_init,
4269 .sleep = stv090x_sleep,
4270 .get_frontend_algo = stv090x_frontend_algo,
4272 .i2c_gate_ctrl = stv090x_i2c_gate_ctrl,
4274 .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
4275 .diseqc_send_burst = stv090x_send_diseqc_burst,
4276 .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
4277 .set_tone = stv090x_set_tone,
4279 .search = stv090x_search,
4280 .read_status = stv090x_read_status,
4281 .read_ber = stv090x_read_per,
4282 .read_signal_strength = stv090x_read_signal_strength,
4283 .read_snr = stv090x_read_cnr
4287 struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
4288 struct i2c_adapter *i2c,
4289 enum stv090x_demodulator demod)
4291 struct stv090x_state *state = NULL;
4293 state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
4297 state->verbose = &verbose;
4298 state->config = config;
4300 state->frontend.ops = stv090x_ops;
4301 state->frontend.demodulator_priv = state;
4302 state->demod = demod;
4303 state->demod_mode = config->demod_mode; /* Single or Dual mode */
4304 state->device = config->device;
4305 state->rolloff = STV090x_RO_35; /* default */
4307 if (state->demod == STV090x_DEMODULATOR_0)
4308 mutex_init(&demod_lock);
4310 if (stv090x_sleep(&state->frontend) < 0) {
4311 dprintk(FE_ERROR, 1, "Error putting device to sleep");
4315 if (stv090x_setup(&state->frontend) < 0) {
4316 dprintk(FE_ERROR, 1, "Error setting up device");
4319 if (stv090x_wakeup(&state->frontend) < 0) {
4320 dprintk(FE_ERROR, 1, "Error waking device");
4324 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x\n",
4325 state->device == STV0900 ? "STV0900" : "STV0903",
4329 return &state->frontend;
4335 EXPORT_SYMBOL(stv090x_attach);
4336 MODULE_PARM_DESC(verbose, "Set Verbosity level");
4337 MODULE_AUTHOR("Manu Abraham");
4338 MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
4339 MODULE_LICENSE("GPL");