SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16
  17 #include "kvm_svm.h"
  18 #include "x86_emulate.h"
  19 #include "irq.h"
  20
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 #include <linux/vmalloc.h>
  24 #include <linux/highmem.h>
  25 #include <linux/profile.h>
  26 #include <linux/sched.h>
  27
  28 #include <asm/desc.h>
  29
  30 MODULE_AUTHOR("Qumranet");
  31 MODULE_LICENSE("GPL");
  32
  33 #define IOPM_ALLOC_ORDER 2
  34 #define MSRPM_ALLOC_ORDER 1
  35
  36 #define DB_VECTOR 1
  37 #define UD_VECTOR 6
  38 #define GP_VECTOR 13
  39
  40 #define DR7_GD_MASK (1 << 13)
  41 #define DR6_BD_MASK (1 << 13)
  42
  43 #define SEG_TYPE_LDT 2
  44 #define SEG_TYPE_BUSY_TSS16 3
  45
  46 #define KVM_EFER_LMA (1 << 10)
  47 #define KVM_EFER_LME (1 << 8)
  48
  49 #define SVM_FEATURE_NPT  (1 << 0)
  50 #define SVM_FEATURE_LBRV (1 << 1)
  51 #define SVM_DEATURE_SVML (1 << 2)
  52
  53 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  54 {
  55         return container_of(vcpu, struct vcpu_svm, vcpu);
  56 }
  57
  58 unsigned long iopm_base;
  59 unsigned long msrpm_base;
  60
  61 struct kvm_ldttss_desc {
  62         u16 limit0;
  63         u16 base0;
  64         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  65         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  66         u32 base3;
  67         u32 zero1;
  68 } __attribute__((packed));
  69
  70 struct svm_cpu_data {
  71         int cpu;
  72
  73         u64 asid_generation;
  74         u32 max_asid;
  75         u32 next_asid;
  76         struct kvm_ldttss_desc *tss_desc;
  77
  78         struct page *save_area;
  79 };
  80
  81 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  82 static uint32_t svm_features;
  83
  84 struct svm_init_data {
  85         int cpu;
  86         int r;
  87 };
  88
  89 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
  90
  91 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
  92 #define MSRS_RANGE_SIZE 2048
  93 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
  94
  95 #define MAX_INST_SIZE 15
  96
  97 static inline u32 svm_has(u32 feat)
  98 {
  99         return svm_features & feat;
 100 }
 101
 102 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 103 {
 104         int word_index = __ffs(vcpu->irq_summary);
 105         int bit_index = __ffs(vcpu->irq_pending[word_index]);
 106         int irq = word_index * BITS_PER_LONG + bit_index;
 107
 108         clear_bit(bit_index, &vcpu->irq_pending[word_index]);
 109         if (!vcpu->irq_pending[word_index])
 110                 clear_bit(word_index, &vcpu->irq_summary);
 111         return irq;
 112 }
 113
 114 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 115 {
 116         set_bit(irq, vcpu->irq_pending);
 117         set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
 118 }
 119
 120 static inline void clgi(void)
 121 {
 122         asm volatile (SVM_CLGI);
 123 }
 124
 125 static inline void stgi(void)
 126 {
 127         asm volatile (SVM_STGI);
 128 }
 129
 130 static inline void invlpga(unsigned long addr, u32 asid)
 131 {
 132         asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
 133 }
 134
 135 static inline unsigned long kvm_read_cr2(void)
 136 {
 137         unsigned long cr2;
 138
 139         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 140         return cr2;
 141 }
 142
 143 static inline void kvm_write_cr2(unsigned long val)
 144 {
 145         asm volatile ("mov %0, %%cr2" :: "r" (val));
 146 }
 147
 148 static inline unsigned long read_dr6(void)
 149 {
 150         unsigned long dr6;
 151
 152         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 153         return dr6;
 154 }
 155
 156 static inline void write_dr6(unsigned long val)
 157 {
 158         asm volatile ("mov %0, %%dr6" :: "r" (val));
 159 }
 160
 161 static inline unsigned long read_dr7(void)
 162 {
 163         unsigned long dr7;
 164
 165         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 166         return dr7;
 167 }
 168
 169 static inline void write_dr7(unsigned long val)
 170 {
 171         asm volatile ("mov %0, %%dr7" :: "r" (val));
 172 }
 173
 174 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 175 {
 176         to_svm(vcpu)->asid_generation--;
 177 }
 178
 179 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 180 {
 181         force_new_asid(vcpu);
 182 }
 183
 184 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 185 {
 186         if (!(efer & KVM_EFER_LMA))
 187                 efer &= ~KVM_EFER_LME;
 188
 189         to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
 190         vcpu->shadow_efer = efer;
 191 }
 192
 193 static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
 194 {
 195         struct vcpu_svm *svm = to_svm(vcpu);
 196
 197         svm->vmcb->control.event_inj =          SVM_EVTINJ_VALID |
 198                                                 SVM_EVTINJ_VALID_ERR |
 199                                                 SVM_EVTINJ_TYPE_EXEPT |
 200                                                 GP_VECTOR;
 201         svm->vmcb->control.event_inj_err = error_code;
 202 }
 203
 204 static void inject_ud(struct kvm_vcpu *vcpu)
 205 {
 206         to_svm(vcpu)->vmcb->control.event_inj = SVM_EVTINJ_VALID |
 207                                                 SVM_EVTINJ_TYPE_EXEPT |
 208                                                 UD_VECTOR;
 209 }
 210
 211 static int is_page_fault(uint32_t info)
 212 {
 213         info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 214         return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT);
 215 }
 216
 217 static int is_external_interrupt(u32 info)
 218 {
 219         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 220         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 221 }
 222
 223 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 224 {
 225         struct vcpu_svm *svm = to_svm(vcpu);
 226
 227         if (!svm->next_rip) {
 228                 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
 229                 return;
 230         }
 231         if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) {
 232                 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
 233                        __FUNCTION__,
 234                        svm->vmcb->save.rip,
 235                        svm->next_rip);
 236         }
 237
 238         vcpu->rip = svm->vmcb->save.rip = svm->next_rip;
 239         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 240
 241         vcpu->interrupt_window_open = 1;
 242 }
 243
 244 static int has_svm(void)
 245 {
 246         uint32_t eax, ebx, ecx, edx;
 247
 248         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 249                 printk(KERN_INFO "has_svm: not amd\n");
 250                 return 0;
 251         }
 252
 253         cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
 254         if (eax < SVM_CPUID_FUNC) {
 255                 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
 256                 return 0;
 257         }
 258
 259         cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 260         if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
 261                 printk(KERN_DEBUG "has_svm: svm not available\n");
 262                 return 0;
 263         }
 264         return 1;
 265 }
 266
 267 static void svm_hardware_disable(void *garbage)
 268 {
 269         struct svm_cpu_data *svm_data
 270                 = per_cpu(svm_data, raw_smp_processor_id());
 271
 272         if (svm_data) {
 273                 uint64_t efer;
 274
 275                 wrmsrl(MSR_VM_HSAVE_PA, 0);
 276                 rdmsrl(MSR_EFER, efer);
 277                 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
 278                 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 279                 __free_page(svm_data->save_area);
 280                 kfree(svm_data);
 281         }
 282 }
 283
 284 static void svm_hardware_enable(void *garbage)
 285 {
 286
 287         struct svm_cpu_data *svm_data;
 288         uint64_t efer;
 289 #ifdef CONFIG_X86_64
 290         struct desc_ptr gdt_descr;
 291 #else
 292         struct Xgt_desc_struct gdt_descr;
 293 #endif
 294         struct desc_struct *gdt;
 295         int me = raw_smp_processor_id();
 296
 297         if (!has_svm()) {
 298                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 299                 return;
 300         }
 301         svm_data = per_cpu(svm_data, me);
 302
 303         if (!svm_data) {
 304                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 305                        me);
 306                 return;
 307         }
 308
 309         svm_data->asid_generation = 1;
 310         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 311         svm_data->next_asid = svm_data->max_asid + 1;
 312         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 313
 314         asm volatile ( "sgdt %0" : "=m"(gdt_descr) );
 315         gdt = (struct desc_struct *)gdt_descr.address;
 316         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 317
 318         rdmsrl(MSR_EFER, efer);
 319         wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
 320
 321         wrmsrl(MSR_VM_HSAVE_PA,
 322                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 323 }
 324
 325 static int svm_cpu_init(int cpu)
 326 {
 327         struct svm_cpu_data *svm_data;
 328         int r;
 329
 330         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 331         if (!svm_data)
 332                 return -ENOMEM;
 333         svm_data->cpu = cpu;
 334         svm_data->save_area = alloc_page(GFP_KERNEL);
 335         r = -ENOMEM;
 336         if (!svm_data->save_area)
 337                 goto err_1;
 338
 339         per_cpu(svm_data, cpu) = svm_data;
 340
 341         return 0;
 342
 343 err_1:
 344         kfree(svm_data);
 345         return r;
 346
 347 }
 348
 349 static void set_msr_interception(u32 *msrpm, unsigned msr,
 350                                  int read, int write)
 351 {
 352         int i;
 353
 354         for (i = 0; i < NUM_MSR_MAPS; i++) {
 355                 if (msr >= msrpm_ranges[i] &&
 356                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 357                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 358                                           msrpm_ranges[i]) * 2;
 359
 360                         u32 *base = msrpm + (msr_offset / 32);
 361                         u32 msr_shift = msr_offset % 32;
 362                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 363                         *base = (*base & ~(0x3 << msr_shift)) |
 364                                 (mask << msr_shift);
 365                         return;
 366                 }
 367         }
 368         BUG();
 369 }
 370
 371 static __init int svm_hardware_setup(void)
 372 {
 373         int cpu;
 374         struct page *iopm_pages;
 375         struct page *msrpm_pages;
 376         void *iopm_va, *msrpm_va;
 377         int r;
 378
 379         kvm_emulator_want_group7_invlpg();
 380
 381         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 382
 383         if (!iopm_pages)
 384                 return -ENOMEM;
 385
 386         iopm_va = page_address(iopm_pages);
 387         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 388         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 389         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 390
 391
 392         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 393
 394         r = -ENOMEM;
 395         if (!msrpm_pages)
 396                 goto err_1;
 397
 398         msrpm_va = page_address(msrpm_pages);
 399         memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 400         msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
 401
 402 #ifdef CONFIG_X86_64
 403         set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
 404         set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
 405         set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
 406         set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
 407         set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
 408         set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
 409 #endif
 410         set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
 411         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
 412         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
 413         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
 414
 415         for_each_online_cpu(cpu) {
 416                 r = svm_cpu_init(cpu);
 417                 if (r)
 418                         goto err_2;
 419         }
 420         return 0;
 421
 422 err_2:
 423         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 424         msrpm_base = 0;
 425 err_1:
 426         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 427         iopm_base = 0;
 428         return r;
 429 }
 430
 431 static __exit void svm_hardware_unsetup(void)
 432 {
 433         __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
 434         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 435         iopm_base = msrpm_base = 0;
 436 }
 437
 438 static void init_seg(struct vmcb_seg *seg)
 439 {
 440         seg->selector = 0;
 441         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 442                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 443         seg->limit = 0xffff;
 444         seg->base = 0;
 445 }
 446
 447 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 448 {
 449         seg->selector = 0;
 450         seg->attrib = SVM_SELECTOR_P_MASK | type;
 451         seg->limit = 0xffff;
 452         seg->base = 0;
 453 }
 454
 455 static void init_vmcb(struct vmcb *vmcb)
 456 {
 457         struct vmcb_control_area *control = &vmcb->control;
 458         struct vmcb_save_area *save = &vmcb->save;
 459
 460         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 461                                         INTERCEPT_CR3_MASK |
 462                                         INTERCEPT_CR4_MASK;
 463
 464         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 465                                         INTERCEPT_CR3_MASK |
 466                                         INTERCEPT_CR4_MASK;
 467
 468         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 469                                         INTERCEPT_DR1_MASK |
 470                                         INTERCEPT_DR2_MASK |
 471                                         INTERCEPT_DR3_MASK;
 472
 473         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 474                                         INTERCEPT_DR1_MASK |
 475                                         INTERCEPT_DR2_MASK |
 476                                         INTERCEPT_DR3_MASK |
 477                                         INTERCEPT_DR5_MASK |
 478                                         INTERCEPT_DR7_MASK;
 479
 480         control->intercept_exceptions = 1 << PF_VECTOR;
 481
 482
 483         control->intercept =    (1ULL << INTERCEPT_INTR) |
 484                                 (1ULL << INTERCEPT_NMI) |
 485                                 (1ULL << INTERCEPT_SMI) |
 486                 /*
 487                  * selective cr0 intercept bug?
 488                  *      0:   0f 22 d8                mov    %eax,%cr3
 489                  *      3:   0f 20 c0                mov    %cr0,%eax
 490                  *      6:   0d 00 00 00 80          or     $0x80000000,%eax
 491                  *      b:   0f 22 c0                mov    %eax,%cr0
 492                  * set cr3 ->interception
 493                  * get cr0 ->interception
 494                  * set cr0 -> no interception
 495                  */
 496                 /*              (1ULL << INTERCEPT_SELECTIVE_CR0) | */
 497                                 (1ULL << INTERCEPT_CPUID) |
 498                                 (1ULL << INTERCEPT_HLT) |
 499                                 (1ULL << INTERCEPT_INVLPGA) |
 500                                 (1ULL << INTERCEPT_IOIO_PROT) |
 501                                 (1ULL << INTERCEPT_MSR_PROT) |
 502                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 503                                 (1ULL << INTERCEPT_SHUTDOWN) |
 504                                 (1ULL << INTERCEPT_VMRUN) |
 505                                 (1ULL << INTERCEPT_VMMCALL) |
 506                                 (1ULL << INTERCEPT_VMLOAD) |
 507                                 (1ULL << INTERCEPT_VMSAVE) |
 508                                 (1ULL << INTERCEPT_STGI) |
 509                                 (1ULL << INTERCEPT_CLGI) |
 510                                 (1ULL << INTERCEPT_SKINIT) |
 511                                 (1ULL << INTERCEPT_MONITOR) |
 512                                 (1ULL << INTERCEPT_MWAIT);
 513
 514         control->iopm_base_pa = iopm_base;
 515         control->msrpm_base_pa = msrpm_base;
 516         control->tsc_offset = 0;
 517         control->int_ctl = V_INTR_MASKING_MASK;
 518
 519         init_seg(&save->es);
 520         init_seg(&save->ss);
 521         init_seg(&save->ds);
 522         init_seg(&save->fs);
 523         init_seg(&save->gs);
 524
 525         save->cs.selector = 0xf000;
 526         /* Executable/Readable Code Segment */
 527         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 528                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 529         save->cs.limit = 0xffff;
 530         /*
 531          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 532          * be consistent with it.
 533          *
 534          * Replace when we have real mode working for vmx.
 535          */
 536         save->cs.base = 0xf0000;
 537
 538         save->gdtr.limit = 0xffff;
 539         save->idtr.limit = 0xffff;
 540
 541         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 542         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 543
 544         save->efer = MSR_EFER_SVME_MASK;
 545
 546         save->dr6 = 0xffff0ff0;
 547         save->dr7 = 0x400;
 548         save->rflags = 2;
 549         save->rip = 0x0000fff0;
 550
 551         /*
 552          * cr0 val on cpu init should be 0x60000010, we enable cpu
 553          * cache by default. the orderly way is to enable cache in bios.
 554          */
 555         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 556         save->cr4 = X86_CR4_PAE;
 557         /* rdx = ?? */
 558 }
 559
 560 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 561 {
 562         struct vcpu_svm *svm;
 563         struct page *page;
 564         int err;
 565
 566         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 567         if (!svm) {
 568                 err = -ENOMEM;
 569                 goto out;
 570         }
 571
 572         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 573         if (err)
 574                 goto free_svm;
 575
 576         if (irqchip_in_kernel(kvm)) {
 577                 err = kvm_create_lapic(&svm->vcpu);
 578                 if (err < 0)
 579                         goto free_svm;
 580         }
 581
 582         page = alloc_page(GFP_KERNEL);
 583         if (!page) {
 584                 err = -ENOMEM;
 585                 goto uninit;
 586         }
 587
 588         svm->vmcb = page_address(page);
 589         clear_page(svm->vmcb);
 590         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 591         svm->asid_generation = 0;
 592         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 593         init_vmcb(svm->vmcb);
 594
 595         fx_init(&svm->vcpu);
 596         svm->vcpu.fpu_active = 1;
 597         svm->vcpu.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 598         if (svm->vcpu.vcpu_id == 0)
 599                 svm->vcpu.apic_base |= MSR_IA32_APICBASE_BSP;
 600
 601         return &svm->vcpu;
 602
 603 uninit:
 604         kvm_vcpu_uninit(&svm->vcpu);
 605 free_svm:
 606         kmem_cache_free(kvm_vcpu_cache, svm);
 607 out:
 608         return ERR_PTR(err);
 609 }
 610
 611 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 612 {
 613         struct vcpu_svm *svm = to_svm(vcpu);
 614
 615         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 616         kvm_vcpu_uninit(vcpu);
 617         kmem_cache_free(kvm_vcpu_cache, svm);
 618 }
 619
 620 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 621 {
 622         struct vcpu_svm *svm = to_svm(vcpu);
 623         int i;
 624
 625         if (unlikely(cpu != vcpu->cpu)) {
 626                 u64 tsc_this, delta;
 627
 628                 /*
 629                  * Make sure that the guest sees a monotonically
 630                  * increasing TSC.
 631                  */
 632                 rdtscll(tsc_this);
 633                 delta = vcpu->host_tsc - tsc_this;
 634                 svm->vmcb->control.tsc_offset += delta;
 635                 vcpu->cpu = cpu;
 636         }
 637
 638         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 639                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 640 }
 641
 642 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 643 {
 644         struct vcpu_svm *svm = to_svm(vcpu);
 645         int i;
 646
 647         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 648                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 649
 650         rdtscll(vcpu->host_tsc);
 651 }
 652
 653 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
 654 {
 655 }
 656
 657 static void svm_cache_regs(struct kvm_vcpu *vcpu)
 658 {
 659         struct vcpu_svm *svm = to_svm(vcpu);
 660
 661         vcpu->regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
 662         vcpu->regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
 663         vcpu->rip = svm->vmcb->save.rip;
 664 }
 665
 666 static void svm_decache_regs(struct kvm_vcpu *vcpu)
 667 {
 668         struct vcpu_svm *svm = to_svm(vcpu);
 669         svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX];
 670         svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP];
 671         svm->vmcb->save.rip = vcpu->rip;
 672 }
 673
 674 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 675 {
 676         return to_svm(vcpu)->vmcb->save.rflags;
 677 }
 678
 679 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 680 {
 681         to_svm(vcpu)->vmcb->save.rflags = rflags;
 682 }
 683
 684 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 685 {
 686         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 687
 688         switch (seg) {
 689         case VCPU_SREG_CS: return &save->cs;
 690         case VCPU_SREG_DS: return &save->ds;
 691         case VCPU_SREG_ES: return &save->es;
 692         case VCPU_SREG_FS: return &save->fs;
 693         case VCPU_SREG_GS: return &save->gs;
 694         case VCPU_SREG_SS: return &save->ss;
 695         case VCPU_SREG_TR: return &save->tr;
 696         case VCPU_SREG_LDTR: return &save->ldtr;
 697         }
 698         BUG();
 699         return NULL;
 700 }
 701
 702 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 703 {
 704         struct vmcb_seg *s = svm_seg(vcpu, seg);
 705
 706         return s->base;
 707 }
 708
 709 static void svm_get_segment(struct kvm_vcpu *vcpu,
 710                             struct kvm_segment *var, int seg)
 711 {
 712         struct vmcb_seg *s = svm_seg(vcpu, seg);
 713
 714         var->base = s->base;
 715         var->limit = s->limit;
 716         var->selector = s->selector;
 717         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 718         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 719         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 720         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 721         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 722         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 723         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 724         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 725         var->unusable = !var->present;
 726 }
 727
 728 static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
 729 {
 730         struct vmcb_seg *s = svm_seg(vcpu, VCPU_SREG_CS);
 731
 732         *db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 733         *l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 734 }
 735
 736 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 737 {
 738         struct vcpu_svm *svm = to_svm(vcpu);
 739
 740         dt->limit = svm->vmcb->save.idtr.limit;
 741         dt->base = svm->vmcb->save.idtr.base;
 742 }
 743
 744 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 745 {
 746         struct vcpu_svm *svm = to_svm(vcpu);
 747
 748         svm->vmcb->save.idtr.limit = dt->limit;
 749         svm->vmcb->save.idtr.base = dt->base ;
 750 }
 751
 752 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 753 {
 754         struct vcpu_svm *svm = to_svm(vcpu);
 755
 756         dt->limit = svm->vmcb->save.gdtr.limit;
 757         dt->base = svm->vmcb->save.gdtr.base;
 758 }
 759
 760 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 761 {
 762         struct vcpu_svm *svm = to_svm(vcpu);
 763
 764         svm->vmcb->save.gdtr.limit = dt->limit;
 765         svm->vmcb->save.gdtr.base = dt->base ;
 766 }
 767
 768 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 769 {
 770 }
 771
 772 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 773 {
 774         struct vcpu_svm *svm = to_svm(vcpu);
 775
 776 #ifdef CONFIG_X86_64
 777         if (vcpu->shadow_efer & KVM_EFER_LME) {
 778                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 779                         vcpu->shadow_efer |= KVM_EFER_LMA;
 780                         svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME;
 781                 }
 782
 783                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG) ) {
 784                         vcpu->shadow_efer &= ~KVM_EFER_LMA;
 785                         svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME);
 786                 }
 787         }
 788 #endif
 789         if ((vcpu->cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 790                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 791                 vcpu->fpu_active = 1;
 792         }
 793
 794         vcpu->cr0 = cr0;
 795         cr0 |= X86_CR0_PG | X86_CR0_WP;
 796         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 797         svm->vmcb->save.cr0 = cr0;
 798 }
 799
 800 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 801 {
 802        vcpu->cr4 = cr4;
 803        to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE;
 804 }
 805
 806 static void svm_set_segment(struct kvm_vcpu *vcpu,
 807                             struct kvm_segment *var, int seg)
 808 {
 809         struct vcpu_svm *svm = to_svm(vcpu);
 810         struct vmcb_seg *s = svm_seg(vcpu, seg);
 811
 812         s->base = var->base;
 813         s->limit = var->limit;
 814         s->selector = var->selector;
 815         if (var->unusable)
 816                 s->attrib = 0;
 817         else {
 818                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 819                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 820                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 821                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 822                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 823                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 824                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 825                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 826         }
 827         if (seg == VCPU_SREG_CS)
 828                 svm->vmcb->save.cpl
 829                         = (svm->vmcb->save.cs.attrib
 830                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 831
 832 }
 833
 834 /* FIXME:
 835
 836         svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK;
 837         svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
 838
 839 */
 840
 841 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 842 {
 843         return -EOPNOTSUPP;
 844 }
 845
 846 static int svm_get_irq(struct kvm_vcpu *vcpu)
 847 {
 848         struct vcpu_svm *svm = to_svm(vcpu);
 849         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 850
 851         if (is_external_interrupt(exit_int_info))
 852                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 853         return -1;
 854 }
 855
 856 static void load_host_msrs(struct kvm_vcpu *vcpu)
 857 {
 858 #ifdef CONFIG_X86_64
 859         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 860 #endif
 861 }
 862
 863 static void save_host_msrs(struct kvm_vcpu *vcpu)
 864 {
 865 #ifdef CONFIG_X86_64
 866         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 867 #endif
 868 }
 869
 870 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 871 {
 872         if (svm_data->next_asid > svm_data->max_asid) {
 873                 ++svm_data->asid_generation;
 874                 svm_data->next_asid = 1;
 875                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 876         }
 877
 878         svm->vcpu.cpu = svm_data->cpu;
 879         svm->asid_generation = svm_data->asid_generation;
 880         svm->vmcb->control.asid = svm_data->next_asid++;
 881 }
 882
 883 static void svm_invlpg(struct kvm_vcpu *vcpu, gva_t address)
 884 {
 885         invlpga(address, to_svm(vcpu)->vmcb->control.asid); // is needed?
 886 }
 887
 888 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 889 {
 890         return to_svm(vcpu)->db_regs[dr];
 891 }
 892
 893 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 894                        int *exception)
 895 {
 896         struct vcpu_svm *svm = to_svm(vcpu);
 897
 898         *exception = 0;
 899
 900         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 901                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 902                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 903                 *exception = DB_VECTOR;
 904                 return;
 905         }
 906
 907         switch (dr) {
 908         case 0 ... 3:
 909                 svm->db_regs[dr] = value;
 910                 return;
 911         case 4 ... 5:
 912                 if (vcpu->cr4 & X86_CR4_DE) {
 913                         *exception = UD_VECTOR;
 914                         return;
 915                 }
 916         case 7: {
 917                 if (value & ~((1ULL << 32) - 1)) {
 918                         *exception = GP_VECTOR;
 919                         return;
 920                 }
 921                 svm->vmcb->save.dr7 = value;
 922                 return;
 923         }
 924         default:
 925                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
 926                        __FUNCTION__, dr);
 927                 *exception = UD_VECTOR;
 928                 return;
 929         }
 930 }
 931
 932 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 933 {
 934         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 935         struct kvm *kvm = svm->vcpu.kvm;
 936         u64 fault_address;
 937         u32 error_code;
 938         enum emulation_result er;
 939         int r;
 940
 941         if (!irqchip_in_kernel(kvm) &&
 942                 is_external_interrupt(exit_int_info))
 943                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
 944
 945         mutex_lock(&kvm->lock);
 946
 947         fault_address  = svm->vmcb->control.exit_info_2;
 948         error_code = svm->vmcb->control.exit_info_1;
 949         r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
 950         if (r < 0) {
 951                 mutex_unlock(&kvm->lock);
 952                 return r;
 953         }
 954         if (!r) {
 955                 mutex_unlock(&kvm->lock);
 956                 return 1;
 957         }
 958         er = emulate_instruction(&svm->vcpu, kvm_run, fault_address,
 959                                  error_code);
 960         mutex_unlock(&kvm->lock);
 961
 962         switch (er) {
 963         case EMULATE_DONE:
 964                 return 1;
 965         case EMULATE_DO_MMIO:
 966                 ++svm->vcpu.stat.mmio_exits;
 967                 return 0;
 968         case EMULATE_FAIL:
 969                 vcpu_printf(&svm->vcpu, "%s: emulate fail\n", __FUNCTION__);
 970                 break;
 971         default:
 972                 BUG();
 973         }
 974
 975         kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
 976         return 0;
 977 }
 978
 979 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 980 {
 981         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 982         if (!(svm->vcpu.cr0 & X86_CR0_TS))
 983                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
 984         svm->vcpu.fpu_active = 1;
 985
 986         return 1;
 987 }
 988
 989 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 990 {
 991         /*
 992          * VMCB is undefined after a SHUTDOWN intercept
 993          * so reinitialize it.
 994          */
 995         clear_page(svm->vmcb);
 996         init_vmcb(svm->vmcb);
 997
 998         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
 999         return 0;
1000 }
1001
1002 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1003 {
1004         u32 io_info = svm->vmcb->control.exit_info_1; //address size bug?
1005         int size, down, in, string, rep;
1006         unsigned port;
1007
1008         ++svm->vcpu.stat.io_exits;
1009
1010         svm->next_rip = svm->vmcb->control.exit_info_2;
1011
1012         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1013
1014         if (string) {
1015                 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0) == EMULATE_DO_MMIO)
1016                         return 0;
1017                 return 1;
1018         }
1019
1020         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1021         port = io_info >> 16;
1022         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1023         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1024         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1025
1026         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1027 }
1028
1029 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1030 {
1031         return 1;
1032 }
1033
1034 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1035 {
1036         svm->next_rip = svm->vmcb->save.rip + 1;
1037         skip_emulated_instruction(&svm->vcpu);
1038         return kvm_emulate_halt(&svm->vcpu);
1039 }
1040
1041 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1042 {
1043         svm->next_rip = svm->vmcb->save.rip + 3;
1044         skip_emulated_instruction(&svm->vcpu);
1045         return kvm_hypercall(&svm->vcpu, kvm_run);
1046 }
1047
1048 static int invalid_op_interception(struct vcpu_svm *svm,
1049                                    struct kvm_run *kvm_run)
1050 {
1051         inject_ud(&svm->vcpu);
1052         return 1;
1053 }
1054
1055 static int task_switch_interception(struct vcpu_svm *svm,
1056                                     struct kvm_run *kvm_run)
1057 {
1058         pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__);
1059         kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1060         return 0;
1061 }
1062
1063 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1064 {
1065         svm->next_rip = svm->vmcb->save.rip + 2;
1066         kvm_emulate_cpuid(&svm->vcpu);
1067         return 1;
1068 }
1069
1070 static int emulate_on_interception(struct vcpu_svm *svm,
1071                                    struct kvm_run *kvm_run)
1072 {
1073         if (emulate_instruction(&svm->vcpu, NULL, 0, 0) != EMULATE_DONE)
1074                 pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__);
1075         return 1;
1076 }
1077
1078 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1079 {
1080         struct vcpu_svm *svm = to_svm(vcpu);
1081
1082         switch (ecx) {
1083         case MSR_IA32_TIME_STAMP_COUNTER: {
1084                 u64 tsc;
1085
1086                 rdtscll(tsc);
1087                 *data = svm->vmcb->control.tsc_offset + tsc;
1088                 break;
1089         }
1090         case MSR_K6_STAR:
1091                 *data = svm->vmcb->save.star;
1092                 break;
1093 #ifdef CONFIG_X86_64
1094         case MSR_LSTAR:
1095                 *data = svm->vmcb->save.lstar;
1096                 break;
1097         case MSR_CSTAR:
1098                 *data = svm->vmcb->save.cstar;
1099                 break;
1100         case MSR_KERNEL_GS_BASE:
1101                 *data = svm->vmcb->save.kernel_gs_base;
1102                 break;
1103         case MSR_SYSCALL_MASK:
1104                 *data = svm->vmcb->save.sfmask;
1105                 break;
1106 #endif
1107         case MSR_IA32_SYSENTER_CS:
1108                 *data = svm->vmcb->save.sysenter_cs;
1109                 break;
1110         case MSR_IA32_SYSENTER_EIP:
1111                 *data = svm->vmcb->save.sysenter_eip;
1112                 break;
1113         case MSR_IA32_SYSENTER_ESP:
1114                 *data = svm->vmcb->save.sysenter_esp;
1115                 break;
1116         default:
1117                 return kvm_get_msr_common(vcpu, ecx, data);
1118         }
1119         return 0;
1120 }
1121
1122 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1123 {
1124         u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX];
1125         u64 data;
1126
1127         if (svm_get_msr(&svm->vcpu, ecx, &data))
1128                 svm_inject_gp(&svm->vcpu, 0);
1129         else {
1130                 svm->vmcb->save.rax = data & 0xffffffff;
1131                 svm->vcpu.regs[VCPU_REGS_RDX] = data >> 32;
1132                 svm->next_rip = svm->vmcb->save.rip + 2;
1133                 skip_emulated_instruction(&svm->vcpu);
1134         }
1135         return 1;
1136 }
1137
1138 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1139 {
1140         struct vcpu_svm *svm = to_svm(vcpu);
1141
1142         switch (ecx) {
1143         case MSR_IA32_TIME_STAMP_COUNTER: {
1144                 u64 tsc;
1145
1146                 rdtscll(tsc);
1147                 svm->vmcb->control.tsc_offset = data - tsc;
1148                 break;
1149         }
1150         case MSR_K6_STAR:
1151                 svm->vmcb->save.star = data;
1152                 break;
1153 #ifdef CONFIG_X86_64
1154         case MSR_LSTAR:
1155                 svm->vmcb->save.lstar = data;
1156                 break;
1157         case MSR_CSTAR:
1158                 svm->vmcb->save.cstar = data;
1159                 break;
1160         case MSR_KERNEL_GS_BASE:
1161                 svm->vmcb->save.kernel_gs_base = data;
1162                 break;
1163         case MSR_SYSCALL_MASK:
1164                 svm->vmcb->save.sfmask = data;
1165                 break;
1166 #endif
1167         case MSR_IA32_SYSENTER_CS:
1168                 svm->vmcb->save.sysenter_cs = data;
1169                 break;
1170         case MSR_IA32_SYSENTER_EIP:
1171                 svm->vmcb->save.sysenter_eip = data;
1172                 break;
1173         case MSR_IA32_SYSENTER_ESP:
1174                 svm->vmcb->save.sysenter_esp = data;
1175                 break;
1176         default:
1177                 return kvm_set_msr_common(vcpu, ecx, data);
1178         }
1179         return 0;
1180 }
1181
1182 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1183 {
1184         u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX];
1185         u64 data = (svm->vmcb->save.rax & -1u)
1186                 | ((u64)(svm->vcpu.regs[VCPU_REGS_RDX] & -1u) << 32);
1187         svm->next_rip = svm->vmcb->save.rip + 2;
1188         if (svm_set_msr(&svm->vcpu, ecx, data))
1189                 svm_inject_gp(&svm->vcpu, 0);
1190         else
1191                 skip_emulated_instruction(&svm->vcpu);
1192         return 1;
1193 }
1194
1195 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1196 {
1197         if (svm->vmcb->control.exit_info_1)
1198                 return wrmsr_interception(svm, kvm_run);
1199         else
1200                 return rdmsr_interception(svm, kvm_run);
1201 }
1202
1203 static int interrupt_window_interception(struct vcpu_svm *svm,
1204                                    struct kvm_run *kvm_run)
1205 {
1206         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1207         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1208         /*
1209          * If the user space waits to inject interrupts, exit as soon as
1210          * possible
1211          */
1212         if (kvm_run->request_interrupt_window &&
1213             !svm->vcpu.irq_summary) {
1214                 ++svm->vcpu.stat.irq_window_exits;
1215                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1216                 return 0;
1217         }
1218
1219         return 1;
1220 }
1221
1222 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1223                                       struct kvm_run *kvm_run) = {
1224         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1225         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1226         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1227         /* for now: */
1228         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1229         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1230         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1231         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1232         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1233         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1234         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1235         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1236         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1237         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1238         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1239         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1240         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1241         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1242         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1243         [SVM_EXIT_INTR]                         = nop_on_interception,
1244         [SVM_EXIT_NMI]                          = nop_on_interception,
1245         [SVM_EXIT_SMI]                          = nop_on_interception,
1246         [SVM_EXIT_INIT]                         = nop_on_interception,
1247         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1248         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1249         [SVM_EXIT_CPUID]                        = cpuid_interception,
1250         [SVM_EXIT_HLT]                          = halt_interception,
1251         [SVM_EXIT_INVLPG]                       = emulate_on_interception,
1252         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1253         [SVM_EXIT_IOIO]                         = io_interception,
1254         [SVM_EXIT_MSR]                          = msr_interception,
1255         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1256         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1257         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1258         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1259         [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1260         [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1261         [SVM_EXIT_STGI]                         = invalid_op_interception,
1262         [SVM_EXIT_CLGI]                         = invalid_op_interception,
1263         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1264         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1265         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1266 };
1267
1268
1269 static int handle_exit(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1270 {
1271         u32 exit_code = svm->vmcb->control.exit_code;
1272
1273         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1274             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
1275                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1276                        "exit_code 0x%x\n",
1277                        __FUNCTION__, svm->vmcb->control.exit_int_info,
1278                        exit_code);
1279
1280         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1281             || svm_exit_handlers[exit_code] == 0) {
1282                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1283                 kvm_run->hw.hardware_exit_reason = exit_code;
1284                 return 0;
1285         }
1286
1287         return svm_exit_handlers[exit_code](svm, kvm_run);
1288 }
1289
1290 static void reload_tss(struct kvm_vcpu *vcpu)
1291 {
1292         int cpu = raw_smp_processor_id();
1293
1294         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1295         svm_data->tss_desc->type = 9; //available 32/64-bit TSS
1296         load_TR_desc();
1297 }
1298
1299 static void pre_svm_run(struct vcpu_svm *svm)
1300 {
1301         int cpu = raw_smp_processor_id();
1302
1303         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1304
1305         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1306         if (svm->vcpu.cpu != cpu ||
1307             svm->asid_generation != svm_data->asid_generation)
1308                 new_asid(svm, svm_data);
1309 }
1310
1311
1312 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1313 {
1314         struct vmcb_control_area *control;
1315
1316         control = &svm->vmcb->control;
1317         control->int_vector = irq;
1318         control->int_ctl &= ~V_INTR_PRIO_MASK;
1319         control->int_ctl |= V_IRQ_MASK |
1320                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1321 }
1322
1323 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1324 {
1325         struct vcpu_svm *svm = to_svm(vcpu);
1326
1327         svm_inject_irq(svm, irq);
1328 }
1329
1330 static void svm_intr_assist(struct vcpu_svm *svm)
1331 {
1332         struct vmcb *vmcb = svm->vmcb;
1333         int intr_vector = -1;
1334         struct kvm_vcpu *vcpu = &svm->vcpu;
1335
1336         kvm_inject_pending_timer_irqs(vcpu);
1337         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1338             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1339                 intr_vector = vmcb->control.exit_int_info &
1340                               SVM_EVTINJ_VEC_MASK;
1341                 vmcb->control.exit_int_info = 0;
1342                 svm_inject_irq(svm, intr_vector);
1343                 return;
1344         }
1345
1346         if (vmcb->control.int_ctl & V_IRQ_MASK)
1347                 return;
1348
1349         if (!kvm_cpu_has_interrupt(vcpu))
1350                 return;
1351
1352         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1353             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1354             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1355                 /* unable to deliver irq, set pending irq */
1356                 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1357                 svm_inject_irq(svm, 0x0);
1358                 return;
1359         }
1360         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1361         intr_vector = kvm_cpu_get_interrupt(vcpu);
1362         svm_inject_irq(svm, intr_vector);
1363         kvm_timer_intr_post(vcpu, intr_vector);
1364 }
1365
1366 static void kvm_reput_irq(struct vcpu_svm *svm)
1367 {
1368         struct vmcb_control_area *control = &svm->vmcb->control;
1369
1370         if ((control->int_ctl & V_IRQ_MASK)
1371             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1372                 control->int_ctl &= ~V_IRQ_MASK;
1373                 push_irq(&svm->vcpu, control->int_vector);
1374         }
1375
1376         svm->vcpu.interrupt_window_open =
1377                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1378 }
1379
1380 static void svm_do_inject_vector(struct vcpu_svm *svm)
1381 {
1382         struct kvm_vcpu *vcpu = &svm->vcpu;
1383         int word_index = __ffs(vcpu->irq_summary);
1384         int bit_index = __ffs(vcpu->irq_pending[word_index]);
1385         int irq = word_index * BITS_PER_LONG + bit_index;
1386
1387         clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1388         if (!vcpu->irq_pending[word_index])
1389                 clear_bit(word_index, &vcpu->irq_summary);
1390         svm_inject_irq(svm, irq);
1391 }
1392
1393 static void do_interrupt_requests(struct vcpu_svm *svm,
1394                                        struct kvm_run *kvm_run)
1395 {
1396         struct vmcb_control_area *control = &svm->vmcb->control;
1397
1398         svm->vcpu.interrupt_window_open =
1399                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1400                  (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1401
1402         if (svm->vcpu.interrupt_window_open && svm->vcpu.irq_summary)
1403                 /*
1404                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1405                  */
1406                 svm_do_inject_vector(svm);
1407
1408         /*
1409          * Interrupts blocked.  Wait for unblock.
1410          */
1411         if (!svm->vcpu.interrupt_window_open &&
1412             (svm->vcpu.irq_summary || kvm_run->request_interrupt_window)) {
1413                 control->intercept |= 1ULL << INTERCEPT_VINTR;
1414         } else
1415                 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1416 }
1417
1418 static void post_kvm_run_save(struct vcpu_svm *svm,
1419                               struct kvm_run *kvm_run)
1420 {
1421         if (irqchip_in_kernel(svm->vcpu.kvm))
1422                 kvm_run->ready_for_interrupt_injection = 1;
1423         else
1424                 kvm_run->ready_for_interrupt_injection =
1425                                          (svm->vcpu.interrupt_window_open &&
1426                                           svm->vcpu.irq_summary == 0);
1427         kvm_run->if_flag = (svm->vmcb->save.rflags & X86_EFLAGS_IF) != 0;
1428         kvm_run->cr8 = get_cr8(&svm->vcpu);
1429         kvm_run->apic_base = kvm_get_apic_base(&svm->vcpu);
1430 }
1431
1432 /*
1433  * Check if userspace requested an interrupt window, and that the
1434  * interrupt window is open.
1435  *
1436  * No need to exit to userspace if we already have an interrupt queued.
1437  */
1438 static int dm_request_for_irq_injection(struct vcpu_svm *svm,
1439                                           struct kvm_run *kvm_run)
1440 {
1441         return (!svm->vcpu.irq_summary &&
1442                 kvm_run->request_interrupt_window &&
1443                 svm->vcpu.interrupt_window_open &&
1444                 (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1445 }
1446
1447 static void save_db_regs(unsigned long *db_regs)
1448 {
1449         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1450         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1451         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1452         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1453 }
1454
1455 static void load_db_regs(unsigned long *db_regs)
1456 {
1457         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1458         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1459         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1460         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1461 }
1462
1463 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1464 {
1465         force_new_asid(vcpu);
1466 }
1467
1468 static int svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1469 {
1470         struct vcpu_svm *svm = to_svm(vcpu);
1471         u16 fs_selector;
1472         u16 gs_selector;
1473         u16 ldt_selector;
1474         int r;
1475
1476 again:
1477         r = kvm_mmu_reload(vcpu);
1478         if (unlikely(r))
1479                 return r;
1480
1481         clgi();
1482
1483         if (signal_pending(current)) {
1484                 stgi();
1485                 ++vcpu->stat.signal_exits;
1486                 post_kvm_run_save(svm, kvm_run);
1487                 kvm_run->exit_reason = KVM_EXIT_INTR;
1488                 return -EINTR;
1489         }
1490
1491         if (irqchip_in_kernel(vcpu->kvm))
1492                 svm_intr_assist(svm);
1493         else if (!vcpu->mmio_read_completed)
1494                 do_interrupt_requests(svm, kvm_run);
1495
1496         vcpu->guest_mode = 1;
1497         if (vcpu->requests)
1498                 if (test_and_clear_bit(KVM_TLB_FLUSH, &vcpu->requests))
1499                     svm_flush_tlb(vcpu);
1500
1501         pre_svm_run(svm);
1502
1503         save_host_msrs(vcpu);
1504         fs_selector = read_fs();
1505         gs_selector = read_gs();
1506         ldt_selector = read_ldt();
1507         svm->host_cr2 = kvm_read_cr2();
1508         svm->host_dr6 = read_dr6();
1509         svm->host_dr7 = read_dr7();
1510         svm->vmcb->save.cr2 = vcpu->cr2;
1511
1512         if (svm->vmcb->save.dr7 & 0xff) {
1513                 write_dr7(0);
1514                 save_db_regs(svm->host_db_regs);
1515                 load_db_regs(svm->db_regs);
1516         }
1517
1518         if (vcpu->fpu_active) {
1519                 fx_save(&vcpu->host_fx_image);
1520                 fx_restore(&vcpu->guest_fx_image);
1521         }
1522
1523         asm volatile (
1524 #ifdef CONFIG_X86_64
1525                 "push %%rbx; push %%rcx; push %%rdx;"
1526                 "push %%rsi; push %%rdi; push %%rbp;"
1527                 "push %%r8;  push %%r9;  push %%r10; push %%r11;"
1528                 "push %%r12; push %%r13; push %%r14; push %%r15;"
1529 #else
1530                 "push %%ebx; push %%ecx; push %%edx;"
1531                 "push %%esi; push %%edi; push %%ebp;"
1532 #endif
1533
1534 #ifdef CONFIG_X86_64
1535                 "mov %c[rbx](%[svm]), %%rbx \n\t"
1536                 "mov %c[rcx](%[svm]), %%rcx \n\t"
1537                 "mov %c[rdx](%[svm]), %%rdx \n\t"
1538                 "mov %c[rsi](%[svm]), %%rsi \n\t"
1539                 "mov %c[rdi](%[svm]), %%rdi \n\t"
1540                 "mov %c[rbp](%[svm]), %%rbp \n\t"
1541                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1542                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1543                 "mov %c[r10](%[svm]), %%r10 \n\t"
1544                 "mov %c[r11](%[svm]), %%r11 \n\t"
1545                 "mov %c[r12](%[svm]), %%r12 \n\t"
1546                 "mov %c[r13](%[svm]), %%r13 \n\t"
1547                 "mov %c[r14](%[svm]), %%r14 \n\t"
1548                 "mov %c[r15](%[svm]), %%r15 \n\t"
1549 #else
1550                 "mov %c[rbx](%[svm]), %%ebx \n\t"
1551                 "mov %c[rcx](%[svm]), %%ecx \n\t"
1552                 "mov %c[rdx](%[svm]), %%edx \n\t"
1553                 "mov %c[rsi](%[svm]), %%esi \n\t"
1554                 "mov %c[rdi](%[svm]), %%edi \n\t"
1555                 "mov %c[rbp](%[svm]), %%ebp \n\t"
1556 #endif
1557
1558 #ifdef CONFIG_X86_64
1559                 /* Enter guest mode */
1560                 "push %%rax \n\t"
1561                 "mov %c[vmcb](%[svm]), %%rax \n\t"
1562                 SVM_VMLOAD "\n\t"
1563                 SVM_VMRUN "\n\t"
1564                 SVM_VMSAVE "\n\t"
1565                 "pop %%rax \n\t"
1566 #else
1567                 /* Enter guest mode */
1568                 "push %%eax \n\t"
1569                 "mov %c[vmcb](%[svm]), %%eax \n\t"
1570                 SVM_VMLOAD "\n\t"
1571                 SVM_VMRUN "\n\t"
1572                 SVM_VMSAVE "\n\t"
1573                 "pop %%eax \n\t"
1574 #endif
1575
1576                 /* Save guest registers, load host registers */
1577 #ifdef CONFIG_X86_64
1578                 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1579                 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1580                 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1581                 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1582                 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1583                 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1584                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1585                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1586                 "mov %%r10, %c[r10](%[svm]) \n\t"
1587                 "mov %%r11, %c[r11](%[svm]) \n\t"
1588                 "mov %%r12, %c[r12](%[svm]) \n\t"
1589                 "mov %%r13, %c[r13](%[svm]) \n\t"
1590                 "mov %%r14, %c[r14](%[svm]) \n\t"
1591                 "mov %%r15, %c[r15](%[svm]) \n\t"
1592
1593                 "pop  %%r15; pop  %%r14; pop  %%r13; pop  %%r12;"
1594                 "pop  %%r11; pop  %%r10; pop  %%r9;  pop  %%r8;"
1595                 "pop  %%rbp; pop  %%rdi; pop  %%rsi;"
1596                 "pop  %%rdx; pop  %%rcx; pop  %%rbx; \n\t"
1597 #else
1598                 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1599                 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1600                 "mov %%edx, %c[rdx](%[svm]) \n\t"
1601                 "mov %%esi, %c[rsi](%[svm]) \n\t"
1602                 "mov %%edi, %c[rdi](%[svm]) \n\t"
1603                 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1604
1605                 "pop  %%ebp; pop  %%edi; pop  %%esi;"
1606                 "pop  %%edx; pop  %%ecx; pop  %%ebx; \n\t"
1607 #endif
1608                 :
1609                 : [svm]"a"(svm),
1610                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1611                   [rbx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBX])),
1612                   [rcx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RCX])),
1613                   [rdx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDX])),
1614                   [rsi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RSI])),
1615                   [rdi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDI])),
1616                   [rbp]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBP]))
1617 #ifdef CONFIG_X86_64
1618                   ,[r8 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R8])),
1619                   [r9 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R9 ])),
1620                   [r10]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R10])),
1621                   [r11]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R11])),
1622                   [r12]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R12])),
1623                   [r13]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R13])),
1624                   [r14]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R14])),
1625                   [r15]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R15]))
1626 #endif
1627                 : "cc", "memory" );
1628
1629         vcpu->guest_mode = 0;
1630
1631         if (vcpu->fpu_active) {
1632                 fx_save(&vcpu->guest_fx_image);
1633                 fx_restore(&vcpu->host_fx_image);
1634         }
1635
1636         if ((svm->vmcb->save.dr7 & 0xff))
1637                 load_db_regs(svm->host_db_regs);
1638
1639         vcpu->cr2 = svm->vmcb->save.cr2;
1640
1641         write_dr6(svm->host_dr6);
1642         write_dr7(svm->host_dr7);
1643         kvm_write_cr2(svm->host_cr2);
1644
1645         load_fs(fs_selector);
1646         load_gs(gs_selector);
1647         load_ldt(ldt_selector);
1648         load_host_msrs(vcpu);
1649
1650         reload_tss(vcpu);
1651
1652         /*
1653          * Profile KVM exit RIPs:
1654          */
1655         if (unlikely(prof_on == KVM_PROFILING))
1656                 profile_hit(KVM_PROFILING,
1657                         (void *)(unsigned long)svm->vmcb->save.rip);
1658
1659         stgi();
1660
1661         kvm_reput_irq(svm);
1662
1663         svm->next_rip = 0;
1664
1665         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1666                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1667                 kvm_run->fail_entry.hardware_entry_failure_reason
1668                         = svm->vmcb->control.exit_code;
1669                 post_kvm_run_save(svm, kvm_run);
1670                 return 0;
1671         }
1672
1673         r = handle_exit(svm, kvm_run);
1674         if (r > 0) {
1675                 if (dm_request_for_irq_injection(svm, kvm_run)) {
1676                         ++vcpu->stat.request_irq_exits;
1677                         post_kvm_run_save(svm, kvm_run);
1678                         kvm_run->exit_reason = KVM_EXIT_INTR;
1679                         return -EINTR;
1680                 }
1681                 kvm_resched(vcpu);
1682                 goto again;
1683         }
1684         post_kvm_run_save(svm, kvm_run);
1685         return r;
1686 }
1687
1688 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1689 {
1690         struct vcpu_svm *svm = to_svm(vcpu);
1691
1692         svm->vmcb->save.cr3 = root;
1693         force_new_asid(vcpu);
1694
1695         if (vcpu->fpu_active) {
1696                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1697                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1698                 vcpu->fpu_active = 0;
1699         }
1700 }
1701
1702 static void svm_inject_page_fault(struct kvm_vcpu *vcpu,
1703                                   unsigned long  addr,
1704                                   uint32_t err_code)
1705 {
1706         struct vcpu_svm *svm = to_svm(vcpu);
1707         uint32_t exit_int_info = svm->vmcb->control.exit_int_info;
1708
1709         ++vcpu->stat.pf_guest;
1710
1711         if (is_page_fault(exit_int_info)) {
1712
1713                 svm->vmcb->control.event_inj_err = 0;
1714                 svm->vmcb->control.event_inj =  SVM_EVTINJ_VALID |
1715                                                 SVM_EVTINJ_VALID_ERR |
1716                                                 SVM_EVTINJ_TYPE_EXEPT |
1717                                                 DF_VECTOR;
1718                 return;
1719         }
1720         vcpu->cr2 = addr;
1721         svm->vmcb->save.cr2 = addr;
1722         svm->vmcb->control.event_inj =  SVM_EVTINJ_VALID |
1723                                         SVM_EVTINJ_VALID_ERR |
1724                                         SVM_EVTINJ_TYPE_EXEPT |
1725                                         PF_VECTOR;
1726         svm->vmcb->control.event_inj_err = err_code;
1727 }
1728
1729
1730 static int is_disabled(void)
1731 {
1732         u64 vm_cr;
1733
1734         rdmsrl(MSR_VM_CR, vm_cr);
1735         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1736                 return 1;
1737
1738         return 0;
1739 }
1740
1741 static void
1742 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1743 {
1744         /*
1745          * Patch in the VMMCALL instruction:
1746          */
1747         hypercall[0] = 0x0f;
1748         hypercall[1] = 0x01;
1749         hypercall[2] = 0xd9;
1750         hypercall[3] = 0xc3;
1751 }
1752
1753 static void svm_check_processor_compat(void *rtn)
1754 {
1755         *(int *)rtn = 0;
1756 }
1757
1758 static struct kvm_arch_ops svm_arch_ops = {
1759         .cpu_has_kvm_support = has_svm,
1760         .disabled_by_bios = is_disabled,
1761         .hardware_setup = svm_hardware_setup,
1762         .hardware_unsetup = svm_hardware_unsetup,
1763         .check_processor_compatibility = svm_check_processor_compat,
1764         .hardware_enable = svm_hardware_enable,
1765         .hardware_disable = svm_hardware_disable,
1766
1767         .vcpu_create = svm_create_vcpu,
1768         .vcpu_free = svm_free_vcpu,
1769
1770         .vcpu_load = svm_vcpu_load,
1771         .vcpu_put = svm_vcpu_put,
1772         .vcpu_decache = svm_vcpu_decache,
1773
1774         .set_guest_debug = svm_guest_debug,
1775         .get_msr = svm_get_msr,
1776         .set_msr = svm_set_msr,
1777         .get_segment_base = svm_get_segment_base,
1778         .get_segment = svm_get_segment,
1779         .set_segment = svm_set_segment,
1780         .get_cs_db_l_bits = svm_get_cs_db_l_bits,
1781         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1782         .set_cr0 = svm_set_cr0,
1783         .set_cr3 = svm_set_cr3,
1784         .set_cr4 = svm_set_cr4,
1785         .set_efer = svm_set_efer,
1786         .get_idt = svm_get_idt,
1787         .set_idt = svm_set_idt,
1788         .get_gdt = svm_get_gdt,
1789         .set_gdt = svm_set_gdt,
1790         .get_dr = svm_get_dr,
1791         .set_dr = svm_set_dr,
1792         .cache_regs = svm_cache_regs,
1793         .decache_regs = svm_decache_regs,
1794         .get_rflags = svm_get_rflags,
1795         .set_rflags = svm_set_rflags,
1796
1797         .invlpg = svm_invlpg,
1798         .tlb_flush = svm_flush_tlb,
1799         .inject_page_fault = svm_inject_page_fault,
1800
1801         .inject_gp = svm_inject_gp,
1802
1803         .run = svm_vcpu_run,
1804         .skip_emulated_instruction = skip_emulated_instruction,
1805         .patch_hypercall = svm_patch_hypercall,
1806         .get_irq = svm_get_irq,
1807         .set_irq = svm_set_irq,
1808 };
1809
1810 static int __init svm_init(void)
1811 {
1812         return kvm_init_arch(&svm_arch_ops, sizeof(struct vcpu_svm),
1813                               THIS_MODULE);
1814 }
1815
1816 static void __exit svm_exit(void)
1817 {
1818         kvm_exit_arch();
1819 }
1820
1821 module_init(svm_init)
1822 module_exit(svm_exit)