SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include "x86.h"
  17 #include "kvm_svm.h"
  18 #include "x86_emulate.h"
  19 #include "irq.h"
  20
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 #include <linux/vmalloc.h>
  24 #include <linux/highmem.h>
  25 #include <linux/sched.h>
  26
  27 #include <asm/desc.h>
  28
  29 MODULE_AUTHOR("Qumranet");
  30 MODULE_LICENSE("GPL");
  31
  32 #define IOPM_ALLOC_ORDER 2
  33 #define MSRPM_ALLOC_ORDER 1
  34
  35 #define DB_VECTOR 1
  36 #define UD_VECTOR 6
  37 #define GP_VECTOR 13
  38
  39 #define DR7_GD_MASK (1 << 13)
  40 #define DR6_BD_MASK (1 << 13)
  41
  42 #define SEG_TYPE_LDT 2
  43 #define SEG_TYPE_BUSY_TSS16 3
  44
  45 #define SVM_FEATURE_NPT  (1 << 0)
  46 #define SVM_FEATURE_LBRV (1 << 1)
  47 #define SVM_DEATURE_SVML (1 << 2)
  48
  49 static void kvm_reput_irq(struct vcpu_svm *svm);
  50
  51 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  52 {
  53         return container_of(vcpu, struct vcpu_svm, vcpu);
  54 }
  55
  56 unsigned long iopm_base;
  57 unsigned long msrpm_base;
  58
  59 struct kvm_ldttss_desc {
  60         u16 limit0;
  61         u16 base0;
  62         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  63         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  64         u32 base3;
  65         u32 zero1;
  66 } __attribute__((packed));
  67
  68 struct svm_cpu_data {
  69         int cpu;
  70
  71         u64 asid_generation;
  72         u32 max_asid;
  73         u32 next_asid;
  74         struct kvm_ldttss_desc *tss_desc;
  75
  76         struct page *save_area;
  77 };
  78
  79 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  80 static uint32_t svm_features;
  81
  82 struct svm_init_data {
  83         int cpu;
  84         int r;
  85 };
  86
  87 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
  88
  89 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
  90 #define MSRS_RANGE_SIZE 2048
  91 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
  92
  93 #define MAX_INST_SIZE 15
  94
  95 static inline u32 svm_has(u32 feat)
  96 {
  97         return svm_features & feat;
  98 }
  99
 100 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 101 {
 102         int word_index = __ffs(vcpu->irq_summary);
 103         int bit_index = __ffs(vcpu->irq_pending[word_index]);
 104         int irq = word_index * BITS_PER_LONG + bit_index;
 105
 106         clear_bit(bit_index, &vcpu->irq_pending[word_index]);
 107         if (!vcpu->irq_pending[word_index])
 108                 clear_bit(word_index, &vcpu->irq_summary);
 109         return irq;
 110 }
 111
 112 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 113 {
 114         set_bit(irq, vcpu->irq_pending);
 115         set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
 116 }
 117
 118 static inline void clgi(void)
 119 {
 120         asm volatile (SVM_CLGI);
 121 }
 122
 123 static inline void stgi(void)
 124 {
 125         asm volatile (SVM_STGI);
 126 }
 127
 128 static inline void invlpga(unsigned long addr, u32 asid)
 129 {
 130         asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
 131 }
 132
 133 static inline unsigned long kvm_read_cr2(void)
 134 {
 135         unsigned long cr2;
 136
 137         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 138         return cr2;
 139 }
 140
 141 static inline void kvm_write_cr2(unsigned long val)
 142 {
 143         asm volatile ("mov %0, %%cr2" :: "r" (val));
 144 }
 145
 146 static inline unsigned long read_dr6(void)
 147 {
 148         unsigned long dr6;
 149
 150         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 151         return dr6;
 152 }
 153
 154 static inline void write_dr6(unsigned long val)
 155 {
 156         asm volatile ("mov %0, %%dr6" :: "r" (val));
 157 }
 158
 159 static inline unsigned long read_dr7(void)
 160 {
 161         unsigned long dr7;
 162
 163         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 164         return dr7;
 165 }
 166
 167 static inline void write_dr7(unsigned long val)
 168 {
 169         asm volatile ("mov %0, %%dr7" :: "r" (val));
 170 }
 171
 172 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 173 {
 174         to_svm(vcpu)->asid_generation--;
 175 }
 176
 177 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 178 {
 179         force_new_asid(vcpu);
 180 }
 181
 182 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 183 {
 184         if (!(efer & EFER_LMA))
 185                 efer &= ~EFER_LME;
 186
 187         to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
 188         vcpu->shadow_efer = efer;
 189 }
 190
 191 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 192                                 bool has_error_code, u32 error_code)
 193 {
 194         struct vcpu_svm *svm = to_svm(vcpu);
 195
 196         svm->vmcb->control.event_inj = nr
 197                 | SVM_EVTINJ_VALID
 198                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 199                 | SVM_EVTINJ_TYPE_EXEPT;
 200         svm->vmcb->control.event_inj_err = error_code;
 201 }
 202
 203 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 204 {
 205         struct vcpu_svm *svm = to_svm(vcpu);
 206
 207         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 208 }
 209
 210 static int is_external_interrupt(u32 info)
 211 {
 212         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 213         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 214 }
 215
 216 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 217 {
 218         struct vcpu_svm *svm = to_svm(vcpu);
 219
 220         if (!svm->next_rip) {
 221                 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
 222                 return;
 223         }
 224         if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE)
 225                 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
 226                        __FUNCTION__,
 227                        svm->vmcb->save.rip,
 228                        svm->next_rip);
 229
 230         vcpu->rip = svm->vmcb->save.rip = svm->next_rip;
 231         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 232
 233         vcpu->interrupt_window_open = 1;
 234 }
 235
 236 static int has_svm(void)
 237 {
 238         uint32_t eax, ebx, ecx, edx;
 239
 240         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 241                 printk(KERN_INFO "has_svm: not amd\n");
 242                 return 0;
 243         }
 244
 245         cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
 246         if (eax < SVM_CPUID_FUNC) {
 247                 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
 248                 return 0;
 249         }
 250
 251         cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 252         if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
 253                 printk(KERN_DEBUG "has_svm: svm not available\n");
 254                 return 0;
 255         }
 256         return 1;
 257 }
 258
 259 static void svm_hardware_disable(void *garbage)
 260 {
 261         struct svm_cpu_data *svm_data
 262                 = per_cpu(svm_data, raw_smp_processor_id());
 263
 264         if (svm_data) {
 265                 uint64_t efer;
 266
 267                 wrmsrl(MSR_VM_HSAVE_PA, 0);
 268                 rdmsrl(MSR_EFER, efer);
 269                 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
 270                 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 271                 __free_page(svm_data->save_area);
 272                 kfree(svm_data);
 273         }
 274 }
 275
 276 static void svm_hardware_enable(void *garbage)
 277 {
 278
 279         struct svm_cpu_data *svm_data;
 280         uint64_t efer;
 281 #ifdef CONFIG_X86_64
 282         struct desc_ptr gdt_descr;
 283 #else
 284         struct desc_ptr gdt_descr;
 285 #endif
 286         struct desc_struct *gdt;
 287         int me = raw_smp_processor_id();
 288
 289         if (!has_svm()) {
 290                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 291                 return;
 292         }
 293         svm_data = per_cpu(svm_data, me);
 294
 295         if (!svm_data) {
 296                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 297                        me);
 298                 return;
 299         }
 300
 301         svm_data->asid_generation = 1;
 302         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 303         svm_data->next_asid = svm_data->max_asid + 1;
 304         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 305
 306         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 307         gdt = (struct desc_struct *)gdt_descr.address;
 308         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 309
 310         rdmsrl(MSR_EFER, efer);
 311         wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
 312
 313         wrmsrl(MSR_VM_HSAVE_PA,
 314                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 315 }
 316
 317 static int svm_cpu_init(int cpu)
 318 {
 319         struct svm_cpu_data *svm_data;
 320         int r;
 321
 322         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 323         if (!svm_data)
 324                 return -ENOMEM;
 325         svm_data->cpu = cpu;
 326         svm_data->save_area = alloc_page(GFP_KERNEL);
 327         r = -ENOMEM;
 328         if (!svm_data->save_area)
 329                 goto err_1;
 330
 331         per_cpu(svm_data, cpu) = svm_data;
 332
 333         return 0;
 334
 335 err_1:
 336         kfree(svm_data);
 337         return r;
 338
 339 }
 340
 341 static void set_msr_interception(u32 *msrpm, unsigned msr,
 342                                  int read, int write)
 343 {
 344         int i;
 345
 346         for (i = 0; i < NUM_MSR_MAPS; i++) {
 347                 if (msr >= msrpm_ranges[i] &&
 348                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 349                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 350                                           msrpm_ranges[i]) * 2;
 351
 352                         u32 *base = msrpm + (msr_offset / 32);
 353                         u32 msr_shift = msr_offset % 32;
 354                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 355                         *base = (*base & ~(0x3 << msr_shift)) |
 356                                 (mask << msr_shift);
 357                         return;
 358                 }
 359         }
 360         BUG();
 361 }
 362
 363 static __init int svm_hardware_setup(void)
 364 {
 365         int cpu;
 366         struct page *iopm_pages;
 367         struct page *msrpm_pages;
 368         void *iopm_va, *msrpm_va;
 369         int r;
 370
 371         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 372
 373         if (!iopm_pages)
 374                 return -ENOMEM;
 375
 376         iopm_va = page_address(iopm_pages);
 377         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 378         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 379         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 380
 381
 382         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 383
 384         r = -ENOMEM;
 385         if (!msrpm_pages)
 386                 goto err_1;
 387
 388         msrpm_va = page_address(msrpm_pages);
 389         memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 390         msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
 391
 392 #ifdef CONFIG_X86_64
 393         set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
 394         set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
 395         set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
 396         set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
 397         set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
 398         set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
 399 #endif
 400         set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
 401         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
 402         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
 403         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
 404
 405         for_each_online_cpu(cpu) {
 406                 r = svm_cpu_init(cpu);
 407                 if (r)
 408                         goto err_2;
 409         }
 410         return 0;
 411
 412 err_2:
 413         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 414         msrpm_base = 0;
 415 err_1:
 416         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 417         iopm_base = 0;
 418         return r;
 419 }
 420
 421 static __exit void svm_hardware_unsetup(void)
 422 {
 423         __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
 424         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 425         iopm_base = msrpm_base = 0;
 426 }
 427
 428 static void init_seg(struct vmcb_seg *seg)
 429 {
 430         seg->selector = 0;
 431         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 432                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 433         seg->limit = 0xffff;
 434         seg->base = 0;
 435 }
 436
 437 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 438 {
 439         seg->selector = 0;
 440         seg->attrib = SVM_SELECTOR_P_MASK | type;
 441         seg->limit = 0xffff;
 442         seg->base = 0;
 443 }
 444
 445 static void init_vmcb(struct vmcb *vmcb)
 446 {
 447         struct vmcb_control_area *control = &vmcb->control;
 448         struct vmcb_save_area *save = &vmcb->save;
 449
 450         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 451                                         INTERCEPT_CR3_MASK |
 452                                         INTERCEPT_CR4_MASK;
 453
 454         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 455                                         INTERCEPT_CR3_MASK |
 456                                         INTERCEPT_CR4_MASK;
 457
 458         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 459                                         INTERCEPT_DR1_MASK |
 460                                         INTERCEPT_DR2_MASK |
 461                                         INTERCEPT_DR3_MASK;
 462
 463         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 464                                         INTERCEPT_DR1_MASK |
 465                                         INTERCEPT_DR2_MASK |
 466                                         INTERCEPT_DR3_MASK |
 467                                         INTERCEPT_DR5_MASK |
 468                                         INTERCEPT_DR7_MASK;
 469
 470         control->intercept_exceptions = (1 << PF_VECTOR) |
 471                                         (1 << UD_VECTOR);
 472
 473
 474         control->intercept =    (1ULL << INTERCEPT_INTR) |
 475                                 (1ULL << INTERCEPT_NMI) |
 476                                 (1ULL << INTERCEPT_SMI) |
 477                 /*
 478                  * selective cr0 intercept bug?
 479                  *      0:   0f 22 d8                mov    %eax,%cr3
 480                  *      3:   0f 20 c0                mov    %cr0,%eax
 481                  *      6:   0d 00 00 00 80          or     $0x80000000,%eax
 482                  *      b:   0f 22 c0                mov    %eax,%cr0
 483                  * set cr3 ->interception
 484                  * get cr0 ->interception
 485                  * set cr0 -> no interception
 486                  */
 487                 /*              (1ULL << INTERCEPT_SELECTIVE_CR0) | */
 488                                 (1ULL << INTERCEPT_CPUID) |
 489                                 (1ULL << INTERCEPT_INVD) |
 490                                 (1ULL << INTERCEPT_HLT) |
 491                                 (1ULL << INTERCEPT_INVLPGA) |
 492                                 (1ULL << INTERCEPT_IOIO_PROT) |
 493                                 (1ULL << INTERCEPT_MSR_PROT) |
 494                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 495                                 (1ULL << INTERCEPT_SHUTDOWN) |
 496                                 (1ULL << INTERCEPT_VMRUN) |
 497                                 (1ULL << INTERCEPT_VMMCALL) |
 498                                 (1ULL << INTERCEPT_VMLOAD) |
 499                                 (1ULL << INTERCEPT_VMSAVE) |
 500                                 (1ULL << INTERCEPT_STGI) |
 501                                 (1ULL << INTERCEPT_CLGI) |
 502                                 (1ULL << INTERCEPT_SKINIT) |
 503                                 (1ULL << INTERCEPT_WBINVD) |
 504                                 (1ULL << INTERCEPT_MONITOR) |
 505                                 (1ULL << INTERCEPT_MWAIT);
 506
 507         control->iopm_base_pa = iopm_base;
 508         control->msrpm_base_pa = msrpm_base;
 509         control->tsc_offset = 0;
 510         control->int_ctl = V_INTR_MASKING_MASK;
 511
 512         init_seg(&save->es);
 513         init_seg(&save->ss);
 514         init_seg(&save->ds);
 515         init_seg(&save->fs);
 516         init_seg(&save->gs);
 517
 518         save->cs.selector = 0xf000;
 519         /* Executable/Readable Code Segment */
 520         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 521                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 522         save->cs.limit = 0xffff;
 523         /*
 524          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 525          * be consistent with it.
 526          *
 527          * Replace when we have real mode working for vmx.
 528          */
 529         save->cs.base = 0xf0000;
 530
 531         save->gdtr.limit = 0xffff;
 532         save->idtr.limit = 0xffff;
 533
 534         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 535         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 536
 537         save->efer = MSR_EFER_SVME_MASK;
 538         save->dr6 = 0xffff0ff0;
 539         save->dr7 = 0x400;
 540         save->rflags = 2;
 541         save->rip = 0x0000fff0;
 542
 543         /*
 544          * cr0 val on cpu init should be 0x60000010, we enable cpu
 545          * cache by default. the orderly way is to enable cache in bios.
 546          */
 547         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 548         save->cr4 = X86_CR4_PAE;
 549         /* rdx = ?? */
 550 }
 551
 552 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 553 {
 554         struct vcpu_svm *svm = to_svm(vcpu);
 555
 556         init_vmcb(svm->vmcb);
 557
 558         if (vcpu->vcpu_id != 0) {
 559                 svm->vmcb->save.rip = 0;
 560                 svm->vmcb->save.cs.base = svm->vcpu.sipi_vector << 12;
 561                 svm->vmcb->save.cs.selector = svm->vcpu.sipi_vector << 8;
 562         }
 563
 564         return 0;
 565 }
 566
 567 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 568 {
 569         struct vcpu_svm *svm;
 570         struct page *page;
 571         int err;
 572
 573         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 574         if (!svm) {
 575                 err = -ENOMEM;
 576                 goto out;
 577         }
 578
 579         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 580         if (err)
 581                 goto free_svm;
 582
 583         page = alloc_page(GFP_KERNEL);
 584         if (!page) {
 585                 err = -ENOMEM;
 586                 goto uninit;
 587         }
 588
 589         svm->vmcb = page_address(page);
 590         clear_page(svm->vmcb);
 591         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 592         svm->asid_generation = 0;
 593         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 594         init_vmcb(svm->vmcb);
 595
 596         fx_init(&svm->vcpu);
 597         svm->vcpu.fpu_active = 1;
 598         svm->vcpu.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 599         if (svm->vcpu.vcpu_id == 0)
 600                 svm->vcpu.apic_base |= MSR_IA32_APICBASE_BSP;
 601
 602         return &svm->vcpu;
 603
 604 uninit:
 605         kvm_vcpu_uninit(&svm->vcpu);
 606 free_svm:
 607         kmem_cache_free(kvm_vcpu_cache, svm);
 608 out:
 609         return ERR_PTR(err);
 610 }
 611
 612 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 613 {
 614         struct vcpu_svm *svm = to_svm(vcpu);
 615
 616         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 617         kvm_vcpu_uninit(vcpu);
 618         kmem_cache_free(kvm_vcpu_cache, svm);
 619 }
 620
 621 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 622 {
 623         struct vcpu_svm *svm = to_svm(vcpu);
 624         int i;
 625
 626         if (unlikely(cpu != vcpu->cpu)) {
 627                 u64 tsc_this, delta;
 628
 629                 /*
 630                  * Make sure that the guest sees a monotonically
 631                  * increasing TSC.
 632                  */
 633                 rdtscll(tsc_this);
 634                 delta = vcpu->host_tsc - tsc_this;
 635                 svm->vmcb->control.tsc_offset += delta;
 636                 vcpu->cpu = cpu;
 637                 kvm_migrate_apic_timer(vcpu);
 638         }
 639
 640         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 641                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 642 }
 643
 644 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 645 {
 646         struct vcpu_svm *svm = to_svm(vcpu);
 647         int i;
 648
 649         ++vcpu->stat.host_state_reload;
 650         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 651                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 652
 653         rdtscll(vcpu->host_tsc);
 654 }
 655
 656 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
 657 {
 658 }
 659
 660 static void svm_cache_regs(struct kvm_vcpu *vcpu)
 661 {
 662         struct vcpu_svm *svm = to_svm(vcpu);
 663
 664         vcpu->regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
 665         vcpu->regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
 666         vcpu->rip = svm->vmcb->save.rip;
 667 }
 668
 669 static void svm_decache_regs(struct kvm_vcpu *vcpu)
 670 {
 671         struct vcpu_svm *svm = to_svm(vcpu);
 672         svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX];
 673         svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP];
 674         svm->vmcb->save.rip = vcpu->rip;
 675 }
 676
 677 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 678 {
 679         return to_svm(vcpu)->vmcb->save.rflags;
 680 }
 681
 682 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 683 {
 684         to_svm(vcpu)->vmcb->save.rflags = rflags;
 685 }
 686
 687 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 688 {
 689         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 690
 691         switch (seg) {
 692         case VCPU_SREG_CS: return &save->cs;
 693         case VCPU_SREG_DS: return &save->ds;
 694         case VCPU_SREG_ES: return &save->es;
 695         case VCPU_SREG_FS: return &save->fs;
 696         case VCPU_SREG_GS: return &save->gs;
 697         case VCPU_SREG_SS: return &save->ss;
 698         case VCPU_SREG_TR: return &save->tr;
 699         case VCPU_SREG_LDTR: return &save->ldtr;
 700         }
 701         BUG();
 702         return NULL;
 703 }
 704
 705 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 706 {
 707         struct vmcb_seg *s = svm_seg(vcpu, seg);
 708
 709         return s->base;
 710 }
 711
 712 static void svm_get_segment(struct kvm_vcpu *vcpu,
 713                             struct kvm_segment *var, int seg)
 714 {
 715         struct vmcb_seg *s = svm_seg(vcpu, seg);
 716
 717         var->base = s->base;
 718         var->limit = s->limit;
 719         var->selector = s->selector;
 720         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 721         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 722         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 723         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 724         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 725         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 726         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 727         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 728         var->unusable = !var->present;
 729 }
 730
 731 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 732 {
 733         struct vcpu_svm *svm = to_svm(vcpu);
 734
 735         dt->limit = svm->vmcb->save.idtr.limit;
 736         dt->base = svm->vmcb->save.idtr.base;
 737 }
 738
 739 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 740 {
 741         struct vcpu_svm *svm = to_svm(vcpu);
 742
 743         svm->vmcb->save.idtr.limit = dt->limit;
 744         svm->vmcb->save.idtr.base = dt->base ;
 745 }
 746
 747 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 748 {
 749         struct vcpu_svm *svm = to_svm(vcpu);
 750
 751         dt->limit = svm->vmcb->save.gdtr.limit;
 752         dt->base = svm->vmcb->save.gdtr.base;
 753 }
 754
 755 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 756 {
 757         struct vcpu_svm *svm = to_svm(vcpu);
 758
 759         svm->vmcb->save.gdtr.limit = dt->limit;
 760         svm->vmcb->save.gdtr.base = dt->base ;
 761 }
 762
 763 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 764 {
 765 }
 766
 767 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 768 {
 769         struct vcpu_svm *svm = to_svm(vcpu);
 770
 771 #ifdef CONFIG_X86_64
 772         if (vcpu->shadow_efer & EFER_LME) {
 773                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 774                         vcpu->shadow_efer |= EFER_LMA;
 775                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 776                 }
 777
 778                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 779                         vcpu->shadow_efer &= ~EFER_LMA;
 780                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 781                 }
 782         }
 783 #endif
 784         if ((vcpu->cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 785                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 786                 vcpu->fpu_active = 1;
 787         }
 788
 789         vcpu->cr0 = cr0;
 790         cr0 |= X86_CR0_PG | X86_CR0_WP;
 791         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 792         svm->vmcb->save.cr0 = cr0;
 793 }
 794
 795 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 796 {
 797        vcpu->cr4 = cr4;
 798        to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE;
 799 }
 800
 801 static void svm_set_segment(struct kvm_vcpu *vcpu,
 802                             struct kvm_segment *var, int seg)
 803 {
 804         struct vcpu_svm *svm = to_svm(vcpu);
 805         struct vmcb_seg *s = svm_seg(vcpu, seg);
 806
 807         s->base = var->base;
 808         s->limit = var->limit;
 809         s->selector = var->selector;
 810         if (var->unusable)
 811                 s->attrib = 0;
 812         else {
 813                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 814                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 815                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 816                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 817                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 818                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 819                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 820                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 821         }
 822         if (seg == VCPU_SREG_CS)
 823                 svm->vmcb->save.cpl
 824                         = (svm->vmcb->save.cs.attrib
 825                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 826
 827 }
 828
 829 /* FIXME:
 830
 831         svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK;
 832         svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
 833
 834 */
 835
 836 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 837 {
 838         return -EOPNOTSUPP;
 839 }
 840
 841 static int svm_get_irq(struct kvm_vcpu *vcpu)
 842 {
 843         struct vcpu_svm *svm = to_svm(vcpu);
 844         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 845
 846         if (is_external_interrupt(exit_int_info))
 847                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 848         return -1;
 849 }
 850
 851 static void load_host_msrs(struct kvm_vcpu *vcpu)
 852 {
 853 #ifdef CONFIG_X86_64
 854         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 855 #endif
 856 }
 857
 858 static void save_host_msrs(struct kvm_vcpu *vcpu)
 859 {
 860 #ifdef CONFIG_X86_64
 861         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 862 #endif
 863 }
 864
 865 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 866 {
 867         if (svm_data->next_asid > svm_data->max_asid) {
 868                 ++svm_data->asid_generation;
 869                 svm_data->next_asid = 1;
 870                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 871         }
 872
 873         svm->vcpu.cpu = svm_data->cpu;
 874         svm->asid_generation = svm_data->asid_generation;
 875         svm->vmcb->control.asid = svm_data->next_asid++;
 876 }
 877
 878 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 879 {
 880         return to_svm(vcpu)->db_regs[dr];
 881 }
 882
 883 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 884                        int *exception)
 885 {
 886         struct vcpu_svm *svm = to_svm(vcpu);
 887
 888         *exception = 0;
 889
 890         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 891                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 892                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 893                 *exception = DB_VECTOR;
 894                 return;
 895         }
 896
 897         switch (dr) {
 898         case 0 ... 3:
 899                 svm->db_regs[dr] = value;
 900                 return;
 901         case 4 ... 5:
 902                 if (vcpu->cr4 & X86_CR4_DE) {
 903                         *exception = UD_VECTOR;
 904                         return;
 905                 }
 906         case 7: {
 907                 if (value & ~((1ULL << 32) - 1)) {
 908                         *exception = GP_VECTOR;
 909                         return;
 910                 }
 911                 svm->vmcb->save.dr7 = value;
 912                 return;
 913         }
 914         default:
 915                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
 916                        __FUNCTION__, dr);
 917                 *exception = UD_VECTOR;
 918                 return;
 919         }
 920 }
 921
 922 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 923 {
 924         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 925         struct kvm *kvm = svm->vcpu.kvm;
 926         u64 fault_address;
 927         u32 error_code;
 928
 929         if (!irqchip_in_kernel(kvm) &&
 930                 is_external_interrupt(exit_int_info))
 931                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
 932
 933         fault_address  = svm->vmcb->control.exit_info_2;
 934         error_code = svm->vmcb->control.exit_info_1;
 935         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
 936 }
 937
 938 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 939 {
 940         int er;
 941
 942         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0);
 943         if (er != EMULATE_DONE)
 944                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
 945         return 1;
 946 }
 947
 948 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 949 {
 950         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 951         if (!(svm->vcpu.cr0 & X86_CR0_TS))
 952                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
 953         svm->vcpu.fpu_active = 1;
 954
 955         return 1;
 956 }
 957
 958 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 959 {
 960         /*
 961          * VMCB is undefined after a SHUTDOWN intercept
 962          * so reinitialize it.
 963          */
 964         clear_page(svm->vmcb);
 965         init_vmcb(svm->vmcb);
 966
 967         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
 968         return 0;
 969 }
 970
 971 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 972 {
 973         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
 974         int size, down, in, string, rep;
 975         unsigned port;
 976
 977         ++svm->vcpu.stat.io_exits;
 978
 979         svm->next_rip = svm->vmcb->control.exit_info_2;
 980
 981         string = (io_info & SVM_IOIO_STR_MASK) != 0;
 982
 983         if (string) {
 984                 if (emulate_instruction(&svm->vcpu,
 985                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
 986                         return 0;
 987                 return 1;
 988         }
 989
 990         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
 991         port = io_info >> 16;
 992         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
 993         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
 994         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
 995
 996         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
 997 }
 998
 999 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1000 {
1001         return 1;
1002 }
1003
1004 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1005 {
1006         svm->next_rip = svm->vmcb->save.rip + 1;
1007         skip_emulated_instruction(&svm->vcpu);
1008         return kvm_emulate_halt(&svm->vcpu);
1009 }
1010
1011 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1012 {
1013         svm->next_rip = svm->vmcb->save.rip + 3;
1014         skip_emulated_instruction(&svm->vcpu);
1015         kvm_emulate_hypercall(&svm->vcpu);
1016         return 1;
1017 }
1018
1019 static int invalid_op_interception(struct vcpu_svm *svm,
1020                                    struct kvm_run *kvm_run)
1021 {
1022         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1023         return 1;
1024 }
1025
1026 static int task_switch_interception(struct vcpu_svm *svm,
1027                                     struct kvm_run *kvm_run)
1028 {
1029         pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__);
1030         kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1031         return 0;
1032 }
1033
1034 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1035 {
1036         svm->next_rip = svm->vmcb->save.rip + 2;
1037         kvm_emulate_cpuid(&svm->vcpu);
1038         return 1;
1039 }
1040
1041 static int emulate_on_interception(struct vcpu_svm *svm,
1042                                    struct kvm_run *kvm_run)
1043 {
1044         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1045                 pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__);
1046         return 1;
1047 }
1048
1049 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1050 {
1051         struct vcpu_svm *svm = to_svm(vcpu);
1052
1053         switch (ecx) {
1054         case MSR_IA32_TIME_STAMP_COUNTER: {
1055                 u64 tsc;
1056
1057                 rdtscll(tsc);
1058                 *data = svm->vmcb->control.tsc_offset + tsc;
1059                 break;
1060         }
1061         case MSR_K6_STAR:
1062                 *data = svm->vmcb->save.star;
1063                 break;
1064 #ifdef CONFIG_X86_64
1065         case MSR_LSTAR:
1066                 *data = svm->vmcb->save.lstar;
1067                 break;
1068         case MSR_CSTAR:
1069                 *data = svm->vmcb->save.cstar;
1070                 break;
1071         case MSR_KERNEL_GS_BASE:
1072                 *data = svm->vmcb->save.kernel_gs_base;
1073                 break;
1074         case MSR_SYSCALL_MASK:
1075                 *data = svm->vmcb->save.sfmask;
1076                 break;
1077 #endif
1078         case MSR_IA32_SYSENTER_CS:
1079                 *data = svm->vmcb->save.sysenter_cs;
1080                 break;
1081         case MSR_IA32_SYSENTER_EIP:
1082                 *data = svm->vmcb->save.sysenter_eip;
1083                 break;
1084         case MSR_IA32_SYSENTER_ESP:
1085                 *data = svm->vmcb->save.sysenter_esp;
1086                 break;
1087         default:
1088                 return kvm_get_msr_common(vcpu, ecx, data);
1089         }
1090         return 0;
1091 }
1092
1093 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1094 {
1095         u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX];
1096         u64 data;
1097
1098         if (svm_get_msr(&svm->vcpu, ecx, &data))
1099                 kvm_inject_gp(&svm->vcpu, 0);
1100         else {
1101                 svm->vmcb->save.rax = data & 0xffffffff;
1102                 svm->vcpu.regs[VCPU_REGS_RDX] = data >> 32;
1103                 svm->next_rip = svm->vmcb->save.rip + 2;
1104                 skip_emulated_instruction(&svm->vcpu);
1105         }
1106         return 1;
1107 }
1108
1109 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1110 {
1111         struct vcpu_svm *svm = to_svm(vcpu);
1112
1113         switch (ecx) {
1114         case MSR_IA32_TIME_STAMP_COUNTER: {
1115                 u64 tsc;
1116
1117                 rdtscll(tsc);
1118                 svm->vmcb->control.tsc_offset = data - tsc;
1119                 break;
1120         }
1121         case MSR_K6_STAR:
1122                 svm->vmcb->save.star = data;
1123                 break;
1124 #ifdef CONFIG_X86_64
1125         case MSR_LSTAR:
1126                 svm->vmcb->save.lstar = data;
1127                 break;
1128         case MSR_CSTAR:
1129                 svm->vmcb->save.cstar = data;
1130                 break;
1131         case MSR_KERNEL_GS_BASE:
1132                 svm->vmcb->save.kernel_gs_base = data;
1133                 break;
1134         case MSR_SYSCALL_MASK:
1135                 svm->vmcb->save.sfmask = data;
1136                 break;
1137 #endif
1138         case MSR_IA32_SYSENTER_CS:
1139                 svm->vmcb->save.sysenter_cs = data;
1140                 break;
1141         case MSR_IA32_SYSENTER_EIP:
1142                 svm->vmcb->save.sysenter_eip = data;
1143                 break;
1144         case MSR_IA32_SYSENTER_ESP:
1145                 svm->vmcb->save.sysenter_esp = data;
1146                 break;
1147         default:
1148                 return kvm_set_msr_common(vcpu, ecx, data);
1149         }
1150         return 0;
1151 }
1152
1153 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1154 {
1155         u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX];
1156         u64 data = (svm->vmcb->save.rax & -1u)
1157                 | ((u64)(svm->vcpu.regs[VCPU_REGS_RDX] & -1u) << 32);
1158         svm->next_rip = svm->vmcb->save.rip + 2;
1159         if (svm_set_msr(&svm->vcpu, ecx, data))
1160                 kvm_inject_gp(&svm->vcpu, 0);
1161         else
1162                 skip_emulated_instruction(&svm->vcpu);
1163         return 1;
1164 }
1165
1166 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1167 {
1168         if (svm->vmcb->control.exit_info_1)
1169                 return wrmsr_interception(svm, kvm_run);
1170         else
1171                 return rdmsr_interception(svm, kvm_run);
1172 }
1173
1174 static int interrupt_window_interception(struct vcpu_svm *svm,
1175                                    struct kvm_run *kvm_run)
1176 {
1177         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1178         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1179         /*
1180          * If the user space waits to inject interrupts, exit as soon as
1181          * possible
1182          */
1183         if (kvm_run->request_interrupt_window &&
1184             !svm->vcpu.irq_summary) {
1185                 ++svm->vcpu.stat.irq_window_exits;
1186                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1187                 return 0;
1188         }
1189
1190         return 1;
1191 }
1192
1193 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1194                                       struct kvm_run *kvm_run) = {
1195         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1196         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1197         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1198         /* for now: */
1199         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1200         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1201         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1202         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1203         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1204         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1205         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1206         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1207         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1208         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1209         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1210         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1211         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1212         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1213         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1214         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1215         [SVM_EXIT_INTR]                         = nop_on_interception,
1216         [SVM_EXIT_NMI]                          = nop_on_interception,
1217         [SVM_EXIT_SMI]                          = nop_on_interception,
1218         [SVM_EXIT_INIT]                         = nop_on_interception,
1219         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1220         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1221         [SVM_EXIT_CPUID]                        = cpuid_interception,
1222         [SVM_EXIT_INVD]                         = emulate_on_interception,
1223         [SVM_EXIT_HLT]                          = halt_interception,
1224         [SVM_EXIT_INVLPG]                       = emulate_on_interception,
1225         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1226         [SVM_EXIT_IOIO]                         = io_interception,
1227         [SVM_EXIT_MSR]                          = msr_interception,
1228         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1229         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1230         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1231         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1232         [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1233         [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1234         [SVM_EXIT_STGI]                         = invalid_op_interception,
1235         [SVM_EXIT_CLGI]                         = invalid_op_interception,
1236         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1237         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1238         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1239         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1240 };
1241
1242
1243 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1244 {
1245         struct vcpu_svm *svm = to_svm(vcpu);
1246         u32 exit_code = svm->vmcb->control.exit_code;
1247
1248         kvm_reput_irq(svm);
1249
1250         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1251                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1252                 kvm_run->fail_entry.hardware_entry_failure_reason
1253                         = svm->vmcb->control.exit_code;
1254                 return 0;
1255         }
1256
1257         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1258             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
1259                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1260                        "exit_code 0x%x\n",
1261                        __FUNCTION__, svm->vmcb->control.exit_int_info,
1262                        exit_code);
1263
1264         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1265             || !svm_exit_handlers[exit_code]) {
1266                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1267                 kvm_run->hw.hardware_exit_reason = exit_code;
1268                 return 0;
1269         }
1270
1271         return svm_exit_handlers[exit_code](svm, kvm_run);
1272 }
1273
1274 static void reload_tss(struct kvm_vcpu *vcpu)
1275 {
1276         int cpu = raw_smp_processor_id();
1277
1278         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1279         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1280         load_TR_desc();
1281 }
1282
1283 static void pre_svm_run(struct vcpu_svm *svm)
1284 {
1285         int cpu = raw_smp_processor_id();
1286
1287         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1288
1289         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1290         if (svm->vcpu.cpu != cpu ||
1291             svm->asid_generation != svm_data->asid_generation)
1292                 new_asid(svm, svm_data);
1293 }
1294
1295
1296 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1297 {
1298         struct vmcb_control_area *control;
1299
1300         control = &svm->vmcb->control;
1301         control->int_vector = irq;
1302         control->int_ctl &= ~V_INTR_PRIO_MASK;
1303         control->int_ctl |= V_IRQ_MASK |
1304                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1305 }
1306
1307 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1308 {
1309         struct vcpu_svm *svm = to_svm(vcpu);
1310
1311         svm_inject_irq(svm, irq);
1312 }
1313
1314 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1315 {
1316         struct vcpu_svm *svm = to_svm(vcpu);
1317         struct vmcb *vmcb = svm->vmcb;
1318         int intr_vector = -1;
1319
1320         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1321             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1322                 intr_vector = vmcb->control.exit_int_info &
1323                               SVM_EVTINJ_VEC_MASK;
1324                 vmcb->control.exit_int_info = 0;
1325                 svm_inject_irq(svm, intr_vector);
1326                 return;
1327         }
1328
1329         if (vmcb->control.int_ctl & V_IRQ_MASK)
1330                 return;
1331
1332         if (!kvm_cpu_has_interrupt(vcpu))
1333                 return;
1334
1335         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1336             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1337             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1338                 /* unable to deliver irq, set pending irq */
1339                 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1340                 svm_inject_irq(svm, 0x0);
1341                 return;
1342         }
1343         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1344         intr_vector = kvm_cpu_get_interrupt(vcpu);
1345         svm_inject_irq(svm, intr_vector);
1346         kvm_timer_intr_post(vcpu, intr_vector);
1347 }
1348
1349 static void kvm_reput_irq(struct vcpu_svm *svm)
1350 {
1351         struct vmcb_control_area *control = &svm->vmcb->control;
1352
1353         if ((control->int_ctl & V_IRQ_MASK)
1354             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1355                 control->int_ctl &= ~V_IRQ_MASK;
1356                 push_irq(&svm->vcpu, control->int_vector);
1357         }
1358
1359         svm->vcpu.interrupt_window_open =
1360                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1361 }
1362
1363 static void svm_do_inject_vector(struct vcpu_svm *svm)
1364 {
1365         struct kvm_vcpu *vcpu = &svm->vcpu;
1366         int word_index = __ffs(vcpu->irq_summary);
1367         int bit_index = __ffs(vcpu->irq_pending[word_index]);
1368         int irq = word_index * BITS_PER_LONG + bit_index;
1369
1370         clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1371         if (!vcpu->irq_pending[word_index])
1372                 clear_bit(word_index, &vcpu->irq_summary);
1373         svm_inject_irq(svm, irq);
1374 }
1375
1376 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1377                                        struct kvm_run *kvm_run)
1378 {
1379         struct vcpu_svm *svm = to_svm(vcpu);
1380         struct vmcb_control_area *control = &svm->vmcb->control;
1381
1382         svm->vcpu.interrupt_window_open =
1383                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1384                  (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1385
1386         if (svm->vcpu.interrupt_window_open && svm->vcpu.irq_summary)
1387                 /*
1388                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1389                  */
1390                 svm_do_inject_vector(svm);
1391
1392         /*
1393          * Interrupts blocked.  Wait for unblock.
1394          */
1395         if (!svm->vcpu.interrupt_window_open &&
1396             (svm->vcpu.irq_summary || kvm_run->request_interrupt_window))
1397                 control->intercept |= 1ULL << INTERCEPT_VINTR;
1398          else
1399                 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1400 }
1401
1402 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1403 {
1404         return 0;
1405 }
1406
1407 static void save_db_regs(unsigned long *db_regs)
1408 {
1409         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1410         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1411         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1412         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1413 }
1414
1415 static void load_db_regs(unsigned long *db_regs)
1416 {
1417         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1418         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1419         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1420         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1421 }
1422
1423 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1424 {
1425         force_new_asid(vcpu);
1426 }
1427
1428 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1429 {
1430 }
1431
1432 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1433 {
1434         struct vcpu_svm *svm = to_svm(vcpu);
1435         u16 fs_selector;
1436         u16 gs_selector;
1437         u16 ldt_selector;
1438
1439         pre_svm_run(svm);
1440
1441         save_host_msrs(vcpu);
1442         fs_selector = read_fs();
1443         gs_selector = read_gs();
1444         ldt_selector = read_ldt();
1445         svm->host_cr2 = kvm_read_cr2();
1446         svm->host_dr6 = read_dr6();
1447         svm->host_dr7 = read_dr7();
1448         svm->vmcb->save.cr2 = vcpu->cr2;
1449
1450         if (svm->vmcb->save.dr7 & 0xff) {
1451                 write_dr7(0);
1452                 save_db_regs(svm->host_db_regs);
1453                 load_db_regs(svm->db_regs);
1454         }
1455
1456         clgi();
1457
1458         local_irq_enable();
1459
1460         asm volatile (
1461 #ifdef CONFIG_X86_64
1462                 "push %%rbp; \n\t"
1463 #else
1464                 "push %%ebp; \n\t"
1465 #endif
1466
1467 #ifdef CONFIG_X86_64
1468                 "mov %c[rbx](%[svm]), %%rbx \n\t"
1469                 "mov %c[rcx](%[svm]), %%rcx \n\t"
1470                 "mov %c[rdx](%[svm]), %%rdx \n\t"
1471                 "mov %c[rsi](%[svm]), %%rsi \n\t"
1472                 "mov %c[rdi](%[svm]), %%rdi \n\t"
1473                 "mov %c[rbp](%[svm]), %%rbp \n\t"
1474                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1475                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1476                 "mov %c[r10](%[svm]), %%r10 \n\t"
1477                 "mov %c[r11](%[svm]), %%r11 \n\t"
1478                 "mov %c[r12](%[svm]), %%r12 \n\t"
1479                 "mov %c[r13](%[svm]), %%r13 \n\t"
1480                 "mov %c[r14](%[svm]), %%r14 \n\t"
1481                 "mov %c[r15](%[svm]), %%r15 \n\t"
1482 #else
1483                 "mov %c[rbx](%[svm]), %%ebx \n\t"
1484                 "mov %c[rcx](%[svm]), %%ecx \n\t"
1485                 "mov %c[rdx](%[svm]), %%edx \n\t"
1486                 "mov %c[rsi](%[svm]), %%esi \n\t"
1487                 "mov %c[rdi](%[svm]), %%edi \n\t"
1488                 "mov %c[rbp](%[svm]), %%ebp \n\t"
1489 #endif
1490
1491 #ifdef CONFIG_X86_64
1492                 /* Enter guest mode */
1493                 "push %%rax \n\t"
1494                 "mov %c[vmcb](%[svm]), %%rax \n\t"
1495                 SVM_VMLOAD "\n\t"
1496                 SVM_VMRUN "\n\t"
1497                 SVM_VMSAVE "\n\t"
1498                 "pop %%rax \n\t"
1499 #else
1500                 /* Enter guest mode */
1501                 "push %%eax \n\t"
1502                 "mov %c[vmcb](%[svm]), %%eax \n\t"
1503                 SVM_VMLOAD "\n\t"
1504                 SVM_VMRUN "\n\t"
1505                 SVM_VMSAVE "\n\t"
1506                 "pop %%eax \n\t"
1507 #endif
1508
1509                 /* Save guest registers, load host registers */
1510 #ifdef CONFIG_X86_64
1511                 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1512                 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1513                 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1514                 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1515                 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1516                 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1517                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1518                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1519                 "mov %%r10, %c[r10](%[svm]) \n\t"
1520                 "mov %%r11, %c[r11](%[svm]) \n\t"
1521                 "mov %%r12, %c[r12](%[svm]) \n\t"
1522                 "mov %%r13, %c[r13](%[svm]) \n\t"
1523                 "mov %%r14, %c[r14](%[svm]) \n\t"
1524                 "mov %%r15, %c[r15](%[svm]) \n\t"
1525
1526                 "pop  %%rbp; \n\t"
1527 #else
1528                 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1529                 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1530                 "mov %%edx, %c[rdx](%[svm]) \n\t"
1531                 "mov %%esi, %c[rsi](%[svm]) \n\t"
1532                 "mov %%edi, %c[rdi](%[svm]) \n\t"
1533                 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1534
1535                 "pop  %%ebp; \n\t"
1536 #endif
1537                 :
1538                 : [svm]"a"(svm),
1539                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1540                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RBX])),
1541                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RCX])),
1542                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RDX])),
1543                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RSI])),
1544                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RDI])),
1545                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RBP]))
1546 #ifdef CONFIG_X86_64
1547                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R8])),
1548                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R9])),
1549                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R10])),
1550                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R11])),
1551                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R12])),
1552                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R13])),
1553                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R14])),
1554                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R15]))
1555 #endif
1556                 : "cc", "memory"
1557 #ifdef CONFIG_X86_64
1558                 , "rbx", "rcx", "rdx", "rsi", "rdi"
1559                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1560 #else
1561                 , "ebx", "ecx", "edx" , "esi", "edi"
1562 #endif
1563                 );
1564
1565         if ((svm->vmcb->save.dr7 & 0xff))
1566                 load_db_regs(svm->host_db_regs);
1567
1568         vcpu->cr2 = svm->vmcb->save.cr2;
1569
1570         write_dr6(svm->host_dr6);
1571         write_dr7(svm->host_dr7);
1572         kvm_write_cr2(svm->host_cr2);
1573
1574         load_fs(fs_selector);
1575         load_gs(gs_selector);
1576         load_ldt(ldt_selector);
1577         load_host_msrs(vcpu);
1578
1579         reload_tss(vcpu);
1580
1581         local_irq_disable();
1582
1583         stgi();
1584
1585         svm->next_rip = 0;
1586 }
1587
1588 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1589 {
1590         struct vcpu_svm *svm = to_svm(vcpu);
1591
1592         svm->vmcb->save.cr3 = root;
1593         force_new_asid(vcpu);
1594
1595         if (vcpu->fpu_active) {
1596                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1597                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1598                 vcpu->fpu_active = 0;
1599         }
1600 }
1601
1602 static int is_disabled(void)
1603 {
1604         u64 vm_cr;
1605
1606         rdmsrl(MSR_VM_CR, vm_cr);
1607         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1608                 return 1;
1609
1610         return 0;
1611 }
1612
1613 static void
1614 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1615 {
1616         /*
1617          * Patch in the VMMCALL instruction:
1618          */
1619         hypercall[0] = 0x0f;
1620         hypercall[1] = 0x01;
1621         hypercall[2] = 0xd9;
1622 }
1623
1624 static void svm_check_processor_compat(void *rtn)
1625 {
1626         *(int *)rtn = 0;
1627 }
1628
1629 static struct kvm_x86_ops svm_x86_ops = {
1630         .cpu_has_kvm_support = has_svm,
1631         .disabled_by_bios = is_disabled,
1632         .hardware_setup = svm_hardware_setup,
1633         .hardware_unsetup = svm_hardware_unsetup,
1634         .check_processor_compatibility = svm_check_processor_compat,
1635         .hardware_enable = svm_hardware_enable,
1636         .hardware_disable = svm_hardware_disable,
1637
1638         .vcpu_create = svm_create_vcpu,
1639         .vcpu_free = svm_free_vcpu,
1640         .vcpu_reset = svm_vcpu_reset,
1641
1642         .prepare_guest_switch = svm_prepare_guest_switch,
1643         .vcpu_load = svm_vcpu_load,
1644         .vcpu_put = svm_vcpu_put,
1645         .vcpu_decache = svm_vcpu_decache,
1646
1647         .set_guest_debug = svm_guest_debug,
1648         .get_msr = svm_get_msr,
1649         .set_msr = svm_set_msr,
1650         .get_segment_base = svm_get_segment_base,
1651         .get_segment = svm_get_segment,
1652         .set_segment = svm_set_segment,
1653         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1654         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1655         .set_cr0 = svm_set_cr0,
1656         .set_cr3 = svm_set_cr3,
1657         .set_cr4 = svm_set_cr4,
1658         .set_efer = svm_set_efer,
1659         .get_idt = svm_get_idt,
1660         .set_idt = svm_set_idt,
1661         .get_gdt = svm_get_gdt,
1662         .set_gdt = svm_set_gdt,
1663         .get_dr = svm_get_dr,
1664         .set_dr = svm_set_dr,
1665         .cache_regs = svm_cache_regs,
1666         .decache_regs = svm_decache_regs,
1667         .get_rflags = svm_get_rflags,
1668         .set_rflags = svm_set_rflags,
1669
1670         .tlb_flush = svm_flush_tlb,
1671
1672         .run = svm_vcpu_run,
1673         .handle_exit = handle_exit,
1674         .skip_emulated_instruction = skip_emulated_instruction,
1675         .patch_hypercall = svm_patch_hypercall,
1676         .get_irq = svm_get_irq,
1677         .set_irq = svm_set_irq,
1678         .queue_exception = svm_queue_exception,
1679         .exception_injected = svm_exception_injected,
1680         .inject_pending_irq = svm_intr_assist,
1681         .inject_pending_vectors = do_interrupt_requests,
1682
1683         .set_tss_addr = svm_set_tss_addr,
1684 };
1685
1686 static int __init svm_init(void)
1687 {
1688         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1689                               THIS_MODULE);
1690 }
1691
1692 static void __exit svm_exit(void)
1693 {
1694         kvm_exit();
1695 }
1696
1697 module_init(svm_init)
1698 module_exit(svm_exit)