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   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005 Cisco Systems, Inc. All rights reserved.
   5  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   6  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   7  *
   8  * This software is available to you under a choice of one of two
   9  * licenses.  You may choose to be licensed under the terms of the GNU
  10  * General Public License (GPL) Version 2, available from the file
  11  * COPYING in the main directory of this source tree, or the
  12  * OpenIB.org BSD license below:
  13  *
  14  *     Redistribution and use in source and binary forms, with or
  15  *     without modification, are permitted provided that the following
  16  *     conditions are met:
  17  *
  18  *      - Redistributions of source code must retain the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer.
  21  *
  22  *      - Redistributions in binary form must reproduce the above
  23  *        copyright notice, this list of conditions and the following
  24  *        disclaimer in the documentation and/or other materials
  25  *        provided with the distribution.
  26  *
  27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  28  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  29  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  30  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  31  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  32  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  33  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  34  * SOFTWARE.
  35  *
  36  * $Id: mthca_cq.c 1369 2004-12-20 16:17:07Z roland $
  37  */
  38
  39 #include <linux/init.h>
  40 #include <linux/hardirq.h>
  41
  42 #include <rdma/ib_pack.h>
  43
  44 #include "mthca_dev.h"
  45 #include "mthca_cmd.h"
  46 #include "mthca_memfree.h"
  47
  48 enum {
  49         MTHCA_MAX_DIRECT_CQ_SIZE = 4 * PAGE_SIZE
  50 };
  51
  52 enum {
  53         MTHCA_CQ_ENTRY_SIZE = 0x20
  54 };
  55
  56 /*
  57  * Must be packed because start is 64 bits but only aligned to 32 bits.
  58  */
  59 struct mthca_cq_context {
  60         __be32 flags;
  61         __be64 start;
  62         __be32 logsize_usrpage;
  63         __be32 error_eqn;       /* Tavor only */
  64         __be32 comp_eqn;
  65         __be32 pd;
  66         __be32 lkey;
  67         __be32 last_notified_index;
  68         __be32 solicit_producer_index;
  69         __be32 consumer_index;
  70         __be32 producer_index;
  71         __be32 cqn;
  72         __be32 ci_db;           /* Arbel only */
  73         __be32 state_db;        /* Arbel only */
  74         u32    reserved;
  75 } __attribute__((packed));
  76
  77 #define MTHCA_CQ_STATUS_OK          ( 0 << 28)
  78 #define MTHCA_CQ_STATUS_OVERFLOW    ( 9 << 28)
  79 #define MTHCA_CQ_STATUS_WRITE_FAIL  (10 << 28)
  80 #define MTHCA_CQ_FLAG_TR            ( 1 << 18)
  81 #define MTHCA_CQ_FLAG_OI            ( 1 << 17)
  82 #define MTHCA_CQ_STATE_DISARMED     ( 0 <<  8)
  83 #define MTHCA_CQ_STATE_ARMED        ( 1 <<  8)
  84 #define MTHCA_CQ_STATE_ARMED_SOL    ( 4 <<  8)
  85 #define MTHCA_EQ_STATE_FIRED        (10 <<  8)
  86
  87 enum {
  88         MTHCA_ERROR_CQE_OPCODE_MASK = 0xfe
  89 };
  90
  91 enum {
  92         SYNDROME_LOCAL_LENGTH_ERR        = 0x01,
  93         SYNDROME_LOCAL_QP_OP_ERR         = 0x02,
  94         SYNDROME_LOCAL_EEC_OP_ERR        = 0x03,
  95         SYNDROME_LOCAL_PROT_ERR          = 0x04,
  96         SYNDROME_WR_FLUSH_ERR            = 0x05,
  97         SYNDROME_MW_BIND_ERR             = 0x06,
  98         SYNDROME_BAD_RESP_ERR            = 0x10,
  99         SYNDROME_LOCAL_ACCESS_ERR        = 0x11,
 100         SYNDROME_REMOTE_INVAL_REQ_ERR    = 0x12,
 101         SYNDROME_REMOTE_ACCESS_ERR       = 0x13,
 102         SYNDROME_REMOTE_OP_ERR           = 0x14,
 103         SYNDROME_RETRY_EXC_ERR           = 0x15,
 104         SYNDROME_RNR_RETRY_EXC_ERR       = 0x16,
 105         SYNDROME_LOCAL_RDD_VIOL_ERR      = 0x20,
 106         SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21,
 107         SYNDROME_REMOTE_ABORTED_ERR      = 0x22,
 108         SYNDROME_INVAL_EECN_ERR          = 0x23,
 109         SYNDROME_INVAL_EEC_STATE_ERR     = 0x24
 110 };
 111
 112 struct mthca_cqe {
 113         __be32 my_qpn;
 114         __be32 my_ee;
 115         __be32 rqpn;
 116         __be16 sl_g_mlpath;
 117         __be16 rlid;
 118         __be32 imm_etype_pkey_eec;
 119         __be32 byte_cnt;
 120         __be32 wqe;
 121         u8     opcode;
 122         u8     is_send;
 123         u8     reserved;
 124         u8     owner;
 125 };
 126
 127 struct mthca_err_cqe {
 128         __be32 my_qpn;
 129         u32    reserved1[3];
 130         u8     syndrome;
 131         u8     reserved2;
 132         __be16 db_cnt;
 133         u32    reserved3;
 134         __be32 wqe;
 135         u8     opcode;
 136         u8     reserved4[2];
 137         u8     owner;
 138 };
 139
 140 #define MTHCA_CQ_ENTRY_OWNER_SW      (0 << 7)
 141 #define MTHCA_CQ_ENTRY_OWNER_HW      (1 << 7)
 142
 143 #define MTHCA_TAVOR_CQ_DB_INC_CI       (1 << 24)
 144 #define MTHCA_TAVOR_CQ_DB_REQ_NOT      (2 << 24)
 145 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL  (3 << 24)
 146 #define MTHCA_TAVOR_CQ_DB_SET_CI       (4 << 24)
 147 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24)
 148
 149 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL  (1 << 24)
 150 #define MTHCA_ARBEL_CQ_DB_REQ_NOT      (2 << 24)
 151 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24)
 152
 153 static inline struct mthca_cqe *get_cqe(struct mthca_cq *cq, int entry)
 154 {
 155         if (cq->is_direct)
 156                 return cq->queue.direct.buf + (entry * MTHCA_CQ_ENTRY_SIZE);
 157         else
 158                 return cq->queue.page_list[entry * MTHCA_CQ_ENTRY_SIZE / PAGE_SIZE].buf
 159                         + (entry * MTHCA_CQ_ENTRY_SIZE) % PAGE_SIZE;
 160 }
 161
 162 static inline struct mthca_cqe *cqe_sw(struct mthca_cq *cq, int i)
 163 {
 164         struct mthca_cqe *cqe = get_cqe(cq, i);
 165         return MTHCA_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe;
 166 }
 167
 168 static inline struct mthca_cqe *next_cqe_sw(struct mthca_cq *cq)
 169 {
 170         return cqe_sw(cq, cq->cons_index & cq->ibcq.cqe);
 171 }
 172
 173 static inline void set_cqe_hw(struct mthca_cqe *cqe)
 174 {
 175         cqe->owner = MTHCA_CQ_ENTRY_OWNER_HW;
 176 }
 177
 178 static void dump_cqe(struct mthca_dev *dev, void *cqe_ptr)
 179 {
 180         __be32 *cqe = cqe_ptr;
 181
 182         (void) cqe;     /* avoid warning if mthca_dbg compiled away... */
 183         mthca_dbg(dev, "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
 184                   be32_to_cpu(cqe[0]), be32_to_cpu(cqe[1]), be32_to_cpu(cqe[2]),
 185                   be32_to_cpu(cqe[3]), be32_to_cpu(cqe[4]), be32_to_cpu(cqe[5]),
 186                   be32_to_cpu(cqe[6]), be32_to_cpu(cqe[7]));
 187 }
 188
 189 /*
 190  * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index
 191  * should be correct before calling update_cons_index().
 192  */
 193 static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq,
 194                                      int incr)
 195 {
 196         __be32 doorbell[2];
 197
 198         if (mthca_is_memfree(dev)) {
 199                 *cq->set_ci_db = cpu_to_be32(cq->cons_index);
 200                 wmb();
 201         } else {
 202                 doorbell[0] = cpu_to_be32(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn);
 203                 doorbell[1] = cpu_to_be32(incr - 1);
 204
 205                 mthca_write64(doorbell,
 206                               dev->kar + MTHCA_CQ_DOORBELL,
 207                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
 208         }
 209 }
 210
 211 void mthca_cq_completion(struct mthca_dev *dev, u32 cqn)
 212 {
 213         struct mthca_cq *cq;
 214
 215         cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
 216
 217         if (!cq) {
 218                 mthca_warn(dev, "Completion event for bogus CQ %08x\n", cqn);
 219                 return;
 220         }
 221
 222         ++cq->arm_sn;
 223
 224         cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
 225 }
 226
 227 void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
 228                     enum ib_event_type event_type)
 229 {
 230         struct mthca_cq *cq;
 231         struct ib_event event;
 232
 233         spin_lock(&dev->cq_table.lock);
 234
 235         cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
 236
 237         if (cq)
 238                 atomic_inc(&cq->refcount);
 239         spin_unlock(&dev->cq_table.lock);
 240
 241         if (!cq) {
 242                 mthca_warn(dev, "Async event for bogus CQ %08x\n", cqn);
 243                 return;
 244         }
 245
 246         event.device      = &dev->ib_dev;
 247         event.event       = event_type;
 248         event.element.cq  = &cq->ibcq;
 249         if (cq->ibcq.event_handler)
 250                 cq->ibcq.event_handler(&event, cq->ibcq.cq_context);
 251
 252         if (atomic_dec_and_test(&cq->refcount))
 253                 wake_up(&cq->wait);
 254 }
 255
 256 void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn,
 257                     struct mthca_srq *srq)
 258 {
 259         struct mthca_cq *cq;
 260         struct mthca_cqe *cqe;
 261         u32 prod_index;
 262         int nfreed = 0;
 263
 264         spin_lock_irq(&dev->cq_table.lock);
 265         cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
 266         if (cq)
 267                 atomic_inc(&cq->refcount);
 268         spin_unlock_irq(&dev->cq_table.lock);
 269
 270         if (!cq)
 271                 return;
 272
 273         spin_lock_irq(&cq->lock);
 274
 275         /*
 276          * First we need to find the current producer index, so we
 277          * know where to start cleaning from.  It doesn't matter if HW
 278          * adds new entries after this loop -- the QP we're worried
 279          * about is already in RESET, so the new entries won't come
 280          * from our QP and therefore don't need to be checked.
 281          */
 282         for (prod_index = cq->cons_index;
 283              cqe_sw(cq, prod_index & cq->ibcq.cqe);
 284              ++prod_index)
 285                 if (prod_index == cq->cons_index + cq->ibcq.cqe)
 286                         break;
 287
 288         if (0)
 289                 mthca_dbg(dev, "Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n",
 290                           qpn, cqn, cq->cons_index, prod_index);
 291
 292         /*
 293          * Now sweep backwards through the CQ, removing CQ entries
 294          * that match our QP by copying older entries on top of them.
 295          */
 296         while ((int) --prod_index - (int) cq->cons_index >= 0) {
 297                 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
 298                 if (cqe->my_qpn == cpu_to_be32(qpn)) {
 299                         if (srq)
 300                                 mthca_free_srq_wqe(srq, be32_to_cpu(cqe->wqe));
 301                         ++nfreed;
 302                 } else if (nfreed)
 303                         memcpy(get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe),
 304                                cqe, MTHCA_CQ_ENTRY_SIZE);
 305         }
 306
 307         if (nfreed) {
 308                 wmb();
 309                 cq->cons_index += nfreed;
 310                 update_cons_index(dev, cq, nfreed);
 311         }
 312
 313         spin_unlock_irq(&cq->lock);
 314         if (atomic_dec_and_test(&cq->refcount))
 315                 wake_up(&cq->wait);
 316 }
 317
 318 static int handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq,
 319                             struct mthca_qp *qp, int wqe_index, int is_send,
 320                             struct mthca_err_cqe *cqe,
 321                             struct ib_wc *entry, int *free_cqe)
 322 {
 323         int err;
 324         int dbd;
 325         __be32 new_wqe;
 326
 327         if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) {
 328                 mthca_dbg(dev, "local QP operation err "
 329                           "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n",
 330                           be32_to_cpu(cqe->my_qpn), be32_to_cpu(cqe->wqe),
 331                           cq->cqn, cq->cons_index);
 332                 dump_cqe(dev, cqe);
 333         }
 334
 335         /*
 336          * For completions in error, only work request ID, status (and
 337          * freed resource count for RD) have to be set.
 338          */
 339         switch (cqe->syndrome) {
 340         case SYNDROME_LOCAL_LENGTH_ERR:
 341                 entry->status = IB_WC_LOC_LEN_ERR;
 342                 break;
 343         case SYNDROME_LOCAL_QP_OP_ERR:
 344                 entry->status = IB_WC_LOC_QP_OP_ERR;
 345                 break;
 346         case SYNDROME_LOCAL_EEC_OP_ERR:
 347                 entry->status = IB_WC_LOC_EEC_OP_ERR;
 348                 break;
 349         case SYNDROME_LOCAL_PROT_ERR:
 350                 entry->status = IB_WC_LOC_PROT_ERR;
 351                 break;
 352         case SYNDROME_WR_FLUSH_ERR:
 353                 entry->status = IB_WC_WR_FLUSH_ERR;
 354                 break;
 355         case SYNDROME_MW_BIND_ERR:
 356                 entry->status = IB_WC_MW_BIND_ERR;
 357                 break;
 358         case SYNDROME_BAD_RESP_ERR:
 359                 entry->status = IB_WC_BAD_RESP_ERR;
 360                 break;
 361         case SYNDROME_LOCAL_ACCESS_ERR:
 362                 entry->status = IB_WC_LOC_ACCESS_ERR;
 363                 break;
 364         case SYNDROME_REMOTE_INVAL_REQ_ERR:
 365                 entry->status = IB_WC_REM_INV_REQ_ERR;
 366                 break;
 367         case SYNDROME_REMOTE_ACCESS_ERR:
 368                 entry->status = IB_WC_REM_ACCESS_ERR;
 369                 break;
 370         case SYNDROME_REMOTE_OP_ERR:
 371                 entry->status = IB_WC_REM_OP_ERR;
 372                 break;
 373         case SYNDROME_RETRY_EXC_ERR:
 374                 entry->status = IB_WC_RETRY_EXC_ERR;
 375                 break;
 376         case SYNDROME_RNR_RETRY_EXC_ERR:
 377                 entry->status = IB_WC_RNR_RETRY_EXC_ERR;
 378                 break;
 379         case SYNDROME_LOCAL_RDD_VIOL_ERR:
 380                 entry->status = IB_WC_LOC_RDD_VIOL_ERR;
 381                 break;
 382         case SYNDROME_REMOTE_INVAL_RD_REQ_ERR:
 383                 entry->status = IB_WC_REM_INV_RD_REQ_ERR;
 384                 break;
 385         case SYNDROME_REMOTE_ABORTED_ERR:
 386                 entry->status = IB_WC_REM_ABORT_ERR;
 387                 break;
 388         case SYNDROME_INVAL_EECN_ERR:
 389                 entry->status = IB_WC_INV_EECN_ERR;
 390                 break;
 391         case SYNDROME_INVAL_EEC_STATE_ERR:
 392                 entry->status = IB_WC_INV_EEC_STATE_ERR;
 393                 break;
 394         default:
 395                 entry->status = IB_WC_GENERAL_ERR;
 396                 break;
 397         }
 398
 399         /*
 400          * Mem-free HCAs always generate one CQE per WQE, even in the
 401          * error case, so we don't have to check the doorbell count, etc.
 402          */
 403         if (mthca_is_memfree(dev))
 404                 return 0;
 405
 406         err = mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe);
 407         if (err)
 408                 return err;
 409
 410         /*
 411          * If we're at the end of the WQE chain, or we've used up our
 412          * doorbell count, free the CQE.  Otherwise just update it for
 413          * the next poll operation.
 414          */
 415         if (!(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd))
 416                 return 0;
 417
 418         cqe->db_cnt   = cpu_to_be16(be16_to_cpu(cqe->db_cnt) - dbd);
 419         cqe->wqe      = new_wqe;
 420         cqe->syndrome = SYNDROME_WR_FLUSH_ERR;
 421
 422         *free_cqe = 0;
 423
 424         return 0;
 425 }
 426
 427 static inline int mthca_poll_one(struct mthca_dev *dev,
 428                                  struct mthca_cq *cq,
 429                                  struct mthca_qp **cur_qp,
 430                                  int *freed,
 431                                  struct ib_wc *entry)
 432 {
 433         struct mthca_wq *wq;
 434         struct mthca_cqe *cqe;
 435         int wqe_index;
 436         int is_error;
 437         int is_send;
 438         int free_cqe = 1;
 439         int err = 0;
 440
 441         cqe = next_cqe_sw(cq);
 442         if (!cqe)
 443                 return -EAGAIN;
 444
 445         /*
 446          * Make sure we read CQ entry contents after we've checked the
 447          * ownership bit.
 448          */
 449         rmb();
 450
 451         if (0) {
 452                 mthca_dbg(dev, "%x/%d: CQE -> QPN %06x, WQE @ %08x\n",
 453                           cq->cqn, cq->cons_index, be32_to_cpu(cqe->my_qpn),
 454                           be32_to_cpu(cqe->wqe));
 455                 dump_cqe(dev, cqe);
 456         }
 457
 458         is_error = (cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
 459                 MTHCA_ERROR_CQE_OPCODE_MASK;
 460         is_send  = is_error ? cqe->opcode & 0x01 : cqe->is_send & 0x80;
 461
 462         if (!*cur_qp || be32_to_cpu(cqe->my_qpn) != (*cur_qp)->qpn) {
 463                 /*
 464                  * We do not have to take the QP table lock here,
 465                  * because CQs will be locked while QPs are removed
 466                  * from the table.
 467                  */
 468                 *cur_qp = mthca_array_get(&dev->qp_table.qp,
 469                                           be32_to_cpu(cqe->my_qpn) &
 470                                           (dev->limits.num_qps - 1));
 471                 if (!*cur_qp) {
 472                         mthca_warn(dev, "CQ entry for unknown QP %06x\n",
 473                                    be32_to_cpu(cqe->my_qpn) & 0xffffff);
 474                         err = -EINVAL;
 475                         goto out;
 476                 }
 477         }
 478
 479         entry->qp_num = (*cur_qp)->qpn;
 480
 481         if (is_send) {
 482                 wq = &(*cur_qp)->sq;
 483                 wqe_index = ((be32_to_cpu(cqe->wqe) - (*cur_qp)->send_wqe_offset)
 484                              >> wq->wqe_shift);
 485                 entry->wr_id = (*cur_qp)->wrid[wqe_index +
 486                                                (*cur_qp)->rq.max];
 487         } else if ((*cur_qp)->ibqp.srq) {
 488                 struct mthca_srq *srq = to_msrq((*cur_qp)->ibqp.srq);
 489                 u32 wqe = be32_to_cpu(cqe->wqe);
 490                 wq = NULL;
 491                 wqe_index = wqe >> srq->wqe_shift;
 492                 entry->wr_id = srq->wrid[wqe_index];
 493                 mthca_free_srq_wqe(srq, wqe);
 494         } else {
 495                 wq = &(*cur_qp)->rq;
 496                 wqe_index = be32_to_cpu(cqe->wqe) >> wq->wqe_shift;
 497                 entry->wr_id = (*cur_qp)->wrid[wqe_index];
 498         }
 499
 500         if (wq) {
 501                 if (wq->last_comp < wqe_index)
 502                         wq->tail += wqe_index - wq->last_comp;
 503                 else
 504                         wq->tail += wqe_index + wq->max - wq->last_comp;
 505
 506                 wq->last_comp = wqe_index;
 507         }
 508
 509         if (is_error) {
 510                 err = handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send,
 511                                        (struct mthca_err_cqe *) cqe,
 512                                        entry, &free_cqe);
 513                 goto out;
 514         }
 515
 516         if (is_send) {
 517                 entry->wc_flags = 0;
 518                 switch (cqe->opcode) {
 519                 case MTHCA_OPCODE_RDMA_WRITE:
 520                         entry->opcode    = IB_WC_RDMA_WRITE;
 521                         break;
 522                 case MTHCA_OPCODE_RDMA_WRITE_IMM:
 523                         entry->opcode    = IB_WC_RDMA_WRITE;
 524                         entry->wc_flags |= IB_WC_WITH_IMM;
 525                         break;
 526                 case MTHCA_OPCODE_SEND:
 527                         entry->opcode    = IB_WC_SEND;
 528                         break;
 529                 case MTHCA_OPCODE_SEND_IMM:
 530                         entry->opcode    = IB_WC_SEND;
 531                         entry->wc_flags |= IB_WC_WITH_IMM;
 532                         break;
 533                 case MTHCA_OPCODE_RDMA_READ:
 534                         entry->opcode    = IB_WC_RDMA_READ;
 535                         entry->byte_len  = be32_to_cpu(cqe->byte_cnt);
 536                         break;
 537                 case MTHCA_OPCODE_ATOMIC_CS:
 538                         entry->opcode    = IB_WC_COMP_SWAP;
 539                         entry->byte_len  = be32_to_cpu(cqe->byte_cnt);
 540                         break;
 541                 case MTHCA_OPCODE_ATOMIC_FA:
 542                         entry->opcode    = IB_WC_FETCH_ADD;
 543                         entry->byte_len  = be32_to_cpu(cqe->byte_cnt);
 544                         break;
 545                 case MTHCA_OPCODE_BIND_MW:
 546                         entry->opcode    = IB_WC_BIND_MW;
 547                         break;
 548                 default:
 549                         entry->opcode    = MTHCA_OPCODE_INVALID;
 550                         break;
 551                 }
 552         } else {
 553                 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
 554                 switch (cqe->opcode & 0x1f) {
 555                 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE:
 556                 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE:
 557                         entry->wc_flags = IB_WC_WITH_IMM;
 558                         entry->imm_data = cqe->imm_etype_pkey_eec;
 559                         entry->opcode = IB_WC_RECV;
 560                         break;
 561                 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE:
 562                 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE:
 563                         entry->wc_flags = IB_WC_WITH_IMM;
 564                         entry->imm_data = cqe->imm_etype_pkey_eec;
 565                         entry->opcode = IB_WC_RECV_RDMA_WITH_IMM;
 566                         break;
 567                 default:
 568                         entry->wc_flags = 0;
 569                         entry->opcode = IB_WC_RECV;
 570                         break;
 571                 }
 572                 entry->slid        = be16_to_cpu(cqe->rlid);
 573                 entry->sl          = be16_to_cpu(cqe->sl_g_mlpath) >> 12;
 574                 entry->src_qp      = be32_to_cpu(cqe->rqpn) & 0xffffff;
 575                 entry->dlid_path_bits = be16_to_cpu(cqe->sl_g_mlpath) & 0x7f;
 576                 entry->pkey_index  = be32_to_cpu(cqe->imm_etype_pkey_eec) >> 16;
 577                 entry->wc_flags   |= be16_to_cpu(cqe->sl_g_mlpath) & 0x80 ?
 578                                         IB_WC_GRH : 0;
 579         }
 580
 581         entry->status = IB_WC_SUCCESS;
 582
 583  out:
 584         if (likely(free_cqe)) {
 585                 set_cqe_hw(cqe);
 586                 ++(*freed);
 587                 ++cq->cons_index;
 588         }
 589
 590         return err;
 591 }
 592
 593 int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
 594                   struct ib_wc *entry)
 595 {
 596         struct mthca_dev *dev = to_mdev(ibcq->device);
 597         struct mthca_cq *cq = to_mcq(ibcq);
 598         struct mthca_qp *qp = NULL;
 599         unsigned long flags;
 600         int err = 0;
 601         int freed = 0;
 602         int npolled;
 603
 604         spin_lock_irqsave(&cq->lock, flags);
 605
 606         for (npolled = 0; npolled < num_entries; ++npolled) {
 607                 err = mthca_poll_one(dev, cq, &qp,
 608                                      &freed, entry + npolled);
 609                 if (err)
 610                         break;
 611         }
 612
 613         if (freed) {
 614                 wmb();
 615                 update_cons_index(dev, cq, freed);
 616         }
 617
 618         spin_unlock_irqrestore(&cq->lock, flags);
 619
 620         return err == 0 || err == -EAGAIN ? npolled : err;
 621 }
 622
 623 int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify)
 624 {
 625         __be32 doorbell[2];
 626
 627         doorbell[0] = cpu_to_be32((notify == IB_CQ_SOLICITED ?
 628                                    MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL :
 629                                    MTHCA_TAVOR_CQ_DB_REQ_NOT)      |
 630                                   to_mcq(cq)->cqn);
 631         doorbell[1] = (__force __be32) 0xffffffff;
 632
 633         mthca_write64(doorbell,
 634                       to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL,
 635                       MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock));
 636
 637         return 0;
 638 }
 639
 640 int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify notify)
 641 {
 642         struct mthca_cq *cq = to_mcq(ibcq);
 643         __be32 doorbell[2];
 644         u32 sn;
 645         __be32 ci;
 646
 647         sn = cq->arm_sn & 3;
 648         ci = cpu_to_be32(cq->cons_index);
 649
 650         doorbell[0] = ci;
 651         doorbell[1] = cpu_to_be32((cq->cqn << 8) | (2 << 5) | (sn << 3) |
 652                                   (notify == IB_CQ_SOLICITED ? 1 : 2));
 653
 654         mthca_write_db_rec(doorbell, cq->arm_db);
 655
 656         /*
 657          * Make sure that the doorbell record in host memory is
 658          * written before ringing the doorbell via PCI MMIO.
 659          */
 660         wmb();
 661
 662         doorbell[0] = cpu_to_be32((sn << 28)                       |
 663                                   (notify == IB_CQ_SOLICITED ?
 664                                    MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL :
 665                                    MTHCA_ARBEL_CQ_DB_REQ_NOT)      |
 666                                   cq->cqn);
 667         doorbell[1] = ci;
 668
 669         mthca_write64(doorbell,
 670                       to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL,
 671                       MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock));
 672
 673         return 0;
 674 }
 675
 676 static void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq *cq)
 677 {
 678         mthca_buf_free(dev, (cq->ibcq.cqe + 1) * MTHCA_CQ_ENTRY_SIZE,
 679                        &cq->queue, cq->is_direct, &cq->mr);
 680 }
 681
 682 int mthca_init_cq(struct mthca_dev *dev, int nent,
 683                   struct mthca_ucontext *ctx, u32 pdn,
 684                   struct mthca_cq *cq)
 685 {
 686         int size = nent * MTHCA_CQ_ENTRY_SIZE;
 687         struct mthca_mailbox *mailbox;
 688         struct mthca_cq_context *cq_context;
 689         int err = -ENOMEM;
 690         u8 status;
 691         int i;
 692
 693         might_sleep();
 694
 695         cq->ibcq.cqe  = nent - 1;
 696         cq->is_kernel = !ctx;
 697
 698         cq->cqn = mthca_alloc(&dev->cq_table.alloc);
 699         if (cq->cqn == -1)
 700                 return -ENOMEM;
 701
 702         if (mthca_is_memfree(dev)) {
 703                 err = mthca_table_get(dev, dev->cq_table.table, cq->cqn);
 704                 if (err)
 705                         goto err_out;
 706
 707                 if (cq->is_kernel) {
 708                         cq->arm_sn = 1;
 709
 710                         err = -ENOMEM;
 711
 712                         cq->set_ci_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_SET_CI,
 713                                                              cq->cqn, &cq->set_ci_db);
 714                         if (cq->set_ci_db_index < 0)
 715                                 goto err_out_icm;
 716
 717                         cq->arm_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_ARM,
 718                                                           cq->cqn, &cq->arm_db);
 719                         if (cq->arm_db_index < 0)
 720                                 goto err_out_ci;
 721                 }
 722         }
 723
 724         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 725         if (IS_ERR(mailbox))
 726                 goto err_out_arm;
 727
 728         cq_context = mailbox->buf;
 729
 730         if (cq->is_kernel) {
 731                 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_CQ_SIZE,
 732                                       &cq->queue, &cq->is_direct,
 733                                       &dev->driver_pd, 1, &cq->mr);
 734                 if (err)
 735                         goto err_out_mailbox;
 736
 737                 for (i = 0; i < nent; ++i)
 738                         set_cqe_hw(get_cqe(cq, i));
 739         }
 740
 741         spin_lock_init(&cq->lock);
 742         atomic_set(&cq->refcount, 1);
 743         init_waitqueue_head(&cq->wait);
 744
 745         memset(cq_context, 0, sizeof *cq_context);
 746         cq_context->flags           = cpu_to_be32(MTHCA_CQ_STATUS_OK      |
 747                                                   MTHCA_CQ_STATE_DISARMED |
 748                                                   MTHCA_CQ_FLAG_TR);
 749         cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24);
 750         if (ctx)
 751                 cq_context->logsize_usrpage |= cpu_to_be32(ctx->uar.index);
 752         else
 753                 cq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index);
 754         cq_context->error_eqn       = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn);
 755         cq_context->comp_eqn        = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_COMP].eqn);
 756         cq_context->pd              = cpu_to_be32(pdn);
 757         cq_context->lkey            = cpu_to_be32(cq->mr.ibmr.lkey);
 758         cq_context->cqn             = cpu_to_be32(cq->cqn);
 759
 760         if (mthca_is_memfree(dev)) {
 761                 cq_context->ci_db    = cpu_to_be32(cq->set_ci_db_index);
 762                 cq_context->state_db = cpu_to_be32(cq->arm_db_index);
 763         }
 764
 765         err = mthca_SW2HW_CQ(dev, mailbox, cq->cqn, &status);
 766         if (err) {
 767                 mthca_warn(dev, "SW2HW_CQ failed (%d)\n", err);
 768                 goto err_out_free_mr;
 769         }
 770
 771         if (status) {
 772                 mthca_warn(dev, "SW2HW_CQ returned status 0x%02x\n",
 773                            status);
 774                 err = -EINVAL;
 775                 goto err_out_free_mr;
 776         }
 777
 778         spin_lock_irq(&dev->cq_table.lock);
 779         if (mthca_array_set(&dev->cq_table.cq,
 780                             cq->cqn & (dev->limits.num_cqs - 1),
 781                             cq)) {
 782                 spin_unlock_irq(&dev->cq_table.lock);
 783                 goto err_out_free_mr;
 784         }
 785         spin_unlock_irq(&dev->cq_table.lock);
 786
 787         cq->cons_index = 0;
 788
 789         mthca_free_mailbox(dev, mailbox);
 790
 791         return 0;
 792
 793 err_out_free_mr:
 794         if (cq->is_kernel)
 795                 mthca_free_cq_buf(dev, cq);
 796
 797 err_out_mailbox:
 798         mthca_free_mailbox(dev, mailbox);
 799
 800 err_out_arm:
 801         if (cq->is_kernel && mthca_is_memfree(dev))
 802                 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
 803
 804 err_out_ci:
 805         if (cq->is_kernel && mthca_is_memfree(dev))
 806                 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
 807
 808 err_out_icm:
 809         mthca_table_put(dev, dev->cq_table.table, cq->cqn);
 810
 811 err_out:
 812         mthca_free(&dev->cq_table.alloc, cq->cqn);
 813
 814         return err;
 815 }
 816
 817 void mthca_free_cq(struct mthca_dev *dev,
 818                    struct mthca_cq *cq)
 819 {
 820         struct mthca_mailbox *mailbox;
 821         int err;
 822         u8 status;
 823
 824         might_sleep();
 825
 826         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 827         if (IS_ERR(mailbox)) {
 828                 mthca_warn(dev, "No memory for mailbox to free CQ.\n");
 829                 return;
 830         }
 831
 832         err = mthca_HW2SW_CQ(dev, mailbox, cq->cqn, &status);
 833         if (err)
 834                 mthca_warn(dev, "HW2SW_CQ failed (%d)\n", err);
 835         else if (status)
 836                 mthca_warn(dev, "HW2SW_CQ returned status 0x%02x\n", status);
 837
 838         if (0) {
 839                 __be32 *ctx = mailbox->buf;
 840                 int j;
 841
 842                 printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n",
 843                        cq->cqn, cq->cons_index,
 844                        cq->is_kernel ? !!next_cqe_sw(cq) : 0);
 845                 for (j = 0; j < 16; ++j)
 846                         printk(KERN_ERR "[%2x] %08x\n", j * 4, be32_to_cpu(ctx[j]));
 847         }
 848
 849         spin_lock_irq(&dev->cq_table.lock);
 850         mthca_array_clear(&dev->cq_table.cq,
 851                           cq->cqn & (dev->limits.num_cqs - 1));
 852         spin_unlock_irq(&dev->cq_table.lock);
 853
 854         if (dev->mthca_flags & MTHCA_FLAG_MSI_X)
 855                 synchronize_irq(dev->eq_table.eq[MTHCA_EQ_COMP].msi_x_vector);
 856         else
 857                 synchronize_irq(dev->pdev->irq);
 858
 859         atomic_dec(&cq->refcount);
 860         wait_event(cq->wait, !atomic_read(&cq->refcount));
 861
 862         if (cq->is_kernel) {
 863                 mthca_free_cq_buf(dev, cq);
 864                 if (mthca_is_memfree(dev)) {
 865                         mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM,    cq->arm_db_index);
 866                         mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
 867                 }
 868         }
 869
 870         mthca_table_put(dev, dev->cq_table.table, cq->cqn);
 871         mthca_free(&dev->cq_table.alloc, cq->cqn);
 872         mthca_free_mailbox(dev, mailbox);
 873 }
 874
 875 int __devinit mthca_init_cq_table(struct mthca_dev *dev)
 876 {
 877         int err;
 878
 879         spin_lock_init(&dev->cq_table.lock);
 880
 881         err = mthca_alloc_init(&dev->cq_table.alloc,
 882                                dev->limits.num_cqs,
 883                                (1 << 24) - 1,
 884                                dev->limits.reserved_cqs);
 885         if (err)
 886                 return err;
 887
 888         err = mthca_array_init(&dev->cq_table.cq,
 889                                dev->limits.num_cqs);
 890         if (err)
 891                 mthca_alloc_cleanup(&dev->cq_table.alloc);
 892
 893         return err;
 894 }
 895
 896 void __devexit mthca_cleanup_cq_table(struct mthca_dev *dev)
 897 {
 898         mthca_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs);
 899         mthca_alloc_cleanup(&dev->cq_table.alloc);
 900 }