1 #ifndef _IPATH_KERNEL_H
2 #define _IPATH_KERNEL_H
4 * Copyright (c) 2006 QLogic, Inc. All rights reserved.
5 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 * This header file is the base header file for infinipath kernel code
38 * ipath_user.h serves a similar purpose for user code.
41 #include <linux/interrupt.h>
44 #include "ipath_common.h"
45 #include "ipath_debug.h"
46 #include "ipath_registers.h"
48 /* only s/w major version of InfiniPath we can handle */
49 #define IPATH_CHIP_VERS_MAJ 2U
51 /* don't care about this except printing */
52 #define IPATH_CHIP_VERS_MIN 0U
54 /* temporary, maybe always */
55 extern struct infinipath_stats ipath_stats;
57 #define IPATH_CHIP_SWVERSION IPATH_CHIP_VERS_MAJ
59 struct ipath_portdata {
60 void **port_rcvegrbuf;
61 dma_addr_t *port_rcvegrbuf_phys;
62 /* rcvhdrq base, needs mmap before useful */
64 /* kernel virtual address where hdrqtail is updated */
65 u64 *port_rcvhdrtail_kvaddr;
66 /* page * used for uaddr */
67 struct page *port_rcvhdrtail_pagep;
69 * temp buffer for expected send setup, allocated at open, instead
72 void *port_tid_pg_list;
73 /* when waiting for rcv or pioavail */
74 wait_queue_head_t port_wait;
76 * rcvegr bufs base, physical, must fit
77 * in 44 bits so 32 bit programs mmap64 44 bit works)
79 dma_addr_t port_rcvegr_phys;
80 /* mmap of hdrq, must fit in 44 bits */
81 dma_addr_t port_rcvhdrq_phys;
83 * the actual user address that we ipath_mlock'ed, so we can
84 * ipath_munlock it at close
86 unsigned long port_rcvhdrtail_uaddr;
88 * number of opens on this instance (0 or 1; ignoring forks, dup,
93 * how much space to leave at start of eager TID entries for
94 * protocol use, on each TID
96 /* instead of calculating it */
98 /* chip offset of PIO buffers for this port */
100 /* how many alloc_pages() chunks in port_rcvegrbuf_pages */
101 u32 port_rcvegrbuf_chunks;
102 /* how many egrbufs per chunk */
103 u32 port_rcvegrbufs_perchunk;
104 /* order for port_rcvegrbuf_pages */
105 size_t port_rcvegrbuf_size;
106 /* rcvhdrq size (for freeing) */
107 size_t port_rcvhdrq_size;
108 /* next expected TID to check when looking for free */
110 /* next expected TID to check */
111 unsigned long port_flag;
112 /* WAIT_RCV that timed out, no interrupt */
114 /* WAIT_PIO that timed out, no interrupt */
116 /* WAIT_RCV already happened, no wait */
118 /* WAIT_PIO already happened, no wait */
120 /* total number of rcvhdrqfull errors */
122 /* pid of process using this port */
124 /* same size as task_struct .comm[] */
126 /* pkeys set by this use of this port */
128 /* so file ops can get at unit */
129 struct ipath_devdata *port_dd;
135 * control information for layered drivers
137 struct _ipath_layer {
141 /* Verbs layer interface */
142 struct _verbs_layer {
144 struct timer_list l_timer;
147 struct ipath_devdata {
148 struct list_head ipath_list;
150 struct ipath_kregs const *ipath_kregs;
151 struct ipath_cregs const *ipath_cregs;
153 /* mem-mapped pointer to base of chip regs */
154 u64 __iomem *ipath_kregbase;
155 /* end of mem-mapped chip space; range checking */
156 u64 __iomem *ipath_kregend;
157 /* physical address of chip for io_remap, etc. */
158 unsigned long ipath_physaddr;
159 /* base of memory alloced for ipath_kregbase, for free */
160 u64 *ipath_kregalloc;
162 * virtual address where port0 rcvhdrqtail updated for this unit.
163 * only written to by the chip, not the driver.
165 volatile __le64 *ipath_hdrqtailptr;
166 dma_addr_t ipath_dma_addr;
167 /* ipath_cfgports pointers */
168 struct ipath_portdata **ipath_pd;
169 /* sk_buffs used by port 0 eager receive queue */
170 struct sk_buff **ipath_port0_skbs;
171 /* kvirt address of 1st 2k pio buffer */
172 void __iomem *ipath_pio2kbase;
173 /* kvirt address of 1st 4k pio buffer */
174 void __iomem *ipath_pio4kbase;
176 * points to area where PIOavail registers will be DMA'ed.
177 * Has to be on a page of it's own, because the page will be
178 * mapped into user program space. This copy is *ONLY* ever
179 * written by DMA, not by the driver! Need a copy per device
180 * when we get to multiple devices
182 volatile __le64 *ipath_pioavailregs_dma;
183 /* physical address where updates occur */
184 dma_addr_t ipath_pioavailregs_phys;
185 struct _ipath_layer ipath_layer;
187 int (*ipath_f_intrsetup)(struct ipath_devdata *);
188 /* setup on-chip bus config */
189 int (*ipath_f_bus)(struct ipath_devdata *, struct pci_dev *);
190 /* hard reset chip */
191 int (*ipath_f_reset)(struct ipath_devdata *);
192 int (*ipath_f_get_boardname)(struct ipath_devdata *, char *,
194 void (*ipath_f_init_hwerrors)(struct ipath_devdata *);
195 void (*ipath_f_handle_hwerrors)(struct ipath_devdata *, char *,
197 void (*ipath_f_quiet_serdes)(struct ipath_devdata *);
198 int (*ipath_f_bringup_serdes)(struct ipath_devdata *);
199 int (*ipath_f_early_init)(struct ipath_devdata *);
200 void (*ipath_f_clear_tids)(struct ipath_devdata *, unsigned);
201 void (*ipath_f_put_tid)(struct ipath_devdata *, u64 __iomem*,
203 void (*ipath_f_tidtemplate)(struct ipath_devdata *);
204 void (*ipath_f_cleanup)(struct ipath_devdata *);
205 void (*ipath_f_setextled)(struct ipath_devdata *, u64, u64);
206 /* fill out chip-specific fields */
207 int (*ipath_f_get_base_info)(struct ipath_portdata *, void *);
208 struct _verbs_layer verbs_layer;
209 /* total dwords sent (summed from counter) */
211 /* total dwords rcvd (summed from counter) */
213 /* total packets sent (summed from counter) */
215 /* total packets rcvd (summed from counter) */
217 /* ipath_statusp initially points to this. */
219 /* GUID for this interface, in network order */
222 * aggregrate of error bits reported since last cleared, for
223 * limiting of error reporting
225 ipath_err_t ipath_lasterror;
227 * aggregrate of error bits reported since last cleared, for
228 * limiting of hwerror reporting
230 ipath_err_t ipath_lasthwerror;
232 * errors masked because they occur too fast, also includes errors
233 * that are always ignored (ipath_ignorederrs)
235 ipath_err_t ipath_maskederrs;
236 /* time in jiffies at which to re-enable maskederrs */
237 unsigned long ipath_unmasktime;
239 * errors always ignored (masked), at least for a given
240 * chip/device, because they are wrong or not useful
242 ipath_err_t ipath_ignorederrs;
243 /* count of egrfull errors, combined for all ports */
244 u64 ipath_last_tidfull;
245 /* for ipath_qcheck() */
246 u64 ipath_lastport0rcv_cnt;
247 /* template for writing TIDs */
248 u64 ipath_tidtemplate;
249 /* value to write to free TIDs */
250 u64 ipath_tidinvalid;
251 /* PE-800 rcv interrupt setup */
252 u64 ipath_rhdrhead_intr_off;
254 /* size of memory at ipath_kregbase */
256 /* number of registers used for pioavail */
258 /* IPATH_POLL, etc. */
260 /* ipath_flags sma is waiting for */
261 u32 ipath_sma_state_wanted;
262 /* last buffer for user use, first buf for kernel use is this
264 u32 ipath_lastport_piobuf;
265 /* is a stats timer active */
266 u32 ipath_stats_timer_active;
267 /* dwords sent read from counter */
269 /* dwords received read from counter */
271 /* sent packets read from counter */
273 /* received packets read from counter */
275 /* pio bufs allocated per port */
278 * number of ports configured as max; zero is set to number chip
279 * supports, less gives more pio bufs/port, etc.
282 /* port0 rcvhdrq head offset */
284 /* count of port 0 hdrqfull errors */
285 u32 ipath_p0_hdrqfull;
288 * (*cfgports) used to suppress multiple instances of same
289 * port staying stuck at same point
291 u32 *ipath_lastrcvhdrqtails;
293 * (*cfgports) used to suppress multiple instances of same
294 * port staying stuck at same point
296 u32 *ipath_lastegrheads;
298 * index of last piobuffer we used. Speeds up searching, by
299 * starting at this point. Doesn't matter if multiple cpu's use and
300 * update, last updater is only write that matters. Whenever it
301 * wraps, we update shadow copies. Need a copy per device when we
302 * get to multiple devices
304 u32 ipath_lastpioindex;
305 /* max length of freezemsg */
308 * consecutive times we wanted a PIO buffer but were unable to
311 u32 ipath_consec_nopiobuf;
313 * hint that we should update ipath_pioavailshadow before
314 * looking for a PIO buffer
316 u32 ipath_upd_pio_shadow;
317 /* so we can rewrite it after a chip reset */
319 /* so we can rewrite it after a chip reset */
321 /* sequential tries for SMA send and no bufs */
322 u32 ipath_nosma_bufs;
323 /* duration (seconds) ipath_nosma_bufs set */
324 u32 ipath_nosma_secs;
326 /* HT/PCI Vendor ID (here for NodeInfo) */
328 /* HT/PCI Device ID (here for NodeInfo) */
330 /* offset in HT config space of slave/primary interface block */
331 u8 ipath_ht_slave_off;
332 /* for write combining settings */
333 unsigned long ipath_wc_cookie;
334 /* ref count for each pkey */
335 atomic_t ipath_pkeyrefs[4];
336 /* shadow copy of all exptids physaddr; used only by funcsim */
337 u64 *ipath_tidsimshadow;
338 /* shadow copy of struct page *'s for exp tid pages */
339 struct page **ipath_pageshadow;
340 /* lock to workaround chip bug 9437 */
341 spinlock_t ipath_tid_lock;
345 * this address is mapped readonly into user processes so they can
346 * get status cheaply, whenever they want.
349 /* freeze msg if hw error put chip in freeze */
350 char *ipath_freezemsg;
351 /* pci access data structure */
352 struct pci_dev *pcidev;
353 struct cdev *user_cdev;
354 struct cdev *diag_cdev;
355 struct class_device *user_class_dev;
356 struct class_device *diag_class_dev;
357 /* timer used to prevent stats overflow, error throttling, etc. */
358 struct timer_list ipath_stats_timer;
359 /* check for stale messages in rcv queue */
360 /* only allow one intr at a time. */
361 unsigned long ipath_rcv_pending;
364 * Shadow copies of registers; size indicates read access size.
365 * Most of them are readonly, but some are write-only register,
366 * where we manipulate the bits in the shadow copy, and then write
367 * the shadow copy to infinipath.
369 * We deliberately make most of these 32 bits, since they have
370 * restricted range. For any that we read, we won't to generate 32
371 * bit accesses, since Opteron will generate 2 separate 32 bit HT
372 * transactions for a 64 bit read, and we want to avoid unnecessary
376 /* This is the 64 bit group */
379 * shadow of pioavail, check to be sure it's large enough at
382 unsigned long ipath_pioavailshadow[8];
383 /* shadow of kr_gpio_out, for rmw ops */
385 /* kr_revision shadow */
388 * shadow of ibcctrl, for interrupt handling of link changes,
393 * last ibcstatus, to suppress "duplicate" status change messages,
396 u64 ipath_lastibcstat;
397 /* hwerrmask shadow */
398 ipath_err_t ipath_hwerrmask;
399 /* interrupt config reg shadow */
401 /* kr_sendpiobufbase value */
402 u64 ipath_piobufbase;
404 /* these are the "32 bit" regs */
407 * number of GUIDs in the flash for this interface; may need some
408 * rethinking for setting on other ifaces
412 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
413 * all expect bit fields to be "unsigned long"
415 /* shadow kr_rcvctrl */
416 unsigned long ipath_rcvctrl;
417 /* shadow kr_sendctrl */
418 unsigned long ipath_sendctrl;
420 /* value we put in kr_rcvhdrcnt */
422 /* value we put in kr_rcvhdrsize */
423 u32 ipath_rcvhdrsize;
424 /* value we put in kr_rcvhdrentsize */
425 u32 ipath_rcvhdrentsize;
426 /* offset of last entry in rcvhdrq */
428 /* kr_portcnt value */
430 /* kr_pagealign value */
432 /* number of "2KB" PIO buffers */
434 /* size in bytes of "2KB" PIO buffers */
436 /* number of "4KB" PIO buffers */
438 /* size in bytes of "4KB" PIO buffers */
440 /* kr_rcvegrbase value */
441 u32 ipath_rcvegrbase;
442 /* kr_rcvegrcnt value */
444 /* kr_rcvtidbase value */
445 u32 ipath_rcvtidbase;
446 /* kr_rcvtidcnt value */
452 /* kr_counterregbase */
454 /* shadow the control register contents */
456 /* shadow the gpio output contents */
458 /* PCI revision register (HTC rev on FPGA) */
461 /* chip address space used by 4k pio buffers */
463 /* The MTU programmed for this unit */
466 * The max size IB packet, included IB headers that we can send.
467 * Starts same as ipath_piosize, but is affected when ibmtu is
468 * changed, or by size of eager buffers
472 * ibmaxlen at init time, limited by chip and by receive buffer
473 * size. Not changed after init.
475 u32 ipath_init_ibmaxlen;
476 /* size of each rcvegrbuffer */
477 u32 ipath_rcvegrbufsize;
478 /* width (2,4,8,16,32) from HT config reg */
480 /* HT speed (200,400,800,1000) from HT config */
482 /* ports waiting for PIOavail intr */
483 unsigned long ipath_portpiowait;
485 * number of sequential ibcstatus change for polling active/quiet
486 * (i.e., link not coming up).
489 /* low and high portions of MSI capability/vector */
491 /* saved after PCIe init for restore after reset */
493 /* MSI data (vector) saved for restore */
495 /* MLID programmed for this instance */
497 /* LID programmed for this instance */
499 /* list of pkeys programmed; 0 if not set */
501 /* ASCII serial number, from flash */
503 /* human readable board version */
504 u8 ipath_boardversion[80];
505 /* chip major rev, from ipath_revision */
507 /* chip minor rev, from ipath_revision */
509 /* board rev, from ipath_revision */
511 /* unit # of this chip, if present */
513 /* saved for restore after reset */
514 u8 ipath_pci_cacheline;
515 /* LID mask control */
519 extern volatile __le64 *ipath_port0_rcvhdrtail;
520 extern dma_addr_t ipath_port0_rcvhdrtail_dma;
522 #define IPATH_PORT0_RCVHDRTAIL_SIZE PAGE_SIZE
524 extern struct list_head ipath_dev_list;
525 extern spinlock_t ipath_devs_lock;
526 extern struct ipath_devdata *ipath_lookup(int unit);
528 extern u16 ipath_layer_rcv_opcode;
529 extern int __ipath_layer_intr(struct ipath_devdata *, u32);
530 extern int ipath_layer_intr(struct ipath_devdata *, u32);
531 extern int __ipath_layer_rcv(struct ipath_devdata *, void *,
533 extern int __ipath_layer_rcv_lid(struct ipath_devdata *, void *);
534 extern int __ipath_verbs_piobufavail(struct ipath_devdata *);
535 extern int __ipath_verbs_rcv(struct ipath_devdata *, void *, void *, u32);
537 void ipath_layer_add(struct ipath_devdata *);
538 void ipath_layer_remove(struct ipath_devdata *);
540 int ipath_init_chip(struct ipath_devdata *, int);
541 int ipath_enable_wc(struct ipath_devdata *dd);
542 void ipath_disable_wc(struct ipath_devdata *dd);
543 int ipath_count_units(int *npresentp, int *nupp, u32 *maxportsp);
544 void ipath_shutdown_device(struct ipath_devdata *);
546 struct file_operations;
547 int ipath_cdev_init(int minor, char *name, struct file_operations *fops,
548 struct cdev **cdevp, struct class_device **class_devp);
549 void ipath_cdev_cleanup(struct cdev **cdevp,
550 struct class_device **class_devp);
552 int ipath_diag_add(struct ipath_devdata *);
553 void ipath_diag_remove(struct ipath_devdata *);
554 void ipath_diag_bringup_link(struct ipath_devdata *);
556 extern wait_queue_head_t ipath_sma_state_wait;
558 int ipath_user_add(struct ipath_devdata *dd);
559 void ipath_user_remove(struct ipath_devdata *dd);
561 struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd, gfp_t);
563 extern int ipath_diag_inuse;
565 irqreturn_t ipath_intr(int irq, void *devid, struct pt_regs *regs);
566 void ipath_decode_err(char *buf, size_t blen, ipath_err_t err);
567 #if __IPATH_INFO || __IPATH_DBG
568 extern const char *ipath_ibcstatus_str[];
571 /* clean up any per-chip chip-specific stuff */
572 void ipath_chip_cleanup(struct ipath_devdata *);
573 /* clean up any chip type-specific stuff */
574 void ipath_chip_done(void);
576 /* check to see if we have to force ordering for write combining */
577 int ipath_unordered_wc(void);
579 void ipath_disarm_piobufs(struct ipath_devdata *, unsigned first,
582 int ipath_create_rcvhdrq(struct ipath_devdata *, struct ipath_portdata *);
583 void ipath_free_pddata(struct ipath_devdata *, u32, int);
585 int ipath_parse_ushort(const char *str, unsigned short *valp);
587 int ipath_wait_linkstate(struct ipath_devdata *, u32, int);
588 void ipath_set_ib_lstate(struct ipath_devdata *, int);
589 void ipath_kreceive(struct ipath_devdata *);
590 int ipath_setrcvhdrsize(struct ipath_devdata *, unsigned);
591 int ipath_reset_device(int);
592 void ipath_get_faststats(unsigned long);
594 /* for use in system calls, where we want to know device type, etc. */
595 #define port_fp(fp) ((struct ipath_portdata *) (fp)->private_data)
598 * values for ipath_flags
600 /* The chip is up and initted */
601 #define IPATH_INITTED 0x2
602 /* set if any user code has set kr_rcvhdrsize */
603 #define IPATH_RCVHDRSZ_SET 0x4
604 /* The chip is present and valid for accesses */
605 #define IPATH_PRESENT 0x8
606 /* HT link0 is only 8 bits wide, ignore upper byte crc
608 #define IPATH_8BIT_IN_HT0 0x10
609 /* HT link1 is only 8 bits wide, ignore upper byte crc
611 #define IPATH_8BIT_IN_HT1 0x20
612 /* The link is down */
613 #define IPATH_LINKDOWN 0x40
614 /* The link level is up (0x11) */
615 #define IPATH_LINKINIT 0x80
616 /* The link is in the armed (0x21) state */
617 #define IPATH_LINKARMED 0x100
618 /* The link is in the active (0x31) state */
619 #define IPATH_LINKACTIVE 0x200
620 /* link current state is unknown */
621 #define IPATH_LINKUNK 0x400
622 /* no IB cable, or no device on IB cable */
623 #define IPATH_NOCABLE 0x4000
624 /* Supports port zero per packet receive interrupts via
626 #define IPATH_GPIO_INTR 0x8000
627 /* uses the coded 4byte TID, not 8 byte */
628 #define IPATH_4BYTE_TID 0x10000
629 /* packet/word counters are 32 bit, else those 4 counters
631 #define IPATH_32BITCOUNTERS 0x20000
632 /* can miss port0 rx interrupts */
633 #define IPATH_POLL_RX_INTR 0x40000
634 #define IPATH_DISABLED 0x80000 /* administratively disabled */
636 /* portdata flag bit offsets */
637 /* waiting for a packet to arrive */
638 #define IPATH_PORT_WAITING_RCV 2
639 /* waiting for a PIO buffer to be available */
640 #define IPATH_PORT_WAITING_PIO 3
642 /* free up any allocated data at closes */
643 void ipath_free_data(struct ipath_portdata *dd);
644 int ipath_waitfor_mdio_cmdready(struct ipath_devdata *);
645 int ipath_waitfor_complete(struct ipath_devdata *, ipath_kreg, u64, u64 *);
646 u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32 *);
647 /* init PE-800-specific func */
648 void ipath_init_pe800_funcs(struct ipath_devdata *);
649 /* init HT-400-specific func */
650 void ipath_init_ht400_funcs(struct ipath_devdata *);
651 void ipath_get_eeprom_info(struct ipath_devdata *);
652 u64 ipath_snap_cntr(struct ipath_devdata *, ipath_creg);
655 * number of words used for protocol header if not set by ipath_userinit();
657 #define IPATH_DFLT_RCVHDRSIZE 9
659 #define IPATH_MDIO_CMD_WRITE 1
660 #define IPATH_MDIO_CMD_READ 2
661 #define IPATH_MDIO_CLD_DIV 25 /* to get 2.5 Mhz mdio clock */
662 #define IPATH_MDIO_CMDVALID 0x40000000 /* bit 30 */
663 #define IPATH_MDIO_DATAVALID 0x80000000 /* bit 31 */
664 #define IPATH_MDIO_CTRL_STD 0x0
666 static inline u64 ipath_mdio_req(int cmd, int dev, int reg, int data)
668 return (((u64) IPATH_MDIO_CLD_DIV) << 32) |
675 /* signal and fifo status, in bank 31 */
676 #define IPATH_MDIO_CTRL_XGXS_REG_8 0x8
677 /* controls loopback, redundancy */
678 #define IPATH_MDIO_CTRL_8355_REG_1 0x10
679 /* premph, encdec, etc. */
680 #define IPATH_MDIO_CTRL_8355_REG_2 0x11
682 #define IPATH_MDIO_CTRL_8355_REG_6 0x15
683 #define IPATH_MDIO_CTRL_8355_REG_9 0x18
684 #define IPATH_MDIO_CTRL_8355_REG_10 0x1D
686 int ipath_get_user_pages(unsigned long, size_t, struct page **);
687 int ipath_get_user_pages_nocopy(unsigned long, struct page **);
688 void ipath_release_user_pages(struct page **, size_t);
689 void ipath_release_user_pages_on_close(struct page **, size_t);
690 int ipath_eeprom_read(struct ipath_devdata *, u8, void *, int);
691 int ipath_eeprom_write(struct ipath_devdata *, u8, const void *, int);
693 /* these are used for the registers that vary with port */
694 void ipath_write_kreg_port(const struct ipath_devdata *, ipath_kreg,
696 u64 ipath_read_kreg64_port(const struct ipath_devdata *, ipath_kreg,
700 * We could have a single register get/put routine, that takes a group type,
701 * but this is somewhat clearer and cleaner. It also gives us some error
702 * checking. 64 bit register reads should always work, but are inefficient
703 * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
704 * so we use kreg32 wherever possible. User register and counter register
705 * reads are always 32 bit reads, so only one form of those routines.
709 * At the moment, none of the s-registers are writable, so no
710 * ipath_write_sreg(), and none of the c-registers are writable, so no
711 * ipath_write_creg().
715 * ipath_read_ureg32 - read 32-bit virtualized per-port register
717 * @regno: register number
720 * Return the contents of a register that is virtualized to be per port.
721 * Returns -1 on errors (not distinguishable from valid contents at
722 * runtime; we may add a separate error variable at some point).
724 static inline u32 ipath_read_ureg32(const struct ipath_devdata *dd,
725 ipath_ureg regno, int port)
727 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
730 return readl(regno + (u64 __iomem *)
731 (dd->ipath_uregbase +
732 (char __iomem *)dd->ipath_kregbase +
733 dd->ipath_palign * port));
737 * ipath_write_ureg - write 32-bit virtualized per-port register
739 * @regno: register number
743 * Write the contents of a register that is virtualized to be per port.
745 static inline void ipath_write_ureg(const struct ipath_devdata *dd,
746 ipath_ureg regno, u64 value, int port)
748 u64 __iomem *ubase = (u64 __iomem *)
749 (dd->ipath_uregbase + (char __iomem *) dd->ipath_kregbase +
750 dd->ipath_palign * port);
751 if (dd->ipath_kregbase)
752 writeq(value, &ubase[regno]);
755 static inline u32 ipath_read_kreg32(const struct ipath_devdata *dd,
758 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
760 return readl((u32 __iomem *) & dd->ipath_kregbase[regno]);
763 static inline u64 ipath_read_kreg64(const struct ipath_devdata *dd,
766 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
769 return readq(&dd->ipath_kregbase[regno]);
772 static inline void ipath_write_kreg(const struct ipath_devdata *dd,
773 ipath_kreg regno, u64 value)
775 if (dd->ipath_kregbase)
776 writeq(value, &dd->ipath_kregbase[regno]);
779 static inline u64 ipath_read_creg(const struct ipath_devdata *dd,
782 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
785 return readq(regno + (u64 __iomem *)
786 (dd->ipath_cregbase +
787 (char __iomem *)dd->ipath_kregbase));
790 static inline u32 ipath_read_creg32(const struct ipath_devdata *dd,
793 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
795 return readl(regno + (u64 __iomem *)
796 (dd->ipath_cregbase +
797 (char __iomem *)dd->ipath_kregbase));
804 struct device_driver;
806 extern const char ipath_core_version[];
808 int ipath_driver_create_group(struct device_driver *);
809 void ipath_driver_remove_group(struct device_driver *);
811 int ipath_device_create_group(struct device *, struct ipath_devdata *);
812 void ipath_device_remove_group(struct device *, struct ipath_devdata *);
813 int ipath_expose_reset(struct device *);
815 int ipath_init_ipathfs(void);
816 void ipath_exit_ipathfs(void);
817 int ipathfs_add_device(struct ipath_devdata *);
818 int ipathfs_remove_device(struct ipath_devdata *);
821 * Flush write combining store buffers (if present) and perform a write
824 #if defined(CONFIG_X86_64)
825 #define ipath_flush_wc() asm volatile("sfence" ::: "memory")
827 #define ipath_flush_wc() wmb()
830 extern unsigned ipath_debug; /* debugging bit mask */
832 const char *ipath_get_unit_name(int unit);
834 extern struct mutex ipath_mutex;
836 #define IPATH_DRV_NAME "ipath_core"
837 #define IPATH_MAJOR 233
838 #define IPATH_USER_MINOR_BASE 0
839 #define IPATH_SMA_MINOR 128
840 #define IPATH_DIAG_MINOR_BASE 129
841 #define IPATH_NMINORS 255
843 #define ipath_dev_err(dd,fmt,...) \
845 const struct ipath_devdata *__dd = (dd); \
847 dev_err(&__dd->pcidev->dev, "%s: " fmt, \
848 ipath_get_unit_name(__dd->ipath_unit), \
851 printk(KERN_ERR IPATH_DRV_NAME ": %s: " fmt, \
852 ipath_get_unit_name(__dd->ipath_unit), \
858 # define __IPATH_DBG_WHICH(which,fmt,...) \
860 if(unlikely(ipath_debug&(which))) \
861 printk(KERN_DEBUG IPATH_DRV_NAME ": %s: " fmt, \
862 __func__,##__VA_ARGS__); \
865 # define ipath_dbg(fmt,...) \
866 __IPATH_DBG_WHICH(__IPATH_DBG,fmt,##__VA_ARGS__)
867 # define ipath_cdbg(which,fmt,...) \
868 __IPATH_DBG_WHICH(__IPATH_##which##DBG,fmt,##__VA_ARGS__)
870 #else /* ! _IPATH_DEBUGGING */
872 # define ipath_dbg(fmt,...)
873 # define ipath_cdbg(which,fmt,...)
875 #endif /* _IPATH_DEBUGGING */
877 #endif /* _IPATH_KERNEL_H */