1 #ifndef _IPATH_KERNEL_H
2 #define _IPATH_KERNEL_H
4 * Copyright (c) 2006 QLogic, Inc. All rights reserved.
5 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 * This header file is the base header file for infinipath kernel code
38 * ipath_user.h serves a similar purpose for user code.
41 #include <linux/interrupt.h>
42 #include <linux/pci.h>
43 #include <linux/dma-mapping.h>
46 #include "ipath_common.h"
47 #include "ipath_debug.h"
48 #include "ipath_registers.h"
50 /* only s/w major version of InfiniPath we can handle */
51 #define IPATH_CHIP_VERS_MAJ 2U
53 /* don't care about this except printing */
54 #define IPATH_CHIP_VERS_MIN 0U
56 /* temporary, maybe always */
57 extern struct infinipath_stats ipath_stats;
59 #define IPATH_CHIP_SWVERSION IPATH_CHIP_VERS_MAJ
61 * First-cut critierion for "device is active" is
62 * two thousand dwords combined Tx, Rx traffic per
63 * 5-second interval. SMA packets are 64 dwords,
64 * and occur "a few per second", presumably each way.
66 #define IPATH_TRAFFIC_ACTIVE_THRESHOLD (2000)
68 * Struct used to indicate which errors are logged in each of the
69 * error-counters that are logged to EEPROM. A counter is incremented
70 * _once_ (saturating at 255) for each event with any bits set in
71 * the error or hwerror register masks below.
73 #define IPATH_EEP_LOG_CNT (4)
74 struct ipath_eep_log_mask {
79 struct ipath_portdata {
80 void **port_rcvegrbuf;
81 dma_addr_t *port_rcvegrbuf_phys;
82 /* rcvhdrq base, needs mmap before useful */
84 /* kernel virtual address where hdrqtail is updated */
85 void *port_rcvhdrtail_kvaddr;
87 * temp buffer for expected send setup, allocated at open, instead
90 void *port_tid_pg_list;
91 /* when waiting for rcv or pioavail */
92 wait_queue_head_t port_wait;
94 * rcvegr bufs base, physical, must fit
95 * in 44 bits so 32 bit programs mmap64 44 bit works)
97 dma_addr_t port_rcvegr_phys;
98 /* mmap of hdrq, must fit in 44 bits */
99 dma_addr_t port_rcvhdrq_phys;
100 dma_addr_t port_rcvhdrqtailaddr_phys;
102 * number of opens (including slave subports) on this instance
103 * (ignoring forks, dup, etc. for now)
107 * how much space to leave at start of eager TID entries for
108 * protocol use, on each TID
110 /* instead of calculating it */
112 /* non-zero if port is being shared. */
113 u16 port_subport_cnt;
114 /* non-zero if port is being shared. */
116 /* chip offset of PIO buffers for this port */
118 /* how many alloc_pages() chunks in port_rcvegrbuf_pages */
119 u32 port_rcvegrbuf_chunks;
120 /* how many egrbufs per chunk */
121 u32 port_rcvegrbufs_perchunk;
122 /* order for port_rcvegrbuf_pages */
123 size_t port_rcvegrbuf_size;
124 /* rcvhdrq size (for freeing) */
125 size_t port_rcvhdrq_size;
126 /* next expected TID to check when looking for free */
128 /* next expected TID to check */
129 unsigned long port_flag;
130 /* WAIT_RCV that timed out, no interrupt */
132 /* WAIT_PIO that timed out, no interrupt */
134 /* WAIT_RCV already happened, no wait */
136 /* WAIT_PIO already happened, no wait */
138 /* total number of rcvhdrqfull errors */
140 /* pid of process using this port */
142 /* same size as task_struct .comm[] */
144 /* pkeys set by this use of this port */
146 /* so file ops can get at unit */
147 struct ipath_devdata *port_dd;
148 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
149 void *subport_uregbase;
150 /* An array of pages for the eager receive buffers * N */
151 void *subport_rcvegrbuf;
152 /* An array of pages for the eager header queue entries * N */
153 void *subport_rcvhdr_base;
154 /* The version of the library which opened this port */
156 /* Bitmask of active slaves */
163 * control information for layered drivers
165 struct _ipath_layer {
169 struct ipath_skbinfo {
174 struct ipath_devdata {
175 struct list_head ipath_list;
177 struct ipath_kregs const *ipath_kregs;
178 struct ipath_cregs const *ipath_cregs;
180 /* mem-mapped pointer to base of chip regs */
181 u64 __iomem *ipath_kregbase;
182 /* end of mem-mapped chip space; range checking */
183 u64 __iomem *ipath_kregend;
184 /* physical address of chip for io_remap, etc. */
185 unsigned long ipath_physaddr;
186 /* base of memory alloced for ipath_kregbase, for free */
187 u64 *ipath_kregalloc;
189 * virtual address where port0 rcvhdrqtail updated for this unit.
190 * only written to by the chip, not the driver.
192 volatile __le64 *ipath_hdrqtailptr;
193 /* ipath_cfgports pointers */
194 struct ipath_portdata **ipath_pd;
195 /* sk_buffs used by port 0 eager receive queue */
196 struct ipath_skbinfo *ipath_port0_skbinfo;
197 /* kvirt address of 1st 2k pio buffer */
198 void __iomem *ipath_pio2kbase;
199 /* kvirt address of 1st 4k pio buffer */
200 void __iomem *ipath_pio4kbase;
202 * points to area where PIOavail registers will be DMA'ed.
203 * Has to be on a page of it's own, because the page will be
204 * mapped into user program space. This copy is *ONLY* ever
205 * written by DMA, not by the driver! Need a copy per device
206 * when we get to multiple devices
208 volatile __le64 *ipath_pioavailregs_dma;
209 /* physical address where updates occur */
210 dma_addr_t ipath_pioavailregs_phys;
211 struct _ipath_layer ipath_layer;
213 int (*ipath_f_intrsetup)(struct ipath_devdata *);
214 /* setup on-chip bus config */
215 int (*ipath_f_bus)(struct ipath_devdata *, struct pci_dev *);
216 /* hard reset chip */
217 int (*ipath_f_reset)(struct ipath_devdata *);
218 int (*ipath_f_get_boardname)(struct ipath_devdata *, char *,
220 void (*ipath_f_init_hwerrors)(struct ipath_devdata *);
221 void (*ipath_f_handle_hwerrors)(struct ipath_devdata *, char *,
223 void (*ipath_f_quiet_serdes)(struct ipath_devdata *);
224 int (*ipath_f_bringup_serdes)(struct ipath_devdata *);
225 int (*ipath_f_early_init)(struct ipath_devdata *);
226 void (*ipath_f_clear_tids)(struct ipath_devdata *, unsigned);
227 void (*ipath_f_put_tid)(struct ipath_devdata *, u64 __iomem*,
229 void (*ipath_f_tidtemplate)(struct ipath_devdata *);
230 void (*ipath_f_cleanup)(struct ipath_devdata *);
231 void (*ipath_f_setextled)(struct ipath_devdata *, u64, u64);
232 /* fill out chip-specific fields */
233 int (*ipath_f_get_base_info)(struct ipath_portdata *, void *);
235 void (*ipath_f_free_irq)(struct ipath_devdata *);
236 struct ipath_ibdev *verbs_dev;
237 struct timer_list verbs_timer;
238 /* total dwords sent (summed from counter) */
240 /* total dwords rcvd (summed from counter) */
242 /* total packets sent (summed from counter) */
244 /* total packets rcvd (summed from counter) */
246 /* ipath_statusp initially points to this. */
248 /* GUID for this interface, in network order */
251 * aggregrate of error bits reported since last cleared, for
252 * limiting of error reporting
254 ipath_err_t ipath_lasterror;
256 * aggregrate of error bits reported since last cleared, for
257 * limiting of hwerror reporting
259 ipath_err_t ipath_lasthwerror;
261 * errors masked because they occur too fast, also includes errors
262 * that are always ignored (ipath_ignorederrs)
264 ipath_err_t ipath_maskederrs;
265 /* time in jiffies at which to re-enable maskederrs */
266 unsigned long ipath_unmasktime;
268 * errors always ignored (masked), at least for a given
269 * chip/device, because they are wrong or not useful
271 ipath_err_t ipath_ignorederrs;
272 /* count of egrfull errors, combined for all ports */
273 u64 ipath_last_tidfull;
274 /* for ipath_qcheck() */
275 u64 ipath_lastport0rcv_cnt;
276 /* template for writing TIDs */
277 u64 ipath_tidtemplate;
278 /* value to write to free TIDs */
279 u64 ipath_tidinvalid;
280 /* IBA6120 rcv interrupt setup */
281 u64 ipath_rhdrhead_intr_off;
283 /* size of memory at ipath_kregbase */
285 /* number of registers used for pioavail */
287 /* IPATH_POLL, etc. */
289 /* ipath_flags driver is waiting for */
290 u32 ipath_state_wanted;
291 /* last buffer for user use, first buf for kernel use is this
293 u32 ipath_lastport_piobuf;
294 /* is a stats timer active */
295 u32 ipath_stats_timer_active;
296 /* dwords sent read from counter */
298 /* dwords received read from counter */
300 /* sent packets read from counter */
302 /* received packets read from counter */
304 /* pio bufs allocated per port */
307 * number of ports configured as max; zero is set to number chip
308 * supports, less gives more pio bufs/port, etc.
311 /* port0 rcvhdrq head offset */
313 /* count of port 0 hdrqfull errors */
314 u32 ipath_p0_hdrqfull;
317 * (*cfgports) used to suppress multiple instances of same
318 * port staying stuck at same point
320 u32 *ipath_lastrcvhdrqtails;
322 * (*cfgports) used to suppress multiple instances of same
323 * port staying stuck at same point
325 u32 *ipath_lastegrheads;
327 * index of last piobuffer we used. Speeds up searching, by
328 * starting at this point. Doesn't matter if multiple cpu's use and
329 * update, last updater is only write that matters. Whenever it
330 * wraps, we update shadow copies. Need a copy per device when we
331 * get to multiple devices
333 u32 ipath_lastpioindex;
334 /* max length of freezemsg */
337 * consecutive times we wanted a PIO buffer but were unable to
340 u32 ipath_consec_nopiobuf;
342 * hint that we should update ipath_pioavailshadow before
343 * looking for a PIO buffer
345 u32 ipath_upd_pio_shadow;
346 /* so we can rewrite it after a chip reset */
348 /* so we can rewrite it after a chip reset */
351 /* interrupt number */
353 /* HT/PCI Vendor ID (here for NodeInfo) */
355 /* HT/PCI Device ID (here for NodeInfo) */
357 /* offset in HT config space of slave/primary interface block */
358 u8 ipath_ht_slave_off;
359 /* for write combining settings */
360 unsigned long ipath_wc_cookie;
361 unsigned long ipath_wc_base;
362 unsigned long ipath_wc_len;
363 /* ref count for each pkey */
364 atomic_t ipath_pkeyrefs[4];
365 /* shadow copy of all exptids physaddr; used only by funcsim */
366 u64 *ipath_tidsimshadow;
367 /* shadow copy of struct page *'s for exp tid pages */
368 struct page **ipath_pageshadow;
369 /* shadow copy of dma handles for exp tid pages */
370 dma_addr_t *ipath_physshadow;
371 /* lock to workaround chip bug 9437 */
372 spinlock_t ipath_tid_lock;
376 * this address is mapped readonly into user processes so they can
377 * get status cheaply, whenever they want.
380 /* freeze msg if hw error put chip in freeze */
381 char *ipath_freezemsg;
382 /* pci access data structure */
383 struct pci_dev *pcidev;
384 struct cdev *user_cdev;
385 struct cdev *diag_cdev;
386 struct class_device *user_class_dev;
387 struct class_device *diag_class_dev;
388 /* timer used to prevent stats overflow, error throttling, etc. */
389 struct timer_list ipath_stats_timer;
390 /* check for stale messages in rcv queue */
391 /* only allow one intr at a time. */
392 unsigned long ipath_rcv_pending;
393 void *ipath_dummy_hdrq; /* used after port close */
394 dma_addr_t ipath_dummy_hdrq_phys;
397 * Shadow copies of registers; size indicates read access size.
398 * Most of them are readonly, but some are write-only register,
399 * where we manipulate the bits in the shadow copy, and then write
400 * the shadow copy to infinipath.
402 * We deliberately make most of these 32 bits, since they have
403 * restricted range. For any that we read, we won't to generate 32
404 * bit accesses, since Opteron will generate 2 separate 32 bit HT
405 * transactions for a 64 bit read, and we want to avoid unnecessary
409 /* This is the 64 bit group */
412 * shadow of pioavail, check to be sure it's large enough at
415 unsigned long ipath_pioavailshadow[8];
416 /* shadow of kr_gpio_out, for rmw ops */
418 /* shadow the gpio mask register */
420 /* shadow the gpio output enable, etc... */
422 /* kr_revision shadow */
425 * shadow of ibcctrl, for interrupt handling of link changes,
430 * last ibcstatus, to suppress "duplicate" status change messages,
433 u64 ipath_lastibcstat;
434 /* hwerrmask shadow */
435 ipath_err_t ipath_hwerrmask;
436 /* interrupt config reg shadow */
438 /* kr_sendpiobufbase value */
439 u64 ipath_piobufbase;
441 /* these are the "32 bit" regs */
444 * number of GUIDs in the flash for this interface; may need some
445 * rethinking for setting on other ifaces
449 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
450 * all expect bit fields to be "unsigned long"
452 /* shadow kr_rcvctrl */
453 unsigned long ipath_rcvctrl;
454 /* shadow kr_sendctrl */
455 unsigned long ipath_sendctrl;
456 /* ports waiting for PIOavail intr */
457 unsigned long ipath_portpiowait;
458 unsigned long ipath_lastcancel; /* to not count armlaunch after cancel */
460 /* value we put in kr_rcvhdrcnt */
462 /* value we put in kr_rcvhdrsize */
463 u32 ipath_rcvhdrsize;
464 /* value we put in kr_rcvhdrentsize */
465 u32 ipath_rcvhdrentsize;
466 /* offset of last entry in rcvhdrq */
468 /* kr_portcnt value */
470 /* kr_pagealign value */
472 /* number of "2KB" PIO buffers */
474 /* size in bytes of "2KB" PIO buffers */
476 /* number of "4KB" PIO buffers */
478 /* size in bytes of "4KB" PIO buffers */
480 /* kr_rcvegrbase value */
481 u32 ipath_rcvegrbase;
482 /* kr_rcvegrcnt value */
484 /* kr_rcvtidbase value */
485 u32 ipath_rcvtidbase;
486 /* kr_rcvtidcnt value */
492 /* kr_counterregbase */
494 /* shadow the control register contents */
496 /* PCI revision register (HTC rev on FPGA) */
499 /* chip address space used by 4k pio buffers */
501 /* The MTU programmed for this unit */
504 * The max size IB packet, included IB headers that we can send.
505 * Starts same as ipath_piosize, but is affected when ibmtu is
506 * changed, or by size of eager buffers
510 * ibmaxlen at init time, limited by chip and by receive buffer
511 * size. Not changed after init.
513 u32 ipath_init_ibmaxlen;
514 /* size of each rcvegrbuffer */
515 u32 ipath_rcvegrbufsize;
516 /* width (2,4,8,16,32) from HT config reg */
518 /* HT speed (200,400,800,1000) from HT config */
521 * number of sequential ibcstatus change for polling active/quiet
522 * (i.e., link not coming up).
525 /* low and high portions of MSI capability/vector */
527 /* saved after PCIe init for restore after reset */
529 /* MSI data (vector) saved for restore */
531 /* MLID programmed for this instance */
533 /* LID programmed for this instance */
535 /* list of pkeys programmed; 0 if not set */
538 * ASCII serial number, from flash, large enough for original
539 * all digit strings, and longer QLogic serial number format
542 /* human readable board version */
543 u8 ipath_boardversion[80];
544 /* chip major rev, from ipath_revision */
546 /* chip minor rev, from ipath_revision */
548 /* board rev, from ipath_revision */
550 /* unit # of this chip, if present */
552 /* saved for restore after reset */
553 u8 ipath_pci_cacheline;
554 /* LID mask control */
556 /* Rx Polarity inversion (compensate for ~tx on partner) */
559 /* local link integrity counter */
560 u32 ipath_lli_counter;
561 /* local link integrity errors */
562 u32 ipath_lli_errors;
564 * Above counts only cases where _successive_ LocalLinkIntegrity
565 * errors were seen in the receive headers of kern-packets.
566 * Below are the three (monotonically increasing) counters
567 * maintained via GPIO interrupts on iba6120-rev2.
569 u32 ipath_rxfc_unsupvl_errs;
570 u32 ipath_overrun_thresh_errs;
574 * Not all devices managed by a driver instance are the same
575 * type, so these fields must be per-device.
577 u64 ipath_i_bitsextant;
578 ipath_err_t ipath_e_bitsextant;
579 ipath_err_t ipath_hwe_bitsextant;
582 * Below should be computable from number of ports,
583 * since they are never modified.
585 u32 ipath_i_rcvavail_mask;
586 u32 ipath_i_rcvurg_mask;
589 * Register bits for selecting i2c direction and values, used for
592 u16 ipath_gpio_sda_num;
593 u16 ipath_gpio_scl_num;
597 /* lock for doing RMW of shadows/regs for ExtCtrl and GPIO */
598 spinlock_t ipath_gpio_lock;
600 /* used to override LED behavior */
601 u8 ipath_led_override; /* Substituted for normal value, if non-zero */
602 u16 ipath_led_override_timeoff; /* delta to next timer event */
603 u8 ipath_led_override_vals[2]; /* Alternates per blink-frame */
604 u8 ipath_led_override_phase; /* Just counts, LSB picks from vals[] */
605 atomic_t ipath_led_override_timer_active;
606 /* Used to flash LEDs in override mode */
607 struct timer_list ipath_led_override_timer;
609 /* Support (including locks) for EEPROM logging of errors and time */
610 /* control access to actual counters, timer */
611 spinlock_t ipath_eep_st_lock;
612 /* control high-level access to EEPROM */
613 struct semaphore ipath_eep_sem;
614 /* Below inc'd by ipath_snap_cntrs(), locked by ipath_eep_st_lock */
615 uint64_t ipath_traffic_wds;
616 /* active time is kept in seconds, but logged in hours */
617 atomic_t ipath_active_time;
618 /* Below are nominal shadow of EEPROM, new since last EEPROM update */
619 uint8_t ipath_eep_st_errs[IPATH_EEP_LOG_CNT];
620 uint8_t ipath_eep_st_new_errs[IPATH_EEP_LOG_CNT];
621 uint16_t ipath_eep_hrs;
623 * masks for which bits of errs, hwerrs that cause
624 * each of the counters to increment.
626 struct ipath_eep_log_mask ipath_eep_st_masks[IPATH_EEP_LOG_CNT];
629 /* Private data for file operations */
630 struct ipath_filedata {
631 struct ipath_portdata *pd;
635 extern struct list_head ipath_dev_list;
636 extern spinlock_t ipath_devs_lock;
637 extern struct ipath_devdata *ipath_lookup(int unit);
639 int ipath_init_chip(struct ipath_devdata *, int);
640 int ipath_enable_wc(struct ipath_devdata *dd);
641 void ipath_disable_wc(struct ipath_devdata *dd);
642 int ipath_count_units(int *npresentp, int *nupp, u32 *maxportsp);
643 void ipath_shutdown_device(struct ipath_devdata *);
645 struct file_operations;
646 int ipath_cdev_init(int minor, char *name, const struct file_operations *fops,
647 struct cdev **cdevp, struct class_device **class_devp);
648 void ipath_cdev_cleanup(struct cdev **cdevp,
649 struct class_device **class_devp);
651 int ipath_diag_add(struct ipath_devdata *);
652 void ipath_diag_remove(struct ipath_devdata *);
654 extern wait_queue_head_t ipath_state_wait;
656 int ipath_user_add(struct ipath_devdata *dd);
657 void ipath_user_remove(struct ipath_devdata *dd);
659 struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd, gfp_t);
661 extern int ipath_diag_inuse;
663 irqreturn_t ipath_intr(int irq, void *devid);
664 int ipath_decode_err(char *buf, size_t blen, ipath_err_t err);
665 #if __IPATH_INFO || __IPATH_DBG
666 extern const char *ipath_ibcstatus_str[];
669 /* clean up any per-chip chip-specific stuff */
670 void ipath_chip_cleanup(struct ipath_devdata *);
671 /* clean up any chip type-specific stuff */
672 void ipath_chip_done(void);
674 /* check to see if we have to force ordering for write combining */
675 int ipath_unordered_wc(void);
677 void ipath_disarm_piobufs(struct ipath_devdata *, unsigned first,
679 void ipath_cancel_sends(struct ipath_devdata *);
681 int ipath_create_rcvhdrq(struct ipath_devdata *, struct ipath_portdata *);
682 void ipath_free_pddata(struct ipath_devdata *, struct ipath_portdata *);
684 int ipath_parse_ushort(const char *str, unsigned short *valp);
686 void ipath_kreceive(struct ipath_devdata *);
687 int ipath_setrcvhdrsize(struct ipath_devdata *, unsigned);
688 int ipath_reset_device(int);
689 void ipath_get_faststats(unsigned long);
690 int ipath_set_linkstate(struct ipath_devdata *, u8);
691 int ipath_set_mtu(struct ipath_devdata *, u16);
692 int ipath_set_lid(struct ipath_devdata *, u32, u8);
693 int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv);
695 /* for use in system calls, where we want to know device type, etc. */
696 #define port_fp(fp) ((struct ipath_filedata *)(fp)->private_data)->pd
697 #define subport_fp(fp) \
698 ((struct ipath_filedata *)(fp)->private_data)->subport
699 #define tidcursor_fp(fp) \
700 ((struct ipath_filedata *)(fp)->private_data)->tidcursor
703 * values for ipath_flags
705 /* The chip is up and initted */
706 #define IPATH_INITTED 0x2
707 /* set if any user code has set kr_rcvhdrsize */
708 #define IPATH_RCVHDRSZ_SET 0x4
709 /* The chip is present and valid for accesses */
710 #define IPATH_PRESENT 0x8
711 /* HT link0 is only 8 bits wide, ignore upper byte crc
713 #define IPATH_8BIT_IN_HT0 0x10
714 /* HT link1 is only 8 bits wide, ignore upper byte crc
716 #define IPATH_8BIT_IN_HT1 0x20
717 /* The link is down */
718 #define IPATH_LINKDOWN 0x40
719 /* The link level is up (0x11) */
720 #define IPATH_LINKINIT 0x80
721 /* The link is in the armed (0x21) state */
722 #define IPATH_LINKARMED 0x100
723 /* The link is in the active (0x31) state */
724 #define IPATH_LINKACTIVE 0x200
725 /* link current state is unknown */
726 #define IPATH_LINKUNK 0x400
727 /* no IB cable, or no device on IB cable */
728 #define IPATH_NOCABLE 0x4000
729 /* Supports port zero per packet receive interrupts via
731 #define IPATH_GPIO_INTR 0x8000
732 /* uses the coded 4byte TID, not 8 byte */
733 #define IPATH_4BYTE_TID 0x10000
734 /* packet/word counters are 32 bit, else those 4 counters
736 #define IPATH_32BITCOUNTERS 0x20000
737 /* can miss port0 rx interrupts */
738 #define IPATH_POLL_RX_INTR 0x40000
739 #define IPATH_DISABLED 0x80000 /* administratively disabled */
740 /* Use GPIO interrupts for new counters */
741 #define IPATH_GPIO_ERRINTRS 0x100000
743 /* Bits in GPIO for the added interrupts */
744 #define IPATH_GPIO_PORT0_BIT 2
745 #define IPATH_GPIO_RXUVL_BIT 3
746 #define IPATH_GPIO_OVRUN_BIT 4
747 #define IPATH_GPIO_LLI_BIT 5
748 #define IPATH_GPIO_ERRINTR_MASK 0x38
750 /* portdata flag bit offsets */
751 /* waiting for a packet to arrive */
752 #define IPATH_PORT_WAITING_RCV 2
753 /* waiting for a PIO buffer to be available */
754 #define IPATH_PORT_WAITING_PIO 3
755 /* master has not finished initializing */
756 #define IPATH_PORT_MASTER_UNINIT 4
758 /* free up any allocated data at closes */
759 void ipath_free_data(struct ipath_portdata *dd);
760 int ipath_waitfor_mdio_cmdready(struct ipath_devdata *);
761 int ipath_waitfor_complete(struct ipath_devdata *, ipath_kreg, u64, u64 *);
762 u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32 *);
763 void ipath_init_iba6120_funcs(struct ipath_devdata *);
764 void ipath_init_iba6110_funcs(struct ipath_devdata *);
765 void ipath_get_eeprom_info(struct ipath_devdata *);
766 int ipath_update_eeprom_log(struct ipath_devdata *dd);
767 void ipath_inc_eeprom_err(struct ipath_devdata *dd, u32 eidx, u32 incr);
768 u64 ipath_snap_cntr(struct ipath_devdata *, ipath_creg);
769 void ipath_disarm_senderrbufs(struct ipath_devdata *, int);
772 * Set LED override, only the two LSBs have "public" meaning, but
773 * any non-zero value substitutes them for the Link and LinkTrain
776 #define IPATH_LED_PHYS 1 /* Physical (linktraining) GREEN LED */
777 #define IPATH_LED_LOG 2 /* Logical (link) YELLOW LED */
778 void ipath_set_led_override(struct ipath_devdata *dd, unsigned int val);
781 * number of words used for protocol header if not set by ipath_userinit();
783 #define IPATH_DFLT_RCVHDRSIZE 9
785 #define IPATH_MDIO_CMD_WRITE 1
786 #define IPATH_MDIO_CMD_READ 2
787 #define IPATH_MDIO_CLD_DIV 25 /* to get 2.5 Mhz mdio clock */
788 #define IPATH_MDIO_CMDVALID 0x40000000 /* bit 30 */
789 #define IPATH_MDIO_DATAVALID 0x80000000 /* bit 31 */
790 #define IPATH_MDIO_CTRL_STD 0x0
792 static inline u64 ipath_mdio_req(int cmd, int dev, int reg, int data)
794 return (((u64) IPATH_MDIO_CLD_DIV) << 32) |
801 /* signal and fifo status, in bank 31 */
802 #define IPATH_MDIO_CTRL_XGXS_REG_8 0x8
803 /* controls loopback, redundancy */
804 #define IPATH_MDIO_CTRL_8355_REG_1 0x10
805 /* premph, encdec, etc. */
806 #define IPATH_MDIO_CTRL_8355_REG_2 0x11
808 #define IPATH_MDIO_CTRL_8355_REG_6 0x15
809 #define IPATH_MDIO_CTRL_8355_REG_9 0x18
810 #define IPATH_MDIO_CTRL_8355_REG_10 0x1D
812 int ipath_get_user_pages(unsigned long, size_t, struct page **);
813 int ipath_get_user_pages_nocopy(unsigned long, struct page **);
814 void ipath_release_user_pages(struct page **, size_t);
815 void ipath_release_user_pages_on_close(struct page **, size_t);
816 int ipath_eeprom_read(struct ipath_devdata *, u8, void *, int);
817 int ipath_eeprom_write(struct ipath_devdata *, u8, const void *, int);
819 /* these are used for the registers that vary with port */
820 void ipath_write_kreg_port(const struct ipath_devdata *, ipath_kreg,
824 * We could have a single register get/put routine, that takes a group type,
825 * but this is somewhat clearer and cleaner. It also gives us some error
826 * checking. 64 bit register reads should always work, but are inefficient
827 * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
828 * so we use kreg32 wherever possible. User register and counter register
829 * reads are always 32 bit reads, so only one form of those routines.
833 * At the moment, none of the s-registers are writable, so no
834 * ipath_write_sreg(), and none of the c-registers are writable, so no
835 * ipath_write_creg().
839 * ipath_read_ureg32 - read 32-bit virtualized per-port register
841 * @regno: register number
844 * Return the contents of a register that is virtualized to be per port.
845 * Returns -1 on errors (not distinguishable from valid contents at
846 * runtime; we may add a separate error variable at some point).
848 static inline u32 ipath_read_ureg32(const struct ipath_devdata *dd,
849 ipath_ureg regno, int port)
851 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
854 return readl(regno + (u64 __iomem *)
855 (dd->ipath_uregbase +
856 (char __iomem *)dd->ipath_kregbase +
857 dd->ipath_palign * port));
861 * ipath_write_ureg - write 32-bit virtualized per-port register
863 * @regno: register number
867 * Write the contents of a register that is virtualized to be per port.
869 static inline void ipath_write_ureg(const struct ipath_devdata *dd,
870 ipath_ureg regno, u64 value, int port)
872 u64 __iomem *ubase = (u64 __iomem *)
873 (dd->ipath_uregbase + (char __iomem *) dd->ipath_kregbase +
874 dd->ipath_palign * port);
875 if (dd->ipath_kregbase)
876 writeq(value, &ubase[regno]);
879 static inline u32 ipath_read_kreg32(const struct ipath_devdata *dd,
882 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
884 return readl((u32 __iomem *) & dd->ipath_kregbase[regno]);
887 static inline u64 ipath_read_kreg64(const struct ipath_devdata *dd,
890 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
893 return readq(&dd->ipath_kregbase[regno]);
896 static inline void ipath_write_kreg(const struct ipath_devdata *dd,
897 ipath_kreg regno, u64 value)
899 if (dd->ipath_kregbase)
900 writeq(value, &dd->ipath_kregbase[regno]);
903 static inline u64 ipath_read_creg(const struct ipath_devdata *dd,
906 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
909 return readq(regno + (u64 __iomem *)
910 (dd->ipath_cregbase +
911 (char __iomem *)dd->ipath_kregbase));
914 static inline u32 ipath_read_creg32(const struct ipath_devdata *dd,
917 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
919 return readl(regno + (u64 __iomem *)
920 (dd->ipath_cregbase +
921 (char __iomem *)dd->ipath_kregbase));
928 struct device_driver;
930 extern const char ib_ipath_version[];
932 int ipath_driver_create_group(struct device_driver *);
933 void ipath_driver_remove_group(struct device_driver *);
935 int ipath_device_create_group(struct device *, struct ipath_devdata *);
936 void ipath_device_remove_group(struct device *, struct ipath_devdata *);
937 int ipath_expose_reset(struct device *);
939 int ipath_init_ipathfs(void);
940 void ipath_exit_ipathfs(void);
941 int ipathfs_add_device(struct ipath_devdata *);
942 int ipathfs_remove_device(struct ipath_devdata *);
945 * dma_addr wrappers - all 0's invalid for hw
947 dma_addr_t ipath_map_page(struct pci_dev *, struct page *, unsigned long,
949 dma_addr_t ipath_map_single(struct pci_dev *, void *, size_t, int);
952 * Flush write combining store buffers (if present) and perform a write
955 #if defined(CONFIG_X86_64)
956 #define ipath_flush_wc() asm volatile("sfence" ::: "memory")
958 #define ipath_flush_wc() wmb()
961 extern unsigned ipath_debug; /* debugging bit mask */
963 #define IPATH_MAX_PARITY_ATTEMPTS 10000 /* max times to try recovery */
965 const char *ipath_get_unit_name(int unit);
967 extern struct mutex ipath_mutex;
969 #define IPATH_DRV_NAME "ib_ipath"
970 #define IPATH_MAJOR 233
971 #define IPATH_USER_MINOR_BASE 0
972 #define IPATH_DIAGPKT_MINOR 127
973 #define IPATH_DIAG_MINOR_BASE 129
974 #define IPATH_NMINORS 255
976 #define ipath_dev_err(dd,fmt,...) \
978 const struct ipath_devdata *__dd = (dd); \
980 dev_err(&__dd->pcidev->dev, "%s: " fmt, \
981 ipath_get_unit_name(__dd->ipath_unit), \
984 printk(KERN_ERR IPATH_DRV_NAME ": %s: " fmt, \
985 ipath_get_unit_name(__dd->ipath_unit), \
991 # define __IPATH_DBG_WHICH(which,fmt,...) \
993 if(unlikely(ipath_debug&(which))) \
994 printk(KERN_DEBUG IPATH_DRV_NAME ": %s: " fmt, \
995 __func__,##__VA_ARGS__); \
998 # define ipath_dbg(fmt,...) \
999 __IPATH_DBG_WHICH(__IPATH_DBG,fmt,##__VA_ARGS__)
1000 # define ipath_cdbg(which,fmt,...) \
1001 __IPATH_DBG_WHICH(__IPATH_##which##DBG,fmt,##__VA_ARGS__)
1003 #else /* ! _IPATH_DEBUGGING */
1005 # define ipath_dbg(fmt,...)
1006 # define ipath_cdbg(which,fmt,...)
1008 #endif /* _IPATH_DEBUGGING */
1011 * this is used for formatting hw error messages...
1013 struct ipath_hwerror_msgs {
1018 #define INFINIPATH_HWE_MSG(a, b) { .mask = INFINIPATH_HWE_##a, .msg = b }
1020 /* in ipath_intr.c... */
1021 void ipath_format_hwerrors(u64 hwerrs,
1022 const struct ipath_hwerror_msgs *hwerrmsgs,
1024 char *msg, size_t lmsg);
1026 #endif /* _IPATH_KERNEL_H */