1 #ifndef _IPATH_KERNEL_H
2 #define _IPATH_KERNEL_H
4 * Copyright (c) 2006 QLogic, Inc. All rights reserved.
5 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 * This header file is the base header file for infinipath kernel code
38 * ipath_user.h serves a similar purpose for user code.
41 #include <linux/interrupt.h>
42 #include <linux/pci.h>
43 #include <linux/dma-mapping.h>
46 #include "ipath_common.h"
47 #include "ipath_debug.h"
48 #include "ipath_registers.h"
50 /* only s/w major version of InfiniPath we can handle */
51 #define IPATH_CHIP_VERS_MAJ 2U
53 /* don't care about this except printing */
54 #define IPATH_CHIP_VERS_MIN 0U
56 /* temporary, maybe always */
57 extern struct infinipath_stats ipath_stats;
59 #define IPATH_CHIP_SWVERSION IPATH_CHIP_VERS_MAJ
61 struct ipath_portdata {
62 void **port_rcvegrbuf;
63 dma_addr_t *port_rcvegrbuf_phys;
64 /* rcvhdrq base, needs mmap before useful */
66 /* kernel virtual address where hdrqtail is updated */
67 void *port_rcvhdrtail_kvaddr;
69 * temp buffer for expected send setup, allocated at open, instead
72 void *port_tid_pg_list;
73 /* when waiting for rcv or pioavail */
74 wait_queue_head_t port_wait;
76 * rcvegr bufs base, physical, must fit
77 * in 44 bits so 32 bit programs mmap64 44 bit works)
79 dma_addr_t port_rcvegr_phys;
80 /* mmap of hdrq, must fit in 44 bits */
81 dma_addr_t port_rcvhdrq_phys;
82 dma_addr_t port_rcvhdrqtailaddr_phys;
84 * number of opens (including slave subports) on this instance
85 * (ignoring forks, dup, etc. for now)
89 * how much space to leave at start of eager TID entries for
90 * protocol use, on each TID
92 /* instead of calculating it */
94 /* non-zero if port is being shared. */
96 /* non-zero if port is being shared. */
98 /* chip offset of PIO buffers for this port */
100 /* how many alloc_pages() chunks in port_rcvegrbuf_pages */
101 u32 port_rcvegrbuf_chunks;
102 /* how many egrbufs per chunk */
103 u32 port_rcvegrbufs_perchunk;
104 /* order for port_rcvegrbuf_pages */
105 size_t port_rcvegrbuf_size;
106 /* rcvhdrq size (for freeing) */
107 size_t port_rcvhdrq_size;
108 /* next expected TID to check when looking for free */
110 /* next expected TID to check */
111 unsigned long port_flag;
112 /* WAIT_RCV that timed out, no interrupt */
114 /* WAIT_PIO that timed out, no interrupt */
116 /* WAIT_RCV already happened, no wait */
118 /* WAIT_PIO already happened, no wait */
120 /* total number of rcvhdrqfull errors */
122 /* pid of process using this port */
124 /* same size as task_struct .comm[] */
126 /* pkeys set by this use of this port */
128 /* so file ops can get at unit */
129 struct ipath_devdata *port_dd;
130 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
131 void *subport_uregbase;
132 /* An array of pages for the eager receive buffers * N */
133 void *subport_rcvegrbuf;
134 /* An array of pages for the eager header queue entries * N */
135 void *subport_rcvhdr_base;
136 /* The version of the library which opened this port */
138 /* Bitmask of active slaves */
145 * control information for layered drivers
147 struct _ipath_layer {
151 struct ipath_skbinfo {
156 struct ipath_devdata {
157 struct list_head ipath_list;
159 struct ipath_kregs const *ipath_kregs;
160 struct ipath_cregs const *ipath_cregs;
162 /* mem-mapped pointer to base of chip regs */
163 u64 __iomem *ipath_kregbase;
164 /* end of mem-mapped chip space; range checking */
165 u64 __iomem *ipath_kregend;
166 /* physical address of chip for io_remap, etc. */
167 unsigned long ipath_physaddr;
168 /* base of memory alloced for ipath_kregbase, for free */
169 u64 *ipath_kregalloc;
171 * virtual address where port0 rcvhdrqtail updated for this unit.
172 * only written to by the chip, not the driver.
174 volatile __le64 *ipath_hdrqtailptr;
175 /* ipath_cfgports pointers */
176 struct ipath_portdata **ipath_pd;
177 /* sk_buffs used by port 0 eager receive queue */
178 struct ipath_skbinfo *ipath_port0_skbinfo;
179 /* kvirt address of 1st 2k pio buffer */
180 void __iomem *ipath_pio2kbase;
181 /* kvirt address of 1st 4k pio buffer */
182 void __iomem *ipath_pio4kbase;
184 * points to area where PIOavail registers will be DMA'ed.
185 * Has to be on a page of it's own, because the page will be
186 * mapped into user program space. This copy is *ONLY* ever
187 * written by DMA, not by the driver! Need a copy per device
188 * when we get to multiple devices
190 volatile __le64 *ipath_pioavailregs_dma;
191 /* physical address where updates occur */
192 dma_addr_t ipath_pioavailregs_phys;
193 struct _ipath_layer ipath_layer;
195 int (*ipath_f_intrsetup)(struct ipath_devdata *);
196 /* setup on-chip bus config */
197 int (*ipath_f_bus)(struct ipath_devdata *, struct pci_dev *);
198 /* hard reset chip */
199 int (*ipath_f_reset)(struct ipath_devdata *);
200 int (*ipath_f_get_boardname)(struct ipath_devdata *, char *,
202 void (*ipath_f_init_hwerrors)(struct ipath_devdata *);
203 void (*ipath_f_handle_hwerrors)(struct ipath_devdata *, char *,
205 void (*ipath_f_quiet_serdes)(struct ipath_devdata *);
206 int (*ipath_f_bringup_serdes)(struct ipath_devdata *);
207 int (*ipath_f_early_init)(struct ipath_devdata *);
208 void (*ipath_f_clear_tids)(struct ipath_devdata *, unsigned);
209 void (*ipath_f_put_tid)(struct ipath_devdata *, u64 __iomem*,
211 void (*ipath_f_tidtemplate)(struct ipath_devdata *);
212 void (*ipath_f_cleanup)(struct ipath_devdata *);
213 void (*ipath_f_setextled)(struct ipath_devdata *, u64, u64);
214 /* fill out chip-specific fields */
215 int (*ipath_f_get_base_info)(struct ipath_portdata *, void *);
216 struct ipath_ibdev *verbs_dev;
217 struct timer_list verbs_timer;
218 /* total dwords sent (summed from counter) */
220 /* total dwords rcvd (summed from counter) */
222 /* total packets sent (summed from counter) */
224 /* total packets rcvd (summed from counter) */
226 /* ipath_statusp initially points to this. */
228 /* GUID for this interface, in network order */
231 * aggregrate of error bits reported since last cleared, for
232 * limiting of error reporting
234 ipath_err_t ipath_lasterror;
236 * aggregrate of error bits reported since last cleared, for
237 * limiting of hwerror reporting
239 ipath_err_t ipath_lasthwerror;
241 * errors masked because they occur too fast, also includes errors
242 * that are always ignored (ipath_ignorederrs)
244 ipath_err_t ipath_maskederrs;
245 /* time in jiffies at which to re-enable maskederrs */
246 unsigned long ipath_unmasktime;
248 * errors always ignored (masked), at least for a given
249 * chip/device, because they are wrong or not useful
251 ipath_err_t ipath_ignorederrs;
252 /* count of egrfull errors, combined for all ports */
253 u64 ipath_last_tidfull;
254 /* for ipath_qcheck() */
255 u64 ipath_lastport0rcv_cnt;
256 /* template for writing TIDs */
257 u64 ipath_tidtemplate;
258 /* value to write to free TIDs */
259 u64 ipath_tidinvalid;
260 /* IBA6120 rcv interrupt setup */
261 u64 ipath_rhdrhead_intr_off;
263 /* size of memory at ipath_kregbase */
265 /* number of registers used for pioavail */
267 /* IPATH_POLL, etc. */
269 /* ipath_flags driver is waiting for */
270 u32 ipath_state_wanted;
271 /* last buffer for user use, first buf for kernel use is this
273 u32 ipath_lastport_piobuf;
274 /* is a stats timer active */
275 u32 ipath_stats_timer_active;
276 /* dwords sent read from counter */
278 /* dwords received read from counter */
280 /* sent packets read from counter */
282 /* received packets read from counter */
284 /* pio bufs allocated per port */
287 * number of ports configured as max; zero is set to number chip
288 * supports, less gives more pio bufs/port, etc.
291 /* port0 rcvhdrq head offset */
293 /* count of port 0 hdrqfull errors */
294 u32 ipath_p0_hdrqfull;
297 * (*cfgports) used to suppress multiple instances of same
298 * port staying stuck at same point
300 u32 *ipath_lastrcvhdrqtails;
302 * (*cfgports) used to suppress multiple instances of same
303 * port staying stuck at same point
305 u32 *ipath_lastegrheads;
307 * index of last piobuffer we used. Speeds up searching, by
308 * starting at this point. Doesn't matter if multiple cpu's use and
309 * update, last updater is only write that matters. Whenever it
310 * wraps, we update shadow copies. Need a copy per device when we
311 * get to multiple devices
313 u32 ipath_lastpioindex;
314 /* max length of freezemsg */
317 * consecutive times we wanted a PIO buffer but were unable to
320 u32 ipath_consec_nopiobuf;
322 * hint that we should update ipath_pioavailshadow before
323 * looking for a PIO buffer
325 u32 ipath_upd_pio_shadow;
326 /* so we can rewrite it after a chip reset */
328 /* so we can rewrite it after a chip reset */
331 /* HT/PCI Vendor ID (here for NodeInfo) */
333 /* HT/PCI Device ID (here for NodeInfo) */
335 /* offset in HT config space of slave/primary interface block */
336 u8 ipath_ht_slave_off;
337 /* for write combining settings */
338 unsigned long ipath_wc_cookie;
339 /* ref count for each pkey */
340 atomic_t ipath_pkeyrefs[4];
341 /* shadow copy of all exptids physaddr; used only by funcsim */
342 u64 *ipath_tidsimshadow;
343 /* shadow copy of struct page *'s for exp tid pages */
344 struct page **ipath_pageshadow;
345 /* shadow copy of dma handles for exp tid pages */
346 dma_addr_t *ipath_physshadow;
347 /* lock to workaround chip bug 9437 */
348 spinlock_t ipath_tid_lock;
352 * this address is mapped readonly into user processes so they can
353 * get status cheaply, whenever they want.
356 /* freeze msg if hw error put chip in freeze */
357 char *ipath_freezemsg;
358 /* pci access data structure */
359 struct pci_dev *pcidev;
360 struct cdev *user_cdev;
361 struct cdev *diag_cdev;
362 struct class_device *user_class_dev;
363 struct class_device *diag_class_dev;
364 /* timer used to prevent stats overflow, error throttling, etc. */
365 struct timer_list ipath_stats_timer;
366 /* check for stale messages in rcv queue */
367 /* only allow one intr at a time. */
368 unsigned long ipath_rcv_pending;
369 void *ipath_dummy_hdrq; /* used after port close */
370 dma_addr_t ipath_dummy_hdrq_phys;
373 * Shadow copies of registers; size indicates read access size.
374 * Most of them are readonly, but some are write-only register,
375 * where we manipulate the bits in the shadow copy, and then write
376 * the shadow copy to infinipath.
378 * We deliberately make most of these 32 bits, since they have
379 * restricted range. For any that we read, we won't to generate 32
380 * bit accesses, since Opteron will generate 2 separate 32 bit HT
381 * transactions for a 64 bit read, and we want to avoid unnecessary
385 /* This is the 64 bit group */
388 * shadow of pioavail, check to be sure it's large enough at
391 unsigned long ipath_pioavailshadow[8];
392 /* shadow of kr_gpio_out, for rmw ops */
394 /* kr_revision shadow */
397 * shadow of ibcctrl, for interrupt handling of link changes,
402 * last ibcstatus, to suppress "duplicate" status change messages,
405 u64 ipath_lastibcstat;
406 /* hwerrmask shadow */
407 ipath_err_t ipath_hwerrmask;
408 /* interrupt config reg shadow */
410 /* kr_sendpiobufbase value */
411 u64 ipath_piobufbase;
413 /* these are the "32 bit" regs */
416 * number of GUIDs in the flash for this interface; may need some
417 * rethinking for setting on other ifaces
421 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
422 * all expect bit fields to be "unsigned long"
424 /* shadow kr_rcvctrl */
425 unsigned long ipath_rcvctrl;
426 /* shadow kr_sendctrl */
427 unsigned long ipath_sendctrl;
429 /* value we put in kr_rcvhdrcnt */
431 /* value we put in kr_rcvhdrsize */
432 u32 ipath_rcvhdrsize;
433 /* value we put in kr_rcvhdrentsize */
434 u32 ipath_rcvhdrentsize;
435 /* offset of last entry in rcvhdrq */
437 /* kr_portcnt value */
439 /* kr_pagealign value */
441 /* number of "2KB" PIO buffers */
443 /* size in bytes of "2KB" PIO buffers */
445 /* number of "4KB" PIO buffers */
447 /* size in bytes of "4KB" PIO buffers */
449 /* kr_rcvegrbase value */
450 u32 ipath_rcvegrbase;
451 /* kr_rcvegrcnt value */
453 /* kr_rcvtidbase value */
454 u32 ipath_rcvtidbase;
455 /* kr_rcvtidcnt value */
461 /* kr_counterregbase */
463 /* shadow the control register contents */
465 /* shadow the gpio output contents */
467 /* PCI revision register (HTC rev on FPGA) */
470 /* chip address space used by 4k pio buffers */
472 /* The MTU programmed for this unit */
475 * The max size IB packet, included IB headers that we can send.
476 * Starts same as ipath_piosize, but is affected when ibmtu is
477 * changed, or by size of eager buffers
481 * ibmaxlen at init time, limited by chip and by receive buffer
482 * size. Not changed after init.
484 u32 ipath_init_ibmaxlen;
485 /* size of each rcvegrbuffer */
486 u32 ipath_rcvegrbufsize;
487 /* width (2,4,8,16,32) from HT config reg */
489 /* HT speed (200,400,800,1000) from HT config */
491 /* ports waiting for PIOavail intr */
492 unsigned long ipath_portpiowait;
494 * number of sequential ibcstatus change for polling active/quiet
495 * (i.e., link not coming up).
498 /* low and high portions of MSI capability/vector */
500 /* saved after PCIe init for restore after reset */
502 /* MSI data (vector) saved for restore */
504 /* MLID programmed for this instance */
506 /* LID programmed for this instance */
508 /* list of pkeys programmed; 0 if not set */
511 * ASCII serial number, from flash, large enough for original
512 * all digit strings, and longer QLogic serial number format
515 /* human readable board version */
516 u8 ipath_boardversion[80];
517 /* chip major rev, from ipath_revision */
519 /* chip minor rev, from ipath_revision */
521 /* board rev, from ipath_revision */
523 /* unit # of this chip, if present */
525 /* saved for restore after reset */
526 u8 ipath_pci_cacheline;
527 /* LID mask control */
529 /* Rx Polarity inversion (compensate for ~tx on partner) */
532 /* local link integrity counter */
533 u32 ipath_lli_counter;
534 /* local link integrity errors */
535 u32 ipath_lli_errors;
537 * Above counts only cases where _successive_ LocalLinkIntegrity
538 * errors were seen in the receive headers of kern-packets.
539 * Below are the three (monotonically increasing) counters
540 * maintained via GPIO interrupts on iba6120-rev2.
542 u32 ipath_rxfc_unsupvl_errs;
543 u32 ipath_overrun_thresh_errs;
547 * Not all devices managed by a driver instance are the same
548 * type, so these fields must be per-device.
550 u64 ipath_i_bitsextant;
551 ipath_err_t ipath_e_bitsextant;
552 ipath_err_t ipath_hwe_bitsextant;
555 * Below should be computable from number of ports,
556 * since they are never modified.
558 u32 ipath_i_rcvavail_mask;
559 u32 ipath_i_rcvurg_mask;
562 * Register bits for selecting i2c direction and values, used for
565 u16 ipath_gpio_sda_num;
566 u16 ipath_gpio_scl_num;
571 /* Private data for file operations */
572 struct ipath_filedata {
573 struct ipath_portdata *pd;
577 extern struct list_head ipath_dev_list;
578 extern spinlock_t ipath_devs_lock;
579 extern struct ipath_devdata *ipath_lookup(int unit);
581 int ipath_init_chip(struct ipath_devdata *, int);
582 int ipath_enable_wc(struct ipath_devdata *dd);
583 void ipath_disable_wc(struct ipath_devdata *dd);
584 int ipath_count_units(int *npresentp, int *nupp, u32 *maxportsp);
585 void ipath_shutdown_device(struct ipath_devdata *);
587 struct file_operations;
588 int ipath_cdev_init(int minor, char *name, struct file_operations *fops,
589 struct cdev **cdevp, struct class_device **class_devp);
590 void ipath_cdev_cleanup(struct cdev **cdevp,
591 struct class_device **class_devp);
593 int ipath_diag_add(struct ipath_devdata *);
594 void ipath_diag_remove(struct ipath_devdata *);
596 extern wait_queue_head_t ipath_state_wait;
598 int ipath_user_add(struct ipath_devdata *dd);
599 void ipath_user_remove(struct ipath_devdata *dd);
601 struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd, gfp_t);
603 extern int ipath_diag_inuse;
605 irqreturn_t ipath_intr(int irq, void *devid, struct pt_regs *regs);
606 void ipath_decode_err(char *buf, size_t blen, ipath_err_t err);
607 #if __IPATH_INFO || __IPATH_DBG
608 extern const char *ipath_ibcstatus_str[];
611 /* clean up any per-chip chip-specific stuff */
612 void ipath_chip_cleanup(struct ipath_devdata *);
613 /* clean up any chip type-specific stuff */
614 void ipath_chip_done(void);
616 /* check to see if we have to force ordering for write combining */
617 int ipath_unordered_wc(void);
619 void ipath_disarm_piobufs(struct ipath_devdata *, unsigned first,
622 int ipath_create_rcvhdrq(struct ipath_devdata *, struct ipath_portdata *);
623 void ipath_free_pddata(struct ipath_devdata *, struct ipath_portdata *);
625 int ipath_parse_ushort(const char *str, unsigned short *valp);
627 void ipath_kreceive(struct ipath_devdata *);
628 int ipath_setrcvhdrsize(struct ipath_devdata *, unsigned);
629 int ipath_reset_device(int);
630 void ipath_get_faststats(unsigned long);
631 int ipath_set_linkstate(struct ipath_devdata *, u8);
632 int ipath_set_mtu(struct ipath_devdata *, u16);
633 int ipath_set_lid(struct ipath_devdata *, u32, u8);
634 int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv);
636 /* for use in system calls, where we want to know device type, etc. */
637 #define port_fp(fp) ((struct ipath_filedata *)(fp)->private_data)->pd
638 #define subport_fp(fp) \
639 ((struct ipath_filedata *)(fp)->private_data)->subport
640 #define tidcursor_fp(fp) \
641 ((struct ipath_filedata *)(fp)->private_data)->tidcursor
644 * values for ipath_flags
646 /* The chip is up and initted */
647 #define IPATH_INITTED 0x2
648 /* set if any user code has set kr_rcvhdrsize */
649 #define IPATH_RCVHDRSZ_SET 0x4
650 /* The chip is present and valid for accesses */
651 #define IPATH_PRESENT 0x8
652 /* HT link0 is only 8 bits wide, ignore upper byte crc
654 #define IPATH_8BIT_IN_HT0 0x10
655 /* HT link1 is only 8 bits wide, ignore upper byte crc
657 #define IPATH_8BIT_IN_HT1 0x20
658 /* The link is down */
659 #define IPATH_LINKDOWN 0x40
660 /* The link level is up (0x11) */
661 #define IPATH_LINKINIT 0x80
662 /* The link is in the armed (0x21) state */
663 #define IPATH_LINKARMED 0x100
664 /* The link is in the active (0x31) state */
665 #define IPATH_LINKACTIVE 0x200
666 /* link current state is unknown */
667 #define IPATH_LINKUNK 0x400
668 /* no IB cable, or no device on IB cable */
669 #define IPATH_NOCABLE 0x4000
670 /* Supports port zero per packet receive interrupts via
672 #define IPATH_GPIO_INTR 0x8000
673 /* uses the coded 4byte TID, not 8 byte */
674 #define IPATH_4BYTE_TID 0x10000
675 /* packet/word counters are 32 bit, else those 4 counters
677 #define IPATH_32BITCOUNTERS 0x20000
678 /* can miss port0 rx interrupts */
679 #define IPATH_POLL_RX_INTR 0x40000
680 #define IPATH_DISABLED 0x80000 /* administratively disabled */
681 /* Use GPIO interrupts for new counters */
682 #define IPATH_GPIO_ERRINTRS 0x100000
684 /* Bits in GPIO for the added interrupts */
685 #define IPATH_GPIO_PORT0_BIT 2
686 #define IPATH_GPIO_RXUVL_BIT 3
687 #define IPATH_GPIO_OVRUN_BIT 4
688 #define IPATH_GPIO_LLI_BIT 5
689 #define IPATH_GPIO_ERRINTR_MASK 0x38
691 /* portdata flag bit offsets */
692 /* waiting for a packet to arrive */
693 #define IPATH_PORT_WAITING_RCV 2
694 /* waiting for a PIO buffer to be available */
695 #define IPATH_PORT_WAITING_PIO 3
697 /* free up any allocated data at closes */
698 void ipath_free_data(struct ipath_portdata *dd);
699 int ipath_waitfor_mdio_cmdready(struct ipath_devdata *);
700 int ipath_waitfor_complete(struct ipath_devdata *, ipath_kreg, u64, u64 *);
701 u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32 *);
702 void ipath_init_iba6120_funcs(struct ipath_devdata *);
703 void ipath_init_iba6110_funcs(struct ipath_devdata *);
704 void ipath_get_eeprom_info(struct ipath_devdata *);
705 u64 ipath_snap_cntr(struct ipath_devdata *, ipath_creg);
708 * number of words used for protocol header if not set by ipath_userinit();
710 #define IPATH_DFLT_RCVHDRSIZE 9
712 #define IPATH_MDIO_CMD_WRITE 1
713 #define IPATH_MDIO_CMD_READ 2
714 #define IPATH_MDIO_CLD_DIV 25 /* to get 2.5 Mhz mdio clock */
715 #define IPATH_MDIO_CMDVALID 0x40000000 /* bit 30 */
716 #define IPATH_MDIO_DATAVALID 0x80000000 /* bit 31 */
717 #define IPATH_MDIO_CTRL_STD 0x0
719 static inline u64 ipath_mdio_req(int cmd, int dev, int reg, int data)
721 return (((u64) IPATH_MDIO_CLD_DIV) << 32) |
728 /* signal and fifo status, in bank 31 */
729 #define IPATH_MDIO_CTRL_XGXS_REG_8 0x8
730 /* controls loopback, redundancy */
731 #define IPATH_MDIO_CTRL_8355_REG_1 0x10
732 /* premph, encdec, etc. */
733 #define IPATH_MDIO_CTRL_8355_REG_2 0x11
735 #define IPATH_MDIO_CTRL_8355_REG_6 0x15
736 #define IPATH_MDIO_CTRL_8355_REG_9 0x18
737 #define IPATH_MDIO_CTRL_8355_REG_10 0x1D
739 int ipath_get_user_pages(unsigned long, size_t, struct page **);
740 int ipath_get_user_pages_nocopy(unsigned long, struct page **);
741 void ipath_release_user_pages(struct page **, size_t);
742 void ipath_release_user_pages_on_close(struct page **, size_t);
743 int ipath_eeprom_read(struct ipath_devdata *, u8, void *, int);
744 int ipath_eeprom_write(struct ipath_devdata *, u8, const void *, int);
746 /* these are used for the registers that vary with port */
747 void ipath_write_kreg_port(const struct ipath_devdata *, ipath_kreg,
749 u64 ipath_read_kreg64_port(const struct ipath_devdata *, ipath_kreg,
753 * We could have a single register get/put routine, that takes a group type,
754 * but this is somewhat clearer and cleaner. It also gives us some error
755 * checking. 64 bit register reads should always work, but are inefficient
756 * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
757 * so we use kreg32 wherever possible. User register and counter register
758 * reads are always 32 bit reads, so only one form of those routines.
762 * At the moment, none of the s-registers are writable, so no
763 * ipath_write_sreg(), and none of the c-registers are writable, so no
764 * ipath_write_creg().
768 * ipath_read_ureg32 - read 32-bit virtualized per-port register
770 * @regno: register number
773 * Return the contents of a register that is virtualized to be per port.
774 * Returns -1 on errors (not distinguishable from valid contents at
775 * runtime; we may add a separate error variable at some point).
777 static inline u32 ipath_read_ureg32(const struct ipath_devdata *dd,
778 ipath_ureg regno, int port)
780 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
783 return readl(regno + (u64 __iomem *)
784 (dd->ipath_uregbase +
785 (char __iomem *)dd->ipath_kregbase +
786 dd->ipath_palign * port));
790 * ipath_write_ureg - write 32-bit virtualized per-port register
792 * @regno: register number
796 * Write the contents of a register that is virtualized to be per port.
798 static inline void ipath_write_ureg(const struct ipath_devdata *dd,
799 ipath_ureg regno, u64 value, int port)
801 u64 __iomem *ubase = (u64 __iomem *)
802 (dd->ipath_uregbase + (char __iomem *) dd->ipath_kregbase +
803 dd->ipath_palign * port);
804 if (dd->ipath_kregbase)
805 writeq(value, &ubase[regno]);
808 static inline u32 ipath_read_kreg32(const struct ipath_devdata *dd,
811 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
813 return readl((u32 __iomem *) & dd->ipath_kregbase[regno]);
816 static inline u64 ipath_read_kreg64(const struct ipath_devdata *dd,
819 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
822 return readq(&dd->ipath_kregbase[regno]);
825 static inline void ipath_write_kreg(const struct ipath_devdata *dd,
826 ipath_kreg regno, u64 value)
828 if (dd->ipath_kregbase)
829 writeq(value, &dd->ipath_kregbase[regno]);
832 static inline u64 ipath_read_creg(const struct ipath_devdata *dd,
835 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
838 return readq(regno + (u64 __iomem *)
839 (dd->ipath_cregbase +
840 (char __iomem *)dd->ipath_kregbase));
843 static inline u32 ipath_read_creg32(const struct ipath_devdata *dd,
846 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
848 return readl(regno + (u64 __iomem *)
849 (dd->ipath_cregbase +
850 (char __iomem *)dd->ipath_kregbase));
857 struct device_driver;
859 extern const char ib_ipath_version[];
861 int ipath_driver_create_group(struct device_driver *);
862 void ipath_driver_remove_group(struct device_driver *);
864 int ipath_device_create_group(struct device *, struct ipath_devdata *);
865 void ipath_device_remove_group(struct device *, struct ipath_devdata *);
866 int ipath_expose_reset(struct device *);
868 int ipath_diagpkt_add(void);
869 void ipath_diagpkt_remove(void);
871 int ipath_init_ipathfs(void);
872 void ipath_exit_ipathfs(void);
873 int ipathfs_add_device(struct ipath_devdata *);
874 int ipathfs_remove_device(struct ipath_devdata *);
877 * dma_addr wrappers - all 0's invalid for hw
879 dma_addr_t ipath_map_page(struct pci_dev *, struct page *, unsigned long,
881 dma_addr_t ipath_map_single(struct pci_dev *, void *, size_t, int);
884 * Flush write combining store buffers (if present) and perform a write
887 #if defined(CONFIG_X86_64)
888 #define ipath_flush_wc() asm volatile("sfence" ::: "memory")
890 #define ipath_flush_wc() wmb()
893 extern unsigned ipath_debug; /* debugging bit mask */
895 const char *ipath_get_unit_name(int unit);
897 extern struct mutex ipath_mutex;
899 #define IPATH_DRV_NAME "ib_ipath"
900 #define IPATH_MAJOR 233
901 #define IPATH_USER_MINOR_BASE 0
902 #define IPATH_DIAGPKT_MINOR 127
903 #define IPATH_DIAG_MINOR_BASE 129
904 #define IPATH_NMINORS 255
906 #define ipath_dev_err(dd,fmt,...) \
908 const struct ipath_devdata *__dd = (dd); \
910 dev_err(&__dd->pcidev->dev, "%s: " fmt, \
911 ipath_get_unit_name(__dd->ipath_unit), \
914 printk(KERN_ERR IPATH_DRV_NAME ": %s: " fmt, \
915 ipath_get_unit_name(__dd->ipath_unit), \
921 # define __IPATH_DBG_WHICH(which,fmt,...) \
923 if(unlikely(ipath_debug&(which))) \
924 printk(KERN_DEBUG IPATH_DRV_NAME ": %s: " fmt, \
925 __func__,##__VA_ARGS__); \
928 # define ipath_dbg(fmt,...) \
929 __IPATH_DBG_WHICH(__IPATH_DBG,fmt,##__VA_ARGS__)
930 # define ipath_cdbg(which,fmt,...) \
931 __IPATH_DBG_WHICH(__IPATH_##which##DBG,fmt,##__VA_ARGS__)
933 #else /* ! _IPATH_DEBUGGING */
935 # define ipath_dbg(fmt,...)
936 # define ipath_cdbg(which,fmt,...)
938 #endif /* _IPATH_DEBUGGING */
941 * this is used for formatting hw error messages...
943 struct ipath_hwerror_msgs {
948 #define INFINIPATH_HWE_MSG(a, b) { .mask = INFINIPATH_HWE_##a, .msg = b }
950 /* in ipath_intr.c... */
951 void ipath_format_hwerrors(u64 hwerrs,
952 const struct ipath_hwerror_msgs *hwerrmsgs,
954 char *msg, size_t lmsg);
956 #endif /* _IPATH_KERNEL_H */