SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/infiniband/hw/ipath/ipath_init_chip.c

   1 /*
   2  * Copyright (c) 2006 QLogic, Inc. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/pci.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/vmalloc.h>
  37
  38 #include "ipath_kernel.h"
  39 #include "ips_common.h"
  40
  41 /*
  42  * min buffers we want to have per port, after driver
  43  */
  44 #define IPATH_MIN_USER_PORT_BUFCNT 8
  45
  46 /*
  47  * Number of ports we are configured to use (to allow for more pio
  48  * buffers per port, etc.)  Zero means use chip value.
  49  */
  50 static ushort ipath_cfgports;
  51
  52 module_param_named(cfgports, ipath_cfgports, ushort, S_IRUGO);
  53 MODULE_PARM_DESC(cfgports, "Set max number of ports to use");
  54
  55 /*
  56  * Number of buffers reserved for driver (layered drivers and SMA
  57  * send).  Reserved at end of buffer list.   Initialized based on
  58  * number of PIO buffers if not set via module interface.
  59  * The problem with this is that it's global, but we'll use different
  60  * numbers for different chip types.  So the default value is not
  61  * very useful.  I've redefined it for the 1.3 release so that it's
  62  * zero unless set by the user to something else, in which case we
  63  * try to respect it.
  64  */
  65 static ushort ipath_kpiobufs;
  66
  67 static int ipath_set_kpiobufs(const char *val, struct kernel_param *kp);
  68
  69 module_param_call(kpiobufs, ipath_set_kpiobufs, param_get_ushort,
  70                   &ipath_kpiobufs, S_IWUSR | S_IRUGO);
  71 MODULE_PARM_DESC(kpiobufs, "Set number of PIO buffers for driver");
  72
  73 /**
  74  * create_port0_egr - allocate the eager TID buffers
  75  * @dd: the infinipath device
  76  *
  77  * This code is now quite different for user and kernel, because
  78  * the kernel uses skb's, for the accelerated network performance.
  79  * This is the kernel (port0) version.
  80  *
  81  * Allocate the eager TID buffers and program them into infinipath.
  82  * We use the network layer alloc_skb() allocator to allocate the
  83  * memory, and either use the buffers as is for things like SMA
  84  * packets, or pass the buffers up to the ipath layered driver and
  85  * thence the network layer, replacing them as we do so (see
  86  * ipath_rcv_layer()).
  87  */
  88 static int create_port0_egr(struct ipath_devdata *dd)
  89 {
  90         unsigned e, egrcnt;
  91         struct sk_buff **skbs;
  92         int ret;
  93
  94         egrcnt = dd->ipath_rcvegrcnt;
  95
  96         skbs = vmalloc(sizeof(*dd->ipath_port0_skbs) * egrcnt);
  97         if (skbs == NULL) {
  98                 ipath_dev_err(dd, "allocation error for eager TID "
  99                               "skb array\n");
 100                 ret = -ENOMEM;
 101                 goto bail;
 102         }
 103         for (e = 0; e < egrcnt; e++) {
 104                 /*
 105                  * This is a bit tricky in that we allocate extra
 106                  * space for 2 bytes of the 14 byte ethernet header.
 107                  * These two bytes are passed in the ipath header so
 108                  * the rest of the data is word aligned.  We allocate
 109                  * 4 bytes so that the data buffer stays word aligned.
 110                  * See ipath_kreceive() for more details.
 111                  */
 112                 skbs[e] = ipath_alloc_skb(dd, GFP_KERNEL);
 113                 if (!skbs[e]) {
 114                         ipath_dev_err(dd, "SKB allocation error for "
 115                                       "eager TID %u\n", e);
 116                         while (e != 0)
 117                                 dev_kfree_skb(skbs[--e]);
 118                         ret = -ENOMEM;
 119                         goto bail;
 120                 }
 121         }
 122         /*
 123          * After loop above, so we can test non-NULL to see if ready
 124          * to use at receive, etc.
 125          */
 126         dd->ipath_port0_skbs = skbs;
 127
 128         for (e = 0; e < egrcnt; e++) {
 129                 unsigned long phys =
 130                         virt_to_phys(dd->ipath_port0_skbs[e]->data);
 131                 dd->ipath_f_put_tid(dd, e + (u64 __iomem *)
 132                                     ((char __iomem *) dd->ipath_kregbase +
 133                                      dd->ipath_rcvegrbase), 0, phys);
 134         }
 135
 136         ret = 0;
 137
 138 bail:
 139         return ret;
 140 }
 141
 142 static int bringup_link(struct ipath_devdata *dd)
 143 {
 144         u64 val, ibc;
 145         int ret = 0;
 146
 147         /* hold IBC in reset */
 148         dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
 149         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 150                          dd->ipath_control);
 151
 152         /*
 153          * Note that prior to try 14 or 15 of IB, the credit scaling
 154          * wasn't working, because it was swapped for writes with the
 155          * 1 bit default linkstate field
 156          */
 157
 158         /* ignore pbc and align word */
 159         val = dd->ipath_piosize2k - 2 * sizeof(u32);
 160         /*
 161          * for ICRC, which we only send in diag test pkt mode, and we
 162          * don't need to worry about that for mtu
 163          */
 164         val += 1;
 165         /*
 166          * Set the IBC maxpktlength to the size of our pio buffers the
 167          * maxpktlength is in words.  This is *not* the IB data MTU.
 168          */
 169         ibc = (val / sizeof(u32)) << INFINIPATH_IBCC_MAXPKTLEN_SHIFT;
 170         /* in KB */
 171         ibc |= 0x5ULL << INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT;
 172         /*
 173          * How often flowctrl sent.  More or less in usecs; balance against
 174          * watermark value, so that in theory senders always get a flow
 175          * control update in time to not let the IB link go idle.
 176          */
 177         ibc |= 0x3ULL << INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT;
 178         /* max error tolerance */
 179         ibc |= 0xfULL << INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT;
 180         /* use "real" buffer space for */
 181         ibc |= 4ULL << INFINIPATH_IBCC_CREDITSCALE_SHIFT;
 182         /* IB credit flow control. */
 183         ibc |= 0xfULL << INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT;
 184         /* initially come up waiting for TS1, without sending anything. */
 185         dd->ipath_ibcctrl = ibc;
 186         /*
 187          * Want to start out with both LINKCMD and LINKINITCMD in NOP
 188          * (0 and 0).  Don't put linkinitcmd in ipath_ibcctrl, want that
 189          * to stay a NOP
 190          */
 191         ibc |= INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
 192                 INFINIPATH_IBCC_LINKINITCMD_SHIFT;
 193         ipath_cdbg(VERBOSE, "Writing 0x%llx to ibcctrl\n",
 194                    (unsigned long long) ibc);
 195         ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, ibc);
 196
 197         // be sure chip saw it
 198         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 199
 200         ret = dd->ipath_f_bringup_serdes(dd);
 201
 202         if (ret)
 203                 dev_info(&dd->pcidev->dev, "Could not initialize SerDes, "
 204                          "not usable\n");
 205         else {
 206                 /* enable IBC */
 207                 dd->ipath_control |= INFINIPATH_C_LINKENABLE;
 208                 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 209                                  dd->ipath_control);
 210         }
 211
 212         return ret;
 213 }
 214
 215 static int init_chip_first(struct ipath_devdata *dd,
 216                            struct ipath_portdata **pdp)
 217 {
 218         struct ipath_portdata *pd = NULL;
 219         int ret = 0;
 220         u64 val;
 221
 222         /*
 223          * skip cfgports stuff because we are not allocating memory,
 224          * and we don't want problems if the portcnt changed due to
 225          * cfgports.  We do still check and report a difference, if
 226          * not same (should be impossible).
 227          */
 228         dd->ipath_portcnt =
 229                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
 230         if (!ipath_cfgports)
 231                 dd->ipath_cfgports = dd->ipath_portcnt;
 232         else if (ipath_cfgports <= dd->ipath_portcnt) {
 233                 dd->ipath_cfgports = ipath_cfgports;
 234                 ipath_dbg("Configured to use %u ports out of %u in chip\n",
 235                           dd->ipath_cfgports, dd->ipath_portcnt);
 236         } else {
 237                 dd->ipath_cfgports = dd->ipath_portcnt;
 238                 ipath_dbg("Tried to configured to use %u ports; chip "
 239                           "only supports %u\n", ipath_cfgports,
 240                           dd->ipath_portcnt);
 241         }
 242         dd->ipath_pd = kzalloc(sizeof(*dd->ipath_pd) * dd->ipath_cfgports,
 243                                GFP_KERNEL);
 244
 245         if (!dd->ipath_pd) {
 246                 ipath_dev_err(dd, "Unable to allocate portdata array, "
 247                               "failing\n");
 248                 ret = -ENOMEM;
 249                 goto done;
 250         }
 251
 252         dd->ipath_lastegrheads = kzalloc(sizeof(*dd->ipath_lastegrheads)
 253                                          * dd->ipath_cfgports,
 254                                          GFP_KERNEL);
 255         dd->ipath_lastrcvhdrqtails =
 256                 kzalloc(sizeof(*dd->ipath_lastrcvhdrqtails)
 257                         * dd->ipath_cfgports, GFP_KERNEL);
 258
 259         if (!dd->ipath_lastegrheads || !dd->ipath_lastrcvhdrqtails) {
 260                 ipath_dev_err(dd, "Unable to allocate head arrays, "
 261                               "failing\n");
 262                 ret = -ENOMEM;
 263                 goto done;
 264         }
 265
 266         dd->ipath_pd[0] = kzalloc(sizeof(*pd), GFP_KERNEL);
 267
 268         if (!dd->ipath_pd[0]) {
 269                 ipath_dev_err(dd, "Unable to allocate portdata for port "
 270                               "0, failing\n");
 271                 ret = -ENOMEM;
 272                 goto done;
 273         }
 274         pd = dd->ipath_pd[0];
 275         pd->port_dd = dd;
 276         pd->port_port = 0;
 277         pd->port_cnt = 1;
 278         /* The port 0 pkey table is used by the layer interface. */
 279         pd->port_pkeys[0] = IPS_DEFAULT_P_KEY;
 280         dd->ipath_rcvtidcnt =
 281                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
 282         dd->ipath_rcvtidbase =
 283                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
 284         dd->ipath_rcvegrcnt =
 285                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
 286         dd->ipath_rcvegrbase =
 287                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
 288         dd->ipath_palign =
 289                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
 290         dd->ipath_piobufbase =
 291                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufbase);
 292         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiosize);
 293         dd->ipath_piosize2k = val & ~0U;
 294         dd->ipath_piosize4k = val >> 32;
 295         dd->ipath_ibmtu = 4096; /* default to largest legal MTU */
 296         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufcnt);
 297         dd->ipath_piobcnt2k = val & ~0U;
 298         dd->ipath_piobcnt4k = val >> 32;
 299         dd->ipath_pio2kbase =
 300                 (u32 __iomem *) (((char __iomem *) dd->ipath_kregbase) +
 301                                  (dd->ipath_piobufbase & 0xffffffff));
 302         if (dd->ipath_piobcnt4k) {
 303                 dd->ipath_pio4kbase = (u32 __iomem *)
 304                         (((char __iomem *) dd->ipath_kregbase) +
 305                          (dd->ipath_piobufbase >> 32));
 306                 /*
 307                  * 4K buffers take 2 pages; we use roundup just to be
 308                  * paranoid; we calculate it once here, rather than on
 309                  * ever buf allocate
 310                  */
 311                 dd->ipath_4kalign = ALIGN(dd->ipath_piosize4k,
 312                                           dd->ipath_palign);
 313                 ipath_dbg("%u 2k(%x) piobufs @ %p, %u 4k(%x) @ %p "
 314                           "(%x aligned)\n",
 315                           dd->ipath_piobcnt2k, dd->ipath_piosize2k,
 316                           dd->ipath_pio2kbase, dd->ipath_piobcnt4k,
 317                           dd->ipath_piosize4k, dd->ipath_pio4kbase,
 318                           dd->ipath_4kalign);
 319         }
 320         else ipath_dbg("%u 2k piobufs @ %p\n",
 321                        dd->ipath_piobcnt2k, dd->ipath_pio2kbase);
 322
 323         spin_lock_init(&dd->ipath_tid_lock);
 324
 325 done:
 326         *pdp = pd;
 327         return ret;
 328 }
 329
 330 /**
 331  * init_chip_reset - re-initialize after a reset, or enable
 332  * @dd: the infinipath device
 333  * @pdp: output for port data
 334  *
 335  * sanity check at least some of the values after reset, and
 336  * ensure no receive or transmit (explictly, in case reset
 337  * failed
 338  */
 339 static int init_chip_reset(struct ipath_devdata *dd,
 340                            struct ipath_portdata **pdp)
 341 {
 342         struct ipath_portdata *pd;
 343         u32 rtmp;
 344
 345         *pdp = pd = dd->ipath_pd[0];
 346         /* ensure chip does no sends or receives while we re-initialize */
 347         dd->ipath_control = dd->ipath_sendctrl = dd->ipath_rcvctrl = 0U;
 348         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, 0);
 349         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, 0);
 350         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0);
 351
 352         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
 353         if (dd->ipath_portcnt != rtmp)
 354                 dev_info(&dd->pcidev->dev, "portcnt was %u before "
 355                          "reset, now %u, using original\n",
 356                          dd->ipath_portcnt, rtmp);
 357         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
 358         if (rtmp != dd->ipath_rcvtidcnt)
 359                 dev_info(&dd->pcidev->dev, "tidcnt was %u before "
 360                          "reset, now %u, using original\n",
 361                          dd->ipath_rcvtidcnt, rtmp);
 362         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
 363         if (rtmp != dd->ipath_rcvtidbase)
 364                 dev_info(&dd->pcidev->dev, "tidbase was %u before "
 365                          "reset, now %u, using original\n",
 366                          dd->ipath_rcvtidbase, rtmp);
 367         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
 368         if (rtmp != dd->ipath_rcvegrcnt)
 369                 dev_info(&dd->pcidev->dev, "egrcnt was %u before "
 370                          "reset, now %u, using original\n",
 371                          dd->ipath_rcvegrcnt, rtmp);
 372         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
 373         if (rtmp != dd->ipath_rcvegrbase)
 374                 dev_info(&dd->pcidev->dev, "egrbase was %u before "
 375                          "reset, now %u, using original\n",
 376                          dd->ipath_rcvegrbase, rtmp);
 377
 378         return 0;
 379 }
 380
 381 static int init_pioavailregs(struct ipath_devdata *dd)
 382 {
 383         int ret;
 384
 385         dd->ipath_pioavailregs_dma = dma_alloc_coherent(
 386                 &dd->pcidev->dev, PAGE_SIZE, &dd->ipath_pioavailregs_phys,
 387                 GFP_KERNEL);
 388         if (!dd->ipath_pioavailregs_dma) {
 389                 ipath_dev_err(dd, "failed to allocate PIOavail reg area "
 390                               "in memory\n");
 391                 ret = -ENOMEM;
 392                 goto done;
 393         }
 394
 395         /*
 396          * we really want L2 cache aligned, but for current CPUs of
 397          * interest, they are the same.
 398          */
 399         dd->ipath_statusp = (u64 *)
 400                 ((char *)dd->ipath_pioavailregs_dma +
 401                  ((2 * L1_CACHE_BYTES +
 402                    dd->ipath_pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
 403         /* copy the current value now that it's really allocated */
 404         *dd->ipath_statusp = dd->_ipath_status;
 405         /*
 406          * setup buffer to hold freeze msg, accessible to apps,
 407          * following statusp
 408          */
 409         dd->ipath_freezemsg = (char *)&dd->ipath_statusp[1];
 410         /* and its length */
 411         dd->ipath_freezelen = L1_CACHE_BYTES - sizeof(dd->ipath_statusp[0]);
 412
 413         if (dd->ipath_unit * 64 > (IPATH_PORT0_RCVHDRTAIL_SIZE - 64)) {
 414                 ipath_dev_err(dd, "unit %u too large for port 0 "
 415                               "rcvhdrtail buffer size\n", dd->ipath_unit);
 416                 ret = -ENODEV;
 417         }
 418         else
 419                 ret = 0;
 420
 421         /* so we can get current tail in ipath_kreceive(), per chip */
 422         dd->ipath_hdrqtailptr = &ipath_port0_rcvhdrtail[
 423                 dd->ipath_unit * (64 / sizeof(*ipath_port0_rcvhdrtail))];
 424 done:
 425         return ret;
 426 }
 427
 428 /**
 429  * init_shadow_tids - allocate the shadow TID array
 430  * @dd: the infinipath device
 431  *
 432  * allocate the shadow TID array, so we can ipath_munlock previous
 433  * entries.  It may make more sense to move the pageshadow to the
 434  * port data structure, so we only allocate memory for ports actually
 435  * in use, since we at 8k per port, now.
 436  */
 437 static void init_shadow_tids(struct ipath_devdata *dd)
 438 {
 439         dd->ipath_pageshadow = (struct page **)
 440                 vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
 441                         sizeof(struct page *));
 442         if (!dd->ipath_pageshadow)
 443                 ipath_dev_err(dd, "failed to allocate shadow page * "
 444                               "array, no expected sends!\n");
 445         else
 446                 memset(dd->ipath_pageshadow, 0,
 447                        dd->ipath_cfgports * dd->ipath_rcvtidcnt *
 448                        sizeof(struct page *));
 449 }
 450
 451 static void enable_chip(struct ipath_devdata *dd,
 452                         struct ipath_portdata *pd, int reinit)
 453 {
 454         u32 val;
 455         int i;
 456
 457         if (!reinit) {
 458                 init_waitqueue_head(&ipath_sma_state_wait);
 459         }
 460         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 461                          dd->ipath_rcvctrl);
 462
 463         /* Enable PIO send, and update of PIOavail regs to memory. */
 464         dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE |
 465                 INFINIPATH_S_PIOBUFAVAILUPD;
 466         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
 467                          dd->ipath_sendctrl);
 468
 469         /*
 470          * enable port 0 receive, and receive interrupt.  other ports
 471          * done as user opens and inits them.
 472          */
 473         dd->ipath_rcvctrl = INFINIPATH_R_TAILUPD |
 474                 (1ULL << INFINIPATH_R_PORTENABLE_SHIFT) |
 475                 (1ULL << INFINIPATH_R_INTRAVAIL_SHIFT);
 476         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 477                          dd->ipath_rcvctrl);
 478
 479         /*
 480          * now ready for use.  this should be cleared whenever we
 481          * detect a reset, or initiate one.
 482          */
 483         dd->ipath_flags |= IPATH_INITTED;
 484
 485         /*
 486          * init our shadow copies of head from tail values, and write
 487          * head values to match.
 488          */
 489         val = ipath_read_ureg32(dd, ur_rcvegrindextail, 0);
 490         (void)ipath_write_ureg(dd, ur_rcvegrindexhead, val, 0);
 491         dd->ipath_port0head = ipath_read_ureg32(dd, ur_rcvhdrtail, 0);
 492
 493         /* Initialize so we interrupt on next packet received */
 494         (void)ipath_write_ureg(dd, ur_rcvhdrhead,
 495                                dd->ipath_rhdrhead_intr_off |
 496                                dd->ipath_port0head, 0);
 497
 498         /*
 499          * by now pioavail updates to memory should have occurred, so
 500          * copy them into our working/shadow registers; this is in
 501          * case something went wrong with abort, but mostly to get the
 502          * initial values of the generation bit correct.
 503          */
 504         for (i = 0; i < dd->ipath_pioavregs; i++) {
 505                 __le64 val;
 506
 507                 /*
 508                  * Chip Errata bug 6641; even and odd qwords>3 are swapped.
 509                  */
 510                 if (i > 3) {
 511                         if (i & 1)
 512                                 val = dd->ipath_pioavailregs_dma[i - 1];
 513                         else
 514                                 val = dd->ipath_pioavailregs_dma[i + 1];
 515                 }
 516                 else
 517                         val = dd->ipath_pioavailregs_dma[i];
 518                 dd->ipath_pioavailshadow[i] = le64_to_cpu(val);
 519         }
 520         /* can get counters, stats, etc. */
 521         dd->ipath_flags |= IPATH_PRESENT;
 522 }
 523
 524 static int init_housekeeping(struct ipath_devdata *dd,
 525                              struct ipath_portdata **pdp, int reinit)
 526 {
 527         char boardn[32];
 528         int ret = 0;
 529
 530         /*
 531          * have to clear shadow copies of registers at init that are
 532          * not otherwise set here, or all kinds of bizarre things
 533          * happen with driver on chip reset
 534          */
 535         dd->ipath_rcvhdrsize = 0;
 536
 537         /*
 538          * Don't clear ipath_flags as 8bit mode was set before
 539          * entering this func. However, we do set the linkstate to
 540          * unknown, so we can watch for a transition.
 541          * PRESENT is set because we want register reads to work,
 542          * and the kernel infrastructure saw it in config space;
 543          * We clear it if we have failures.
 544          */
 545         dd->ipath_flags |= IPATH_LINKUNK | IPATH_PRESENT;
 546         dd->ipath_flags &= ~(IPATH_LINKACTIVE | IPATH_LINKARMED |
 547                              IPATH_LINKDOWN | IPATH_LINKINIT);
 548
 549         ipath_cdbg(VERBOSE, "Try to read spc chip revision\n");
 550         dd->ipath_revision =
 551                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
 552
 553         /*
 554          * set up fundamental info we need to use the chip; we assume
 555          * if the revision reg and these regs are OK, we don't need to
 556          * special case the rest
 557          */
 558         dd->ipath_sregbase =
 559                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_sendregbase);
 560         dd->ipath_cregbase =
 561                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_counterregbase);
 562         dd->ipath_uregbase =
 563                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_userregbase);
 564         ipath_cdbg(VERBOSE, "ipath_kregbase %p, sendbase %x usrbase %x, "
 565                    "cntrbase %x\n", dd->ipath_kregbase, dd->ipath_sregbase,
 566                    dd->ipath_uregbase, dd->ipath_cregbase);
 567         if ((dd->ipath_revision & 0xffffffff) == 0xffffffff
 568             || (dd->ipath_sregbase & 0xffffffff) == 0xffffffff
 569             || (dd->ipath_cregbase & 0xffffffff) == 0xffffffff
 570             || (dd->ipath_uregbase & 0xffffffff) == 0xffffffff) {
 571                 ipath_dev_err(dd, "Register read failures from chip, "
 572                               "giving up initialization\n");
 573                 dd->ipath_flags &= ~IPATH_PRESENT;
 574                 ret = -ENODEV;
 575                 goto done;
 576         }
 577
 578         /* clear the initial reset flag, in case first driver load */
 579         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
 580                          INFINIPATH_E_RESET);
 581
 582         if (reinit)
 583                 ret = init_chip_reset(dd, pdp);
 584         else
 585                 ret = init_chip_first(dd, pdp);
 586
 587         if (ret)
 588                 goto done;
 589
 590         ipath_cdbg(VERBOSE, "Revision %llx (PCI %x), %u ports, %u tids, "
 591                    "%u egrtids\n", (unsigned long long) dd->ipath_revision,
 592                    dd->ipath_pcirev, dd->ipath_portcnt, dd->ipath_rcvtidcnt,
 593                    dd->ipath_rcvegrcnt);
 594
 595         if (((dd->ipath_revision >> INFINIPATH_R_SOFTWARE_SHIFT) &
 596              INFINIPATH_R_SOFTWARE_MASK) != IPATH_CHIP_SWVERSION) {
 597                 ipath_dev_err(dd, "Driver only handles version %d, "
 598                               "chip swversion is %d (%llx), failng\n",
 599                               IPATH_CHIP_SWVERSION,
 600                               (int)(dd->ipath_revision >>
 601                                     INFINIPATH_R_SOFTWARE_SHIFT) &
 602                               INFINIPATH_R_SOFTWARE_MASK,
 603                               (unsigned long long) dd->ipath_revision);
 604                 ret = -ENOSYS;
 605                 goto done;
 606         }
 607         dd->ipath_majrev = (u8) ((dd->ipath_revision >>
 608                                   INFINIPATH_R_CHIPREVMAJOR_SHIFT) &
 609                                  INFINIPATH_R_CHIPREVMAJOR_MASK);
 610         dd->ipath_minrev = (u8) ((dd->ipath_revision >>
 611                                   INFINIPATH_R_CHIPREVMINOR_SHIFT) &
 612                                  INFINIPATH_R_CHIPREVMINOR_MASK);
 613         dd->ipath_boardrev = (u8) ((dd->ipath_revision >>
 614                                     INFINIPATH_R_BOARDID_SHIFT) &
 615                                    INFINIPATH_R_BOARDID_MASK);
 616
 617         ret = dd->ipath_f_get_boardname(dd, boardn, sizeof boardn);
 618
 619         snprintf(dd->ipath_boardversion, sizeof(dd->ipath_boardversion),
 620                  "Driver %u.%u, %s, InfiniPath%u %u.%u, PCI %u, "
 621                  "SW Compat %u\n",
 622                  IPATH_CHIP_VERS_MAJ, IPATH_CHIP_VERS_MIN, boardn,
 623                  (unsigned)(dd->ipath_revision >> INFINIPATH_R_ARCH_SHIFT) &
 624                  INFINIPATH_R_ARCH_MASK,
 625                  dd->ipath_majrev, dd->ipath_minrev, dd->ipath_pcirev,
 626                  (unsigned)(dd->ipath_revision >>
 627                             INFINIPATH_R_SOFTWARE_SHIFT) &
 628                  INFINIPATH_R_SOFTWARE_MASK);
 629
 630         ipath_dbg("%s", dd->ipath_boardversion);
 631
 632 done:
 633         return ret;
 634 }
 635
 636
 637 /**
 638  * ipath_init_chip - do the actual initialization sequence on the chip
 639  * @dd: the infinipath device
 640  * @reinit: reinitializing, so don't allocate new memory
 641  *
 642  * Do the actual initialization sequence on the chip.  This is done
 643  * both from the init routine called from the PCI infrastructure, and
 644  * when we reset the chip, or detect that it was reset internally,
 645  * or it's administratively re-enabled.
 646  *
 647  * Memory allocation here and in called routines is only done in
 648  * the first case (reinit == 0).  We have to be careful, because even
 649  * without memory allocation, we need to re-write all the chip registers
 650  * TIDs, etc. after the reset or enable has completed.
 651  */
 652 int ipath_init_chip(struct ipath_devdata *dd, int reinit)
 653 {
 654         int ret = 0, i;
 655         u32 val32, kpiobufs;
 656         u64 val, atmp;
 657         struct ipath_portdata *pd = NULL; /* keep gcc4 happy */
 658
 659         ret = init_housekeeping(dd, &pd, reinit);
 660         if (ret)
 661                 goto done;
 662
 663         /*
 664          * we ignore most issues after reporting them, but have to specially
 665          * handle hardware-disabled chips.
 666          */
 667         if (ret == 2) {
 668                 /* unique error, known to ipath_init_one */
 669                 ret = -EPERM;
 670                 goto done;
 671         }
 672
 673         /*
 674          * We could bump this to allow for full rcvegrcnt + rcvtidcnt,
 675          * but then it no longer nicely fits power of two, and since
 676          * we now use routines that backend onto __get_free_pages, the
 677          * rest would be wasted.
 678          */
 679         dd->ipath_rcvhdrcnt = dd->ipath_rcvegrcnt;
 680         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt,
 681                          dd->ipath_rcvhdrcnt);
 682
 683         /*
 684          * Set up the shadow copies of the piobufavail registers,
 685          * which we compare against the chip registers for now, and
 686          * the in memory DMA'ed copies of the registers.  This has to
 687          * be done early, before we calculate lastport, etc.
 688          */
 689         val = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
 690         /*
 691          * calc number of pioavail registers, and save it; we have 2
 692          * bits per buffer.
 693          */
 694         dd->ipath_pioavregs = ALIGN(val, sizeof(u64) * BITS_PER_BYTE / 2)
 695                 / (sizeof(u64) * BITS_PER_BYTE / 2);
 696         if (ipath_kpiobufs == 0) {
 697                 /* not set by user, or set explictly to default  */
 698                 if ((dd->ipath_piobcnt2k + dd->ipath_piobcnt4k) > 128)
 699                         kpiobufs = 32;
 700                 else
 701                         kpiobufs = 16;
 702         }
 703         else
 704                 kpiobufs = ipath_kpiobufs;
 705
 706         if (kpiobufs >
 707             (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
 708              (dd->ipath_cfgports * IPATH_MIN_USER_PORT_BUFCNT))) {
 709                 i = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
 710                         (dd->ipath_cfgports * IPATH_MIN_USER_PORT_BUFCNT);
 711                 if (i < 0)
 712                         i = 0;
 713                 dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs for "
 714                          "kernel leaves too few for %d user ports "
 715                          "(%d each); using %u\n", kpiobufs,
 716                          dd->ipath_cfgports - 1,
 717                          IPATH_MIN_USER_PORT_BUFCNT, i);
 718                 /*
 719                  * shouldn't change ipath_kpiobufs, because could be
 720                  * different for different devices...
 721                  */
 722                 kpiobufs = i;
 723         }
 724         dd->ipath_lastport_piobuf =
 725                 dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - kpiobufs;
 726         dd->ipath_pbufsport = dd->ipath_cfgports > 1
 727                 ? dd->ipath_lastport_piobuf / (dd->ipath_cfgports - 1)
 728                 : 0;
 729         val32 = dd->ipath_lastport_piobuf -
 730                 (dd->ipath_pbufsport * (dd->ipath_cfgports - 1));
 731         if (val32 > 0) {
 732                 ipath_dbg("allocating %u pbufs/port leaves %u unused, "
 733                           "add to kernel\n", dd->ipath_pbufsport, val32);
 734                 dd->ipath_lastport_piobuf -= val32;
 735                 ipath_dbg("%u pbufs/port leaves %u unused, add to kernel\n",
 736                           dd->ipath_pbufsport, val32);
 737         }
 738         dd->ipath_lastpioindex = dd->ipath_lastport_piobuf;
 739         ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u "
 740                    "each for %u user ports\n", kpiobufs,
 741                    dd->ipath_piobcnt2k + dd->ipath_piobcnt4k,
 742                    dd->ipath_pbufsport, dd->ipath_cfgports - 1);
 743
 744         dd->ipath_f_early_init(dd);
 745
 746         /* early_init sets rcvhdrentsize and rcvhdrsize, so this must be
 747          * done after early_init */
 748         dd->ipath_hdrqlast =
 749                 dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1);
 750         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize,
 751                          dd->ipath_rcvhdrentsize);
 752         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
 753                          dd->ipath_rcvhdrsize);
 754
 755         if (!reinit) {
 756                 ret = init_pioavailregs(dd);
 757                 init_shadow_tids(dd);
 758                 if (ret)
 759                         goto done;
 760         }
 761
 762         (void)ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr,
 763                                dd->ipath_pioavailregs_phys);
 764         /*
 765          * this is to detect s/w errors, which the h/w works around by
 766          * ignoring the low 6 bits of address, if it wasn't aligned.
 767          */
 768         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr);
 769         if (val != dd->ipath_pioavailregs_phys) {
 770                 ipath_dev_err(dd, "Catastrophic software error, "
 771                               "SendPIOAvailAddr written as %lx, "
 772                               "read back as %llx\n",
 773                               (unsigned long) dd->ipath_pioavailregs_phys,
 774                               (unsigned long long) val);
 775                 ret = -EINVAL;
 776                 goto done;
 777         }
 778
 779         val = ipath_port0_rcvhdrtail_dma + dd->ipath_unit * 64;
 780
 781         /* verify that the alignment requirement was met */
 782         ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdrtailaddr,
 783                               0, val);
 784         atmp = ipath_read_kreg64_port(
 785                 dd, dd->ipath_kregs->kr_rcvhdrtailaddr, 0);
 786         if (val != atmp) {
 787                 ipath_dev_err(dd, "Catastrophic software error, "
 788                               "RcvHdrTailAddr0 written as %llx, "
 789                               "read back as %llx from %x\n",
 790                               (unsigned long long) val,
 791                               (unsigned long long) atmp,
 792                               dd->ipath_kregs->kr_rcvhdrtailaddr);
 793                 ret = -EINVAL;
 794                 goto done;
 795         }
 796
 797         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP);
 798
 799         /*
 800          * make sure we are not in freeze, and PIO send enabled, so
 801          * writes to pbc happen
 802          */
 803         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL);
 804         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 805                          ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
 806         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
 807         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
 808                          INFINIPATH_S_PIOENABLE);
 809
 810         /*
 811          * before error clears, since we expect serdes pll errors during
 812          * this, the first time after reset
 813          */
 814         if (bringup_link(dd)) {
 815                 dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n");
 816                 ret = -ENETDOWN;
 817                 goto done;
 818         }
 819
 820         /*
 821          * clear any "expected" hwerrs from reset and/or initialization
 822          * clear any that aren't enabled (at least this once), and then
 823          * set the enable mask
 824          */
 825         dd->ipath_f_init_hwerrors(dd);
 826         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 827                          ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
 828         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 829                          dd->ipath_hwerrmask);
 830
 831         dd->ipath_maskederrs = dd->ipath_ignorederrs;
 832         /* clear all */
 833         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
 834         /* enable errors that are masked, at least this first time. */
 835         ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
 836                          ~dd->ipath_maskederrs);
 837         /* clear any interrups up to this point (ints still not enabled) */
 838         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
 839
 840         ipath_stats.sps_lid[dd->ipath_unit] = dd->ipath_lid;
 841
 842         /*
 843          * Set up the port 0 (kernel) rcvhdr q and egr TIDs.  If doing
 844          * re-init, the simplest way to handle this is to free
 845          * existing, and re-allocate.
 846          */
 847         if (reinit)
 848                 ipath_free_pddata(dd, 0, 0);
 849         dd->ipath_f_tidtemplate(dd);
 850         ret = ipath_create_rcvhdrq(dd, pd);
 851         if (!ret)
 852                 ret = create_port0_egr(dd);
 853         if (ret)
 854                 ipath_dev_err(dd, "failed to allocate port 0 (kernel) "
 855                               "rcvhdrq and/or egr bufs\n");
 856         else
 857                 enable_chip(dd, pd, reinit);
 858
 859         /*
 860          * cause retrigger of pending interrupts ignored during init,
 861          * even if we had errors
 862          */
 863         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
 864
 865         if(!dd->ipath_stats_timer_active) {
 866                 /*
 867                  * first init, or after an admin disable/enable
 868                  * set up stats retrieval timer, even if we had errors
 869                  * in last portion of setup
 870                  */
 871                 init_timer(&dd->ipath_stats_timer);
 872                 dd->ipath_stats_timer.function = ipath_get_faststats;
 873                 dd->ipath_stats_timer.data = (unsigned long) dd;
 874                 /* every 5 seconds; */
 875                 dd->ipath_stats_timer.expires = jiffies + 5 * HZ;
 876                 /* takes ~16 seconds to overflow at full IB 4x bandwdith */
 877                 add_timer(&dd->ipath_stats_timer);
 878                 dd->ipath_stats_timer_active = 1;
 879         }
 880
 881 done:
 882         if (!ret) {
 883                 *dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT;
 884                 if (!dd->ipath_f_intrsetup(dd)) {
 885                         /* now we can enable all interrupts from the chip */
 886                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
 887                                          -1LL);
 888                         /* force re-interrupt of any pending interrupts. */
 889                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear,
 890                                          0ULL);
 891                         /* chip is usable; mark it as initialized */
 892                         *dd->ipath_statusp |= IPATH_STATUS_INITTED;
 893                 } else
 894                         ipath_dev_err(dd, "No interrupts enabled, couldn't "
 895                                       "setup interrupt address\n");
 896
 897                 if (dd->ipath_cfgports > ipath_stats.sps_nports)
 898                         /*
 899                          * sps_nports is a global, so, we set it to
 900                          * the highest number of ports of any of the
 901                          * chips we find; we never decrement it, at
 902                          * least for now.  Since this might have changed
 903                          * over disable/enable or prior to reset, always
 904                          * do the check and potentially adjust.
 905                          */
 906                         ipath_stats.sps_nports = dd->ipath_cfgports;
 907         } else
 908                 ipath_dbg("Failed (%d) to initialize chip\n", ret);
 909
 910         /* if ret is non-zero, we probably should do some cleanup
 911            here... */
 912         return ret;
 913 }
 914
 915 static int ipath_set_kpiobufs(const char *str, struct kernel_param *kp)
 916 {
 917         struct ipath_devdata *dd;
 918         unsigned long flags;
 919         unsigned short val;
 920         int ret;
 921
 922         ret = ipath_parse_ushort(str, &val);
 923
 924         spin_lock_irqsave(&ipath_devs_lock, flags);
 925
 926         if (ret < 0)
 927                 goto bail;
 928
 929         if (val == 0) {
 930                 ret = -EINVAL;
 931                 goto bail;
 932         }
 933
 934         list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
 935                 if (dd->ipath_kregbase)
 936                         continue;
 937                 if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
 938                            (dd->ipath_cfgports *
 939                             IPATH_MIN_USER_PORT_BUFCNT)))
 940                 {
 941                         ipath_dev_err(
 942                                 dd,
 943                                 "Allocating %d PIO bufs for kernel leaves "
 944                                 "too few for %d user ports (%d each)\n",
 945                                 val, dd->ipath_cfgports - 1,
 946                                 IPATH_MIN_USER_PORT_BUFCNT);
 947                         ret = -EINVAL;
 948                         goto bail;
 949                 }
 950                 dd->ipath_lastport_piobuf =
 951                         dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val;
 952         }
 953
 954         ret = 0;
 955 bail:
 956         spin_unlock_irqrestore(&ipath_devs_lock, flags);
 957
 958         return ret;
 959 }