SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/infiniband/hw/ipath/ipath_init_chip.c

   1 /*
   2  * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/pci.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/vmalloc.h>
  37
  38 #include "ipath_kernel.h"
  39 #include "ipath_common.h"
  40
  41 /*
  42  * min buffers we want to have per port, after driver
  43  */
  44 #define IPATH_MIN_USER_PORT_BUFCNT 8
  45
  46 /*
  47  * Number of ports we are configured to use (to allow for more pio
  48  * buffers per port, etc.)  Zero means use chip value.
  49  */
  50 static ushort ipath_cfgports;
  51
  52 module_param_named(cfgports, ipath_cfgports, ushort, S_IRUGO);
  53 MODULE_PARM_DESC(cfgports, "Set max number of ports to use");
  54
  55 /*
  56  * Number of buffers reserved for driver (verbs and layered drivers.)
  57  * Reserved at end of buffer list.   Initialized based on
  58  * number of PIO buffers if not set via module interface.
  59  * The problem with this is that it's global, but we'll use different
  60  * numbers for different chip types.  So the default value is not
  61  * very useful.  I've redefined it for the 1.3 release so that it's
  62  * zero unless set by the user to something else, in which case we
  63  * try to respect it.
  64  */
  65 static ushort ipath_kpiobufs;
  66
  67 static int ipath_set_kpiobufs(const char *val, struct kernel_param *kp);
  68
  69 module_param_call(kpiobufs, ipath_set_kpiobufs, param_get_ushort,
  70                   &ipath_kpiobufs, S_IWUSR | S_IRUGO);
  71 MODULE_PARM_DESC(kpiobufs, "Set number of PIO buffers for driver");
  72
  73 /**
  74  * create_port0_egr - allocate the eager TID buffers
  75  * @dd: the infinipath device
  76  *
  77  * This code is now quite different for user and kernel, because
  78  * the kernel uses skb's, for the accelerated network performance.
  79  * This is the kernel (port0) version.
  80  *
  81  * Allocate the eager TID buffers and program them into infinipath.
  82  * We use the network layer alloc_skb() allocator to allocate the
  83  * memory, and either use the buffers as is for things like verbs
  84  * packets, or pass the buffers up to the ipath layered driver and
  85  * thence the network layer, replacing them as we do so (see
  86  * ipath_rcv_layer()).
  87  */
  88 static int create_port0_egr(struct ipath_devdata *dd)
  89 {
  90         unsigned e, egrcnt;
  91         struct ipath_skbinfo *skbinfo;
  92         int ret;
  93
  94         egrcnt = dd->ipath_p0_rcvegrcnt;
  95
  96         skbinfo = vmalloc(sizeof(*dd->ipath_port0_skbinfo) * egrcnt);
  97         if (skbinfo == NULL) {
  98                 ipath_dev_err(dd, "allocation error for eager TID "
  99                               "skb array\n");
 100                 ret = -ENOMEM;
 101                 goto bail;
 102         }
 103         for (e = 0; e < egrcnt; e++) {
 104                 /*
 105                  * This is a bit tricky in that we allocate extra
 106                  * space for 2 bytes of the 14 byte ethernet header.
 107                  * These two bytes are passed in the ipath header so
 108                  * the rest of the data is word aligned.  We allocate
 109                  * 4 bytes so that the data buffer stays word aligned.
 110                  * See ipath_kreceive() for more details.
 111                  */
 112                 skbinfo[e].skb = ipath_alloc_skb(dd, GFP_KERNEL);
 113                 if (!skbinfo[e].skb) {
 114                         ipath_dev_err(dd, "SKB allocation error for "
 115                                       "eager TID %u\n", e);
 116                         while (e != 0)
 117                                 dev_kfree_skb(skbinfo[--e].skb);
 118                         vfree(skbinfo);
 119                         ret = -ENOMEM;
 120                         goto bail;
 121                 }
 122         }
 123         /*
 124          * After loop above, so we can test non-NULL to see if ready
 125          * to use at receive, etc.
 126          */
 127         dd->ipath_port0_skbinfo = skbinfo;
 128
 129         for (e = 0; e < egrcnt; e++) {
 130                 dd->ipath_port0_skbinfo[e].phys =
 131                   ipath_map_single(dd->pcidev,
 132                                    dd->ipath_port0_skbinfo[e].skb->data,
 133                                    dd->ipath_ibmaxlen, PCI_DMA_FROMDEVICE);
 134                 dd->ipath_f_put_tid(dd, e + (u64 __iomem *)
 135                                     ((char __iomem *) dd->ipath_kregbase +
 136                                      dd->ipath_rcvegrbase),
 137                                     RCVHQ_RCV_TYPE_EAGER,
 138                                     dd->ipath_port0_skbinfo[e].phys);
 139         }
 140
 141         ret = 0;
 142
 143 bail:
 144         return ret;
 145 }
 146
 147 static int bringup_link(struct ipath_devdata *dd)
 148 {
 149         u64 val, ibc;
 150         int ret = 0;
 151
 152         /* hold IBC in reset */
 153         dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
 154         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 155                          dd->ipath_control);
 156
 157         /*
 158          * Note that prior to try 14 or 15 of IB, the credit scaling
 159          * wasn't working, because it was swapped for writes with the
 160          * 1 bit default linkstate field
 161          */
 162
 163         /* ignore pbc and align word */
 164         val = dd->ipath_piosize2k - 2 * sizeof(u32);
 165         /*
 166          * for ICRC, which we only send in diag test pkt mode, and we
 167          * don't need to worry about that for mtu
 168          */
 169         val += 1;
 170         /*
 171          * Set the IBC maxpktlength to the size of our pio buffers the
 172          * maxpktlength is in words.  This is *not* the IB data MTU.
 173          */
 174         ibc = (val / sizeof(u32)) << INFINIPATH_IBCC_MAXPKTLEN_SHIFT;
 175         /* in KB */
 176         ibc |= 0x5ULL << INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT;
 177         /*
 178          * How often flowctrl sent.  More or less in usecs; balance against
 179          * watermark value, so that in theory senders always get a flow
 180          * control update in time to not let the IB link go idle.
 181          */
 182         ibc |= 0x3ULL << INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT;
 183         /* max error tolerance */
 184         ibc |= 0xfULL << INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT;
 185         /* use "real" buffer space for */
 186         ibc |= 4ULL << INFINIPATH_IBCC_CREDITSCALE_SHIFT;
 187         /* IB credit flow control. */
 188         ibc |= 0xfULL << INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT;
 189         /* initially come up waiting for TS1, without sending anything. */
 190         dd->ipath_ibcctrl = ibc;
 191         /*
 192          * Want to start out with both LINKCMD and LINKINITCMD in NOP
 193          * (0 and 0).  Don't put linkinitcmd in ipath_ibcctrl, want that
 194          * to stay a NOP
 195          */
 196         ibc |= INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
 197                 INFINIPATH_IBCC_LINKINITCMD_SHIFT;
 198         ipath_cdbg(VERBOSE, "Writing 0x%llx to ibcctrl\n",
 199                    (unsigned long long) ibc);
 200         ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, ibc);
 201
 202         // be sure chip saw it
 203         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 204
 205         ret = dd->ipath_f_bringup_serdes(dd);
 206
 207         if (ret)
 208                 dev_info(&dd->pcidev->dev, "Could not initialize SerDes, "
 209                          "not usable\n");
 210         else {
 211                 /* enable IBC */
 212                 dd->ipath_control |= INFINIPATH_C_LINKENABLE;
 213                 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 214                                  dd->ipath_control);
 215         }
 216
 217         return ret;
 218 }
 219
 220 static struct ipath_portdata *create_portdata0(struct ipath_devdata *dd)
 221 {
 222         struct ipath_portdata *pd = NULL;
 223
 224         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 225         if (pd) {
 226                 pd->port_dd = dd;
 227                 pd->port_cnt = 1;
 228                 /* The port 0 pkey table is used by the layer interface. */
 229                 pd->port_pkeys[0] = IPATH_DEFAULT_P_KEY;
 230         }
 231         return pd;
 232 }
 233
 234 static int init_chip_first(struct ipath_devdata *dd,
 235                            struct ipath_portdata **pdp)
 236 {
 237         struct ipath_portdata *pd = NULL;
 238         int ret = 0;
 239         u64 val;
 240
 241         /*
 242          * skip cfgports stuff because we are not allocating memory,
 243          * and we don't want problems if the portcnt changed due to
 244          * cfgports.  We do still check and report a difference, if
 245          * not same (should be impossible).
 246          */
 247         dd->ipath_f_config_ports(dd, ipath_cfgports);
 248         if (!ipath_cfgports)
 249                 dd->ipath_cfgports = dd->ipath_portcnt;
 250         else if (ipath_cfgports <= dd->ipath_portcnt) {
 251                 dd->ipath_cfgports = ipath_cfgports;
 252                 ipath_dbg("Configured to use %u ports out of %u in chip\n",
 253                           dd->ipath_cfgports, dd->ipath_portcnt);
 254         } else {
 255                 dd->ipath_cfgports = dd->ipath_portcnt;
 256                 ipath_dbg("Tried to configured to use %u ports; chip "
 257                           "only supports %u\n", ipath_cfgports,
 258                           dd->ipath_portcnt);
 259         }
 260         /*
 261          * Allocate full portcnt array, rather than just cfgports, because
 262          * cleanup iterates across all possible ports.
 263          */
 264         dd->ipath_pd = kzalloc(sizeof(*dd->ipath_pd) * dd->ipath_portcnt,
 265                                GFP_KERNEL);
 266
 267         if (!dd->ipath_pd) {
 268                 ipath_dev_err(dd, "Unable to allocate portdata array, "
 269                               "failing\n");
 270                 ret = -ENOMEM;
 271                 goto done;
 272         }
 273
 274         pd = create_portdata0(dd);
 275         if (!pd) {
 276                 ipath_dev_err(dd, "Unable to allocate portdata for port "
 277                               "0, failing\n");
 278                 ret = -ENOMEM;
 279                 goto done;
 280         }
 281         dd->ipath_pd[0] = pd;
 282
 283         dd->ipath_rcvtidcnt =
 284                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
 285         dd->ipath_rcvtidbase =
 286                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
 287         dd->ipath_rcvegrcnt =
 288                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
 289         dd->ipath_rcvegrbase =
 290                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
 291         dd->ipath_palign =
 292                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
 293         dd->ipath_piobufbase =
 294                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufbase);
 295         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiosize);
 296         dd->ipath_piosize2k = val & ~0U;
 297         dd->ipath_piosize4k = val >> 32;
 298         /*
 299          * Note: the chips support a maximum MTU of 4096, but the driver
 300          * hasn't implemented this feature yet, so set the initial value
 301          * to 2048.
 302          */
 303         dd->ipath_ibmtu = 2048;
 304         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufcnt);
 305         dd->ipath_piobcnt2k = val & ~0U;
 306         dd->ipath_piobcnt4k = val >> 32;
 307         dd->ipath_pio2kbase =
 308                 (u32 __iomem *) (((char __iomem *) dd->ipath_kregbase) +
 309                                  (dd->ipath_piobufbase & 0xffffffff));
 310         if (dd->ipath_piobcnt4k) {
 311                 dd->ipath_pio4kbase = (u32 __iomem *)
 312                         (((char __iomem *) dd->ipath_kregbase) +
 313                          (dd->ipath_piobufbase >> 32));
 314                 /*
 315                  * 4K buffers take 2 pages; we use roundup just to be
 316                  * paranoid; we calculate it once here, rather than on
 317                  * ever buf allocate
 318                  */
 319                 dd->ipath_4kalign = ALIGN(dd->ipath_piosize4k,
 320                                           dd->ipath_palign);
 321                 ipath_dbg("%u 2k(%x) piobufs @ %p, %u 4k(%x) @ %p "
 322                           "(%x aligned)\n",
 323                           dd->ipath_piobcnt2k, dd->ipath_piosize2k,
 324                           dd->ipath_pio2kbase, dd->ipath_piobcnt4k,
 325                           dd->ipath_piosize4k, dd->ipath_pio4kbase,
 326                           dd->ipath_4kalign);
 327         }
 328         else ipath_dbg("%u 2k piobufs @ %p\n",
 329                        dd->ipath_piobcnt2k, dd->ipath_pio2kbase);
 330
 331         spin_lock_init(&dd->ipath_tid_lock);
 332         spin_lock_init(&dd->ipath_sendctrl_lock);
 333         spin_lock_init(&dd->ipath_gpio_lock);
 334         spin_lock_init(&dd->ipath_eep_st_lock);
 335         mutex_init(&dd->ipath_eep_lock);
 336
 337 done:
 338         *pdp = pd;
 339         return ret;
 340 }
 341
 342 /**
 343  * init_chip_reset - re-initialize after a reset, or enable
 344  * @dd: the infinipath device
 345  * @pdp: output for port data
 346  *
 347  * sanity check at least some of the values after reset, and
 348  * ensure no receive or transmit (explictly, in case reset
 349  * failed
 350  */
 351 static int init_chip_reset(struct ipath_devdata *dd,
 352                            struct ipath_portdata **pdp)
 353 {
 354         u32 rtmp;
 355
 356         *pdp = dd->ipath_pd[0];
 357         /* ensure chip does no sends or receives while we re-initialize */
 358         dd->ipath_control = dd->ipath_sendctrl = dd->ipath_rcvctrl = 0U;
 359         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, dd->ipath_rcvctrl);
 360         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
 361         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, dd->ipath_control);
 362
 363         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
 364         if (dd->ipath_portcnt != rtmp)
 365                 dev_info(&dd->pcidev->dev, "portcnt was %u before "
 366                          "reset, now %u, using original\n",
 367                          dd->ipath_portcnt, rtmp);
 368         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
 369         if (rtmp != dd->ipath_rcvtidcnt)
 370                 dev_info(&dd->pcidev->dev, "tidcnt was %u before "
 371                          "reset, now %u, using original\n",
 372                          dd->ipath_rcvtidcnt, rtmp);
 373         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
 374         if (rtmp != dd->ipath_rcvtidbase)
 375                 dev_info(&dd->pcidev->dev, "tidbase was %u before "
 376                          "reset, now %u, using original\n",
 377                          dd->ipath_rcvtidbase, rtmp);
 378         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
 379         if (rtmp != dd->ipath_rcvegrcnt)
 380                 dev_info(&dd->pcidev->dev, "egrcnt was %u before "
 381                          "reset, now %u, using original\n",
 382                          dd->ipath_rcvegrcnt, rtmp);
 383         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
 384         if (rtmp != dd->ipath_rcvegrbase)
 385                 dev_info(&dd->pcidev->dev, "egrbase was %u before "
 386                          "reset, now %u, using original\n",
 387                          dd->ipath_rcvegrbase, rtmp);
 388
 389         return 0;
 390 }
 391
 392 static int init_pioavailregs(struct ipath_devdata *dd)
 393 {
 394         int ret;
 395
 396         dd->ipath_pioavailregs_dma = dma_alloc_coherent(
 397                 &dd->pcidev->dev, PAGE_SIZE, &dd->ipath_pioavailregs_phys,
 398                 GFP_KERNEL);
 399         if (!dd->ipath_pioavailregs_dma) {
 400                 ipath_dev_err(dd, "failed to allocate PIOavail reg area "
 401                               "in memory\n");
 402                 ret = -ENOMEM;
 403                 goto done;
 404         }
 405
 406         /*
 407          * we really want L2 cache aligned, but for current CPUs of
 408          * interest, they are the same.
 409          */
 410         dd->ipath_statusp = (u64 *)
 411                 ((char *)dd->ipath_pioavailregs_dma +
 412                  ((2 * L1_CACHE_BYTES +
 413                    dd->ipath_pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
 414         /* copy the current value now that it's really allocated */
 415         *dd->ipath_statusp = dd->_ipath_status;
 416         /*
 417          * setup buffer to hold freeze msg, accessible to apps,
 418          * following statusp
 419          */
 420         dd->ipath_freezemsg = (char *)&dd->ipath_statusp[1];
 421         /* and its length */
 422         dd->ipath_freezelen = L1_CACHE_BYTES - sizeof(dd->ipath_statusp[0]);
 423
 424         ret = 0;
 425
 426 done:
 427         return ret;
 428 }
 429
 430 /**
 431  * init_shadow_tids - allocate the shadow TID array
 432  * @dd: the infinipath device
 433  *
 434  * allocate the shadow TID array, so we can ipath_munlock previous
 435  * entries.  It may make more sense to move the pageshadow to the
 436  * port data structure, so we only allocate memory for ports actually
 437  * in use, since we at 8k per port, now.
 438  */
 439 static void init_shadow_tids(struct ipath_devdata *dd)
 440 {
 441         struct page **pages;
 442         dma_addr_t *addrs;
 443
 444         pages = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
 445                         sizeof(struct page *));
 446         if (!pages) {
 447                 ipath_dev_err(dd, "failed to allocate shadow page * "
 448                               "array, no expected sends!\n");
 449                 dd->ipath_pageshadow = NULL;
 450                 return;
 451         }
 452
 453         addrs = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
 454                         sizeof(dma_addr_t));
 455         if (!addrs) {
 456                 ipath_dev_err(dd, "failed to allocate shadow dma handle "
 457                               "array, no expected sends!\n");
 458                 vfree(dd->ipath_pageshadow);
 459                 dd->ipath_pageshadow = NULL;
 460                 return;
 461         }
 462
 463         memset(pages, 0, dd->ipath_cfgports * dd->ipath_rcvtidcnt *
 464                sizeof(struct page *));
 465
 466         dd->ipath_pageshadow = pages;
 467         dd->ipath_physshadow = addrs;
 468 }
 469
 470 static void enable_chip(struct ipath_devdata *dd,
 471                         struct ipath_portdata *pd, int reinit)
 472 {
 473         u32 val;
 474         unsigned long flags;
 475         int i;
 476
 477         if (!reinit)
 478                 init_waitqueue_head(&ipath_state_wait);
 479
 480         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 481                          dd->ipath_rcvctrl);
 482
 483         spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
 484         /* Enable PIO send, and update of PIOavail regs to memory. */
 485         dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE |
 486                 INFINIPATH_S_PIOBUFAVAILUPD;
 487         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
 488         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 489         spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
 490
 491         /*
 492          * enable port 0 receive, and receive interrupt.  other ports
 493          * done as user opens and inits them.
 494          */
 495         dd->ipath_rcvctrl = (1ULL << dd->ipath_r_tailupd_shift) |
 496                 (1ULL << dd->ipath_r_portenable_shift) |
 497                 (1ULL << dd->ipath_r_intravail_shift);
 498         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 499                          dd->ipath_rcvctrl);
 500
 501         /*
 502          * now ready for use.  this should be cleared whenever we
 503          * detect a reset, or initiate one.
 504          */
 505         dd->ipath_flags |= IPATH_INITTED;
 506
 507         /*
 508          * init our shadow copies of head from tail values, and write
 509          * head values to match.
 510          */
 511         val = ipath_read_ureg32(dd, ur_rcvegrindextail, 0);
 512         (void)ipath_write_ureg(dd, ur_rcvegrindexhead, val, 0);
 513
 514         /* Initialize so we interrupt on next packet received */
 515         (void)ipath_write_ureg(dd, ur_rcvhdrhead,
 516                                dd->ipath_rhdrhead_intr_off |
 517                                dd->ipath_pd[0]->port_head, 0);
 518
 519         /*
 520          * by now pioavail updates to memory should have occurred, so
 521          * copy them into our working/shadow registers; this is in
 522          * case something went wrong with abort, but mostly to get the
 523          * initial values of the generation bit correct.
 524          */
 525         for (i = 0; i < dd->ipath_pioavregs; i++) {
 526                 __le64 val;
 527
 528                 /*
 529                  * Chip Errata bug 6641; even and odd qwords>3 are swapped.
 530                  */
 531                 if (i > 3) {
 532                         if (i & 1)
 533                                 val = dd->ipath_pioavailregs_dma[i - 1];
 534                         else
 535                                 val = dd->ipath_pioavailregs_dma[i + 1];
 536                 }
 537                 else
 538                         val = dd->ipath_pioavailregs_dma[i];
 539                 dd->ipath_pioavailshadow[i] = le64_to_cpu(val);
 540         }
 541         /* can get counters, stats, etc. */
 542         dd->ipath_flags |= IPATH_PRESENT;
 543 }
 544
 545 static int init_housekeeping(struct ipath_devdata *dd,
 546                              struct ipath_portdata **pdp, int reinit)
 547 {
 548         char boardn[32];
 549         int ret = 0;
 550
 551         /*
 552          * have to clear shadow copies of registers at init that are
 553          * not otherwise set here, or all kinds of bizarre things
 554          * happen with driver on chip reset
 555          */
 556         dd->ipath_rcvhdrsize = 0;
 557
 558         /*
 559          * Don't clear ipath_flags as 8bit mode was set before
 560          * entering this func. However, we do set the linkstate to
 561          * unknown, so we can watch for a transition.
 562          * PRESENT is set because we want register reads to work,
 563          * and the kernel infrastructure saw it in config space;
 564          * We clear it if we have failures.
 565          */
 566         dd->ipath_flags |= IPATH_LINKUNK | IPATH_PRESENT;
 567         dd->ipath_flags &= ~(IPATH_LINKACTIVE | IPATH_LINKARMED |
 568                              IPATH_LINKDOWN | IPATH_LINKINIT);
 569
 570         ipath_cdbg(VERBOSE, "Try to read spc chip revision\n");
 571         dd->ipath_revision =
 572                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
 573
 574         /*
 575          * set up fundamental info we need to use the chip; we assume
 576          * if the revision reg and these regs are OK, we don't need to
 577          * special case the rest
 578          */
 579         dd->ipath_sregbase =
 580                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_sendregbase);
 581         dd->ipath_cregbase =
 582                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_counterregbase);
 583         dd->ipath_uregbase =
 584                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_userregbase);
 585         ipath_cdbg(VERBOSE, "ipath_kregbase %p, sendbase %x usrbase %x, "
 586                    "cntrbase %x\n", dd->ipath_kregbase, dd->ipath_sregbase,
 587                    dd->ipath_uregbase, dd->ipath_cregbase);
 588         if ((dd->ipath_revision & 0xffffffff) == 0xffffffff
 589             || (dd->ipath_sregbase & 0xffffffff) == 0xffffffff
 590             || (dd->ipath_cregbase & 0xffffffff) == 0xffffffff
 591             || (dd->ipath_uregbase & 0xffffffff) == 0xffffffff) {
 592                 ipath_dev_err(dd, "Register read failures from chip, "
 593                               "giving up initialization\n");
 594                 dd->ipath_flags &= ~IPATH_PRESENT;
 595                 ret = -ENODEV;
 596                 goto done;
 597         }
 598
 599
 600         /* clear diagctrl register, in case diags were running and crashed */
 601         ipath_write_kreg (dd, dd->ipath_kregs->kr_hwdiagctrl, 0);
 602
 603         /* clear the initial reset flag, in case first driver load */
 604         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
 605                          INFINIPATH_E_RESET);
 606
 607         if (reinit)
 608                 ret = init_chip_reset(dd, pdp);
 609         else
 610                 ret = init_chip_first(dd, pdp);
 611
 612         if (ret)
 613                 goto done;
 614
 615         ipath_cdbg(VERBOSE, "Revision %llx (PCI %x), %u ports, %u tids, "
 616                    "%u egrtids\n", (unsigned long long) dd->ipath_revision,
 617                    dd->ipath_pcirev, dd->ipath_portcnt, dd->ipath_rcvtidcnt,
 618                    dd->ipath_rcvegrcnt);
 619
 620         if (((dd->ipath_revision >> INFINIPATH_R_SOFTWARE_SHIFT) &
 621              INFINIPATH_R_SOFTWARE_MASK) != IPATH_CHIP_SWVERSION) {
 622                 ipath_dev_err(dd, "Driver only handles version %d, "
 623                               "chip swversion is %d (%llx), failng\n",
 624                               IPATH_CHIP_SWVERSION,
 625                               (int)(dd->ipath_revision >>
 626                                     INFINIPATH_R_SOFTWARE_SHIFT) &
 627                               INFINIPATH_R_SOFTWARE_MASK,
 628                               (unsigned long long) dd->ipath_revision);
 629                 ret = -ENOSYS;
 630                 goto done;
 631         }
 632         dd->ipath_majrev = (u8) ((dd->ipath_revision >>
 633                                   INFINIPATH_R_CHIPREVMAJOR_SHIFT) &
 634                                  INFINIPATH_R_CHIPREVMAJOR_MASK);
 635         dd->ipath_minrev = (u8) ((dd->ipath_revision >>
 636                                   INFINIPATH_R_CHIPREVMINOR_SHIFT) &
 637                                  INFINIPATH_R_CHIPREVMINOR_MASK);
 638         dd->ipath_boardrev = (u8) ((dd->ipath_revision >>
 639                                     INFINIPATH_R_BOARDID_SHIFT) &
 640                                    INFINIPATH_R_BOARDID_MASK);
 641
 642         ret = dd->ipath_f_get_boardname(dd, boardn, sizeof boardn);
 643
 644         snprintf(dd->ipath_boardversion, sizeof(dd->ipath_boardversion),
 645                  "ChipABI %u.%u, %s, InfiniPath%u %u.%u, PCI %u, "
 646                  "SW Compat %u\n",
 647                  IPATH_CHIP_VERS_MAJ, IPATH_CHIP_VERS_MIN, boardn,
 648                  (unsigned)(dd->ipath_revision >> INFINIPATH_R_ARCH_SHIFT) &
 649                  INFINIPATH_R_ARCH_MASK,
 650                  dd->ipath_majrev, dd->ipath_minrev, dd->ipath_pcirev,
 651                  (unsigned)(dd->ipath_revision >>
 652                             INFINIPATH_R_SOFTWARE_SHIFT) &
 653                  INFINIPATH_R_SOFTWARE_MASK);
 654
 655         ipath_dbg("%s", dd->ipath_boardversion);
 656
 657 done:
 658         return ret;
 659 }
 660
 661
 662 /**
 663  * ipath_init_chip - do the actual initialization sequence on the chip
 664  * @dd: the infinipath device
 665  * @reinit: reinitializing, so don't allocate new memory
 666  *
 667  * Do the actual initialization sequence on the chip.  This is done
 668  * both from the init routine called from the PCI infrastructure, and
 669  * when we reset the chip, or detect that it was reset internally,
 670  * or it's administratively re-enabled.
 671  *
 672  * Memory allocation here and in called routines is only done in
 673  * the first case (reinit == 0).  We have to be careful, because even
 674  * without memory allocation, we need to re-write all the chip registers
 675  * TIDs, etc. after the reset or enable has completed.
 676  */
 677 int ipath_init_chip(struct ipath_devdata *dd, int reinit)
 678 {
 679         int ret = 0;
 680         u32 val32, kpiobufs;
 681         u32 piobufs, uports;
 682         u64 val;
 683         struct ipath_portdata *pd = NULL; /* keep gcc4 happy */
 684         gfp_t gfp_flags = GFP_USER | __GFP_COMP;
 685         unsigned long flags;
 686
 687         ret = init_housekeeping(dd, &pd, reinit);
 688         if (ret)
 689                 goto done;
 690
 691         /*
 692          * we ignore most issues after reporting them, but have to specially
 693          * handle hardware-disabled chips.
 694          */
 695         if (ret == 2) {
 696                 /* unique error, known to ipath_init_one */
 697                 ret = -EPERM;
 698                 goto done;
 699         }
 700
 701         /*
 702          * We could bump this to allow for full rcvegrcnt + rcvtidcnt,
 703          * but then it no longer nicely fits power of two, and since
 704          * we now use routines that backend onto __get_free_pages, the
 705          * rest would be wasted.
 706          */
 707         dd->ipath_rcvhdrcnt = dd->ipath_rcvegrcnt;
 708         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt,
 709                          dd->ipath_rcvhdrcnt);
 710
 711         /*
 712          * Set up the shadow copies of the piobufavail registers,
 713          * which we compare against the chip registers for now, and
 714          * the in memory DMA'ed copies of the registers.  This has to
 715          * be done early, before we calculate lastport, etc.
 716          */
 717         piobufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
 718         /*
 719          * calc number of pioavail registers, and save it; we have 2
 720          * bits per buffer.
 721          */
 722         dd->ipath_pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2)
 723                 / (sizeof(u64) * BITS_PER_BYTE / 2);
 724         uports = dd->ipath_cfgports ? dd->ipath_cfgports - 1 : 0;
 725         if (ipath_kpiobufs == 0) {
 726                 /* not set by user (this is default) */
 727                 if (piobufs > 144)
 728                         kpiobufs = 32;
 729                 else
 730                         kpiobufs = 16;
 731         }
 732         else
 733                 kpiobufs = ipath_kpiobufs;
 734
 735         if (kpiobufs + (uports * IPATH_MIN_USER_PORT_BUFCNT) > piobufs) {
 736                 int i = (int) piobufs -
 737                         (int) (uports * IPATH_MIN_USER_PORT_BUFCNT);
 738                 if (i < 0)
 739                         i = 0;
 740                 dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs of "
 741                          "%d for kernel leaves too few for %d user ports "
 742                          "(%d each); using %u\n", kpiobufs,
 743                          piobufs, uports, IPATH_MIN_USER_PORT_BUFCNT, i);
 744                 /*
 745                  * shouldn't change ipath_kpiobufs, because could be
 746                  * different for different devices...
 747                  */
 748                 kpiobufs = i;
 749         }
 750         dd->ipath_lastport_piobuf = piobufs - kpiobufs;
 751         dd->ipath_pbufsport =
 752                 uports ? dd->ipath_lastport_piobuf / uports : 0;
 753         val32 = dd->ipath_lastport_piobuf - (dd->ipath_pbufsport * uports);
 754         if (val32 > 0) {
 755                 ipath_dbg("allocating %u pbufs/port leaves %u unused, "
 756                           "add to kernel\n", dd->ipath_pbufsport, val32);
 757                 dd->ipath_lastport_piobuf -= val32;
 758                 ipath_dbg("%u pbufs/port leaves %u unused, add to kernel\n",
 759                           dd->ipath_pbufsport, val32);
 760         }
 761         dd->ipath_lastpioindex = dd->ipath_lastport_piobuf;
 762         ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u "
 763                    "each for %u user ports\n", kpiobufs,
 764                    piobufs, dd->ipath_pbufsport, uports);
 765
 766         dd->ipath_f_early_init(dd);
 767         /*
 768          * cancel any possible active sends from early driver load.
 769          * Follows early_init because some chips have to initialize
 770          * PIO buffers in early_init to avoid false parity errors.
 771          */
 772         ipath_cancel_sends(dd, 0);
 773
 774         /* early_init sets rcvhdrentsize and rcvhdrsize, so this must be
 775          * done after early_init */
 776         dd->ipath_hdrqlast =
 777                 dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1);
 778         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize,
 779                          dd->ipath_rcvhdrentsize);
 780         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
 781                          dd->ipath_rcvhdrsize);
 782
 783         if (!reinit) {
 784                 ret = init_pioavailregs(dd);
 785                 init_shadow_tids(dd);
 786                 if (ret)
 787                         goto done;
 788         }
 789
 790         (void)ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr,
 791                                dd->ipath_pioavailregs_phys);
 792         /*
 793          * this is to detect s/w errors, which the h/w works around by
 794          * ignoring the low 6 bits of address, if it wasn't aligned.
 795          */
 796         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr);
 797         if (val != dd->ipath_pioavailregs_phys) {
 798                 ipath_dev_err(dd, "Catastrophic software error, "
 799                               "SendPIOAvailAddr written as %lx, "
 800                               "read back as %llx\n",
 801                               (unsigned long) dd->ipath_pioavailregs_phys,
 802                               (unsigned long long) val);
 803                 ret = -EINVAL;
 804                 goto done;
 805         }
 806
 807         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP);
 808
 809         /*
 810          * make sure we are not in freeze, and PIO send enabled, so
 811          * writes to pbc happen
 812          */
 813         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL);
 814         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 815                          ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
 816         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
 817
 818         spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
 819         dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE;
 820         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
 821         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 822         spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
 823
 824         /*
 825          * before error clears, since we expect serdes pll errors during
 826          * this, the first time after reset
 827          */
 828         if (bringup_link(dd)) {
 829                 dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n");
 830                 ret = -ENETDOWN;
 831                 goto done;
 832         }
 833
 834         /*
 835          * clear any "expected" hwerrs from reset and/or initialization
 836          * clear any that aren't enabled (at least this once), and then
 837          * set the enable mask
 838          */
 839         dd->ipath_f_init_hwerrors(dd);
 840         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 841                          ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
 842         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 843                          dd->ipath_hwerrmask);
 844
 845         /* clear all */
 846         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
 847         /* enable errors that are masked, at least this first time. */
 848         ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
 849                          ~dd->ipath_maskederrs);
 850         dd->ipath_errormask = ipath_read_kreg64(dd,
 851                 dd->ipath_kregs->kr_errormask);
 852         /* clear any interrupts up to this point (ints still not enabled) */
 853         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
 854
 855         /*
 856          * Set up the port 0 (kernel) rcvhdr q and egr TIDs.  If doing
 857          * re-init, the simplest way to handle this is to free
 858          * existing, and re-allocate.
 859          * Need to re-create rest of port 0 portdata as well.
 860          */
 861         if (reinit) {
 862                 /* Alloc and init new ipath_portdata for port0,
 863                  * Then free old pd. Could lead to fragmentation, but also
 864                  * makes later support for hot-swap easier.
 865                  */
 866                 struct ipath_portdata *npd;
 867                 npd = create_portdata0(dd);
 868                 if (npd) {
 869                         ipath_free_pddata(dd, pd);
 870                         dd->ipath_pd[0] = pd = npd;
 871                 } else {
 872                         ipath_dev_err(dd, "Unable to allocate portdata for"
 873                                       "  port 0, failing\n");
 874                         ret = -ENOMEM;
 875                         goto done;
 876                 }
 877         }
 878         dd->ipath_f_tidtemplate(dd);
 879         ret = ipath_create_rcvhdrq(dd, pd);
 880         if (!ret) {
 881                 dd->ipath_hdrqtailptr =
 882                         (volatile __le64 *)pd->port_rcvhdrtail_kvaddr;
 883                 ret = create_port0_egr(dd);
 884         }
 885         if (ret)
 886                 ipath_dev_err(dd, "failed to allocate port 0 (kernel) "
 887                               "rcvhdrq and/or egr bufs\n");
 888         else
 889                 enable_chip(dd, pd, reinit);
 890
 891
 892         if (!ret && !reinit) {
 893             /* used when we close a port, for DMA already in flight at close */
 894                 dd->ipath_dummy_hdrq = dma_alloc_coherent(
 895                         &dd->pcidev->dev, pd->port_rcvhdrq_size,
 896                         &dd->ipath_dummy_hdrq_phys,
 897                         gfp_flags);
 898                 if (!dd->ipath_dummy_hdrq ) {
 899                         dev_info(&dd->pcidev->dev,
 900                                 "Couldn't allocate 0x%lx bytes for dummy hdrq\n",
 901                                 pd->port_rcvhdrq_size);
 902                         /* fallback to just 0'ing */
 903                         dd->ipath_dummy_hdrq_phys = 0UL;
 904                 }
 905         }
 906
 907         /*
 908          * cause retrigger of pending interrupts ignored during init,
 909          * even if we had errors
 910          */
 911         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
 912
 913         if(!dd->ipath_stats_timer_active) {
 914                 /*
 915                  * first init, or after an admin disable/enable
 916                  * set up stats retrieval timer, even if we had errors
 917                  * in last portion of setup
 918                  */
 919                 init_timer(&dd->ipath_stats_timer);
 920                 dd->ipath_stats_timer.function = ipath_get_faststats;
 921                 dd->ipath_stats_timer.data = (unsigned long) dd;
 922                 /* every 5 seconds; */
 923                 dd->ipath_stats_timer.expires = jiffies + 5 * HZ;
 924                 /* takes ~16 seconds to overflow at full IB 4x bandwdith */
 925                 add_timer(&dd->ipath_stats_timer);
 926                 dd->ipath_stats_timer_active = 1;
 927         }
 928
 929 done:
 930         if (!ret) {
 931                 *dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT;
 932                 if (!dd->ipath_f_intrsetup(dd)) {
 933                         /* now we can enable all interrupts from the chip */
 934                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
 935                                          -1LL);
 936                         /* force re-interrupt of any pending interrupts. */
 937                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear,
 938                                          0ULL);
 939                         /* chip is usable; mark it as initialized */
 940                         *dd->ipath_statusp |= IPATH_STATUS_INITTED;
 941                 } else
 942                         ipath_dev_err(dd, "No interrupts enabled, couldn't "
 943                                       "setup interrupt address\n");
 944
 945                 if (dd->ipath_cfgports > ipath_stats.sps_nports)
 946                         /*
 947                          * sps_nports is a global, so, we set it to
 948                          * the highest number of ports of any of the
 949                          * chips we find; we never decrement it, at
 950                          * least for now.  Since this might have changed
 951                          * over disable/enable or prior to reset, always
 952                          * do the check and potentially adjust.
 953                          */
 954                         ipath_stats.sps_nports = dd->ipath_cfgports;
 955         } else
 956                 ipath_dbg("Failed (%d) to initialize chip\n", ret);
 957
 958         /* if ret is non-zero, we probably should do some cleanup
 959            here... */
 960         return ret;
 961 }
 962
 963 static int ipath_set_kpiobufs(const char *str, struct kernel_param *kp)
 964 {
 965         struct ipath_devdata *dd;
 966         unsigned long flags;
 967         unsigned short val;
 968         int ret;
 969
 970         ret = ipath_parse_ushort(str, &val);
 971
 972         spin_lock_irqsave(&ipath_devs_lock, flags);
 973
 974         if (ret < 0)
 975                 goto bail;
 976
 977         if (val == 0) {
 978                 ret = -EINVAL;
 979                 goto bail;
 980         }
 981
 982         list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
 983                 if (dd->ipath_kregbase)
 984                         continue;
 985                 if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
 986                            (dd->ipath_cfgports *
 987                             IPATH_MIN_USER_PORT_BUFCNT)))
 988                 {
 989                         ipath_dev_err(
 990                                 dd,
 991                                 "Allocating %d PIO bufs for kernel leaves "
 992                                 "too few for %d user ports (%d each)\n",
 993                                 val, dd->ipath_cfgports - 1,
 994                                 IPATH_MIN_USER_PORT_BUFCNT);
 995                         ret = -EINVAL;
 996                         goto bail;
 997                 }
 998                 dd->ipath_lastport_piobuf =
 999                         dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val;
1000         }
1001
1002         ipath_kpiobufs = val;
1003         ret = 0;
1004 bail:
1005         spin_unlock_irqrestore(&ipath_devs_lock, flags);
1006
1007         return ret;
1008 }