SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/infiniband/hw/ipath/ipath_iba6110.c

   1 /*
   2  * Copyright (c) 2006 QLogic, Inc. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 /*
  35  * This file contains all of the code that is specific to the InfiniPath
  36  * HT chip.
  37  */
  38
  39 #include <linux/pci.h>
  40 #include <linux/delay.h>
  41 #include <linux/htirq.h>
  42
  43 #include "ipath_kernel.h"
  44 #include "ipath_registers.h"
  45
  46 /*
  47  * This lists the InfiniPath registers, in the actual chip layout.
  48  * This structure should never be directly accessed.
  49  *
  50  * The names are in InterCap form because they're taken straight from
  51  * the chip specification.  Since they're only used in this file, they
  52  * don't pollute the rest of the source.
  53 */
  54
  55 struct _infinipath_do_not_use_kernel_regs {
  56         unsigned long long Revision;
  57         unsigned long long Control;
  58         unsigned long long PageAlign;
  59         unsigned long long PortCnt;
  60         unsigned long long DebugPortSelect;
  61         unsigned long long DebugPort;
  62         unsigned long long SendRegBase;
  63         unsigned long long UserRegBase;
  64         unsigned long long CounterRegBase;
  65         unsigned long long Scratch;
  66         unsigned long long ReservedMisc1;
  67         unsigned long long InterruptConfig;
  68         unsigned long long IntBlocked;
  69         unsigned long long IntMask;
  70         unsigned long long IntStatus;
  71         unsigned long long IntClear;
  72         unsigned long long ErrorMask;
  73         unsigned long long ErrorStatus;
  74         unsigned long long ErrorClear;
  75         unsigned long long HwErrMask;
  76         unsigned long long HwErrStatus;
  77         unsigned long long HwErrClear;
  78         unsigned long long HwDiagCtrl;
  79         unsigned long long MDIO;
  80         unsigned long long IBCStatus;
  81         unsigned long long IBCCtrl;
  82         unsigned long long ExtStatus;
  83         unsigned long long ExtCtrl;
  84         unsigned long long GPIOOut;
  85         unsigned long long GPIOMask;
  86         unsigned long long GPIOStatus;
  87         unsigned long long GPIOClear;
  88         unsigned long long RcvCtrl;
  89         unsigned long long RcvBTHQP;
  90         unsigned long long RcvHdrSize;
  91         unsigned long long RcvHdrCnt;
  92         unsigned long long RcvHdrEntSize;
  93         unsigned long long RcvTIDBase;
  94         unsigned long long RcvTIDCnt;
  95         unsigned long long RcvEgrBase;
  96         unsigned long long RcvEgrCnt;
  97         unsigned long long RcvBufBase;
  98         unsigned long long RcvBufSize;
  99         unsigned long long RxIntMemBase;
 100         unsigned long long RxIntMemSize;
 101         unsigned long long RcvPartitionKey;
 102         unsigned long long ReservedRcv[10];
 103         unsigned long long SendCtrl;
 104         unsigned long long SendPIOBufBase;
 105         unsigned long long SendPIOSize;
 106         unsigned long long SendPIOBufCnt;
 107         unsigned long long SendPIOAvailAddr;
 108         unsigned long long TxIntMemBase;
 109         unsigned long long TxIntMemSize;
 110         unsigned long long ReservedSend[9];
 111         unsigned long long SendBufferError;
 112         unsigned long long SendBufferErrorCONT1;
 113         unsigned long long SendBufferErrorCONT2;
 114         unsigned long long SendBufferErrorCONT3;
 115         unsigned long long ReservedSBE[4];
 116         unsigned long long RcvHdrAddr0;
 117         unsigned long long RcvHdrAddr1;
 118         unsigned long long RcvHdrAddr2;
 119         unsigned long long RcvHdrAddr3;
 120         unsigned long long RcvHdrAddr4;
 121         unsigned long long RcvHdrAddr5;
 122         unsigned long long RcvHdrAddr6;
 123         unsigned long long RcvHdrAddr7;
 124         unsigned long long RcvHdrAddr8;
 125         unsigned long long ReservedRHA[7];
 126         unsigned long long RcvHdrTailAddr0;
 127         unsigned long long RcvHdrTailAddr1;
 128         unsigned long long RcvHdrTailAddr2;
 129         unsigned long long RcvHdrTailAddr3;
 130         unsigned long long RcvHdrTailAddr4;
 131         unsigned long long RcvHdrTailAddr5;
 132         unsigned long long RcvHdrTailAddr6;
 133         unsigned long long RcvHdrTailAddr7;
 134         unsigned long long RcvHdrTailAddr8;
 135         unsigned long long ReservedRHTA[7];
 136         unsigned long long Sync;        /* Software only */
 137         unsigned long long Dump;        /* Software only */
 138         unsigned long long SimVer;      /* Software only */
 139         unsigned long long ReservedSW[5];
 140         unsigned long long SerdesConfig0;
 141         unsigned long long SerdesConfig1;
 142         unsigned long long SerdesStatus;
 143         unsigned long long XGXSConfig;
 144         unsigned long long ReservedSW2[4];
 145 };
 146
 147 #define IPATH_KREG_OFFSET(field) (offsetof(struct \
 148     _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
 149 #define IPATH_CREG_OFFSET(field) (offsetof( \
 150     struct infinipath_counters, field) / sizeof(u64))
 151
 152 static const struct ipath_kregs ipath_ht_kregs = {
 153         .kr_control = IPATH_KREG_OFFSET(Control),
 154         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
 155         .kr_debugport = IPATH_KREG_OFFSET(DebugPort),
 156         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
 157         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
 158         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
 159         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
 160         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
 161         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
 162         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
 163         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
 164         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
 165         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
 166         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
 167         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
 168         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
 169         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
 170         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
 171         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
 172         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
 173         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
 174         .kr_interruptconfig = IPATH_KREG_OFFSET(InterruptConfig),
 175         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
 176         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
 177         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
 178         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
 179         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
 180         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
 181         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
 182         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
 183         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
 184         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
 185         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
 186         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
 187         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
 188         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
 189         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
 190         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
 191         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
 192         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
 193         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
 194         .kr_revision = IPATH_KREG_OFFSET(Revision),
 195         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
 196         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
 197         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
 198         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
 199         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
 200         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
 201         .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
 202         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
 203         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
 204         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
 205         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
 206         .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
 207         .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
 208         .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
 209         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
 210         /*
 211          * These should not be used directly via ipath_write_kreg64(),
 212          * use them with ipath_write_kreg64_port(),
 213          */
 214         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
 215         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0)
 216 };
 217
 218 static const struct ipath_cregs ipath_ht_cregs = {
 219         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
 220         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
 221         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
 222         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
 223         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
 224         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
 225         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
 226         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
 227         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
 228         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
 229         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
 230         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
 231         /* calc from Reg_CounterRegBase + offset */
 232         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
 233         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
 234         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
 235         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
 236         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
 237         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
 238         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
 239         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
 240         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
 241         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
 242         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
 243         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
 244         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
 245         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
 246         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
 247         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
 248         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
 249         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
 250         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
 251         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
 252         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
 253 };
 254
 255 /* kr_intstatus, kr_intclear, kr_intmask bits */
 256 #define INFINIPATH_I_RCVURG_MASK ((1U<<9)-1)
 257 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<9)-1)
 258
 259 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
 260 #define INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT 0
 261 #define INFINIPATH_HWE_HTCMEMPARITYERR_MASK 0x3FFFFFULL
 262 #define INFINIPATH_HWE_HTCLNKABYTE0CRCERR   0x0000000000800000ULL
 263 #define INFINIPATH_HWE_HTCLNKABYTE1CRCERR   0x0000000001000000ULL
 264 #define INFINIPATH_HWE_HTCLNKBBYTE0CRCERR   0x0000000002000000ULL
 265 #define INFINIPATH_HWE_HTCLNKBBYTE1CRCERR   0x0000000004000000ULL
 266 #define INFINIPATH_HWE_HTCMISCERR4          0x0000000008000000ULL
 267 #define INFINIPATH_HWE_HTCMISCERR5          0x0000000010000000ULL
 268 #define INFINIPATH_HWE_HTCMISCERR6          0x0000000020000000ULL
 269 #define INFINIPATH_HWE_HTCMISCERR7          0x0000000040000000ULL
 270 #define INFINIPATH_HWE_HTCBUSTREQPARITYERR  0x0000000080000000ULL
 271 #define INFINIPATH_HWE_HTCBUSTRESPPARITYERR 0x0000000100000000ULL
 272 #define INFINIPATH_HWE_HTCBUSIREQPARITYERR  0x0000000200000000ULL
 273 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
 274 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
 275 #define INFINIPATH_HWE_HTBPLL_FBSLIP        0x0200000000000000ULL
 276 #define INFINIPATH_HWE_HTBPLL_RFSLIP        0x0400000000000000ULL
 277 #define INFINIPATH_HWE_HTAPLL_FBSLIP        0x0800000000000000ULL
 278 #define INFINIPATH_HWE_HTAPLL_RFSLIP        0x1000000000000000ULL
 279 #define INFINIPATH_HWE_SERDESPLLFAILED      0x2000000000000000ULL
 280
 281 /* kr_extstatus bits */
 282 #define INFINIPATH_EXTS_FREQSEL 0x2
 283 #define INFINIPATH_EXTS_SERDESSEL 0x4
 284 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
 285 #define INFINIPATH_EXTS_MEMBIST_CORRECT     0x0000000000008000
 286
 287
 288 /* TID entries (memory), HT-only */
 289 #define INFINIPATH_RT_ADDR_MASK 0xFFFFFFFFFFULL /* 40 bits valid */
 290 #define INFINIPATH_RT_VALID 0x8000000000000000ULL
 291 #define INFINIPATH_RT_ADDR_SHIFT 0
 292 #define INFINIPATH_RT_BUFSIZE_MASK 0x3FFFULL
 293 #define INFINIPATH_RT_BUFSIZE_SHIFT 48
 294
 295 /*
 296  * masks and bits that are different in different chips, or present only
 297  * in one
 298  */
 299 static const ipath_err_t infinipath_hwe_htcmemparityerr_mask =
 300     INFINIPATH_HWE_HTCMEMPARITYERR_MASK;
 301 static const ipath_err_t infinipath_hwe_htcmemparityerr_shift =
 302     INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT;
 303
 304 static const ipath_err_t infinipath_hwe_htclnkabyte0crcerr =
 305     INFINIPATH_HWE_HTCLNKABYTE0CRCERR;
 306 static const ipath_err_t infinipath_hwe_htclnkabyte1crcerr =
 307     INFINIPATH_HWE_HTCLNKABYTE1CRCERR;
 308 static const ipath_err_t infinipath_hwe_htclnkbbyte0crcerr =
 309     INFINIPATH_HWE_HTCLNKBBYTE0CRCERR;
 310 static const ipath_err_t infinipath_hwe_htclnkbbyte1crcerr =
 311     INFINIPATH_HWE_HTCLNKBBYTE1CRCERR;
 312
 313 #define _IPATH_GPIO_SDA_NUM 1
 314 #define _IPATH_GPIO_SCL_NUM 0
 315
 316 #define IPATH_GPIO_SDA \
 317         (1ULL << (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 318 #define IPATH_GPIO_SCL \
 319         (1ULL << (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 320
 321 /* keep the code below somewhat more readonable; not used elsewhere */
 322 #define _IPATH_HTLINK0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
 323                                 infinipath_hwe_htclnkabyte1crcerr)
 324 #define _IPATH_HTLINK1_CRCBITS (infinipath_hwe_htclnkbbyte0crcerr |     \
 325                                 infinipath_hwe_htclnkbbyte1crcerr)
 326 #define _IPATH_HTLANE0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
 327                                 infinipath_hwe_htclnkbbyte0crcerr)
 328 #define _IPATH_HTLANE1_CRCBITS (infinipath_hwe_htclnkabyte1crcerr |     \
 329                                 infinipath_hwe_htclnkbbyte1crcerr)
 330
 331 static void hwerr_crcbits(struct ipath_devdata *dd, ipath_err_t hwerrs,
 332                           char *msg, size_t msgl)
 333 {
 334         char bitsmsg[64];
 335         ipath_err_t crcbits = hwerrs &
 336                 (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS);
 337         /* don't check if 8bit HT */
 338         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
 339                 crcbits &= ~infinipath_hwe_htclnkabyte1crcerr;
 340         /* don't check if 8bit HT */
 341         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
 342                 crcbits &= ~infinipath_hwe_htclnkbbyte1crcerr;
 343         /*
 344          * we'll want to ignore link errors on link that is
 345          * not in use, if any.  For now, complain about both
 346          */
 347         if (crcbits) {
 348                 u16 ctrl0, ctrl1;
 349                 snprintf(bitsmsg, sizeof bitsmsg,
 350                          "[HT%s lane %s CRC (%llx); powercycle to completely clear]",
 351                          !(crcbits & _IPATH_HTLINK1_CRCBITS) ?
 352                          "0 (A)" : (!(crcbits & _IPATH_HTLINK0_CRCBITS)
 353                                     ? "1 (B)" : "0+1 (A+B)"),
 354                          !(crcbits & _IPATH_HTLANE1_CRCBITS) ? "0"
 355                          : (!(crcbits & _IPATH_HTLANE0_CRCBITS) ? "1" :
 356                             "0+1"), (unsigned long long) crcbits);
 357                 strlcat(msg, bitsmsg, msgl);
 358
 359                 /*
 360                  * print extra info for debugging.  slave/primary
 361                  * config word 4, 8 (link control 0, 1)
 362                  */
 363
 364                 if (pci_read_config_word(dd->pcidev,
 365                                          dd->ipath_ht_slave_off + 0x4,
 366                                          &ctrl0))
 367                         dev_info(&dd->pcidev->dev, "Couldn't read "
 368                                  "linkctrl0 of slave/primary "
 369                                  "config block\n");
 370                 else if (!(ctrl0 & 1 << 6))
 371                         /* not if EOC bit set */
 372                         ipath_dbg("HT linkctrl0 0x%x%s%s\n", ctrl0,
 373                                   ((ctrl0 >> 8) & 7) ? " CRC" : "",
 374                                   ((ctrl0 >> 4) & 1) ? "linkfail" :
 375                                   "");
 376                 if (pci_read_config_word(dd->pcidev,
 377                                          dd->ipath_ht_slave_off + 0x8,
 378                                          &ctrl1))
 379                         dev_info(&dd->pcidev->dev, "Couldn't read "
 380                                  "linkctrl1 of slave/primary "
 381                                  "config block\n");
 382                 else if (!(ctrl1 & 1 << 6))
 383                         /* not if EOC bit set */
 384                         ipath_dbg("HT linkctrl1 0x%x%s%s\n", ctrl1,
 385                                   ((ctrl1 >> 8) & 7) ? " CRC" : "",
 386                                   ((ctrl1 >> 4) & 1) ? "linkfail" :
 387                                   "");
 388
 389                 /* disable until driver reloaded */
 390                 dd->ipath_hwerrmask &= ~crcbits;
 391                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 392                                  dd->ipath_hwerrmask);
 393                 ipath_dbg("HT crc errs: %s\n", msg);
 394         } else
 395                 ipath_dbg("ignoring HT crc errors 0x%llx, "
 396                           "not in use\n", (unsigned long long)
 397                           (hwerrs & (_IPATH_HTLINK0_CRCBITS |
 398                                      _IPATH_HTLINK1_CRCBITS)));
 399 }
 400
 401 /* 6110 specific hardware errors... */
 402 static const struct ipath_hwerror_msgs ipath_6110_hwerror_msgs[] = {
 403         INFINIPATH_HWE_MSG(HTCBUSIREQPARITYERR, "HTC Ireq Parity"),
 404         INFINIPATH_HWE_MSG(HTCBUSTREQPARITYERR, "HTC Treq Parity"),
 405         INFINIPATH_HWE_MSG(HTCBUSTRESPPARITYERR, "HTC Tresp Parity"),
 406         INFINIPATH_HWE_MSG(HTCMISCERR5, "HT core Misc5"),
 407         INFINIPATH_HWE_MSG(HTCMISCERR6, "HT core Misc6"),
 408         INFINIPATH_HWE_MSG(HTCMISCERR7, "HT core Misc7"),
 409         INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
 410         INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
 411 };
 412
 413 #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
 414                         INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
 415                         << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
 416 #define RXE_EAGER_PARITY (INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID \
 417                           << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)
 418
 419 static int ipath_ht_txe_recover(struct ipath_devdata *);
 420
 421 /**
 422  * ipath_ht_handle_hwerrors - display hardware errors.
 423  * @dd: the infinipath device
 424  * @msg: the output buffer
 425  * @msgl: the size of the output buffer
 426  *
 427  * Use same msg buffer as regular errors to avoid excessive stack
 428  * use.  Most hardware errors are catastrophic, but for right now,
 429  * we'll print them and continue.  We reuse the same message buffer as
 430  * ipath_handle_errors() to avoid excessive stack usage.
 431  */
 432 static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
 433                                      size_t msgl)
 434 {
 435         ipath_err_t hwerrs;
 436         u32 bits, ctrl;
 437         int isfatal = 0;
 438         char bitsmsg[64];
 439
 440         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
 441
 442         if (!hwerrs) {
 443                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
 444                 /*
 445                  * better than printing cofusing messages
 446                  * This seems to be related to clearing the crc error, or
 447                  * the pll error during init.
 448                  */
 449                 goto bail;
 450         } else if (hwerrs == -1LL) {
 451                 ipath_dev_err(dd, "Read of hardware error status failed "
 452                               "(all bits set); ignoring\n");
 453                 goto bail;
 454         }
 455         ipath_stats.sps_hwerrs++;
 456
 457         /* Always clear the error status register, except MEMBISTFAIL,
 458          * regardless of whether we continue or stop using the chip.
 459          * We want that set so we know it failed, even across driver reload.
 460          * We'll still ignore it in the hwerrmask.  We do this partly for
 461          * diagnostics, but also for support */
 462         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 463                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
 464
 465         hwerrs &= dd->ipath_hwerrmask;
 466
 467         /*
 468          * make sure we get this much out, unless told to be quiet,
 469          * it's a parity error we may recover from,
 470          * or it's occurred within the last 5 seconds
 471          */
 472         if ((hwerrs & ~(dd->ipath_lasthwerror | TXE_PIO_PARITY |
 473                 RXE_EAGER_PARITY)) ||
 474                 (ipath_debug & __IPATH_VERBDBG))
 475                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
 476                          "(cleared)\n", (unsigned long long) hwerrs);
 477         dd->ipath_lasthwerror |= hwerrs;
 478
 479         if (hwerrs & ~dd->ipath_hwe_bitsextant)
 480                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
 481                               "%llx set\n", (unsigned long long)
 482                               (hwerrs & ~dd->ipath_hwe_bitsextant));
 483
 484         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
 485         if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) {
 486                 /*
 487                  * parity errors in send memory are recoverable,
 488                  * just cancel the send (if indicated in * sendbuffererror),
 489                  * count the occurrence, unfreeze (if no other handled
 490                  * hardware error bits are set), and continue. They can
 491                  * occur if a processor speculative read is done to the PIO
 492                  * buffer while we are sending a packet, for example.
 493                  */
 494                 if ((hwerrs & TXE_PIO_PARITY) && ipath_ht_txe_recover(dd))
 495                         hwerrs &= ~TXE_PIO_PARITY;
 496                 if (hwerrs & RXE_EAGER_PARITY)
 497                         ipath_dev_err(dd, "RXE parity, Eager TID error is not "
 498                                 "recoverable\n");
 499                 if (!hwerrs) {
 500                         ipath_dbg("Clearing freezemode on ignored or "
 501                                   "recovered hardware error\n");
 502                         ctrl &= ~INFINIPATH_C_FREEZEMODE;
 503                         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 504                                          ctrl);
 505                 }
 506         }
 507
 508         *msg = '\0';
 509
 510         /*
 511          * may someday want to decode into which bits are which
 512          * functional area for parity errors, etc.
 513          */
 514         if (hwerrs & (infinipath_hwe_htcmemparityerr_mask
 515                       << INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT)) {
 516                 bits = (u32) ((hwerrs >>
 517                                INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) &
 518                               INFINIPATH_HWE_HTCMEMPARITYERR_MASK);
 519                 snprintf(bitsmsg, sizeof bitsmsg, "[HTC Parity Errs %x] ",
 520                          bits);
 521                 strlcat(msg, bitsmsg, msgl);
 522         }
 523
 524         ipath_format_hwerrors(hwerrs,
 525                               ipath_6110_hwerror_msgs,
 526                               sizeof(ipath_6110_hwerror_msgs) /
 527                               sizeof(ipath_6110_hwerror_msgs[0]),
 528                               msg, msgl);
 529
 530         if (hwerrs & (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS))
 531                 hwerr_crcbits(dd, hwerrs, msg, msgl);
 532
 533         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
 534                 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
 535                         msgl);
 536                 /* ignore from now on, so disable until driver reloaded */
 537                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
 538                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 539                                  dd->ipath_hwerrmask);
 540         }
 541 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
 542                          INFINIPATH_HWE_COREPLL_RFSLIP |        \
 543                          INFINIPATH_HWE_HTBPLL_FBSLIP |         \
 544                          INFINIPATH_HWE_HTBPLL_RFSLIP |         \
 545                          INFINIPATH_HWE_HTAPLL_FBSLIP |         \
 546                          INFINIPATH_HWE_HTAPLL_RFSLIP)
 547
 548         if (hwerrs & _IPATH_PLL_FAIL) {
 549                 snprintf(bitsmsg, sizeof bitsmsg,
 550                          "[PLL failed (%llx), InfiniPath hardware unusable]",
 551                          (unsigned long long) (hwerrs & _IPATH_PLL_FAIL));
 552                 strlcat(msg, bitsmsg, msgl);
 553                 /* ignore from now on, so disable until driver reloaded */
 554                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
 555                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 556                                  dd->ipath_hwerrmask);
 557         }
 558
 559         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
 560                 /*
 561                  * If it occurs, it is left masked since the eternal
 562                  * interface is unused
 563                  */
 564                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 565                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 566                                  dd->ipath_hwerrmask);
 567         }
 568
 569         if (hwerrs) {
 570                 /*
 571                  * if any set that we aren't ignoring; only
 572                  * make the complaint once, in case it's stuck
 573                  * or recurring, and we get here multiple
 574                  * times.
 575                  */
 576                 ipath_dev_err(dd, "%s hardware error\n", msg);
 577                 if (dd->ipath_flags & IPATH_INITTED) {
 578                         ipath_dev_err(dd, "Fatal Hardware Error (freeze "
 579                                           "mode), no longer usable, SN %.16s\n",
 580                                           dd->ipath_serial);
 581                         isfatal = 1;
 582                 }
 583                 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
 584                 /* mark as having had error */
 585                 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 586                 /*
 587                  * mark as not usable, at a minimum until driver
 588                  * is reloaded, probably until reboot, since no
 589                  * other reset is possible.
 590                  */
 591                 dd->ipath_flags &= ~IPATH_INITTED;
 592         }
 593         else
 594                 *msg = 0; /* recovered from all of them */
 595         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
 596                 /*
 597                  * for status file; if no trailing brace is copied,
 598                  * we'll know it was truncated.
 599                  */
 600                 snprintf(dd->ipath_freezemsg,
 601                          dd->ipath_freezelen, "{%s}", msg);
 602
 603 bail:;
 604 }
 605
 606 /**
 607  * ipath_ht_boardname - fill in the board name
 608  * @dd: the infinipath device
 609  * @name: the output buffer
 610  * @namelen: the size of the output buffer
 611  *
 612  * fill in the board name, based on the board revision register
 613  */
 614 static int ipath_ht_boardname(struct ipath_devdata *dd, char *name,
 615                               size_t namelen)
 616 {
 617         char *n = NULL;
 618         u8 boardrev = dd->ipath_boardrev;
 619         int ret;
 620
 621         switch (boardrev) {
 622         case 4:         /* Ponderosa is one of the bringup boards */
 623                 n = "Ponderosa";
 624                 break;
 625         case 5:
 626                 /*
 627                  * original production board; two production levels, with
 628                  * different serial number ranges.   See ipath_ht_early_init() for
 629                  * case where we enable IPATH_GPIO_INTR for later serial # range.
 630                  */
 631                 n = "InfiniPath_QHT7040";
 632                 break;
 633         case 6:
 634                 n = "OEM_Board_3";
 635                 break;
 636         case 7:
 637                 /* small form factor production board */
 638                 n = "InfiniPath_QHT7140";
 639                 break;
 640         case 8:
 641                 n = "LS/X-1";
 642                 break;
 643         case 9:         /* Comstock bringup test board */
 644                 n = "Comstock";
 645                 break;
 646         case 10:
 647                 n = "OEM_Board_2";
 648                 break;
 649         case 11:
 650                 n = "InfiniPath_HT-470"; /* obsoleted */
 651                 break;
 652         case 12:
 653                 n = "OEM_Board_4";
 654                 break;
 655         default:                /* don't know, just print the number */
 656                 ipath_dev_err(dd, "Don't yet know about board "
 657                               "with ID %u\n", boardrev);
 658                 snprintf(name, namelen, "Unknown_InfiniPath_QHT7xxx_%u",
 659                          boardrev);
 660                 break;
 661         }
 662         if (n)
 663                 snprintf(name, namelen, "%s", n);
 664
 665         if (dd->ipath_majrev != 3 || (dd->ipath_minrev < 2 ||
 666                 dd->ipath_minrev > 3)) {
 667                 /*
 668                  * This version of the driver only supports Rev 3.2 and 3.3
 669                  */
 670                 ipath_dev_err(dd,
 671                               "Unsupported InfiniPath hardware revision %u.%u!\n",
 672                               dd->ipath_majrev, dd->ipath_minrev);
 673                 ret = 1;
 674                 goto bail;
 675         }
 676         /*
 677          * pkt/word counters are 32 bit, and therefore wrap fast enough
 678          * that we snapshot them from a timer, and maintain 64 bit shadow
 679          * copies
 680          */
 681         dd->ipath_flags |= IPATH_32BITCOUNTERS;
 682         if (dd->ipath_htspeed != 800)
 683                 ipath_dev_err(dd,
 684                               "Incorrectly configured for HT @ %uMHz\n",
 685                               dd->ipath_htspeed);
 686         if (dd->ipath_boardrev == 7 || dd->ipath_boardrev == 11 ||
 687             dd->ipath_boardrev == 6)
 688                 dd->ipath_flags |= IPATH_GPIO_INTR;
 689         else
 690                 dd->ipath_flags |= IPATH_POLL_RX_INTR;
 691         if (dd->ipath_boardrev == 8) {  /* LS/X-1 */
 692                 u64 val;
 693                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
 694                 if (val & INFINIPATH_EXTS_SERDESSEL) {
 695                         /*
 696                          * hardware disabled
 697                          *
 698                          * This means that the chip is hardware disabled,
 699                          * and will not be able to bring up the link,
 700                          * in any case.  We special case this and abort
 701                          * early, to avoid later messages.  We also set
 702                          * the DISABLED status bit
 703                          */
 704                         ipath_dbg("Unit %u is hardware-disabled\n",
 705                                   dd->ipath_unit);
 706                         *dd->ipath_statusp |= IPATH_STATUS_DISABLED;
 707                         /* this value is handled differently */
 708                         ret = 2;
 709                         goto bail;
 710                 }
 711         }
 712         ret = 0;
 713
 714 bail:
 715         return ret;
 716 }
 717
 718 static void ipath_check_htlink(struct ipath_devdata *dd)
 719 {
 720         u8 linkerr, link_off, i;
 721
 722         for (i = 0; i < 2; i++) {
 723                 link_off = dd->ipath_ht_slave_off + i * 4 + 0xd;
 724                 if (pci_read_config_byte(dd->pcidev, link_off, &linkerr))
 725                         dev_info(&dd->pcidev->dev, "Couldn't read "
 726                                  "linkerror%d of HT slave/primary block\n",
 727                                  i);
 728                 else if (linkerr & 0xf0) {
 729                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
 730                                    "clearing\n", linkerr >> 4, i);
 731                         /*
 732                          * writing the linkerr bits that are set should
 733                          * clear them
 734                          */
 735                         if (pci_write_config_byte(dd->pcidev, link_off,
 736                                                   linkerr))
 737                                 ipath_dbg("Failed write to clear HT "
 738                                           "linkerror%d\n", i);
 739                         if (pci_read_config_byte(dd->pcidev, link_off,
 740                                                  &linkerr))
 741                                 dev_info(&dd->pcidev->dev,
 742                                          "Couldn't reread linkerror%d of "
 743                                          "HT slave/primary block\n", i);
 744                         else if (linkerr & 0xf0)
 745                                 dev_info(&dd->pcidev->dev,
 746                                          "HT linkerror%d bits 0x%x "
 747                                          "couldn't be cleared\n",
 748                                          i, linkerr >> 4);
 749                 }
 750         }
 751 }
 752
 753 static int ipath_setup_ht_reset(struct ipath_devdata *dd)
 754 {
 755         ipath_dbg("No reset possible for this InfiniPath hardware\n");
 756         return 0;
 757 }
 758
 759 #define HT_INTR_DISC_CONFIG  0x80       /* HT interrupt and discovery cap */
 760 #define HT_INTR_REG_INDEX    2  /* intconfig requires indirect accesses */
 761
 762 /*
 763  * Bits 13-15 of command==0 is slave/primary block.  Clear any HT CRC
 764  * errors.  We only bother to do this at load time, because it's OK if
 765  * it happened before we were loaded (first time after boot/reset),
 766  * but any time after that, it's fatal anyway.  Also need to not check
 767  * for for upper byte errors if we are in 8 bit mode, so figure out
 768  * our width.  For now, at least, also complain if it's 8 bit.
 769  */
 770 static void slave_or_pri_blk(struct ipath_devdata *dd, struct pci_dev *pdev,
 771                              int pos, u8 cap_type)
 772 {
 773         u8 linkwidth = 0, linkerr, link_a_b_off, link_off;
 774         u16 linkctrl = 0;
 775         int i;
 776
 777         dd->ipath_ht_slave_off = pos;
 778         /* command word, master_host bit */
 779         /* master host || slave */
 780         if ((cap_type >> 2) & 1)
 781                 link_a_b_off = 4;
 782         else
 783                 link_a_b_off = 0;
 784         ipath_cdbg(VERBOSE, "HT%u (Link %c) connected to processor\n",
 785                    link_a_b_off ? 1 : 0,
 786                    link_a_b_off ? 'B' : 'A');
 787
 788         link_a_b_off += pos;
 789
 790         /*
 791          * check both link control registers; clear both HT CRC sets if
 792          * necessary.
 793          */
 794         for (i = 0; i < 2; i++) {
 795                 link_off = pos + i * 4 + 0x4;
 796                 if (pci_read_config_word(pdev, link_off, &linkctrl))
 797                         ipath_dev_err(dd, "Couldn't read HT link control%d "
 798                                       "register\n", i);
 799                 else if (linkctrl & (0xf << 8)) {
 800                         ipath_cdbg(VERBOSE, "Clear linkctrl%d CRC Error "
 801                                    "bits %x\n", i, linkctrl & (0xf << 8));
 802                         /*
 803                          * now write them back to clear the error.
 804                          */
 805                         pci_write_config_byte(pdev, link_off,
 806                                               linkctrl & (0xf << 8));
 807                 }
 808         }
 809
 810         /*
 811          * As with HT CRC bits, same for protocol errors that might occur
 812          * during boot.
 813          */
 814         for (i = 0; i < 2; i++) {
 815                 link_off = pos + i * 4 + 0xd;
 816                 if (pci_read_config_byte(pdev, link_off, &linkerr))
 817                         dev_info(&pdev->dev, "Couldn't read linkerror%d "
 818                                  "of HT slave/primary block\n", i);
 819                 else if (linkerr & 0xf0) {
 820                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
 821                                    "clearing\n", linkerr >> 4, i);
 822                         /*
 823                          * writing the linkerr bits that are set will clear
 824                          * them
 825                          */
 826                         if (pci_write_config_byte
 827                             (pdev, link_off, linkerr))
 828                                 ipath_dbg("Failed write to clear HT "
 829                                           "linkerror%d\n", i);
 830                         if (pci_read_config_byte(pdev, link_off, &linkerr))
 831                                 dev_info(&pdev->dev, "Couldn't reread "
 832                                          "linkerror%d of HT slave/primary "
 833                                          "block\n", i);
 834                         else if (linkerr & 0xf0)
 835                                 dev_info(&pdev->dev, "HT linkerror%d bits "
 836                                          "0x%x couldn't be cleared\n",
 837                                          i, linkerr >> 4);
 838                 }
 839         }
 840
 841         /*
 842          * this is just for our link to the host, not devices connected
 843          * through tunnel.
 844          */
 845
 846         if (pci_read_config_byte(pdev, link_a_b_off + 7, &linkwidth))
 847                 ipath_dev_err(dd, "Couldn't read HT link width "
 848                               "config register\n");
 849         else {
 850                 u32 width;
 851                 switch (linkwidth & 7) {
 852                 case 5:
 853                         width = 4;
 854                         break;
 855                 case 4:
 856                         width = 2;
 857                         break;
 858                 case 3:
 859                         width = 32;
 860                         break;
 861                 case 1:
 862                         width = 16;
 863                         break;
 864                 case 0:
 865                 default:        /* if wrong, assume 8 bit */
 866                         width = 8;
 867                         break;
 868                 }
 869
 870                 dd->ipath_htwidth = width;
 871
 872                 if (linkwidth != 0x11) {
 873                         ipath_dev_err(dd, "Not configured for 16 bit HT "
 874                                       "(%x)\n", linkwidth);
 875                         if (!(linkwidth & 0xf)) {
 876                                 ipath_dbg("Will ignore HT lane1 errors\n");
 877                                 dd->ipath_flags |= IPATH_8BIT_IN_HT0;
 878                         }
 879                 }
 880         }
 881
 882         /*
 883          * this is just for our link to the host, not devices connected
 884          * through tunnel.
 885          */
 886         if (pci_read_config_byte(pdev, link_a_b_off + 0xd, &linkwidth))
 887                 ipath_dev_err(dd, "Couldn't read HT link frequency "
 888                               "config register\n");
 889         else {
 890                 u32 speed;
 891                 switch (linkwidth & 0xf) {
 892                 case 6:
 893                         speed = 1000;
 894                         break;
 895                 case 5:
 896                         speed = 800;
 897                         break;
 898                 case 4:
 899                         speed = 600;
 900                         break;
 901                 case 3:
 902                         speed = 500;
 903                         break;
 904                 case 2:
 905                         speed = 400;
 906                         break;
 907                 case 1:
 908                         speed = 300;
 909                         break;
 910                 default:
 911                         /*
 912                          * assume reserved and vendor-specific are 200...
 913                          */
 914                 case 0:
 915                         speed = 200;
 916                         break;
 917                 }
 918                 dd->ipath_htspeed = speed;
 919         }
 920 }
 921
 922 static int ipath_ht_intconfig(struct ipath_devdata *dd)
 923 {
 924         int ret;
 925
 926         if (dd->ipath_intconfig) {
 927                 ipath_write_kreg(dd, dd->ipath_kregs->kr_interruptconfig,
 928                                  dd->ipath_intconfig);  /* interrupt address */
 929                 ret = 0;
 930         } else {
 931                 ipath_dev_err(dd, "No interrupts enabled, couldn't setup "
 932                               "interrupt address\n");
 933                 ret = -EINVAL;
 934         }
 935
 936         return ret;
 937 }
 938
 939 static void ipath_ht_irq_update(struct pci_dev *dev, int irq,
 940                                 struct ht_irq_msg *msg)
 941 {
 942         struct ipath_devdata *dd = pci_get_drvdata(dev);
 943         u64 prev_intconfig = dd->ipath_intconfig;
 944
 945         dd->ipath_intconfig = msg->address_lo;
 946         dd->ipath_intconfig |= ((u64) msg->address_hi) << 32;
 947
 948         /*
 949          * If the previous value of dd->ipath_intconfig is zero, we're
 950          * getting configured for the first time, and must not program the
 951          * intconfig register here (it will be programmed later, when the
 952          * hardware is ready).  Otherwise, we should.
 953          */
 954         if (prev_intconfig)
 955                 ipath_ht_intconfig(dd);
 956 }
 957
 958 /**
 959  * ipath_setup_ht_config - setup the interruptconfig register
 960  * @dd: the infinipath device
 961  * @pdev: the PCI device
 962  *
 963  * setup the interruptconfig register from the HT config info.
 964  * Also clear CRC errors in HT linkcontrol, if necessary.
 965  * This is done only for the real hardware.  It is done before
 966  * chip address space is initted, so can't touch infinipath registers
 967  */
 968 static int ipath_setup_ht_config(struct ipath_devdata *dd,
 969                                  struct pci_dev *pdev)
 970 {
 971         int pos, ret;
 972
 973         ret = __ht_create_irq(pdev, 0, ipath_ht_irq_update);
 974         if (ret < 0) {
 975                 ipath_dev_err(dd, "Couldn't create interrupt handler: "
 976                               "err %d\n", ret);
 977                 goto bail;
 978         }
 979         dd->ipath_irq = ret;
 980         ret = 0;
 981
 982         /*
 983          * Handle clearing CRC errors in linkctrl register if necessary.  We
 984          * do this early, before we ever enable errors or hardware errors,
 985          * mostly to avoid causing the chip to enter freeze mode.
 986          */
 987         pos = pci_find_capability(pdev, PCI_CAP_ID_HT);
 988         if (!pos) {
 989                 ipath_dev_err(dd, "Couldn't find HyperTransport "
 990                               "capability; no interrupts\n");
 991                 ret = -ENODEV;
 992                 goto bail;
 993         }
 994         do {
 995                 u8 cap_type;
 996
 997                 /* the HT capability type byte is 3 bytes after the
 998                  * capability byte.
 999                  */
1000                 if (pci_read_config_byte(pdev, pos + 3, &cap_type)) {
1001                         dev_info(&pdev->dev, "Couldn't read config "
1002                                  "command @ %d\n", pos);
1003                         continue;
1004                 }
1005                 if (!(cap_type & 0xE0))
1006                         slave_or_pri_blk(dd, pdev, pos, cap_type);
1007         } while ((pos = pci_find_next_capability(pdev, pos,
1008                                                  PCI_CAP_ID_HT)));
1009
1010 bail:
1011         return ret;
1012 }
1013
1014 /**
1015  * ipath_setup_ht_cleanup - clean up any per-chip chip-specific stuff
1016  * @dd: the infinipath device
1017  *
1018  * Called during driver unload.
1019  * This is currently a nop for the HT chip, not for all chips
1020  */
1021 static void ipath_setup_ht_cleanup(struct ipath_devdata *dd)
1022 {
1023 }
1024
1025 /**
1026  * ipath_setup_ht_setextled - set the state of the two external LEDs
1027  * @dd: the infinipath device
1028  * @lst: the L state
1029  * @ltst: the LT state
1030  *
1031  * Set the state of the two external LEDs, to indicate physical and
1032  * logical state of IB link.   For this chip (at least with recommended
1033  * board pinouts), LED1 is Green (physical state), and LED2 is Yellow
1034  * (logical state)
1035  *
1036  * Note:  We try to match the Mellanox HCA LED behavior as best
1037  * we can.  Green indicates physical link state is OK (something is
1038  * plugged in, and we can train).
1039  * Amber indicates the link is logically up (ACTIVE).
1040  * Mellanox further blinks the amber LED to indicate data packet
1041  * activity, but we have no hardware support for that, so it would
1042  * require waking up every 10-20 msecs and checking the counters
1043  * on the chip, and then turning the LED off if appropriate.  That's
1044  * visible overhead, so not something we will do.
1045  *
1046  */
1047 static void ipath_setup_ht_setextled(struct ipath_devdata *dd,
1048                                      u64 lst, u64 ltst)
1049 {
1050         u64 extctl;
1051
1052         /* the diags use the LED to indicate diag info, so we leave
1053          * the external LED alone when the diags are running */
1054         if (ipath_diag_inuse)
1055                 return;
1056
1057         /*
1058          * start by setting both LED control bits to off, then turn
1059          * on the appropriate bit(s).
1060          */
1061         if (dd->ipath_boardrev == 8) { /* LS/X-1 uses different pins */
1062                 /*
1063                  * major difference is that INFINIPATH_EXTC_LEDGBLERR_OFF
1064                  * is inverted,  because it is normally used to indicate
1065                  * a hardware fault at reset, if there were errors
1066                  */
1067                 extctl = (dd->ipath_extctrl & ~INFINIPATH_EXTC_LEDGBLOK_ON)
1068                         | INFINIPATH_EXTC_LEDGBLERR_OFF;
1069                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1070                         extctl &= ~INFINIPATH_EXTC_LEDGBLERR_OFF;
1071                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1072                         extctl |= INFINIPATH_EXTC_LEDGBLOK_ON;
1073         }
1074         else {
1075                 extctl = dd->ipath_extctrl &
1076                         ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1077                           INFINIPATH_EXTC_LED2PRIPORT_ON);
1078                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1079                         extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1080                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1081                         extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1082         }
1083         dd->ipath_extctrl = extctl;
1084         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
1085 }
1086
1087 static void ipath_init_ht_variables(struct ipath_devdata *dd)
1088 {
1089         dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1090         dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1091         dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1092         dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1093
1094         dd->ipath_i_bitsextant =
1095                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1096                 (INFINIPATH_I_RCVAVAIL_MASK <<
1097                  INFINIPATH_I_RCVAVAIL_SHIFT) |
1098                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1099                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1100
1101         dd->ipath_e_bitsextant =
1102                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1103                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1104                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1105                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1106                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1107                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1108                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1109                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1110                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1111                 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1112                 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1113                 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1114                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1115                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1116                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1117                 INFINIPATH_E_HARDWARE;
1118
1119         dd->ipath_hwe_bitsextant =
1120                 (INFINIPATH_HWE_HTCMEMPARITYERR_MASK <<
1121                  INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) |
1122                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1123                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1124                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1125                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1126                 INFINIPATH_HWE_HTCLNKABYTE0CRCERR |
1127                 INFINIPATH_HWE_HTCLNKABYTE1CRCERR |
1128                 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR |
1129                 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR |
1130                 INFINIPATH_HWE_HTCMISCERR4 |
1131                 INFINIPATH_HWE_HTCMISCERR5 | INFINIPATH_HWE_HTCMISCERR6 |
1132                 INFINIPATH_HWE_HTCMISCERR7 |
1133                 INFINIPATH_HWE_HTCBUSTREQPARITYERR |
1134                 INFINIPATH_HWE_HTCBUSTRESPPARITYERR |
1135                 INFINIPATH_HWE_HTCBUSIREQPARITYERR |
1136                 INFINIPATH_HWE_RXDSYNCMEMPARITYERR |
1137                 INFINIPATH_HWE_MEMBISTFAILED |
1138                 INFINIPATH_HWE_COREPLL_FBSLIP |
1139                 INFINIPATH_HWE_COREPLL_RFSLIP |
1140                 INFINIPATH_HWE_HTBPLL_FBSLIP |
1141                 INFINIPATH_HWE_HTBPLL_RFSLIP |
1142                 INFINIPATH_HWE_HTAPLL_FBSLIP |
1143                 INFINIPATH_HWE_HTAPLL_RFSLIP |
1144                 INFINIPATH_HWE_SERDESPLLFAILED |
1145                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1146                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1147
1148         dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1149         dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1150 }
1151
1152 /**
1153  * ipath_ht_init_hwerrors - enable hardware errors
1154  * @dd: the infinipath device
1155  *
1156  * now that we have finished initializing everything that might reasonably
1157  * cause a hardware error, and cleared those errors bits as they occur,
1158  * we can enable hardware errors in the mask (potentially enabling
1159  * freeze mode), and enable hardware errors as errors (along with
1160  * everything else) in errormask
1161  */
1162 static void ipath_ht_init_hwerrors(struct ipath_devdata *dd)
1163 {
1164         ipath_err_t val;
1165         u64 extsval;
1166
1167         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
1168
1169         if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
1170                 ipath_dev_err(dd, "MemBIST did not complete!\n");
1171         if (extsval & INFINIPATH_EXTS_MEMBIST_CORRECT)
1172                 ipath_dbg("MemBIST corrected\n");
1173
1174         ipath_check_htlink(dd);
1175
1176         /* barring bugs, all hwerrors become interrupts, which can */
1177         val = -1LL;
1178         /* don't look at crc lane1 if 8 bit */
1179         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
1180                 val &= ~infinipath_hwe_htclnkabyte1crcerr;
1181         /* don't look at crc lane1 if 8 bit */
1182         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
1183                 val &= ~infinipath_hwe_htclnkbbyte1crcerr;
1184
1185         /*
1186          * disable RXDSYNCMEMPARITY because external serdes is unused,
1187          * and therefore the logic will never be used or initialized,
1188          * and uninitialized state will normally result in this error
1189          * being asserted.  Similarly for the external serdess pll
1190          * lock signal.
1191          */
1192         val &= ~(INFINIPATH_HWE_SERDESPLLFAILED |
1193                  INFINIPATH_HWE_RXDSYNCMEMPARITYERR);
1194
1195         /*
1196          * Disable MISCERR4 because of an inversion in the HT core
1197          * logic checking for errors that cause this bit to be set.
1198          * The errata can also cause the protocol error bit to be set
1199          * in the HT config space linkerror register(s).
1200          */
1201         val &= ~INFINIPATH_HWE_HTCMISCERR4;
1202
1203         /*
1204          * PLL ignored because MDIO interface has a logic problem
1205          * for reads, on Comstock and Ponderosa.  BRINGUP
1206          */
1207         if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9)
1208                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
1209         dd->ipath_hwerrmask = val;
1210 }
1211
1212 /**
1213  * ipath_ht_bringup_serdes - bring up the serdes
1214  * @dd: the infinipath device
1215  */
1216 static int ipath_ht_bringup_serdes(struct ipath_devdata *dd)
1217 {
1218         u64 val, config1;
1219         int ret = 0, change = 0;
1220
1221         ipath_dbg("Trying to bringup serdes\n");
1222
1223         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
1224             INFINIPATH_HWE_SERDESPLLFAILED)
1225         {
1226                 ipath_dbg("At start, serdes PLL failed bit set in "
1227                           "hwerrstatus, clearing and continuing\n");
1228                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
1229                                  INFINIPATH_HWE_SERDESPLLFAILED);
1230         }
1231
1232         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1233         config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
1234
1235         ipath_cdbg(VERBOSE, "Initial serdes status is config0=%llx "
1236                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1237                    (unsigned long long) val, (unsigned long long) config1,
1238                    (unsigned long long)
1239                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1240                    (unsigned long long)
1241                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1242
1243         /* force reset on */
1244         val |= INFINIPATH_SERDC0_RESET_PLL
1245                 /* | INFINIPATH_SERDC0_RESET_MASK */
1246                 ;
1247         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1248         udelay(15);             /* need pll reset set at least for a bit */
1249
1250         if (val & INFINIPATH_SERDC0_RESET_PLL) {
1251                 u64 val2 = val &= ~INFINIPATH_SERDC0_RESET_PLL;
1252                 /* set lane resets, and tx idle, during pll reset */
1253                 val2 |= INFINIPATH_SERDC0_RESET_MASK |
1254                         INFINIPATH_SERDC0_TXIDLE;
1255                 ipath_cdbg(VERBOSE, "Clearing serdes PLL reset (writing "
1256                            "%llx)\n", (unsigned long long) val2);
1257                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1258                                  val2);
1259                 /*
1260                  * be sure chip saw it
1261                  */
1262                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1263                 /*
1264                  * need pll reset clear at least 11 usec before lane
1265                  * resets cleared; give it a few more
1266                  */
1267                 udelay(15);
1268                 val = val2;     /* for check below */
1269         }
1270
1271         if (val & (INFINIPATH_SERDC0_RESET_PLL |
1272                    INFINIPATH_SERDC0_RESET_MASK |
1273                    INFINIPATH_SERDC0_TXIDLE)) {
1274                 val &= ~(INFINIPATH_SERDC0_RESET_PLL |
1275                          INFINIPATH_SERDC0_RESET_MASK |
1276                          INFINIPATH_SERDC0_TXIDLE);
1277                 /* clear them */
1278                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1279                                  val);
1280         }
1281
1282         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1283         if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
1284              INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
1285                 val &= ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
1286                          INFINIPATH_XGXS_MDIOADDR_SHIFT);
1287                 /*
1288                  * we use address 3
1289                  */
1290                 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
1291                 change = 1;
1292         }
1293         if (val & INFINIPATH_XGXS_RESET) {
1294                 /* normally true after boot */
1295                 val &= ~INFINIPATH_XGXS_RESET;
1296                 change = 1;
1297         }
1298         if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
1299              INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
1300                 /* need to compensate for Tx inversion in partner */
1301                 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
1302                          INFINIPATH_XGXS_RX_POL_SHIFT);
1303                 val |= dd->ipath_rx_pol_inv <<
1304                         INFINIPATH_XGXS_RX_POL_SHIFT;
1305                 change = 1;
1306         }
1307         if (change)
1308                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1309
1310         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1311
1312         /* clear current and de-emphasis bits */
1313         config1 &= ~0x0ffffffff00ULL;
1314         /* set current to 20ma */
1315         config1 |= 0x00000000000ULL;
1316         /* set de-emphasis to -5.68dB */
1317         config1 |= 0x0cccc000000ULL;
1318         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
1319
1320         ipath_cdbg(VERBOSE, "After setup: serdes status is config0=%llx "
1321                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1322                    (unsigned long long) val, (unsigned long long) config1,
1323                    (unsigned long long)
1324                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1325                    (unsigned long long)
1326                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1327
1328         if (!ipath_waitfor_mdio_cmdready(dd)) {
1329                 ipath_write_kreg(dd, dd->ipath_kregs->kr_mdio,
1330                                  ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
1331                                                 IPATH_MDIO_CTRL_XGXS_REG_8,
1332                                                 0));
1333                 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
1334                                            IPATH_MDIO_DATAVALID, &val))
1335                         ipath_dbg("Never got MDIO data for XGXS status "
1336                                   "read\n");
1337                 else
1338                         ipath_cdbg(VERBOSE, "MDIO Read reg8, "
1339                                    "'bank' 31 %x\n", (u32) val);
1340         } else
1341                 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
1342
1343         return ret;             /* for now, say we always succeeded */
1344 }
1345
1346 /**
1347  * ipath_ht_quiet_serdes - set serdes to txidle
1348  * @dd: the infinipath device
1349  * driver is being unloaded
1350  */
1351 static void ipath_ht_quiet_serdes(struct ipath_devdata *dd)
1352 {
1353         u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1354
1355         val |= INFINIPATH_SERDC0_TXIDLE;
1356         ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
1357                   (unsigned long long) val);
1358         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1359 }
1360
1361 /**
1362  * ipath_pe_put_tid - write a TID in chip
1363  * @dd: the infinipath device
1364  * @tidptr: pointer to the expected TID (in chip) to udpate
1365  * @tidtype: 0 for eager, 1 for expected
1366  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1367  *
1368  * This exists as a separate routine to allow for special locking etc.
1369  * It's used for both the full cleanup on exit, as well as the normal
1370  * setup and teardown.
1371  */
1372 static void ipath_ht_put_tid(struct ipath_devdata *dd,
1373                              u64 __iomem *tidptr, u32 type,
1374                              unsigned long pa)
1375 {
1376         if (!dd->ipath_kregbase)
1377                 return;
1378
1379         if (pa != dd->ipath_tidinvalid) {
1380                 if (unlikely((pa & ~INFINIPATH_RT_ADDR_MASK))) {
1381                         dev_info(&dd->pcidev->dev,
1382                                  "physaddr %lx has more than "
1383                                  "40 bits, using only 40!!!\n", pa);
1384                         pa &= INFINIPATH_RT_ADDR_MASK;
1385                 }
1386                 if (type == 0)
1387                         pa |= dd->ipath_tidtemplate;
1388                 else {
1389                         /* in words (fixed, full page).  */
1390                         u64 lenvalid = PAGE_SIZE >> 2;
1391                         lenvalid <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1392                         pa |= lenvalid | INFINIPATH_RT_VALID;
1393                 }
1394         }
1395         writeq(pa, tidptr);
1396 }
1397
1398
1399 /**
1400  * ipath_ht_clear_tid - clear all TID entries for a port, expected and eager
1401  * @dd: the infinipath device
1402  * @port: the port
1403  *
1404  * Used from ipath_close(), and at chip initialization.
1405  */
1406 static void ipath_ht_clear_tids(struct ipath_devdata *dd, unsigned port)
1407 {
1408         u64 __iomem *tidbase;
1409         int i;
1410
1411         if (!dd->ipath_kregbase)
1412                 return;
1413
1414         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1415
1416         /*
1417          * need to invalidate all of the expected TID entries for this
1418          * port, so we don't have valid entries that might somehow get
1419          * used (early in next use of this port, or through some bug)
1420          */
1421         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1422                                    dd->ipath_rcvtidbase +
1423                                    port * dd->ipath_rcvtidcnt *
1424                                    sizeof(*tidbase));
1425         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1426                 ipath_ht_put_tid(dd, &tidbase[i], 1, dd->ipath_tidinvalid);
1427
1428         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1429                                    dd->ipath_rcvegrbase +
1430                                    port * dd->ipath_rcvegrcnt *
1431                                    sizeof(*tidbase));
1432
1433         for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1434                 ipath_ht_put_tid(dd, &tidbase[i], 0, dd->ipath_tidinvalid);
1435 }
1436
1437 /**
1438  * ipath_ht_tidtemplate - setup constants for TID updates
1439  * @dd: the infinipath device
1440  *
1441  * We setup stuff that we use a lot, to avoid calculating each time
1442  */
1443 static void ipath_ht_tidtemplate(struct ipath_devdata *dd)
1444 {
1445         dd->ipath_tidtemplate = dd->ipath_ibmaxlen >> 2;
1446         dd->ipath_tidtemplate <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1447         dd->ipath_tidtemplate |= INFINIPATH_RT_VALID;
1448
1449         /*
1450          * work around chip errata bug 7358, by marking invalid tids
1451          * as having max length
1452          */
1453         dd->ipath_tidinvalid = (-1LL & INFINIPATH_RT_BUFSIZE_MASK) <<
1454                 INFINIPATH_RT_BUFSIZE_SHIFT;
1455 }
1456
1457 static int ipath_ht_early_init(struct ipath_devdata *dd)
1458 {
1459         u32 __iomem *piobuf;
1460         u32 pioincr, val32;
1461         int i;
1462
1463         /*
1464          * one cache line; long IB headers will spill over into received
1465          * buffer
1466          */
1467         dd->ipath_rcvhdrentsize = 16;
1468         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1469
1470         /*
1471          * For HT, we allocate a somewhat overly large eager buffer,
1472          * such that we can guarantee that we can receive the largest
1473          * packet that we can send out.  To truly support a 4KB MTU,
1474          * we need to bump this to a large value.  To date, other than
1475          * testing, we have never encountered an HCA that can really
1476          * send 4KB MTU packets, so we do not handle that (we'll get
1477          * errors interrupts if we ever see one).
1478          */
1479         dd->ipath_rcvegrbufsize = dd->ipath_piosize2k;
1480
1481         /*
1482          * the min() check here is currently a nop, but it may not
1483          * always be, depending on just how we do ipath_rcvegrbufsize
1484          */
1485         dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1486                                  dd->ipath_rcvegrbufsize);
1487         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1488         ipath_ht_tidtemplate(dd);
1489
1490         /*
1491          * zero all the TID entries at startup.  We do this for sanity,
1492          * in case of a previous driver crash of some kind, and also
1493          * because the chip powers up with these memories in an unknown
1494          * state.  Use portcnt, not cfgports, since this is for the
1495          * full chip, not for current (possibly different) configuration
1496          * value.
1497          * Chip Errata bug 6447
1498          */
1499         for (val32 = 0; val32 < dd->ipath_portcnt; val32++)
1500                 ipath_ht_clear_tids(dd, val32);
1501
1502         /*
1503          * write the pbc of each buffer, to be sure it's initialized, then
1504          * cancel all the buffers, and also abort any packets that might
1505          * have been in flight for some reason (the latter is for driver
1506          * unload/reload, but isn't a bad idea at first init).  PIO send
1507          * isn't enabled at this point, so there is no danger of sending
1508          * these out on the wire.
1509          * Chip Errata bug 6610
1510          */
1511         piobuf = (u32 __iomem *) (((char __iomem *)(dd->ipath_kregbase)) +
1512                                   dd->ipath_piobufbase);
1513         pioincr = dd->ipath_palign / sizeof(*piobuf);
1514         for (i = 0; i < dd->ipath_piobcnt2k; i++) {
1515                 /*
1516                  * reasonable word count, just to init pbc
1517                  */
1518                 writel(16, piobuf);
1519                 piobuf += pioincr;
1520         }
1521         /*
1522          * self-clearing
1523          */
1524         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1525                          INFINIPATH_S_ABORT);
1526
1527         ipath_get_eeprom_info(dd);
1528         if (dd->ipath_boardrev == 5 && dd->ipath_serial[0] == '1' &&
1529                 dd->ipath_serial[1] == '2' && dd->ipath_serial[2] == '8') {
1530                 /*
1531                  * Later production QHT7040 has same changes as QHT7140, so
1532                  * can use GPIO interrupts.  They have serial #'s starting
1533                  * with 128, rather than 112.
1534                  */
1535                 dd->ipath_flags |= IPATH_GPIO_INTR;
1536                 dd->ipath_flags &= ~IPATH_POLL_RX_INTR;
1537         }
1538         return 0;
1539 }
1540
1541
1542 static int ipath_ht_txe_recover(struct ipath_devdata *dd)
1543 {
1544         int cnt = ++ipath_stats.sps_txeparity;
1545         if (cnt >= IPATH_MAX_PARITY_ATTEMPTS)  {
1546                 if (cnt == IPATH_MAX_PARITY_ATTEMPTS)
1547                         ipath_dev_err(dd,
1548                                 "Too many attempts to recover from "
1549                                 "TXE parity, giving up\n");
1550                 return 0;
1551         }
1552         dev_info(&dd->pcidev->dev,
1553                 "Recovering from TXE PIO parity error\n");
1554         ipath_disarm_senderrbufs(dd, 1);
1555         return 1;
1556 }
1557
1558
1559 /**
1560  * ipath_init_ht_get_base_info - set chip-specific flags for user code
1561  * @dd: the infinipath device
1562  * @kbase: ipath_base_info pointer
1563  *
1564  * We set the PCIE flag because the lower bandwidth on PCIe vs
1565  * HyperTransport can affect some user packet algorithms.
1566  */
1567 static int ipath_ht_get_base_info(struct ipath_portdata *pd, void *kbase)
1568 {
1569         struct ipath_base_info *kinfo = kbase;
1570
1571         kinfo->spi_runtime_flags |= IPATH_RUNTIME_HT |
1572                 IPATH_RUNTIME_RCVHDR_COPY;
1573
1574         return 0;
1575 }
1576
1577 static void ipath_ht_free_irq(struct ipath_devdata *dd)
1578 {
1579         free_irq(dd->ipath_irq, dd);
1580         ht_destroy_irq(dd->ipath_irq);
1581         dd->ipath_irq = 0;
1582         dd->ipath_intconfig = 0;
1583 }
1584
1585 /**
1586  * ipath_init_iba6110_funcs - set up the chip-specific function pointers
1587  * @dd: the infinipath device
1588  *
1589  * This is global, and is called directly at init to set up the
1590  * chip-specific function pointers for later use.
1591  */
1592 void ipath_init_iba6110_funcs(struct ipath_devdata *dd)
1593 {
1594         dd->ipath_f_intrsetup = ipath_ht_intconfig;
1595         dd->ipath_f_bus = ipath_setup_ht_config;
1596         dd->ipath_f_reset = ipath_setup_ht_reset;
1597         dd->ipath_f_get_boardname = ipath_ht_boardname;
1598         dd->ipath_f_init_hwerrors = ipath_ht_init_hwerrors;
1599         dd->ipath_f_early_init = ipath_ht_early_init;
1600         dd->ipath_f_handle_hwerrors = ipath_ht_handle_hwerrors;
1601         dd->ipath_f_quiet_serdes = ipath_ht_quiet_serdes;
1602         dd->ipath_f_bringup_serdes = ipath_ht_bringup_serdes;
1603         dd->ipath_f_clear_tids = ipath_ht_clear_tids;
1604         dd->ipath_f_put_tid = ipath_ht_put_tid;
1605         dd->ipath_f_cleanup = ipath_setup_ht_cleanup;
1606         dd->ipath_f_setextled = ipath_setup_ht_setextled;
1607         dd->ipath_f_get_base_info = ipath_ht_get_base_info;
1608         dd->ipath_f_free_irq = ipath_ht_free_irq;
1609
1610         /*
1611          * initialize chip-specific variables
1612          */
1613         dd->ipath_f_tidtemplate = ipath_ht_tidtemplate;
1614
1615         /*
1616          * setup the register offsets, since they are different for each
1617          * chip
1618          */
1619         dd->ipath_kregs = &ipath_ht_kregs;
1620         dd->ipath_cregs = &ipath_ht_cregs;
1621
1622         /*
1623          * do very early init that is needed before ipath_f_bus is
1624          * called
1625          */
1626         ipath_init_ht_variables(dd);
1627 }