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   1 /*
   2  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
   3  *  Copyright (C) 2006-2007, 2009       MontaVista Software, Inc.
   4  *  Copyright (C) 2007                  Bartlomiej Zolnierkiewicz
   5  *
   6  *  Portions Copyright (C) 1999 Promise Technology, Inc.
   7  *  Author: Frank Tiernan (frankt@promise.com)
   8  *  Released under terms of General Public License
   9  */
  10
  11 #include <linux/types.h>
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/delay.h>
  15 #include <linux/blkdev.h>
  16 #include <linux/pci.h>
  17 #include <linux/init.h>
  18 #include <linux/ide.h>
  19
  20 #include <asm/io.h>
  21
  22 #define DRV_NAME "pdc202xx_old"
  23
  24 #define PDC202XX_DEBUG_DRIVE_INFO       0
  25
  26 static const char *pdc_quirk_drives[] = {
  27         "QUANTUM FIREBALLlct08 08",
  28         "QUANTUM FIREBALLP KA6.4",
  29         "QUANTUM FIREBALLP KA9.1",
  30         "QUANTUM FIREBALLP LM20.4",
  31         "QUANTUM FIREBALLP KX13.6",
  32         "QUANTUM FIREBALLP KX20.5",
  33         "QUANTUM FIREBALLP KX27.3",
  34         "QUANTUM FIREBALLP LM20.5",
  35         NULL
  36 };
  37
  38 static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
  39
  40 static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
  41 {
  42         ide_hwif_t *hwif        = drive->hwif;
  43         struct pci_dev *dev     = to_pci_dev(hwif->dev);
  44         u8 drive_pci            = 0x60 + (drive->dn << 2);
  45
  46         u8                      AP = 0, BP = 0, CP = 0;
  47         u8                      TA = 0, TB = 0, TC = 0;
  48
  49 #if PDC202XX_DEBUG_DRIVE_INFO
  50         u32                     drive_conf = 0;
  51         pci_read_config_dword(dev, drive_pci, &drive_conf);
  52 #endif
  53
  54         /*
  55          * TODO: do this once per channel
  56          */
  57         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
  58                 pdc_old_disable_66MHz_clock(hwif);
  59
  60         pci_read_config_byte(dev, drive_pci,     &AP);
  61         pci_read_config_byte(dev, drive_pci + 1, &BP);
  62         pci_read_config_byte(dev, drive_pci + 2, &CP);
  63
  64         switch(speed) {
  65                 case XFER_UDMA_5:
  66                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
  67                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
  68                 case XFER_UDMA_3:
  69                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
  70                 case XFER_UDMA_0:
  71                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
  72                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
  73                 case XFER_MW_DMA_0:     TB = 0xE0; TC = 0x0F; break;
  74                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
  75                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
  76                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
  77                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
  78                 case XFER_PIO_0:
  79                 default:                TA = 0x09; TB = 0x13; break;
  80         }
  81
  82         if (speed < XFER_SW_DMA_0) {
  83                 /*
  84                  * preserve SYNC_INT / ERDDY_EN bits while clearing
  85                  * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
  86                  */
  87                 AP &= ~0x3f;
  88                 if (ata_id_iordy_disable(drive->id))
  89                         AP |= 0x20;     /* set IORDY_EN bit */
  90                 if (drive->media == ide_disk)
  91                         AP |= 0x10;     /* set Prefetch_EN bit */
  92                 /* clear PB[4:0] bits of register B */
  93                 BP &= ~0x1f;
  94                 pci_write_config_byte(dev, drive_pci,     AP | TA);
  95                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
  96         } else {
  97                 /* clear MB[2:0] bits of register B */
  98                 BP &= ~0xe0;
  99                 /* clear MC[3:0] bits of register C */
 100                 CP &= ~0x0f;
 101                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
 102                 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
 103         }
 104
 105 #if PDC202XX_DEBUG_DRIVE_INFO
 106         printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
 107                 drive->name, ide_xfer_verbose(speed),
 108                 drive->dn, drive_conf);
 109         pci_read_config_dword(dev, drive_pci, &drive_conf);
 110         printk("0x%08x\n", drive_conf);
 111 #endif
 112 }
 113
 114 static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
 115 {
 116         pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
 117 }
 118
 119 static u8 pdc2026x_cable_detect(ide_hwif_t *hwif)
 120 {
 121         struct pci_dev *dev = to_pci_dev(hwif->dev);
 122         u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
 123
 124         pci_read_config_word(dev, 0x50, &CIS);
 125
 126         return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
 127 }
 128
 129 /*
 130  * Set the control register to use the 66MHz system
 131  * clock for UDMA 3/4/5 mode operation when necessary.
 132  *
 133  * FIXME: this register is shared by both channels, some locking is needed
 134  *
 135  * It may also be possible to leave the 66MHz clock on
 136  * and readjust the timing parameters.
 137  */
 138 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
 139 {
 140         unsigned long clock_reg = hwif->extra_base + 0x01;
 141         u8 clock = inb(clock_reg);
 142
 143         outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
 144 }
 145
 146 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
 147 {
 148         unsigned long clock_reg = hwif->extra_base + 0x01;
 149         u8 clock = inb(clock_reg);
 150
 151         outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
 152 }
 153
 154 static void pdc202xx_quirkproc(ide_drive_t *drive)
 155 {
 156         const char **list, *m = (char *)&drive->id[ATA_ID_PROD];
 157
 158         for (list = pdc_quirk_drives; *list != NULL; list++)
 159                 if (strstr(m, *list) != NULL) {
 160                         drive->quirk_list = 2;
 161                         return;
 162                 }
 163
 164         drive->quirk_list = 0;
 165 }
 166
 167 static void pdc202xx_dma_start(ide_drive_t *drive)
 168 {
 169         if (drive->current_speed > XFER_UDMA_2)
 170                 pdc_old_enable_66MHz_clock(drive->hwif);
 171         if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
 172                 ide_hwif_t *hwif        = drive->hwif;
 173                 struct request *rq      = hwif->rq;
 174                 unsigned long high_16   = hwif->extra_base - 16;
 175                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 176                 u32 word_count  = 0;
 177                 u8 clock = inb(high_16 + 0x11);
 178
 179                 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
 180                 word_count = (rq->nr_sectors << 8);
 181                 word_count = (rq_data_dir(rq) == READ) ?
 182                                         word_count | 0x05000000 :
 183                                         word_count | 0x06000000;
 184                 outl(word_count, atapi_reg);
 185         }
 186         ide_dma_start(drive);
 187 }
 188
 189 static int pdc202xx_dma_end(ide_drive_t *drive)
 190 {
 191         if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
 192                 ide_hwif_t *hwif        = drive->hwif;
 193                 unsigned long high_16   = hwif->extra_base - 16;
 194                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 195                 u8 clock                = 0;
 196
 197                 outl(0, atapi_reg); /* zero out extra */
 198                 clock = inb(high_16 + 0x11);
 199                 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
 200         }
 201         if (drive->current_speed > XFER_UDMA_2)
 202                 pdc_old_disable_66MHz_clock(drive->hwif);
 203         return ide_dma_end(drive);
 204 }
 205
 206 static int init_chipset_pdc202xx(struct pci_dev *dev)
 207 {
 208         unsigned long dmabase = pci_resource_start(dev, 4);
 209         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
 210
 211         if (dmabase == 0)
 212                 goto out;
 213
 214         udma_speed_flag = inb(dmabase | 0x1f);
 215         primary_mode    = inb(dmabase | 0x1a);
 216         secondary_mode  = inb(dmabase | 0x1b);
 217         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
 218                 "Primary %s Mode " \
 219                 "Secondary %s Mode.\n", pci_name(dev),
 220                 (udma_speed_flag & 1) ? "EN" : "DIS",
 221                 (primary_mode & 1) ? "MASTER" : "PCI",
 222                 (secondary_mode & 1) ? "MASTER" : "PCI" );
 223
 224         if (!(udma_speed_flag & 1)) {
 225                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
 226                         pci_name(dev), udma_speed_flag,
 227                         (udma_speed_flag|1));
 228                 outb(udma_speed_flag | 1, dmabase | 0x1f);
 229                 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
 230         }
 231 out:
 232         return 0;
 233 }
 234
 235 static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
 236                                            const char *name)
 237 {
 238         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 239                 u8 irq = 0, irq2 = 0;
 240                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 241                 /* 0xbc */
 242                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
 243                 if (irq != irq2) {
 244                         pci_write_config_byte(dev,
 245                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
 246                         printk(KERN_INFO "%s %s: PCI config space interrupt "
 247                                 "mirror fixed\n", name, pci_name(dev));
 248                 }
 249         }
 250 }
 251
 252 #define IDE_HFLAGS_PDC202XX \
 253         (IDE_HFLAG_ERROR_STOPS_FIFO | \
 254          IDE_HFLAG_OFF_BOARD)
 255
 256 static const struct ide_port_ops pdc20246_port_ops = {
 257         .set_pio_mode           = pdc202xx_set_pio_mode,
 258         .set_dma_mode           = pdc202xx_set_mode,
 259         .quirkproc              = pdc202xx_quirkproc,
 260 };
 261
 262 static const struct ide_port_ops pdc2026x_port_ops = {
 263         .set_pio_mode           = pdc202xx_set_pio_mode,
 264         .set_dma_mode           = pdc202xx_set_mode,
 265         .quirkproc              = pdc202xx_quirkproc,
 266         .cable_detect           = pdc2026x_cable_detect,
 267 };
 268
 269 static const struct ide_dma_ops pdc2026x_dma_ops = {
 270         .dma_host_set           = ide_dma_host_set,
 271         .dma_setup              = ide_dma_setup,
 272         .dma_start              = pdc202xx_dma_start,
 273         .dma_end                = pdc202xx_dma_end,
 274         .dma_test_irq           = ide_dma_test_irq,
 275         .dma_lost_irq           = ide_dma_lost_irq,
 276         .dma_timer_expiry       = ide_dma_sff_timer_expiry,
 277         .dma_sff_read_status    = ide_dma_sff_read_status,
 278 };
 279
 280 #define DECLARE_PDC2026X_DEV(udma, sectors) \
 281         { \
 282                 .name           = DRV_NAME, \
 283                 .init_chipset   = init_chipset_pdc202xx, \
 284                 .port_ops       = &pdc2026x_port_ops, \
 285                 .dma_ops        = &pdc2026x_dma_ops, \
 286                 .host_flags     = IDE_HFLAGS_PDC202XX, \
 287                 .pio_mask       = ATA_PIO4, \
 288                 .mwdma_mask     = ATA_MWDMA2, \
 289                 .udma_mask      = udma, \
 290                 .max_sectors    = sectors, \
 291         }
 292
 293 static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
 294         {       /* 0: PDC20246 */
 295                 .name           = DRV_NAME,
 296                 .init_chipset   = init_chipset_pdc202xx,
 297                 .port_ops       = &pdc20246_port_ops,
 298                 .dma_ops        = &sff_dma_ops,
 299                 .host_flags     = IDE_HFLAGS_PDC202XX,
 300                 .pio_mask       = ATA_PIO4,
 301                 .mwdma_mask     = ATA_MWDMA2,
 302                 .udma_mask      = ATA_UDMA2,
 303         },
 304
 305         /* 1: PDC2026{2,3} */
 306         DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
 307         /* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */
 308         DECLARE_PDC2026X_DEV(ATA_UDMA5, 256),
 309 };
 310
 311 /**
 312  *      pdc202xx_init_one       -       called when a PDC202xx is found
 313  *      @dev: the pdc202xx device
 314  *      @id: the matching pci id
 315  *
 316  *      Called when the PCI registration layer (or the IDE initialization)
 317  *      finds a device matching our IDE device tables.
 318  */
 319
 320 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 321 {
 322         const struct ide_port_info *d;
 323         u8 idx = id->driver_data;
 324
 325         d = &pdc202xx_chipsets[idx];
 326
 327         if (idx < 2)
 328                 pdc202ata4_fixup_irq(dev, d->name);
 329
 330         if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
 331                 struct pci_dev *bridge = dev->bus->self;
 332
 333                 if (bridge &&
 334                     bridge->vendor == PCI_VENDOR_ID_INTEL &&
 335                     (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
 336                      bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
 337                         printk(KERN_INFO DRV_NAME " %s: skipping Promise "
 338                                 "PDC20265 attached to I2O RAID controller\n",
 339                                 pci_name(dev));
 340                         return -ENODEV;
 341                 }
 342         }
 343
 344         return ide_pci_init_one(dev, d, NULL);
 345 }
 346
 347 static const struct pci_device_id pdc202xx_pci_tbl[] = {
 348         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
 349         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
 350         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
 351         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
 352         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
 353         { 0, },
 354 };
 355 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
 356
 357 static struct pci_driver pdc202xx_pci_driver = {
 358         .name           = "Promise_Old_IDE",
 359         .id_table       = pdc202xx_pci_tbl,
 360         .probe          = pdc202xx_init_one,
 361         .remove         = ide_pci_remove,
 362         .suspend        = ide_pci_suspend,
 363         .resume         = ide_pci_resume,
 364 };
 365
 366 static int __init pdc202xx_ide_init(void)
 367 {
 368         return ide_pci_register_driver(&pdc202xx_pci_driver);
 369 }
 370
 371 static void __exit pdc202xx_ide_exit(void)
 372 {
 373         pci_unregister_driver(&pdc202xx_pci_driver);
 374 }
 375
 376 module_init(pdc202xx_ide_init);
 377 module_exit(pdc202xx_ide_exit);
 378
 379 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 380 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
 381 MODULE_LICENSE("GPL");