2 * linux/drivers/ide/pci/sc1200.c Version 0.97 Aug 3 2007
4 * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
5 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
7 * May be copied or modified under the terms of the GNU General Public License
9 * Development of this chipset driver was funded
10 * by the nice folks at National Semiconductor.
13 * Available from National Semiconductor
16 #include <linux/module.h>
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/delay.h>
20 #include <linux/timer.h>
22 #include <linux/ioport.h>
23 #include <linux/blkdev.h>
24 #include <linux/hdreg.h>
25 #include <linux/interrupt.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/ide.h>
33 #define SC1200_REV_A 0x00
34 #define SC1200_REV_B1 0x01
35 #define SC1200_REV_B3 0x02
36 #define SC1200_REV_C1 0x03
37 #define SC1200_REV_D1 0x04
39 #define PCI_CLK_33 0x00
40 #define PCI_CLK_48 0x01
41 #define PCI_CLK_66 0x02
42 #define PCI_CLK_33A 0x03
44 static unsigned short sc1200_get_pci_clock (void)
46 unsigned char chip_id, silicon_revision;
47 unsigned int pci_clock;
49 * Check the silicon revision, as not all versions of the chip
50 * have the register with the fast PCI bus timings.
52 chip_id = inb (0x903c);
53 silicon_revision = inb (0x903d);
55 // Read the fast pci clock frequency
56 if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
57 pci_clock = PCI_CLK_33;
59 // check clock generator configuration (cfcc)
60 // the clock is in bits 8 and 9 of this word
62 pci_clock = inw (0x901e);
65 if (pci_clock == PCI_CLK_33A)
66 pci_clock = PCI_CLK_33;
72 * Here are the standard PIO mode 0-4 timings for each "format".
73 * Format-0 uses fast data reg timings, with slower command reg timings.
74 * Format-1 uses fast timings for all registers, but won't work with all drives.
76 static const unsigned int sc1200_pio_timings[4][5] =
77 {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz
78 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz
79 {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz
80 {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz
83 * After chip reset, the PIO timings are set to 0x00009172, which is not valid.
85 //#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
87 static void sc1200_tunepio(ide_drive_t *drive, u8 pio)
89 ide_hwif_t *hwif = drive->hwif;
90 struct pci_dev *pdev = hwif->pci_dev;
91 unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0;
93 pci_read_config_dword(pdev, basereg + 4, &format);
94 format = (format >> 31) & 1;
96 format += sc1200_get_pci_clock();
97 pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3),
98 sc1200_pio_timings[format][pio]);
102 * The SC1200 specifies that two drives sharing a cable cannot mix
103 * UDMA/MDMA. It has to be one or the other, for the pair, though
104 * different timings can still be chosen for each drive. We could
105 * set the appropriate timing bits on the fly, but that might be
106 * a bit confusing. So, for now we statically handle this requirement
107 * by looking at our mate drive to see what it is capable of, before
108 * choosing a mode for our own drive.
110 static u8 sc1200_udma_filter(ide_drive_t *drive)
112 ide_hwif_t *hwif = drive->hwif;
113 ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
114 struct hd_driveid *mateid = mate->id;
115 u8 mask = hwif->ultra_mask;
117 if (mate->present == 0)
120 if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
121 if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
123 if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
130 static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode)
132 ide_hwif_t *hwif = HWIF(drive);
133 int unit = drive->select.b.unit;
134 unsigned int reg, timings;
135 unsigned short pci_clock;
136 unsigned int basereg = hwif->channel ? 0x50 : 0x40;
138 pci_clock = sc1200_get_pci_clock();
141 * Note that each DMA mode has several timings associated with it.
142 * The correct timing depends on the fast PCI clock freq.
148 case PCI_CLK_33: timings = 0x00921250; break;
149 case PCI_CLK_48: timings = 0x00932470; break;
150 case PCI_CLK_66: timings = 0x009436a1; break;
155 case PCI_CLK_33: timings = 0x00911140; break;
156 case PCI_CLK_48: timings = 0x00922260; break;
157 case PCI_CLK_66: timings = 0x00933481; break;
162 case PCI_CLK_33: timings = 0x00911030; break;
163 case PCI_CLK_48: timings = 0x00922140; break;
164 case PCI_CLK_66: timings = 0x00923261; break;
169 case PCI_CLK_33: timings = 0x00077771; break;
170 case PCI_CLK_48: timings = 0x000bbbb2; break;
171 case PCI_CLK_66: timings = 0x000ffff3; break;
176 case PCI_CLK_33: timings = 0x00012121; break;
177 case PCI_CLK_48: timings = 0x00024241; break;
178 case PCI_CLK_66: timings = 0x00035352; break;
183 case PCI_CLK_33: timings = 0x00002020; break;
184 case PCI_CLK_48: timings = 0x00013131; break;
185 case PCI_CLK_66: timings = 0x00015151; break;
190 if (unit == 0) { /* are we configuring drive0? */
191 pci_read_config_dword(hwif->pci_dev, basereg+4, ®);
192 timings |= reg & 0x80000000; /* preserve PIO format bit */
193 pci_write_config_dword(hwif->pci_dev, basereg+4, timings);
195 pci_write_config_dword(hwif->pci_dev, basereg+12, timings);
199 /* Replacement for the standard ide_dma_end action in
202 * returns 1 on error, 0 otherwise
204 static int sc1200_ide_dma_end (ide_drive_t *drive)
206 ide_hwif_t *hwif = HWIF(drive);
207 unsigned long dma_base = hwif->dma_base;
210 dma_stat = inb(dma_base+2); /* get DMA status */
213 printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
214 dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));
216 outb(dma_stat|0x1b, dma_base+2); /* clear the INTR & ERROR bits */
217 outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */
219 drive->waiting_for_dma = 0;
220 ide_destroy_dmatable(drive); /* purge DMA mappings */
222 return (dma_stat & 7) != 4; /* verify good DMA status */
226 * sc1200_set_pio_mode() handles setting of PIO modes
227 * for both the chipset and drive.
229 * All existing BIOSs for this chipset guarantee that all drives
230 * will have valid default PIO timings set up before we get here.
233 static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio)
235 ide_hwif_t *hwif = HWIF(drive);
239 * bad abuse of ->set_pio_mode interface
242 case 200: mode = XFER_UDMA_0; break;
243 case 201: mode = XFER_UDMA_1; break;
244 case 202: mode = XFER_UDMA_2; break;
245 case 100: mode = XFER_MW_DMA_0; break;
246 case 101: mode = XFER_MW_DMA_1; break;
247 case 102: mode = XFER_MW_DMA_2; break;
250 printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
251 hwif->dma_off_quietly(drive);
252 if (ide_set_dma_mode(drive, mode) == 0)
253 hwif->dma_host_on(drive);
257 sc1200_tunepio(drive, pio);
261 struct sc1200_saved_state {
265 static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
267 printk("SC1200: suspend(%u)\n", state.event);
270 * we only save state when going from full power to less
272 if (state.event == PM_EVENT_ON) {
273 struct sc1200_saved_state *ss;
277 * allocate a permanent save area, if not already allocated
279 ss = (struct sc1200_saved_state *)pci_get_drvdata(dev);
281 ss = kmalloc(sizeof(*ss), GFP_KERNEL);
284 pci_set_drvdata(dev, ss);
288 * save timing registers
289 * (this may be unnecessary if BIOS also does it)
291 for (r = 0; r < 8; r++)
292 pci_read_config_dword(dev, 0x40 + r * 4, &ss->regs[r]);
295 pci_disable_device(dev);
296 pci_set_power_state(dev, pci_choose_state(dev, state));
300 static int sc1200_resume (struct pci_dev *dev)
302 struct sc1200_saved_state *ss;
306 i = pci_enable_device(dev);
310 ss = (struct sc1200_saved_state *)pci_get_drvdata(dev);
313 * restore timing registers
314 * (this may be unnecessary if BIOS also does it)
317 for (r = 0; r < 8; r++)
318 pci_write_config_dword(dev, 0x40 + r * 4, ss->regs[r]);
326 * This gets invoked by the IDE driver once for each channel,
327 * and performs channel-specific pre-initialization before drive probing.
329 static void __devinit init_hwif_sc1200 (ide_hwif_t *hwif)
331 hwif->set_pio_mode = &sc1200_set_pio_mode;
332 hwif->set_dma_mode = &sc1200_set_dma_mode;
334 if (hwif->dma_base == 0)
337 hwif->udma_filter = sc1200_udma_filter;
338 hwif->ide_dma_end = &sc1200_ide_dma_end;
341 static const struct ide_port_info sc1200_chipset __devinitdata = {
343 .init_hwif = init_hwif_sc1200,
344 .host_flags = IDE_HFLAG_SERIALIZE |
345 IDE_HFLAG_POST_SET_MODE |
346 IDE_HFLAG_ABUSE_DMA_MODES |
348 .pio_mask = ATA_PIO4,
349 .mwdma_mask = ATA_MWDMA2,
350 .udma_mask = ATA_UDMA2,
353 static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
355 return ide_setup_pci_device(dev, &sc1200_chipset);
358 static const struct pci_device_id sc1200_pci_tbl[] = {
359 { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0},
362 MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);
364 static struct pci_driver driver = {
365 .name = "SC1200_IDE",
366 .id_table = sc1200_pci_tbl,
367 .probe = sc1200_init_one,
369 .suspend = sc1200_suspend,
370 .resume = sc1200_resume,
374 static int __init sc1200_ide_init(void)
376 return ide_pci_register_driver(&driver);
379 module_init(sc1200_ide_init);
381 MODULE_AUTHOR("Mark Lord");
382 MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
383 MODULE_LICENSE("GPL");