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   1 /*
   2  *  linux/drivers/ide/pci/pdc202xx_old.c        Version 0.52    Aug 27, 2007
   3  *
   4  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
   5  *  Copyright (C) 2006-2007             MontaVista Software, Inc.
   6  *  Copyright (C) 2007                  Bartlomiej Zolnierkiewicz
   7  *
   8  *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
   9  *  compiled into the kernel if you have more than one card installed.
  10  *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
  11  *  safe chipset tuning, including this support is harmless
  12  *
  13  *  Promise Ultra66 cards with BIOS v1.11 this
  14  *  compiled into the kernel if you have more than one card installed.
  15  *
  16  *  Promise Ultra100 cards.
  17  *
  18  *  The latest chipset code will support the following ::
  19  *  Three Ultra33 controllers and 12 drives.
  20  *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
  21  *  The 8/4 ratio is a BIOS code limit by promise.
  22  *
  23  *  UNLESS you enable "CONFIG_PDC202XX_BURST"
  24  *
  25  */
  26
  27 /*
  28  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  29  *  Author: Frank Tiernan (frankt@promise.com)
  30  *  Released under terms of General Public License
  31  */
  32
  33 #include <linux/types.h>
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/delay.h>
  37 #include <linux/timer.h>
  38 #include <linux/mm.h>
  39 #include <linux/ioport.h>
  40 #include <linux/blkdev.h>
  41 #include <linux/hdreg.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/pci.h>
  44 #include <linux/init.h>
  45 #include <linux/ide.h>
  46
  47 #include <asm/io.h>
  48 #include <asm/irq.h>
  49
  50 #define PDC202XX_DEBUG_DRIVE_INFO       0
  51
  52 static const char *pdc_quirk_drives[] = {
  53         "QUANTUM FIREBALLlct08 08",
  54         "QUANTUM FIREBALLP KA6.4",
  55         "QUANTUM FIREBALLP KA9.1",
  56         "QUANTUM FIREBALLP LM20.4",
  57         "QUANTUM FIREBALLP KX13.6",
  58         "QUANTUM FIREBALLP KX20.5",
  59         "QUANTUM FIREBALLP KX27.3",
  60         "QUANTUM FIREBALLP LM20.5",
  61         NULL
  62 };
  63
  64 static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
  65
  66 static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
  67 {
  68         ide_hwif_t *hwif        = HWIF(drive);
  69         struct pci_dev *dev     = to_pci_dev(hwif->dev);
  70         u8 drive_pci            = 0x60 + (drive->dn << 2);
  71
  72         u8                      AP = 0, BP = 0, CP = 0;
  73         u8                      TA = 0, TB = 0, TC = 0;
  74
  75 #if PDC202XX_DEBUG_DRIVE_INFO
  76         u32                     drive_conf = 0;
  77         pci_read_config_dword(dev, drive_pci, &drive_conf);
  78 #endif
  79
  80         /*
  81          * TODO: do this once per channel
  82          */
  83         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
  84                 pdc_old_disable_66MHz_clock(hwif);
  85
  86         pci_read_config_byte(dev, drive_pci,     &AP);
  87         pci_read_config_byte(dev, drive_pci + 1, &BP);
  88         pci_read_config_byte(dev, drive_pci + 2, &CP);
  89
  90         switch(speed) {
  91                 case XFER_UDMA_5:
  92                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
  93                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
  94                 case XFER_UDMA_3:
  95                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
  96                 case XFER_UDMA_0:
  97                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
  98                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
  99                 case XFER_MW_DMA_0:     TB = 0xE0; TC = 0x0F; break;
 100                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
 101                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
 102                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
 103                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
 104                 case XFER_PIO_0:
 105                 default:                TA = 0x09; TB = 0x13; break;
 106         }
 107
 108         if (speed < XFER_SW_DMA_0) {
 109                 /*
 110                  * preserve SYNC_INT / ERDDY_EN bits while clearing
 111                  * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
 112                  */
 113                 AP &= ~0x3f;
 114                 if (drive->id->capability & 4)
 115                         AP |= 0x20;     /* set IORDY_EN bit */
 116                 if (drive->media == ide_disk)
 117                         AP |= 0x10;     /* set Prefetch_EN bit */
 118                 /* clear PB[4:0] bits of register B */
 119                 BP &= ~0x1f;
 120                 pci_write_config_byte(dev, drive_pci,     AP | TA);
 121                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
 122         } else {
 123                 /* clear MB[2:0] bits of register B */
 124                 BP &= ~0xe0;
 125                 /* clear MC[3:0] bits of register C */
 126                 CP &= ~0x0f;
 127                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
 128                 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
 129         }
 130
 131 #if PDC202XX_DEBUG_DRIVE_INFO
 132         printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
 133                 drive->name, ide_xfer_verbose(speed),
 134                 drive->dn, drive_conf);
 135         pci_read_config_dword(dev, drive_pci, &drive_conf);
 136         printk("0x%08x\n", drive_conf);
 137 #endif
 138 }
 139
 140 static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
 141 {
 142         pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
 143 }
 144
 145 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
 146 {
 147         struct pci_dev *dev = to_pci_dev(hwif->dev);
 148         u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
 149
 150         pci_read_config_word(dev, 0x50, &CIS);
 151
 152         return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
 153 }
 154
 155 /*
 156  * Set the control register to use the 66MHz system
 157  * clock for UDMA 3/4/5 mode operation when necessary.
 158  *
 159  * FIXME: this register is shared by both channels, some locking is needed
 160  *
 161  * It may also be possible to leave the 66MHz clock on
 162  * and readjust the timing parameters.
 163  */
 164 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
 165 {
 166         unsigned long clock_reg = hwif->extra_base + 0x01;
 167         u8 clock = inb(clock_reg);
 168
 169         outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
 170 }
 171
 172 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
 173 {
 174         unsigned long clock_reg = hwif->extra_base + 0x01;
 175         u8 clock = inb(clock_reg);
 176
 177         outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
 178 }
 179
 180 static void pdc202xx_quirkproc(ide_drive_t *drive)
 181 {
 182         const char **list, *model = drive->id->model;
 183
 184         for (list = pdc_quirk_drives; *list != NULL; list++)
 185                 if (strstr(model, *list) != NULL) {
 186                         drive->quirk_list = 2;
 187                         return;
 188                 }
 189
 190         drive->quirk_list = 0;
 191 }
 192
 193 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
 194 {
 195         if (drive->current_speed > XFER_UDMA_2)
 196                 pdc_old_enable_66MHz_clock(drive->hwif);
 197         if (drive->media != ide_disk || drive->addressing == 1) {
 198                 struct request *rq      = HWGROUP(drive)->rq;
 199                 ide_hwif_t *hwif        = HWIF(drive);
 200                 unsigned long high_16   = hwif->extra_base - 16;
 201                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 202                 u32 word_count  = 0;
 203                 u8 clock = inb(high_16 + 0x11);
 204
 205                 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
 206                 word_count = (rq->nr_sectors << 8);
 207                 word_count = (rq_data_dir(rq) == READ) ?
 208                                         word_count | 0x05000000 :
 209                                         word_count | 0x06000000;
 210                 outl(word_count, atapi_reg);
 211         }
 212         ide_dma_start(drive);
 213 }
 214
 215 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
 216 {
 217         if (drive->media != ide_disk || drive->addressing == 1) {
 218                 ide_hwif_t *hwif        = HWIF(drive);
 219                 unsigned long high_16   = hwif->extra_base - 16;
 220                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 221                 u8 clock                = 0;
 222
 223                 outl(0, atapi_reg); /* zero out extra */
 224                 clock = inb(high_16 + 0x11);
 225                 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
 226         }
 227         if (drive->current_speed > XFER_UDMA_2)
 228                 pdc_old_disable_66MHz_clock(drive->hwif);
 229         return __ide_dma_end(drive);
 230 }
 231
 232 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
 233 {
 234         ide_hwif_t *hwif        = HWIF(drive);
 235         unsigned long high_16   = hwif->extra_base - 16;
 236         u8 dma_stat             = inb(hwif->dma_status);
 237         u8 sc1d                 = inb(high_16 + 0x001d);
 238
 239         if (hwif->channel) {
 240                 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
 241                 if ((sc1d & 0x50) == 0x50)
 242                         goto somebody_else;
 243                 else if ((sc1d & 0x40) == 0x40)
 244                         return (dma_stat & 4) == 4;
 245         } else {
 246                 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
 247                 if ((sc1d & 0x05) == 0x05)
 248                         goto somebody_else;
 249                 else if ((sc1d & 0x04) == 0x04)
 250                         return (dma_stat & 4) == 4;
 251         }
 252 somebody_else:
 253         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
 254 }
 255
 256 static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
 257 {
 258         ide_hwif_t *hwif = HWIF(drive);
 259
 260         if (hwif->resetproc != NULL)
 261                 hwif->resetproc(drive);
 262
 263         ide_dma_lost_irq(drive);
 264 }
 265
 266 static void pdc202xx_dma_timeout(ide_drive_t *drive)
 267 {
 268         ide_hwif_t *hwif = HWIF(drive);
 269
 270         if (hwif->resetproc != NULL)
 271                 hwif->resetproc(drive);
 272
 273         ide_dma_timeout(drive);
 274 }
 275
 276 static void pdc202xx_reset_host (ide_hwif_t *hwif)
 277 {
 278         unsigned long high_16   = hwif->extra_base - 16;
 279         u8 udma_speed_flag      = inb(high_16 | 0x001f);
 280
 281         outb(udma_speed_flag | 0x10, high_16 | 0x001f);
 282         mdelay(100);
 283         outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
 284         mdelay(2000);   /* 2 seconds ?! */
 285
 286         printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
 287                 hwif->channel ? "Secondary" : "Primary");
 288 }
 289
 290 static void pdc202xx_reset (ide_drive_t *drive)
 291 {
 292         ide_hwif_t *hwif        = HWIF(drive);
 293         ide_hwif_t *mate        = hwif->mate;
 294
 295         pdc202xx_reset_host(hwif);
 296         pdc202xx_reset_host(mate);
 297
 298         ide_set_max_pio(drive);
 299 }
 300
 301 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
 302                                                         const char *name)
 303 {
 304         return dev->irq;
 305 }
 306
 307 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
 308 {
 309         struct pci_dev *dev = to_pci_dev(hwif->dev);
 310
 311         hwif->set_pio_mode = &pdc202xx_set_pio_mode;
 312         hwif->set_dma_mode = &pdc202xx_set_mode;
 313
 314         hwif->quirkproc = &pdc202xx_quirkproc;
 315
 316         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
 317                 hwif->resetproc = &pdc202xx_reset;
 318
 319         if (hwif->dma_base == 0)
 320                 return;
 321
 322         hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
 323         hwif->dma_timeout = &pdc202xx_dma_timeout;
 324
 325         if (dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 326                 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
 327                         hwif->cbl = pdc202xx_old_cable_detect(hwif);
 328
 329                 hwif->dma_start = &pdc202xx_old_ide_dma_start;
 330                 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
 331         }
 332         hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
 333 }
 334
 335 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
 336 {
 337         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
 338
 339         if (hwif->channel) {
 340                 ide_setup_dma(hwif, dmabase);
 341                 return;
 342         }
 343
 344         udma_speed_flag = inb(dmabase | 0x1f);
 345         primary_mode    = inb(dmabase | 0x1a);
 346         secondary_mode  = inb(dmabase | 0x1b);
 347         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
 348                 "Primary %s Mode " \
 349                 "Secondary %s Mode.\n", hwif->cds->name,
 350                 (udma_speed_flag & 1) ? "EN" : "DIS",
 351                 (primary_mode & 1) ? "MASTER" : "PCI",
 352                 (secondary_mode & 1) ? "MASTER" : "PCI" );
 353
 354 #ifdef CONFIG_PDC202XX_BURST
 355         if (!(udma_speed_flag & 1)) {
 356                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
 357                         hwif->cds->name, udma_speed_flag,
 358                         (udma_speed_flag|1));
 359                 outb(udma_speed_flag | 1, dmabase | 0x1f);
 360                 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
 361         }
 362 #endif /* CONFIG_PDC202XX_BURST */
 363
 364         ide_setup_dma(hwif, dmabase);
 365 }
 366
 367 static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
 368                                            const char *name)
 369 {
 370         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 371                 u8 irq = 0, irq2 = 0;
 372                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 373                 /* 0xbc */
 374                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
 375                 if (irq != irq2) {
 376                         pci_write_config_byte(dev,
 377                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
 378                         printk(KERN_INFO "%s: PCI config space interrupt "
 379                                          "mirror fixed\n", name);
 380                 }
 381         }
 382 }
 383
 384 #define IDE_HFLAGS_PDC202XX \
 385         (IDE_HFLAG_ERROR_STOPS_FIFO | \
 386          IDE_HFLAG_ABUSE_SET_DMA_MODE | \
 387          IDE_HFLAG_OFF_BOARD)
 388
 389 #define DECLARE_PDC2026X_DEV(name_str, udma, extra_flags) \
 390         { \
 391                 .name           = name_str, \
 392                 .init_chipset   = init_chipset_pdc202xx, \
 393                 .init_hwif      = init_hwif_pdc202xx, \
 394                 .init_dma       = init_dma_pdc202xx, \
 395                 .extra          = 48, \
 396                 .host_flags     = IDE_HFLAGS_PDC202XX | extra_flags, \
 397                 .pio_mask       = ATA_PIO4, \
 398                 .mwdma_mask     = ATA_MWDMA2, \
 399                 .udma_mask      = udma, \
 400         }
 401
 402 static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
 403         {       /* 0 */
 404                 .name           = "PDC20246",
 405                 .init_chipset   = init_chipset_pdc202xx,
 406                 .init_hwif      = init_hwif_pdc202xx,
 407                 .init_dma       = init_dma_pdc202xx,
 408                 .extra          = 16,
 409                 .host_flags     = IDE_HFLAGS_PDC202XX,
 410                 .pio_mask       = ATA_PIO4,
 411                 .mwdma_mask     = ATA_MWDMA2,
 412                 .udma_mask      = ATA_UDMA2,
 413         },
 414
 415         /* 1 */ DECLARE_PDC2026X_DEV("PDC20262", ATA_UDMA4, 0),
 416         /* 2 */ DECLARE_PDC2026X_DEV("PDC20263", ATA_UDMA4, 0),
 417         /* 3 */ DECLARE_PDC2026X_DEV("PDC20265", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
 418         /* 4 */ DECLARE_PDC2026X_DEV("PDC20267", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
 419 };
 420
 421 /**
 422  *      pdc202xx_init_one       -       called when a PDC202xx is found
 423  *      @dev: the pdc202xx device
 424  *      @id: the matching pci id
 425  *
 426  *      Called when the PCI registration layer (or the IDE initialization)
 427  *      finds a device matching our IDE device tables.
 428  */
 429
 430 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 431 {
 432         const struct ide_port_info *d;
 433         u8 idx = id->driver_data;
 434
 435         d = &pdc202xx_chipsets[idx];
 436
 437         if (idx < 3)
 438                 pdc202ata4_fixup_irq(dev, d->name);
 439
 440         if (idx == 3) {
 441                 struct pci_dev *bridge = dev->bus->self;
 442
 443                 if (bridge &&
 444                     bridge->vendor == PCI_VENDOR_ID_INTEL &&
 445                     (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
 446                      bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
 447                         printk(KERN_INFO "ide: Skipping Promise PDC20265 "
 448                                 "attached to I2O RAID controller\n");
 449                         return -ENODEV;
 450                 }
 451         }
 452
 453         return ide_setup_pci_device(dev, d);
 454 }
 455
 456 static const struct pci_device_id pdc202xx_pci_tbl[] = {
 457         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
 458         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
 459         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 2 },
 460         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 3 },
 461         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 4 },
 462         { 0, },
 463 };
 464 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
 465
 466 static struct pci_driver driver = {
 467         .name           = "Promise_Old_IDE",
 468         .id_table       = pdc202xx_pci_tbl,
 469         .probe          = pdc202xx_init_one,
 470 };
 471
 472 static int __init pdc202xx_ide_init(void)
 473 {
 474         return ide_pci_register_driver(&driver);
 475 }
 476
 477 module_init(pdc202xx_ide_init);
 478
 479 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 480 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
 481 MODULE_LICENSE("GPL");