SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/ide/pci/hpt366.c

   1 /*
   2  * linux/drivers/ide/pci/hpt366.c               Version 0.45    May 27, 2006
   3  *
   4  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   5  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
   6  * Portions Copyright (C) 2003          Red Hat Inc
   7  * Portions Copyright (C) 2005-2006     MontaVista Software, Inc.
   8  *
   9  * Thanks to HighPoint Technologies for their assistance, and hardware.
  10  * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
  11  * donation of an ABit BP6 mainboard, processor, and memory acellerated
  12  * development and support.
  13  *
  14  *
  15  * HighPoint has its own drivers (open source except for the RAID part)
  16  * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
  17  * This may be useful to anyone wanting to work on this driver, however  do not
  18  * trust  them too much since the code tends to become less and less meaningful
  19  * as the time passes... :-/
  20  *
  21  * Note that final HPT370 support was done by force extraction of GPL.
  22  *
  23  * - add function for getting/setting power status of drive
  24  * - the HPT370's state machine can get confused. reset it before each dma
  25  *   xfer to prevent that from happening.
  26  * - reset state engine whenever we get an error.
  27  * - check for busmaster state at end of dma.
  28  * - use new highpoint timings.
  29  * - detect bus speed using highpoint register.
  30  * - use pll if we don't have a clock table. added a 66MHz table that's
  31  *   just 2x the 33MHz table.
  32  * - removed turnaround. NOTE: we never want to switch between pll and
  33  *   pci clocks as the chip can glitch in those cases. the highpoint
  34  *   approved workaround slows everything down too much to be useful. in
  35  *   addition, we would have to serialize access to each chip.
  36  *      Adrian Sun <a.sun@sun.com>
  37  *
  38  * add drive timings for 66MHz PCI bus,
  39  * fix ATA Cable signal detection, fix incorrect /proc info
  40  * add /proc display for per-drive PIO/DMA/UDMA mode and
  41  * per-channel ATA-33/66 Cable detect.
  42  *      Duncan Laurie <void@sun.com>
  43  *
  44  * fixup /proc output for multiple controllers
  45  *      Tim Hockin <thockin@sun.com>
  46  *
  47  * On hpt366:
  48  * Reset the hpt366 on error, reset on dma
  49  * Fix disabling Fast Interrupt hpt366.
  50  *      Mike Waychison <crlf@sun.com>
  51  *
  52  * Added support for 372N clocking and clock switching. The 372N needs
  53  * different clocks on read/write. This requires overloading rw_disk and
  54  * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
  55  * keeping me sane.
  56  *              Alan Cox <alan@redhat.com>
  57  *
  58  * - fix the clock turnaround code: it was writing to the wrong ports when
  59  *   called for the secondary channel, caching the current clock mode per-
  60  *   channel caused the cached register value to get out of sync with the
  61  *   actual one, the channels weren't serialized, the turnaround shouldn't
  62  *   be done on 66 MHz PCI bus
  63  * - avoid calibrating PLL twice as the second time results in a wrong PCI
  64  *   frequency and thus in the wrong timings for the secondary channel
  65  * - disable UltraATA/133 for HPT372 and UltraATA/100 for HPT370 by default
  66  *   as the ATA clock being used does not allow for this speed anyway
  67  * - add support for HPT302N and HPT371N clocking (the same as for HPT372N)
  68  * - HPT371/N are single channel chips, so avoid touching the primary channel
  69  *   which exists only virtually (there's no pins for it)
  70  * - fix/remove bad/unused timing tables and use one set of tables for the whole
  71  *   HPT37x chip family; save space by introducing the separate transfer mode
  72  *   table in which the mode lookup is done
  73  * - use f_CNT value saved by  the HighPoint BIOS as reading it directly gives
  74  *   the wrong PCI frequency since DPLL has already been calibrated by BIOS
  75  * - fix the hotswap code:  it caused RESET- to glitch when tristating the bus,
  76  *   and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
  77  * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
  78  *   they tamper with its fields
  79  * - prefix the driver startup messages with the real chip name
  80  * - claim the extra 240 bytes of I/O space for all chips
  81  * - optimize the rate masking/filtering and the drive list lookup code
  82  * - use pci_get_slot() to get to the function 1 of HPT36x/374
  83  *              <source@mvista.com>
  84  *
  85  */
  86
  87
  88 #include <linux/types.h>
  89 #include <linux/module.h>
  90 #include <linux/kernel.h>
  91 #include <linux/delay.h>
  92 #include <linux/timer.h>
  93 #include <linux/mm.h>
  94 #include <linux/ioport.h>
  95 #include <linux/blkdev.h>
  96 #include <linux/hdreg.h>
  97
  98 #include <linux/interrupt.h>
  99 #include <linux/pci.h>
 100 #include <linux/init.h>
 101 #include <linux/ide.h>
 102
 103 #include <asm/uaccess.h>
 104 #include <asm/io.h>
 105 #include <asm/irq.h>
 106
 107 /* various tuning parameters */
 108 #define HPT_RESET_STATE_ENGINE
 109 #undef  HPT_DELAY_INTERRUPT
 110 #define HPT_SERIALIZE_IO        0
 111
 112 static const char *quirk_drives[] = {
 113         "QUANTUM FIREBALLlct08 08",
 114         "QUANTUM FIREBALLP KA6.4",
 115         "QUANTUM FIREBALLP LM20.4",
 116         "QUANTUM FIREBALLP LM20.5",
 117         NULL
 118 };
 119
 120 static const char *bad_ata100_5[] = {
 121         "IBM-DTLA-307075",
 122         "IBM-DTLA-307060",
 123         "IBM-DTLA-307045",
 124         "IBM-DTLA-307030",
 125         "IBM-DTLA-307020",
 126         "IBM-DTLA-307015",
 127         "IBM-DTLA-305040",
 128         "IBM-DTLA-305030",
 129         "IBM-DTLA-305020",
 130         "IC35L010AVER07-0",
 131         "IC35L020AVER07-0",
 132         "IC35L030AVER07-0",
 133         "IC35L040AVER07-0",
 134         "IC35L060AVER07-0",
 135         "WDC AC310200R",
 136         NULL
 137 };
 138
 139 static const char *bad_ata66_4[] = {
 140         "IBM-DTLA-307075",
 141         "IBM-DTLA-307060",
 142         "IBM-DTLA-307045",
 143         "IBM-DTLA-307030",
 144         "IBM-DTLA-307020",
 145         "IBM-DTLA-307015",
 146         "IBM-DTLA-305040",
 147         "IBM-DTLA-305030",
 148         "IBM-DTLA-305020",
 149         "IC35L010AVER07-0",
 150         "IC35L020AVER07-0",
 151         "IC35L030AVER07-0",
 152         "IC35L040AVER07-0",
 153         "IC35L060AVER07-0",
 154         "WDC AC310200R",
 155         NULL
 156 };
 157
 158 static const char *bad_ata66_3[] = {
 159         "WDC AC310200R",
 160         NULL
 161 };
 162
 163 static const char *bad_ata33[] = {
 164         "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
 165         "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
 166         "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
 167         "Maxtor 90510D4",
 168         "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
 169         "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
 170         "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
 171         NULL
 172 };
 173
 174 static u8 xfer_speeds[] = {
 175         XFER_UDMA_6,
 176         XFER_UDMA_5,
 177         XFER_UDMA_4,
 178         XFER_UDMA_3,
 179         XFER_UDMA_2,
 180         XFER_UDMA_1,
 181         XFER_UDMA_0,
 182
 183         XFER_MW_DMA_2,
 184         XFER_MW_DMA_1,
 185         XFER_MW_DMA_0,
 186
 187         XFER_PIO_4,
 188         XFER_PIO_3,
 189         XFER_PIO_2,
 190         XFER_PIO_1,
 191         XFER_PIO_0
 192 };
 193
 194 /* Key for bus clock timings
 195  * 36x   37x
 196  * bits  bits
 197  * 0:3   0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 198  *              cycles = value + 1
 199  * 4:7   4:8    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 200  *              cycles = value + 1
 201  * 8:11  9:12   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 202  *              register access.
 203  * 12:15 13:17  cmd_low_time. Active time of DIOW_/DIOR_ during task file
 204  *              register access.
 205  * 16:18 18:20  udma_cycle_time. Clock cycles for UDMA xfer.
 206  * -     21     CLK frequency: 0=ATA clock, 1=dual ATA clock.
 207  * 19:21 22:24  pre_high_time. Time to initialize the 1st cycle for PIO and
 208  *              MW DMA xfer.
 209  * 22:24 25:27  cmd_pre_high_time. Time to initialize the 1st PIO cycle for
 210  *              task file register access.
 211  * 28    28     UDMA enable.
 212  * 29    29     DMA  enable.
 213  * 30    30     PIO MST enable. If set, the chip is in bus master mode during
 214  *              PIO xfer.
 215  * 31    31     FIFO enable.
 216  */
 217
 218 static u32 forty_base_hpt36x[] = {
 219         /* XFER_UDMA_6 */       0x900fd943,
 220         /* XFER_UDMA_5 */       0x900fd943,
 221         /* XFER_UDMA_4 */       0x900fd943,
 222         /* XFER_UDMA_3 */       0x900ad943,
 223         /* XFER_UDMA_2 */       0x900bd943,
 224         /* XFER_UDMA_1 */       0x9008d943,
 225         /* XFER_UDMA_0 */       0x9008d943,
 226
 227         /* XFER_MW_DMA_2 */     0xa008d943,
 228         /* XFER_MW_DMA_1 */     0xa010d955,
 229         /* XFER_MW_DMA_0 */     0xa010d9fc,
 230
 231         /* XFER_PIO_4 */        0xc008d963,
 232         /* XFER_PIO_3 */        0xc010d974,
 233         /* XFER_PIO_2 */        0xc010d997,
 234         /* XFER_PIO_1 */        0xc010d9c7,
 235         /* XFER_PIO_0 */        0xc018d9d9
 236 };
 237
 238 static u32 thirty_three_base_hpt36x[] = {
 239         /* XFER_UDMA_6 */       0x90c9a731,
 240         /* XFER_UDMA_5 */       0x90c9a731,
 241         /* XFER_UDMA_4 */       0x90c9a731,
 242         /* XFER_UDMA_3 */       0x90cfa731,
 243         /* XFER_UDMA_2 */       0x90caa731,
 244         /* XFER_UDMA_1 */       0x90cba731,
 245         /* XFER_UDMA_0 */       0x90c8a731,
 246
 247         /* XFER_MW_DMA_2 */     0xa0c8a731,
 248         /* XFER_MW_DMA_1 */     0xa0c8a732,     /* 0xa0c8a733 */
 249         /* XFER_MW_DMA_0 */     0xa0c8a797,
 250
 251         /* XFER_PIO_4 */        0xc0c8a731,
 252         /* XFER_PIO_3 */        0xc0c8a742,
 253         /* XFER_PIO_2 */        0xc0d0a753,
 254         /* XFER_PIO_1 */        0xc0d0a7a3,     /* 0xc0d0a793 */
 255         /* XFER_PIO_0 */        0xc0d0a7aa      /* 0xc0d0a7a7 */
 256 };
 257
 258 static u32 twenty_five_base_hpt36x[] = {
 259         /* XFER_UDMA_6 */       0x90c98521,
 260         /* XFER_UDMA_5 */       0x90c98521,
 261         /* XFER_UDMA_4 */       0x90c98521,
 262         /* XFER_UDMA_3 */       0x90cf8521,
 263         /* XFER_UDMA_2 */       0x90cf8521,
 264         /* XFER_UDMA_1 */       0x90cb8521,
 265         /* XFER_UDMA_0 */       0x90cb8521,
 266
 267         /* XFER_MW_DMA_2 */     0xa0ca8521,
 268         /* XFER_MW_DMA_1 */     0xa0ca8532,
 269         /* XFER_MW_DMA_0 */     0xa0ca8575,
 270
 271         /* XFER_PIO_4 */        0xc0ca8521,
 272         /* XFER_PIO_3 */        0xc0ca8532,
 273         /* XFER_PIO_2 */        0xc0ca8542,
 274         /* XFER_PIO_1 */        0xc0d08572,
 275         /* XFER_PIO_0 */        0xc0d08585
 276 };
 277
 278 static u32 thirty_three_base_hpt37x[] = {
 279         /* XFER_UDMA_6 */       0x12446231,     /* 0x12646231 ?? */
 280         /* XFER_UDMA_5 */       0x12446231,
 281         /* XFER_UDMA_4 */       0x12446231,
 282         /* XFER_UDMA_3 */       0x126c6231,
 283         /* XFER_UDMA_2 */       0x12486231,
 284         /* XFER_UDMA_1 */       0x124c6233,
 285         /* XFER_UDMA_0 */       0x12506297,
 286
 287         /* XFER_MW_DMA_2 */     0x22406c31,
 288         /* XFER_MW_DMA_1 */     0x22406c33,
 289         /* XFER_MW_DMA_0 */     0x22406c97,
 290
 291         /* XFER_PIO_4 */        0x06414e31,
 292         /* XFER_PIO_3 */        0x06414e42,
 293         /* XFER_PIO_2 */        0x06414e53,
 294         /* XFER_PIO_1 */        0x06814e93,
 295         /* XFER_PIO_0 */        0x06814ea7
 296 };
 297
 298 static u32 fifty_base_hpt37x[] = {
 299         /* XFER_UDMA_6 */       0x12848242,
 300         /* XFER_UDMA_5 */       0x12848242,
 301         /* XFER_UDMA_4 */       0x12ac8242,
 302         /* XFER_UDMA_3 */       0x128c8242,
 303         /* XFER_UDMA_2 */       0x120c8242,
 304         /* XFER_UDMA_1 */       0x12148254,
 305         /* XFER_UDMA_0 */       0x121882ea,
 306
 307         /* XFER_MW_DMA_2 */     0x22808242,
 308         /* XFER_MW_DMA_1 */     0x22808254,
 309         /* XFER_MW_DMA_0 */     0x228082ea,
 310
 311         /* XFER_PIO_4 */        0x0a81f442,
 312         /* XFER_PIO_3 */        0x0a81f443,
 313         /* XFER_PIO_2 */        0x0a81f454,
 314         /* XFER_PIO_1 */        0x0ac1f465,
 315         /* XFER_PIO_0 */        0x0ac1f48a
 316 };
 317
 318 static u32 sixty_six_base_hpt37x[] = {
 319         /* XFER_UDMA_6 */       0x1c869c62,
 320         /* XFER_UDMA_5 */       0x1cae9c62,     /* 0x1c8a9c62 */
 321         /* XFER_UDMA_4 */       0x1c8a9c62,
 322         /* XFER_UDMA_3 */       0x1c8e9c62,
 323         /* XFER_UDMA_2 */       0x1c929c62,
 324         /* XFER_UDMA_1 */       0x1c9a9c62,
 325         /* XFER_UDMA_0 */       0x1c829c62,
 326
 327         /* XFER_MW_DMA_2 */     0x2c829c62,
 328         /* XFER_MW_DMA_1 */     0x2c829c66,
 329         /* XFER_MW_DMA_0 */     0x2c829d2e,
 330
 331         /* XFER_PIO_4 */        0x0c829c62,
 332         /* XFER_PIO_3 */        0x0c829c84,
 333         /* XFER_PIO_2 */        0x0c829ca6,
 334         /* XFER_PIO_1 */        0x0d029d26,
 335         /* XFER_PIO_0 */        0x0d029d5e
 336 };
 337
 338 #define HPT366_DEBUG_DRIVE_INFO         0
 339 #define HPT374_ALLOW_ATA133_6           0
 340 #define HPT371_ALLOW_ATA133_6           0
 341 #define HPT302_ALLOW_ATA133_6           0
 342 #define HPT372_ALLOW_ATA133_6           0
 343 #define HPT370_ALLOW_ATA100_5           0
 344 #define HPT366_ALLOW_ATA66_4            1
 345 #define HPT366_ALLOW_ATA66_3            1
 346 #define HPT366_MAX_DEVS                 8
 347
 348 #define F_LOW_PCI_33    0x23
 349 #define F_LOW_PCI_40    0x29
 350 #define F_LOW_PCI_50    0x2d
 351 #define F_LOW_PCI_66    0x42
 352
 353 /*
 354  *      Hold all the highpoint quirks and revision information in one
 355  *      place.
 356  */
 357
 358 struct hpt_info
 359 {
 360         u8 max_mode;            /* Speeds allowed */
 361         u8 revision;            /* Chipset revision */
 362         u8 flags;               /* Chipset properties */
 363 #define PLL_MODE        1
 364 #define IS_3xxN         2
 365 #define PCI_66MHZ       4
 366                                 /* Speed table */
 367         u32 *speed;
 368 };
 369
 370 /*
 371  *      This wants fixing so that we do everything not by revision
 372  *      (which breaks on the newest chips) but by creating an
 373  *      enumeration of chip variants and using that
 374  */
 375
 376 static __devinit u8 hpt_revision(struct pci_dev *dev)
 377 {
 378         u8 rev = 0;
 379
 380         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
 381
 382         switch(dev->device) {
 383                 /* Remap new 372N onto 372 */
 384                 case PCI_DEVICE_ID_TTI_HPT372N:
 385                         rev = PCI_DEVICE_ID_TTI_HPT372;
 386                         break;
 387                 case PCI_DEVICE_ID_TTI_HPT374:
 388                         rev = PCI_DEVICE_ID_TTI_HPT374;
 389                         break;
 390                 case PCI_DEVICE_ID_TTI_HPT371:
 391                         rev = PCI_DEVICE_ID_TTI_HPT371;
 392                         break;
 393                 case PCI_DEVICE_ID_TTI_HPT302:
 394                         rev = PCI_DEVICE_ID_TTI_HPT302;
 395                         break;
 396                 case PCI_DEVICE_ID_TTI_HPT372:
 397                         rev = PCI_DEVICE_ID_TTI_HPT372;
 398                         break;
 399                 default:
 400                         break;
 401         }
 402         return rev;
 403 }
 404
 405 static int check_in_drive_list(ide_drive_t *drive, const char **list)
 406 {
 407         struct hd_driveid *id = drive->id;
 408
 409         while (*list)
 410                 if (!strcmp(*list++,id->model))
 411                         return 1;
 412         return 0;
 413 }
 414
 415 static u8 hpt3xx_ratemask(ide_drive_t *drive)
 416 {
 417         struct hpt_info *info   = ide_get_hwifdata(HWIF(drive));
 418         u8 mode                 = info->max_mode;
 419
 420         if (!eighty_ninty_three(drive) && mode)
 421                 mode = min(mode, (u8)1);
 422         return mode;
 423 }
 424
 425 /*
 426  *      Note for the future; the SATA hpt37x we must set
 427  *      either PIO or UDMA modes 0,4,5
 428  */
 429
 430 static u8 hpt3xx_ratefilter(ide_drive_t *drive, u8 speed)
 431 {
 432         struct hpt_info *info   = ide_get_hwifdata(HWIF(drive));
 433         u8 mode                 = hpt3xx_ratemask(drive);
 434
 435         if (drive->media != ide_disk)
 436                 return min(speed, (u8)XFER_PIO_4);
 437
 438         switch (mode) {
 439                 case 0x04:
 440                         speed = min(speed, (u8)XFER_UDMA_6);
 441                         break;
 442                 case 0x03:
 443                         speed = min(speed, (u8)XFER_UDMA_5);
 444                         if (info->revision >= 5)
 445                                 break;
 446                         if (!check_in_drive_list(drive, bad_ata100_5))
 447                                 goto check_bad_ata33;
 448                         /* fall thru */
 449                 case 0x02:
 450                         speed = min_t(u8, speed, XFER_UDMA_4);
 451         /*
 452          * CHECK ME, Does this need to be set to 5 ??
 453          */
 454                         if (info->revision >= 3)
 455                                 goto check_bad_ata33;
 456                         if (HPT366_ALLOW_ATA66_4 &&
 457                             !check_in_drive_list(drive, bad_ata66_4))
 458                                 goto check_bad_ata33;
 459
 460                         speed = min_t(u8, speed, XFER_UDMA_3);
 461                         if (HPT366_ALLOW_ATA66_3 &&
 462                             !check_in_drive_list(drive, bad_ata66_3))
 463                                 goto check_bad_ata33;
 464                         /* fall thru */
 465                 case 0x01:
 466                         speed = min_t(u8, speed, XFER_UDMA_2);
 467
 468                 check_bad_ata33:
 469                         if (info->revision >= 4)
 470                                 break;
 471                         if (!check_in_drive_list(drive, bad_ata33))
 472                                 break;
 473                         /* fall thru */
 474                 case 0x00:
 475                 default:
 476                         speed = min_t(u8, speed, XFER_MW_DMA_2);
 477                         break;
 478         }
 479         return speed;
 480 }
 481
 482 static u32 pci_bus_clock_list(u8 speed, u32 *chipset_table)
 483 {
 484         int i;
 485
 486         /*
 487          * Lookup the transfer mode table to get the index into
 488          * the timing table.
 489          *
 490          * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
 491          */
 492         for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
 493                 if (xfer_speeds[i] == speed)
 494                         break;
 495         return chipset_table[i];
 496 }
 497
 498 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 499 {
 500         ide_hwif_t *hwif        = drive->hwif;
 501         struct pci_dev *dev     = hwif->pci_dev;
 502         struct hpt_info *info   = ide_get_hwifdata(hwif);
 503         u8 speed                = hpt3xx_ratefilter(drive, xferspeed);
 504         u8 regtime              = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
 505         u8 regfast              = (hwif->channel) ? 0x55 : 0x51;
 506         u8 drive_fast           = 0;
 507         u32 reg1 = 0, reg2      = 0;
 508
 509         /*
 510          * Disable the "fast interrupt" prediction.
 511          */
 512         pci_read_config_byte(dev, regfast, &drive_fast);
 513         if (drive_fast & 0x80)
 514                 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
 515
 516         reg2 = pci_bus_clock_list(speed, info->speed);
 517
 518         /*
 519          * Disable on-chip PIO FIFO/buffer
 520          *  (to avoid problems handling I/O errors later)
 521          */
 522         pci_read_config_dword(dev, regtime, &reg1);
 523         if (speed >= XFER_MW_DMA_0) {
 524                 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
 525         } else {
 526                 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
 527         }
 528         reg2 &= ~0x80000000;
 529
 530         pci_write_config_dword(dev, regtime, reg2);
 531
 532         return ide_config_drive_speed(drive, speed);
 533 }
 534
 535 static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 536 {
 537         ide_hwif_t *hwif        = drive->hwif;
 538         struct pci_dev *dev = hwif->pci_dev;
 539         struct hpt_info *info   = ide_get_hwifdata(hwif);
 540         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
 541         u8 regfast      = (drive->hwif->channel) ? 0x55 : 0x51;
 542         u8 drive_pci    = 0x40 + (drive->dn * 4);
 543         u8 new_fast     = 0, drive_fast = 0;
 544         u32 list_conf   = 0, drive_conf = 0;
 545         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 546
 547         /*
 548          * Disable the "fast interrupt" prediction.
 549          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 550          */
 551         pci_read_config_byte(dev, regfast, &drive_fast);
 552         new_fast = drive_fast;
 553         if (new_fast & 0x02)
 554                 new_fast &= ~0x02;
 555
 556 #ifdef HPT_DELAY_INTERRUPT
 557         if (new_fast & 0x01)
 558                 new_fast &= ~0x01;
 559 #else
 560         if ((new_fast & 0x01) == 0)
 561                 new_fast |= 0x01;
 562 #endif
 563         if (new_fast != drive_fast)
 564                 pci_write_config_byte(dev, regfast, new_fast);
 565
 566         list_conf = pci_bus_clock_list(speed, info->speed);
 567
 568         pci_read_config_dword(dev, drive_pci, &drive_conf);
 569         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 570
 571         if (speed < XFER_MW_DMA_0)
 572                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 573         pci_write_config_dword(dev, drive_pci, list_conf);
 574
 575         return ide_config_drive_speed(drive, speed);
 576 }
 577
 578 static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 579 {
 580         ide_hwif_t *hwif        = drive->hwif;
 581         struct pci_dev *dev     = hwif->pci_dev;
 582         struct hpt_info *info   = ide_get_hwifdata(hwif);
 583         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
 584         u8 regfast      = (drive->hwif->channel) ? 0x55 : 0x51;
 585         u8 drive_fast   = 0, drive_pci = 0x40 + (drive->dn * 4);
 586         u32 list_conf   = 0, drive_conf = 0;
 587         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 588
 589         /*
 590          * Disable the "fast interrupt" prediction.
 591          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 592          */
 593         pci_read_config_byte(dev, regfast, &drive_fast);
 594         drive_fast &= ~0x07;
 595         pci_write_config_byte(dev, regfast, drive_fast);
 596
 597         list_conf = pci_bus_clock_list(speed, info->speed);
 598         pci_read_config_dword(dev, drive_pci, &drive_conf);
 599         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 600         if (speed < XFER_MW_DMA_0)
 601                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 602         pci_write_config_dword(dev, drive_pci, list_conf);
 603
 604         return ide_config_drive_speed(drive, speed);
 605 }
 606
 607 static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
 608 {
 609         ide_hwif_t *hwif        = drive->hwif;
 610         struct hpt_info *info   = ide_get_hwifdata(hwif);
 611
 612         if (info->revision >= 8)
 613                 return hpt372_tune_chipset(drive, speed); /* not a typo */
 614         else if (info->revision >= 5)
 615                 return hpt372_tune_chipset(drive, speed);
 616         else if (info->revision >= 3)
 617                 return hpt370_tune_chipset(drive, speed);
 618         else    /* hpt368: hpt_minimum_revision(dev, 2) */
 619                 return hpt36x_tune_chipset(drive, speed);
 620 }
 621
 622 static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
 623 {
 624         pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
 625         (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
 626 }
 627
 628 /*
 629  * This allows the configuration of ide_pci chipset registers
 630  * for cards that learn about the drive's UDMA, DMA, PIO capabilities
 631  * after the drive is reported by the OS.  Initially for designed for
 632  * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
 633  *
 634  * check_in_drive_lists(drive, bad_ata66_4)
 635  * check_in_drive_lists(drive, bad_ata66_3)
 636  * check_in_drive_lists(drive, bad_ata33)
 637  *
 638  */
 639 static int config_chipset_for_dma (ide_drive_t *drive)
 640 {
 641         u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
 642         ide_hwif_t *hwif = drive->hwif;
 643         struct hpt_info *info   = ide_get_hwifdata(hwif);
 644
 645         if (!speed)
 646                 return 0;
 647
 648         /* If we don't have any timings we can't do a lot */
 649         if (info->speed == NULL)
 650                 return 0;
 651
 652         (void) hpt3xx_tune_chipset(drive, speed);
 653         return ide_dma_enable(drive);
 654 }
 655
 656 static int hpt3xx_quirkproc(ide_drive_t *drive)
 657 {
 658         struct hd_driveid *id   = drive->id;
 659         const  char **list      = quirk_drives;
 660
 661         while (*list)
 662                 if (strstr(id->model, *list++))
 663                         return 1;
 664         return 0;
 665 }
 666
 667 static void hpt3xx_intrproc (ide_drive_t *drive)
 668 {
 669         ide_hwif_t *hwif = drive->hwif;
 670
 671         if (drive->quirk_list)
 672                 return;
 673         /* drives in the quirk_list may not like intr setups/cleanups */
 674         hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG);
 675 }
 676
 677 static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
 678 {
 679         ide_hwif_t *hwif = drive->hwif;
 680         struct hpt_info *info = ide_get_hwifdata(hwif);
 681         struct pci_dev *dev = hwif->pci_dev;
 682
 683         if (drive->quirk_list) {
 684                 if (info->revision >= 3) {
 685                         u8 reg5a = 0;
 686                         pci_read_config_byte(dev, 0x5a, &reg5a);
 687                         if (((reg5a & 0x10) >> 4) != mask)
 688                                 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
 689                 } else {
 690                         if (mask) {
 691                                 disable_irq(hwif->irq);
 692                         } else {
 693                                 enable_irq(hwif->irq);
 694                         }
 695                 }
 696         } else {
 697                 if (IDE_CONTROL_REG)
 698                         hwif->OUTB(mask ? (drive->ctl | 2) :
 699                                                  (drive->ctl & ~2),
 700                                                  IDE_CONTROL_REG);
 701         }
 702 }
 703
 704 static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
 705 {
 706         ide_hwif_t *hwif        = drive->hwif;
 707         struct hd_driveid *id   = drive->id;
 708
 709         drive->init_speed = 0;
 710
 711         if ((id->capability & 1) && drive->autodma) {
 712
 713                 if (ide_use_dma(drive)) {
 714                         if (config_chipset_for_dma(drive))
 715                                 return hwif->ide_dma_on(drive);
 716                 }
 717
 718                 goto fast_ata_pio;
 719
 720         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 721 fast_ata_pio:
 722                 hpt3xx_tune_drive(drive, 5);
 723                 return hwif->ide_dma_off_quietly(drive);
 724         }
 725         /* IORDY not supported */
 726         return 0;
 727 }
 728
 729 /*
 730  * This is specific to the HPT366 UDMA bios chipset
 731  * by HighPoint|Triones Technologies, Inc.
 732  */
 733 static int hpt366_ide_dma_lostirq (ide_drive_t *drive)
 734 {
 735         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 736         u8 reg50h = 0, reg52h = 0, reg5ah = 0;
 737
 738         pci_read_config_byte(dev, 0x50, &reg50h);
 739         pci_read_config_byte(dev, 0x52, &reg52h);
 740         pci_read_config_byte(dev, 0x5a, &reg5ah);
 741         printk("%s: (%s)  reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
 742                 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
 743         if (reg5ah & 0x10)
 744                 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
 745         return __ide_dma_lostirq(drive);
 746 }
 747
 748 static void hpt370_clear_engine (ide_drive_t *drive)
 749 {
 750         u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50;
 751         pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37);
 752         udelay(10);
 753 }
 754
 755 static void hpt370_ide_dma_start(ide_drive_t *drive)
 756 {
 757 #ifdef HPT_RESET_STATE_ENGINE
 758         hpt370_clear_engine(drive);
 759 #endif
 760         ide_dma_start(drive);
 761 }
 762
 763 static int hpt370_ide_dma_end (ide_drive_t *drive)
 764 {
 765         ide_hwif_t *hwif        = HWIF(drive);
 766         u8 dma_stat             = hwif->INB(hwif->dma_status);
 767
 768         if (dma_stat & 0x01) {
 769                 /* wait a little */
 770                 udelay(20);
 771                 dma_stat = hwif->INB(hwif->dma_status);
 772         }
 773         if ((dma_stat & 0x01) != 0)
 774                 /* fallthrough */
 775                 (void) HWIF(drive)->ide_dma_timeout(drive);
 776
 777         return __ide_dma_end(drive);
 778 }
 779
 780 static void hpt370_lostirq_timeout (ide_drive_t *drive)
 781 {
 782         ide_hwif_t *hwif        = HWIF(drive);
 783         u8 bfifo = 0, reginfo   = hwif->channel ? 0x56 : 0x52;
 784         u8 dma_stat = 0, dma_cmd = 0;
 785
 786         pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
 787         printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo);
 788         hpt370_clear_engine(drive);
 789         /* get dma command mode */
 790         dma_cmd = hwif->INB(hwif->dma_command);
 791         /* stop dma */
 792         hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
 793         dma_stat = hwif->INB(hwif->dma_status);
 794         /* clear errors */
 795         hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
 796 }
 797
 798 static int hpt370_ide_dma_timeout (ide_drive_t *drive)
 799 {
 800         hpt370_lostirq_timeout(drive);
 801         hpt370_clear_engine(drive);
 802         return __ide_dma_timeout(drive);
 803 }
 804
 805 static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
 806 {
 807         hpt370_lostirq_timeout(drive);
 808         hpt370_clear_engine(drive);
 809         return __ide_dma_lostirq(drive);
 810 }
 811
 812 /* returns 1 if DMA IRQ issued, 0 otherwise */
 813 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
 814 {
 815         ide_hwif_t *hwif        = HWIF(drive);
 816         u16 bfifo               = 0;
 817         u8 reginfo              = hwif->channel ? 0x56 : 0x52;
 818         u8 dma_stat;
 819
 820         pci_read_config_word(hwif->pci_dev, reginfo, &bfifo);
 821         if (bfifo & 0x1FF) {
 822 //              printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 823                 return 0;
 824         }
 825
 826         dma_stat = hwif->INB(hwif->dma_status);
 827         /* return 1 if INTR asserted */
 828         if ((dma_stat & 4) == 4)
 829                 return 1;
 830
 831         if (!drive->waiting_for_dma)
 832                 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
 833                                 drive->name, __FUNCTION__);
 834         return 0;
 835 }
 836
 837 static int hpt374_ide_dma_end (ide_drive_t *drive)
 838 {
 839         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 840         ide_hwif_t *hwif        = HWIF(drive);
 841         u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50;
 842         u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01;
 843
 844         pci_read_config_byte(dev, 0x6a, &bwsr_stat);
 845         pci_read_config_byte(dev, mscreg, &msc_stat);
 846         if ((bwsr_stat & bwsr_mask) == bwsr_mask)
 847                 pci_write_config_byte(dev, mscreg, msc_stat|0x30);
 848         return __ide_dma_end(drive);
 849 }
 850
 851 /**
 852  *      hpt3xxn_set_clock       -       perform clock switching dance
 853  *      @hwif: hwif to switch
 854  *      @mode: clocking mode (0x21 for write, 0x23 otherwise)
 855  *
 856  *      Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
 857  *      NOTE: avoid touching the disabled primary channel on HPT371N -- it
 858  *      doesn't physically exist anyway...
 859  */
 860
 861 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
 862 {
 863         u8 mcr1, scr2 = hwif->INB(hwif->dma_master + 0x7b);
 864
 865         if ((scr2 & 0x7f) == mode)
 866                 return;
 867
 868         /* MISC. control register 1 has the channel enable bit... */
 869         mcr1 = hwif->INB(hwif->dma_master + 0x70);
 870
 871         /* Tristate the bus */
 872         if (mcr1 & 0x04)
 873                 hwif->OUTB(0x80, hwif->dma_master + 0x73);
 874         hwif->OUTB(0x80, hwif->dma_master + 0x77);
 875
 876         /* Switch clock and reset channels */
 877         hwif->OUTB(mode, hwif->dma_master + 0x7b);
 878         hwif->OUTB(0xc0, hwif->dma_master + 0x79);
 879
 880         /* Reset state machines */
 881         if (mcr1 & 0x04)
 882                 hwif->OUTB(0x37, hwif->dma_master + 0x70);
 883         hwif->OUTB(0x37, hwif->dma_master + 0x74);
 884
 885         /* Complete reset */
 886         hwif->OUTB(0x00, hwif->dma_master + 0x79);
 887
 888         /* Reconnect channels to bus */
 889         if (mcr1 & 0x04)
 890                 hwif->OUTB(0x00, hwif->dma_master + 0x73);
 891         hwif->OUTB(0x00, hwif->dma_master + 0x77);
 892 }
 893
 894 /**
 895  *      hpt3xxn_rw_disk         -       prepare for I/O
 896  *      @drive: drive for command
 897  *      @rq: block request structure
 898  *
 899  *      This is called when a disk I/O is issued to HPT3xxN.
 900  *      We need it because of the clock switching.
 901  */
 902
 903 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
 904 {
 905         ide_hwif_t *hwif        = HWIF(drive);
 906         u8 wantclock            = rq_data_dir(rq) ? 0x23 : 0x21;
 907
 908         hpt3xxn_set_clock(hwif, wantclock);
 909 }
 910
 911 /*
 912  * Set/get power state for a drive.
 913  *
 914  * When we turn the power back on, we need to re-initialize things.
 915  */
 916 #define TRISTATE_BIT  0x8000
 917
 918 static int hpt3xx_busproc(ide_drive_t *drive, int state)
 919 {
 920         ide_hwif_t *hwif        = drive->hwif;
 921         struct pci_dev *dev     = hwif->pci_dev;
 922         u8  tristate, resetmask, bus_reg = 0;
 923         u16 tri_reg = 0;
 924
 925         hwif->bus_state = state;
 926
 927         if (hwif->channel) {
 928                 /* secondary channel */
 929                 tristate  = 0x56;
 930                 resetmask = 0x80;
 931         } else {
 932                 /* primary channel */
 933                 tristate  = 0x52;
 934                 resetmask = 0x40;
 935         }
 936
 937         /* Grab the status. */
 938         pci_read_config_word(dev, tristate, &tri_reg);
 939         pci_read_config_byte(dev, 0x59, &bus_reg);
 940
 941         /*
 942          * Set the state. We don't set it if we don't need to do so.
 943          * Make sure that the drive knows that it has failed if it's off.
 944          */
 945         switch (state) {
 946         case BUSSTATE_ON:
 947                 if (!(bus_reg & resetmask))
 948                         return 0;
 949                 hwif->drives[0].failures = hwif->drives[1].failures = 0;
 950
 951                 pci_write_config_byte(dev, 0x59, bus_reg & ~resetmask);
 952                 pci_write_config_word(dev, tristate, tri_reg & ~TRISTATE_BIT);
 953                 return 0;
 954         case BUSSTATE_OFF:
 955                 if ((bus_reg & resetmask) && !(tri_reg & TRISTATE_BIT))
 956                         return 0;
 957                 tri_reg &= ~TRISTATE_BIT;
 958                 break;
 959         case BUSSTATE_TRISTATE:
 960                 if ((bus_reg & resetmask) &&  (tri_reg & TRISTATE_BIT))
 961                         return 0;
 962                 tri_reg |= TRISTATE_BIT;
 963                 break;
 964         default:
 965                 return -EINVAL;
 966         }
 967
 968         hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 969         hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 970
 971         pci_write_config_word(dev, tristate, tri_reg);
 972         pci_write_config_byte(dev, 0x59, bus_reg | resetmask);
 973         return 0;
 974 }
 975
 976 static void __devinit hpt366_clocking(ide_hwif_t *hwif)
 977 {
 978         u32 reg1        = 0;
 979         struct hpt_info *info = ide_get_hwifdata(hwif);
 980
 981         pci_read_config_dword(hwif->pci_dev, 0x40, &reg1);
 982
 983         /* detect bus speed by looking at control reg timing: */
 984         switch((reg1 >> 8) & 7) {
 985                 case 5:
 986                         info->speed = forty_base_hpt36x;
 987                         break;
 988                 case 9:
 989                         info->speed = twenty_five_base_hpt36x;
 990                         break;
 991                 case 7:
 992                 default:
 993                         info->speed = thirty_three_base_hpt36x;
 994                         break;
 995         }
 996 }
 997
 998 static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
 999 {
1000         struct hpt_info *info   = ide_get_hwifdata(hwif);
1001         struct pci_dev  *dev    = hwif->pci_dev;
1002         char *name              = hwif->cds->name;
1003         int adjust, i;
1004         u16 freq = 0;
1005         u32 pll, temp = 0;
1006         u8 reg5bh = 0, mcr1 = 0;
1007
1008         /*
1009          * default to pci clock. make sure MA15/16 are set to output
1010          * to prevent drives having problems with 40-pin cables. Needed
1011          * for some drives such as IBM-DTLA which will not enter ready
1012          * state on reset when PDIAG is a input.
1013          *
1014          * ToDo: should we set 0x21 when using PLL mode ?
1015          */
1016         pci_write_config_byte(dev, 0x5b, 0x23);
1017
1018         /*
1019          * We'll have to read f_CNT value in order to determine
1020          * the PCI clock frequency according to the following ratio:
1021          *
1022          * f_CNT = Fpci * 192 / Fdpll
1023          *
1024          * First try reading the register in which the HighPoint BIOS
1025          * saves f_CNT value before  reprogramming the DPLL from its
1026          * default setting (which differs for the various chips).
1027          * NOTE: This register is only accessible via I/O space.
1028          *
1029          * In case the signature check fails, we'll have to resort to
1030          * reading the f_CNT register itself in hopes that nobody has
1031          * touched the DPLL yet...
1032          */
1033         temp = inl(pci_resource_start(dev, 4) + 0x90);
1034         if ((temp & 0xFFFFF000) != 0xABCDE000) {
1035                 printk(KERN_WARNING "%s: no clock data saved by BIOS\n", name);
1036
1037                 /* Calculate the average value of f_CNT */
1038                 for (temp = i = 0; i < 128; i++) {
1039                         pci_read_config_word(dev, 0x78, &freq);
1040                         temp += freq & 0x1ff;
1041                         mdelay(1);
1042                 }
1043                 freq = temp / 128;
1044         } else
1045                 freq = temp & 0x1ff;
1046
1047         /*
1048          * HPT3xxN chips use different PCI clock information.
1049          * Currently we always set up the PLL for them.
1050          */
1051
1052         if (info->flags & IS_3xxN) {
1053                 if(freq < 0x55)
1054                         pll = F_LOW_PCI_33;
1055                 else if(freq < 0x70)
1056                         pll = F_LOW_PCI_40;
1057                 else if(freq < 0x7F)
1058                         pll = F_LOW_PCI_50;
1059                 else
1060                         pll = F_LOW_PCI_66;
1061
1062         } else {
1063                 if(freq < 0x9C)
1064                         pll = F_LOW_PCI_33;
1065                 else if(freq < 0xb0)
1066                         pll = F_LOW_PCI_40;
1067                 else if(freq <0xc8)
1068                         pll = F_LOW_PCI_50;
1069                 else
1070                         pll = F_LOW_PCI_66;
1071         }
1072         printk(KERN_INFO "%s: FREQ: %d, PLL: %d\n", name, freq, pll);
1073
1074         if (!(info->flags & IS_3xxN)) {
1075                 if (pll == F_LOW_PCI_33) {
1076                         info->speed = thirty_three_base_hpt37x;
1077                         printk(KERN_DEBUG "%s: using 33MHz PCI clock\n", name);
1078                 } else if (pll == F_LOW_PCI_40) {
1079                         /* Unsupported */
1080                 } else if (pll == F_LOW_PCI_50) {
1081                         info->speed = fifty_base_hpt37x;
1082                         printk(KERN_DEBUG "%s: using 50MHz PCI clock\n", name);
1083                 } else {
1084                         info->speed = sixty_six_base_hpt37x;
1085                         printk(KERN_DEBUG "%s: using 66MHz PCI clock\n", name);
1086                 }
1087         }
1088
1089         if (pll == F_LOW_PCI_66)
1090                 info->flags |= PCI_66MHZ;
1091
1092         /*
1093          * only try the pll if we don't have a table for the clock
1094          * speed that we're running at. NOTE: the internal PLL will
1095          * result in slow reads when using a 33MHz PCI clock. we also
1096          * don't like to use the PLL because it will cause glitches
1097          * on PRST/SRST when the HPT state engine gets reset.
1098          *
1099          * ToDo: Use 66MHz PLL when ATA133 devices are present on a
1100          * 372 device so we can get ATA133 support
1101          */
1102         if (info->speed)
1103                 goto init_hpt37X_done;
1104
1105         info->flags |= PLL_MODE;
1106
1107         /*
1108          * Adjust the PLL based upon the PCI clock, enable it, and
1109          * wait for stabilization...
1110          */
1111         adjust = 0;
1112         freq = (pll < F_LOW_PCI_50) ? 2 : 4;
1113         while (adjust++ < 6) {
1114                 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
1115                                        pll | 0x100);
1116
1117                 /* wait for clock stabilization */
1118                 for (i = 0; i < 0x50000; i++) {
1119                         pci_read_config_byte(dev, 0x5b, &reg5bh);
1120                         if (reg5bh & 0x80) {
1121                                 /* spin looking for the clock to destabilize */
1122                                 for (i = 0; i < 0x1000; ++i) {
1123                                         pci_read_config_byte(dev, 0x5b,
1124                                                              &reg5bh);
1125                                         if ((reg5bh & 0x80) == 0)
1126                                                 goto pll_recal;
1127                                 }
1128                                 pci_read_config_dword(dev, 0x5c, &pll);
1129                                 pci_write_config_dword(dev, 0x5c,
1130                                                        pll & ~0x100);
1131                                 pci_write_config_byte(dev, 0x5b, 0x21);
1132
1133                                 info->speed = fifty_base_hpt37x;
1134                                 printk("%s: using 50MHz internal PLL\n", name);
1135                                 goto init_hpt37X_done;
1136                         }
1137                 }
1138 pll_recal:
1139                 if (adjust & 1)
1140                         pll -= (adjust >> 1);
1141                 else
1142                         pll += (adjust >> 1);
1143         }
1144
1145 init_hpt37X_done:
1146         if (!info->speed)
1147                 printk(KERN_ERR "%s: unknown bus timing [%d %d].\n",
1148                        name, pll, freq);
1149         /*
1150          * Reset the state engines.
1151          * NOTE: avoid accidentally enabling the primary channel on HPT371N.
1152          */
1153         pci_read_config_byte(dev, 0x50, &mcr1);
1154         if (mcr1 & 0x04)
1155                 pci_write_config_byte(dev, 0x50, 0x37);
1156         pci_write_config_byte(dev, 0x54, 0x37);
1157         udelay(100);
1158 }
1159
1160 static int __devinit init_hpt37x(struct pci_dev *dev)
1161 {
1162         u8 reg5ah;
1163
1164         pci_read_config_byte(dev, 0x5a, &reg5ah);
1165         /* interrupt force enable */
1166         pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
1167         return 0;
1168 }
1169
1170 static int __devinit init_hpt366(struct pci_dev *dev)
1171 {
1172         u32 reg1        = 0;
1173         u8 drive_fast   = 0;
1174
1175         /*
1176          * Disable the "fast interrupt" prediction.
1177          */
1178         pci_read_config_byte(dev, 0x51, &drive_fast);
1179         if (drive_fast & 0x80)
1180                 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
1181         pci_read_config_dword(dev, 0x40, &reg1);
1182
1183         return 0;
1184 }
1185
1186 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1187 {
1188         int ret = 0;
1189
1190         /*
1191          * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1192          * We don't seem to be using it.
1193          */
1194         if (dev->resource[PCI_ROM_RESOURCE].start)
1195                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1196                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1197
1198         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1199         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1200         pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1201         pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1202
1203         if (hpt_revision(dev) >= 3)
1204                 ret = init_hpt37x(dev);
1205         else
1206                 ret = init_hpt366(dev);
1207
1208         if (ret)
1209                 return ret;
1210
1211         return dev->irq;
1212 }
1213
1214 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1215 {
1216         struct pci_dev *dev             = hwif->pci_dev;
1217         struct hpt_info *info           = ide_get_hwifdata(hwif);
1218         u8 ata66 = 0, regmask           = (hwif->channel) ? 0x01 : 0x02;
1219         int serialize                   = HPT_SERIALIZE_IO;
1220
1221         hwif->tuneproc                  = &hpt3xx_tune_drive;
1222         hwif->speedproc                 = &hpt3xx_tune_chipset;
1223         hwif->quirkproc                 = &hpt3xx_quirkproc;
1224         hwif->intrproc                  = &hpt3xx_intrproc;
1225         hwif->maskproc                  = &hpt3xx_maskproc;
1226
1227         /*
1228          * HPT3xxN chips have some complications:
1229          *
1230          * - on 33 MHz PCI we must clock switch
1231          * - on 66 MHz PCI we must NOT use the PCI clock
1232          */
1233         if ((info->flags & (IS_3xxN | PCI_66MHZ)) == IS_3xxN) {
1234                 /*
1235                  * Clock is shared between the channels,
1236                  * so we'll have to serialize them... :-(
1237                  */
1238                 serialize = 1;
1239                 hwif->rw_disk = &hpt3xxn_rw_disk;
1240         }
1241
1242         /*
1243          * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1244          * address lines to access an external eeprom.  To read valid
1245          * cable detect state the pins must be enabled as inputs.
1246          */
1247         if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) {
1248                 /*
1249                  * HPT374 PCI function 1
1250                  * - set bit 15 of reg 0x52 to enable TCBLID as input
1251                  * - set bit 15 of reg 0x56 to enable FCBLID as input
1252                  */
1253                 u16 mcr3, mcr6;
1254                 pci_read_config_word(dev, 0x52, &mcr3);
1255                 pci_read_config_word(dev, 0x56, &mcr6);
1256                 pci_write_config_word(dev, 0x52, mcr3 | 0x8000);
1257                 pci_write_config_word(dev, 0x56, mcr6 | 0x8000);
1258                 /* now read cable id register */
1259                 pci_read_config_byte(dev, 0x5a, &ata66);
1260                 pci_write_config_word(dev, 0x52, mcr3);
1261                 pci_write_config_word(dev, 0x56, mcr6);
1262         } else if (info->revision >= 3) {
1263                 /*
1264                  * HPT370/372 and 374 pcifn 0
1265                  * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
1266                  */
1267                 u8 scr2;
1268                 pci_read_config_byte(dev, 0x5b, &scr2);
1269                 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1270                 /* now read cable id register */
1271                 pci_read_config_byte(dev, 0x5a, &ata66);
1272                 pci_write_config_byte(dev, 0x5b, scr2);
1273         } else {
1274                 pci_read_config_byte(dev, 0x5a, &ata66);
1275         }
1276
1277 #ifdef DEBUG
1278         printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1279                 ata66, (ata66 & regmask) ? "33" : "66",
1280                 PCI_FUNC(hwif->pci_dev->devfn));
1281 #endif /* DEBUG */
1282
1283         /* Serialize access to this device */
1284         if (serialize && hwif->mate)
1285                 hwif->serialized = hwif->mate->serialized = 1;
1286
1287         /*
1288          * Set up ioctl for power status.
1289          * NOTE:  power affects both drives on each channel.
1290          */
1291         hwif->busproc = &hpt3xx_busproc;
1292
1293         if (!hwif->dma_base) {
1294                 hwif->drives[0].autotune = 1;
1295                 hwif->drives[1].autotune = 1;
1296                 return;
1297         }
1298
1299         hwif->ultra_mask = 0x7f;
1300         hwif->mwdma_mask = 0x07;
1301
1302         if (!(hwif->udma_four))
1303                 hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
1304         hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1305
1306         if (info->revision >= 8) {
1307                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1308                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1309         } else if (info->revision >= 5) {
1310                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1311                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1312         } else if (info->revision >= 3) {
1313                 hwif->dma_start = &hpt370_ide_dma_start;
1314                 hwif->ide_dma_end = &hpt370_ide_dma_end;
1315                 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1316                 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1317         } else if (info->revision >= 2)
1318                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1319         else
1320                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1321
1322         if (!noautodma)
1323                 hwif->autodma = 1;
1324         hwif->drives[0].autodma = hwif->autodma;
1325         hwif->drives[1].autodma = hwif->autodma;
1326 }
1327
1328 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1329 {
1330         struct hpt_info *info   = ide_get_hwifdata(hwif);
1331         u8 masterdma    = 0, slavedma = 0;
1332         u8 dma_new      = 0, dma_old = 0;
1333         u8 primary      = hwif->channel ? 0x4b : 0x43;
1334         u8 secondary    = hwif->channel ? 0x4f : 0x47;
1335         unsigned long flags;
1336
1337         if (!dmabase)
1338                 return;
1339
1340         if(info->speed == NULL) {
1341                 printk(KERN_WARNING "%s: no known IDE timings, disabling DMA.\n",
1342                        hwif->cds->name);
1343                 return;
1344         }
1345
1346         dma_old = hwif->INB(dmabase+2);
1347
1348         local_irq_save(flags);
1349
1350         dma_new = dma_old;
1351         pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
1352         pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
1353
1354         if (masterdma & 0x30)   dma_new |= 0x20;
1355         if (slavedma & 0x30)    dma_new |= 0x40;
1356         if (dma_new != dma_old)
1357                 hwif->OUTB(dma_new, dmabase+2);
1358
1359         local_irq_restore(flags);
1360
1361         ide_setup_dma(hwif, dmabase, 8);
1362 }
1363
1364 /*
1365  *      We "borrow" this hook in order to set the data structures
1366  *      up early enough before dma or init_hwif calls are made.
1367  */
1368
1369 static void __devinit init_iops_hpt366(ide_hwif_t *hwif)
1370 {
1371         struct hpt_info *info   = kzalloc(sizeof(struct hpt_info), GFP_KERNEL);
1372         struct pci_dev  *dev    = hwif->pci_dev;
1373         u16 did                 = dev->device;
1374         u8 mode, rid            = 0;
1375
1376         if(info == NULL) {
1377                 printk(KERN_WARNING "%s: out of memory.\n", hwif->cds->name);
1378                 return;
1379         }
1380         ide_set_hwifdata(hwif, info);
1381
1382         /* Avoid doing the same thing twice. */
1383         if (hwif->channel && hwif->mate) {
1384                 memcpy(info, ide_get_hwifdata(hwif->mate), sizeof(struct hpt_info));
1385                 return;
1386         }
1387
1388         pci_read_config_byte(dev, PCI_REVISION_ID, &rid);
1389
1390         if (( did == PCI_DEVICE_ID_TTI_HPT366  && rid == 6) ||
1391             ((did == PCI_DEVICE_ID_TTI_HPT372  ||
1392               did == PCI_DEVICE_ID_TTI_HPT302  ||
1393               did == PCI_DEVICE_ID_TTI_HPT371) && rid > 1) ||
1394               did == PCI_DEVICE_ID_TTI_HPT372N)
1395                 info->flags |= IS_3xxN;
1396
1397         rid = info->revision = hpt_revision(dev);
1398         if (rid >= 8)                   /* HPT374 */
1399                 mode = HPT374_ALLOW_ATA133_6 ? 4 : 3;
1400         else if (rid >= 7)              /* HPT371 and HPT371N */
1401                 mode = HPT371_ALLOW_ATA133_6 ? 4 : 3;
1402         else if (rid >= 6)              /* HPT302 and HPT302N */
1403                 mode = HPT302_ALLOW_ATA133_6 ? 4 : 3;
1404         else if (rid >= 5)              /* HPT372, HPT372A, and HPT372N */
1405                 mode = HPT372_ALLOW_ATA133_6 ? 4 : 3;
1406         else if (rid >= 3)              /* HPT370 and HPT370A */
1407                 mode = HPT370_ALLOW_ATA100_5 ? 3 : 2;
1408         else                            /* HPT366 and HPT368 */
1409                 mode = (HPT366_ALLOW_ATA66_4 || HPT366_ALLOW_ATA66_3) ? 2 : 1;
1410         info->max_mode = mode;
1411
1412         if (rid >= 3)
1413                 hpt37x_clocking(hwif);
1414         else
1415                 hpt366_clocking(hwif);
1416 }
1417
1418 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1419 {
1420         struct pci_dev *dev2;
1421
1422         if (PCI_FUNC(dev->devfn) & 1)
1423                 return -ENODEV;
1424
1425         if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1426                 int ret;
1427
1428                 if (dev2->irq != dev->irq) {
1429                         /* FIXME: we need a core pci_set_interrupt() */
1430                         dev2->irq = dev->irq;
1431                         printk(KERN_WARNING "%s: PCI config space interrupt "
1432                                "fixed.\n", d->name);
1433                 }
1434                 ret = ide_setup_pci_devices(dev, dev2, d);
1435                 if (ret < 0)
1436                         pci_dev_put(dev2);
1437                 return ret;
1438         }
1439         return ide_setup_pci_device(dev, d);
1440 }
1441
1442 static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
1443 {
1444         return ide_setup_pci_device(dev, d);
1445 }
1446
1447 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1448 {
1449         u8 rev = 0, mcr1 = 0;
1450
1451         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1452
1453         if (rev > 1)
1454                 d->name = "HPT371N";
1455
1456         /*
1457          * HPT371 chips physically have only one channel, the secondary one,
1458          * but the primary channel registers do exist!  Go figure...
1459          * So,  we manually disable the non-existing channel here
1460          * (if the BIOS hasn't done this already).
1461          */
1462         pci_read_config_byte(dev, 0x50, &mcr1);
1463         if (mcr1 & 0x04)
1464                 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1465
1466         return ide_setup_pci_device(dev, d);
1467 }
1468
1469 static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
1470 {
1471         u8 rev = 0;
1472
1473         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1474
1475         if (rev > 1)
1476                 d->name = "HPT372N";
1477
1478         return ide_setup_pci_device(dev, d);
1479 }
1480
1481 static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
1482 {
1483         u8 rev = 0;
1484
1485         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1486
1487         if (rev > 1)
1488                 d->name = "HPT302N";
1489
1490         return ide_setup_pci_device(dev, d);
1491 }
1492
1493 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1494 {
1495         struct pci_dev *dev2;
1496         u8 rev = 0;
1497         static char   *chipset_names[] = { "HPT366", "HPT366",  "HPT368",
1498                                            "HPT370", "HPT370A", "HPT372",
1499                                            "HPT372N" };
1500
1501         if (PCI_FUNC(dev->devfn) & 1)
1502                 return -ENODEV;
1503
1504         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1505
1506         if (rev > 6)
1507                 rev = 6;
1508
1509         d->name = chipset_names[rev];
1510
1511         if (rev > 2)
1512                 goto init_single;
1513
1514         d->channels = 1;
1515
1516         if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1517                 u8  pin1 = 0, pin2 = 0;
1518                 int ret;
1519
1520                 pci_read_config_byte(dev,  PCI_INTERRUPT_PIN, &pin1);
1521                 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1522                 if (pin1 != pin2 && dev->irq == dev2->irq) {
1523                         d->bootable = ON_BOARD;
1524                         printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
1525                                d->name, pin1, pin2);
1526                 }
1527                 ret = ide_setup_pci_devices(dev, dev2, d);
1528                 if (ret < 0)
1529                         pci_dev_put(dev2);
1530                 return ret;
1531         }
1532 init_single:
1533         return ide_setup_pci_device(dev, d);
1534 }
1535
1536 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1537         {       /* 0 */
1538                 .name           = "HPT366",
1539                 .init_setup     = init_setup_hpt366,
1540                 .init_chipset   = init_chipset_hpt366,
1541                 .init_iops      = init_iops_hpt366,
1542                 .init_hwif      = init_hwif_hpt366,
1543                 .init_dma       = init_dma_hpt366,
1544                 .channels       = 2,
1545                 .autodma        = AUTODMA,
1546                 .bootable       = OFF_BOARD,
1547                 .extra          = 240
1548         },{     /* 1 */
1549                 .name           = "HPT372A",
1550                 .init_setup     = init_setup_hpt372a,
1551                 .init_chipset   = init_chipset_hpt366,
1552                 .init_iops      = init_iops_hpt366,
1553                 .init_hwif      = init_hwif_hpt366,
1554                 .init_dma       = init_dma_hpt366,
1555                 .channels       = 2,
1556                 .autodma        = AUTODMA,
1557                 .bootable       = OFF_BOARD,
1558                 .extra          = 240
1559         },{     /* 2 */
1560                 .name           = "HPT302",
1561                 .init_setup     = init_setup_hpt302,
1562                 .init_chipset   = init_chipset_hpt366,
1563                 .init_iops      = init_iops_hpt366,
1564                 .init_hwif      = init_hwif_hpt366,
1565                 .init_dma       = init_dma_hpt366,
1566                 .channels       = 2,
1567                 .autodma        = AUTODMA,
1568                 .bootable       = OFF_BOARD,
1569                 .extra          = 240
1570         },{     /* 3 */
1571                 .name           = "HPT371",
1572                 .init_setup     = init_setup_hpt371,
1573                 .init_chipset   = init_chipset_hpt366,
1574                 .init_iops      = init_iops_hpt366,
1575                 .init_hwif      = init_hwif_hpt366,
1576                 .init_dma       = init_dma_hpt366,
1577                 .channels       = 2,
1578                 .autodma        = AUTODMA,
1579                 .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1580                 .bootable       = OFF_BOARD,
1581                 .extra          = 240
1582         },{     /* 4 */
1583                 .name           = "HPT374",
1584                 .init_setup     = init_setup_hpt374,
1585                 .init_chipset   = init_chipset_hpt366,
1586                 .init_iops      = init_iops_hpt366,
1587                 .init_hwif      = init_hwif_hpt366,
1588                 .init_dma       = init_dma_hpt366,
1589                 .channels       = 2,    /* 4 */
1590                 .autodma        = AUTODMA,
1591                 .bootable       = OFF_BOARD,
1592                 .extra          = 240
1593         },{     /* 5 */
1594                 .name           = "HPT372N",
1595                 .init_setup     = init_setup_hpt372n,
1596                 .init_chipset   = init_chipset_hpt366,
1597                 .init_iops      = init_iops_hpt366,
1598                 .init_hwif      = init_hwif_hpt366,
1599                 .init_dma       = init_dma_hpt366,
1600                 .channels       = 2,    /* 4 */
1601                 .autodma        = AUTODMA,
1602                 .bootable       = OFF_BOARD,
1603                 .extra          = 240
1604         }
1605 };
1606
1607 /**
1608  *      hpt366_init_one -       called when an HPT366 is found
1609  *      @dev: the hpt366 device
1610  *      @id: the matching pci id
1611  *
1612  *      Called when the PCI registration layer (or the IDE initialization)
1613  *      finds a device matching our IDE device tables.
1614  *
1615  *      NOTE: since we'll have to modify some fields of the ide_pci_device_t
1616  *      structure depending on the chip's revision, we'd better pass a local
1617  *      copy down the call chain...
1618  */
1619 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1620 {
1621         ide_pci_device_t d = hpt366_chipsets[id->driver_data];
1622
1623         return d.init_setup(dev, &d);
1624 }
1625
1626 static struct pci_device_id hpt366_pci_tbl[] = {
1627         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1628         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1629         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1630         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1631         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1632         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1633         { 0, },
1634 };
1635 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1636
1637 static struct pci_driver driver = {
1638         .name           = "HPT366_IDE",
1639         .id_table       = hpt366_pci_tbl,
1640         .probe          = hpt366_init_one,
1641 };
1642
1643 static int __init hpt366_ide_init(void)
1644 {
1645         return ide_pci_register_driver(&driver);
1646 }
1647
1648 module_init(hpt366_ide_init);
1649
1650 MODULE_AUTHOR("Andre Hedrick");
1651 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1652 MODULE_LICENSE("GPL");