2 * Copyright (C) 1997-1998 Mark Lord <mlord@pobox.com>
3 * Copyright (C) 1998 Eddie C. Dost <ecd@skynet.be>
4 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org>
7 * Inspired by an earlier effort from David S. Miller <davem@redhat.com>
10 #include <linux/module.h>
11 #include <linux/types.h>
12 #include <linux/kernel.h>
13 #include <linux/interrupt.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include <linux/ide.h>
17 #include <linux/init.h>
21 #define DRV_NAME "ns87415"
24 /* SUPERIO 87560 is a PoS chip that NatSem denies exists.
25 * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
26 * which use the integrated NS87514 cell for CD-ROM support.
27 * i.e we have to support for CD-ROM installs.
28 * See drivers/parisc/superio.c for more gory details.
30 #include <asm/superio.h>
32 #define SUPERIO_IDE_MAX_RETRIES 25
34 /* Because of a defect in Super I/O, all reads of the PCI DMA status
35 * registers, IDE status register and the IDE select register need to be
38 static u8 superio_ide_inb (unsigned long port)
41 int retries = SUPERIO_IDE_MAX_RETRIES;
43 /* printk(" [ reading port 0x%x with retry ] ", port); */
49 } while (tmp == 0 && retries-- > 0);
54 static u8 superio_read_status(ide_hwif_t *hwif)
56 return superio_ide_inb(hwif->io_ports.status_addr);
59 static u8 superio_dma_sff_read_status(ide_hwif_t *hwif)
61 return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
64 static void superio_tf_read(ide_drive_t *drive, struct ide_cmd *cmd)
66 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
67 struct ide_taskfile *tf = &cmd->tf;
69 if (cmd->ftf_flags & IDE_FTFLAG_IN_DATA) {
70 u16 data = inw(io_ports->data_addr);
72 tf->data = data & 0xff;
73 tf->hob_data = (data >> 8) & 0xff;
76 /* be sure we're looking at the low order bits */
77 outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);
79 if (cmd->tf_flags & IDE_TFLAG_IN_FEATURE)
80 tf->feature = inb(io_ports->feature_addr);
81 if (cmd->tf_flags & IDE_TFLAG_IN_NSECT)
82 tf->nsect = inb(io_ports->nsect_addr);
83 if (cmd->tf_flags & IDE_TFLAG_IN_LBAL)
84 tf->lbal = inb(io_ports->lbal_addr);
85 if (cmd->tf_flags & IDE_TFLAG_IN_LBAM)
86 tf->lbam = inb(io_ports->lbam_addr);
87 if (cmd->tf_flags & IDE_TFLAG_IN_LBAH)
88 tf->lbah = inb(io_ports->lbah_addr);
89 if (cmd->tf_flags & IDE_TFLAG_IN_DEVICE)
90 tf->device = superio_ide_inb(io_ports->device_addr);
92 if (cmd->tf_flags & IDE_TFLAG_LBA48) {
93 outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr);
95 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
96 tf->hob_feature = inb(io_ports->feature_addr);
97 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
98 tf->hob_nsect = inb(io_ports->nsect_addr);
99 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
100 tf->hob_lbal = inb(io_ports->lbal_addr);
101 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
102 tf->hob_lbam = inb(io_ports->lbam_addr);
103 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
104 tf->hob_lbah = inb(io_ports->lbah_addr);
108 static const struct ide_tp_ops superio_tp_ops = {
109 .exec_command = ide_exec_command,
110 .read_status = superio_read_status,
111 .read_altstatus = ide_read_altstatus,
113 .set_irq = ide_set_irq,
115 .tf_load = ide_tf_load,
116 .tf_read = superio_tf_read,
118 .input_data = ide_input_data,
119 .output_data = ide_output_data,
122 static void __devinit superio_init_iops(struct hwif_s *hwif)
124 struct pci_dev *pdev = to_pci_dev(hwif->dev);
126 u8 port = hwif->channel, tmp;
128 dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa);
130 /* Clear error/interrupt, enable dma */
131 tmp = superio_ide_inb(dma_stat);
132 outb(tmp | 0x66, dma_stat);
135 #define superio_dma_sff_read_status ide_dma_sff_read_status
138 static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
141 * This routine either enables/disables (according to IDE_DFLAG_PRESENT)
142 * the IRQ associated with the port,
143 * and selects either PIO or DMA handshaking for the next I/O operation.
145 static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
147 ide_hwif_t *hwif = drive->hwif;
148 struct pci_dev *dev = to_pci_dev(hwif->dev);
149 unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data;
152 local_irq_save(flags);
155 /* Adjust IRQ enable bit */
156 bit = 1 << (8 + hwif->channel);
158 if (drive->dev_flags & IDE_DFLAG_PRESENT)
163 /* Select PIO or DMA, DMA may only be selected for one drive/channel. */
164 bit = 1 << (20 + (drive->dn & 1) + (hwif->channel << 1));
165 other = 1 << (20 + (1 - (drive->dn & 1)) + (hwif->channel << 1));
166 new = use_dma ? ((new & ~other) | bit) : (new & ~bit);
172 * Don't change DMA engine settings while Write Buffers
175 (void) pci_read_config_byte(dev, 0x43, &stat);
176 while (stat & 0x03) {
178 (void) pci_read_config_byte(dev, 0x43, &stat);
182 (void) pci_write_config_dword(dev, 0x40, new);
185 * And let things settle...
190 local_irq_restore(flags);
193 static void ns87415_selectproc (ide_drive_t *drive)
195 ns87415_prepare_drive(drive,
196 !!(drive->dev_flags & IDE_DFLAG_USING_DMA));
199 static void ns87415_dma_start(ide_drive_t *drive)
201 ns87415_prepare_drive(drive, 1);
202 ide_dma_start(drive);
205 static int ns87415_dma_end(ide_drive_t *drive)
207 ide_hwif_t *hwif = drive->hwif;
208 u8 dma_stat = 0, dma_cmd = 0;
210 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
211 /* get DMA command mode */
212 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
214 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
215 /* from ERRATA: clear the INTR & ERROR bits */
216 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
217 outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD);
219 ns87415_prepare_drive(drive, 0);
221 /* verify good DMA status */
222 return (dma_stat & 7) != 4;
225 static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
227 struct pci_dev *dev = to_pci_dev(hwif->dev);
228 unsigned int ctrl, using_inta;
236 * We cannot probe for IRQ: both ports share common IRQ on INTA.
237 * Also, leave IRQ masked during drive probing, to prevent infinite
238 * interrupts from a potentially floating INTA..
240 * IRQs get unmasked in selectproc when drive is first used.
242 (void) pci_read_config_dword(dev, 0x40, &ctrl);
243 (void) pci_read_config_byte(dev, 0x09, &progif);
244 /* is irq in "native" mode? */
245 using_inta = progif & (1 << (hwif->channel << 1));
247 using_inta = ctrl & (1 << (4 + hwif->channel));
249 hwif->select_data = hwif->mate->select_data;
251 hwif->select_data = (unsigned long)
252 &ns87415_control[ns87415_count++];
253 ctrl |= (1 << 8) | (1 << 9); /* mask both IRQs */
255 ctrl &= ~(1 << 6); /* unmask INTA */
256 *((unsigned int *)hwif->select_data) = ctrl;
257 (void) pci_write_config_dword(dev, 0x40, ctrl);
260 * Set prefetch size to 512 bytes for both ports,
261 * but don't turn on/off prefetching here.
263 pci_write_config_byte(dev, 0x55, 0xee);
267 * XXX: Reset the device, if we don't it will not respond to
268 * SELECT_DRIVE() properly during first ide_probe_port().
271 outb(12, hwif->io_ports.ctl_addr);
273 outb(8, hwif->io_ports.ctl_addr);
276 stat = hwif->tp_ops->read_status(hwif);
279 } while ((stat & ATA_BUSY) && --timeout);
284 hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel);
289 outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
292 static const struct ide_port_ops ns87415_port_ops = {
293 .selectproc = ns87415_selectproc,
296 static const struct ide_dma_ops ns87415_dma_ops = {
297 .dma_host_set = ide_dma_host_set,
298 .dma_setup = ide_dma_setup,
299 .dma_start = ns87415_dma_start,
300 .dma_end = ns87415_dma_end,
301 .dma_test_irq = ide_dma_test_irq,
302 .dma_lost_irq = ide_dma_lost_irq,
303 .dma_timer_expiry = ide_dma_sff_timer_expiry,
304 .dma_sff_read_status = superio_dma_sff_read_status,
307 static const struct ide_port_info ns87415_chipset __devinitdata = {
309 .init_hwif = init_hwif_ns87415,
310 .port_ops = &ns87415_port_ops,
311 .dma_ops = &ns87415_dma_ops,
312 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
313 IDE_HFLAG_NO_ATAPI_DMA,
316 static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
318 struct ide_port_info d = ns87415_chipset;
320 #ifdef CONFIG_SUPERIO
321 if (PCI_SLOT(dev->devfn) == 0xE) {
322 /* Built-in - assume it's under superio. */
323 d.init_iops = superio_init_iops;
324 d.tp_ops = &superio_tp_ops;
327 return ide_pci_init_one(dev, &d, NULL);
330 static const struct pci_device_id ns87415_pci_tbl[] = {
331 { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
334 MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
336 static struct pci_driver ns87415_pci_driver = {
337 .name = "NS87415_IDE",
338 .id_table = ns87415_pci_tbl,
339 .probe = ns87415_init_one,
340 .remove = ide_pci_remove,
341 .suspend = ide_pci_suspend,
342 .resume = ide_pci_resume,
345 static int __init ns87415_ide_init(void)
347 return ide_pci_register_driver(&ns87415_pci_driver);
350 static void __exit ns87415_ide_exit(void)
352 pci_unregister_driver(&ns87415_pci_driver);
355 module_init(ns87415_ide_init);
356 module_exit(ns87415_ide_exit);
358 MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
359 MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
360 MODULE_LICENSE("GPL");